Flexible circuit board

Abstract

A flexible circuit board according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; a first sensing electrode disposed on the first surface and extending in a first direction; a second sensing electrode disposed on the second surface and extending in a second direction different from the first direction; a first wiring electrode connected to the first sensing electrode; and a second wiring electrode connected to the second sensing electrode, wherein: the first surface includes a chip mounting area; the second surface includes an overlapping area overlapping the chip mounting area in the thickness direction of the substrate; the flexible circuit board includes a first dummy electrode disposed in the chip mounting area and a second dummy electrode disposed in the overlapping area; and at least one of the first dummy electrode and the second dummy electrode comprises a plurality of dummy electrodes extending in a plurality of different directions.

Description

flexible circuit board

[0001] The embodiment relates to a flexible circuit board.

[0002] A fingerprint sensor module detects a fingerprint. The fingerprint sensor module can be applied to an IC card. This enhances the security of the IC card.

[0003] The above fingerprint sensor module is classified into an optical sensor, a capacitive sensor, an ultrasonic sensor, or a thermal sensor depending on the fingerprint sensing method. Depending on the operating principle of each, fingerprint image data can be acquired from the finger.

[0004] The fingerprint sensor module includes a chip that processes the acquired data. Heat is generated in the chip during operation of the fingerprint sensor module.

[0005] Accordingly, the temperature of the fingerprint sensor module may increase.

[0006] Additionally, noise may enter the interior of the fingerprint sensor module. This noise may cause errors in fingerprint sensing.

[0007] Therefore, a new flexible circuit board having a new structure capable of solving the above-described problems and a fingerprint sensor module including the same are required.

[0008] Meanwhile, Korean Patent Publication No. KR10-2022-0013230 (2022.02.04) is disclosed as a prior art related to a fingerprint sensor module.

[0009] The embodiment provides a flexible circuit board having improved heat dissipation properties.

[0010] Additionally, the embodiment provides a flexible circuit board having improved reliability.

[0011] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0012] A flexible circuit board according to an embodiment comprises a substrate including a first surface and a second surface opposite to the first surface; a first sensing electrode disposed on the first surface and extending in a first direction; a second sensing electrode disposed on the second surface and extending in a second direction different from the first direction; a first wiring electrode connected to the first sensing electrode; and a second wiring electrode connected to the second sensing electrode, wherein the first surface includes a chip mounting area, and the second surface includes an overlapping area overlapping the chip mounting area along a thickness direction of the substrate, and includes a first dummy electrode disposed in the chip mounting area and a second dummy electrode disposed in the overlapping area, and at least one of the first dummy electrode and the second dummy electrode includes a plurality of dummy electrodes extending in a plurality of different directions.

[0013] According to another embodiment, a flexible circuit board includes a substrate including a first surface and a second surface opposite to the first surface; and circuit patterns disposed on the first surface and the second surface, the circuit patterns including: a first circuit pattern disposed on the first surface; a second circuit pattern disposed on the first surface and the second surface; and a third circuit pattern disposed on the first surface and the second surface, wherein a first groove is formed on the first surface, a second groove is formed on the second surface, the first groove is disposed between at least one of adjacent first circuit patterns, between adjacent second circuit patterns, and between adjacent third circuit patterns, and the second groove is disposed between at least one of adjacent second circuit patterns and between adjacent third circuit patterns.

[0014] A flexible circuit board according to an embodiment includes a dummy electrode. Specifically, the substrate includes a first side and a first side opposite to the first side. A first dummy electrode is disposed on the chip mounting area of ​​the first side. In addition, a second dummy electrode is disposed on the second side corresponding to the chip mounting area.

[0015] The first dummy electrode and the second dummy electrode each include an open area. Accordingly, the first dummy electrode and the second dummy electrode extend in multiple directions. Accordingly, the path of heat moving through the first dummy electrode and the second dummy electrode increases. Accordingly, the heat dissipation effect through the first dummy electrode and the second dummy electrode increases.

[0016] Additionally, the first dummy electrode and the second dummy electrode are connected through a via. Accordingly, the heat dissipation area of ​​the flexible circuit board increases. Accordingly, when the fingerprint sensor module is operated, the temperature of the fingerprint sensor module can be prevented from increasing.

[0017] Additionally, the flexible circuit board according to the embodiment includes a substrate and a circuit pattern on the substrate.

[0018] The above substrate includes a groove. The groove is positioned on the first and second surfaces of the substrate. The groove is positioned between adjacent circuit patterns. Accordingly, when forming the circuit patterns, any metal layer that may remain between the circuit patterns can be removed.

[0019] Therefore, short-circuiting of adjacent circuit patterns can be prevented. Consequently, the reliability and operating characteristics of the flexible circuit board are improved.

[0020] Additionally, the grooves arranged on the first side and the second side may partially overlap in the thickness direction of the substrate. Alternatively, the grooves arranged on the first side and the second side may not overlap in the thickness direction of the substrate.

[0021] Accordingly, the difference in thickness between the overlapping region of the grooves and other regions is reduced. Consequently, the strength of the substrate is enhanced. Furthermore, bending of the flexible circuit board in specific regions of the substrate can be prevented.

[0022] Additionally, the depth of the groove can vary depending on the spacing between adjacent circuit patterns. Specifically, the groove depth can be large in areas where the spacing between circuit patterns is large. Accordingly, even in areas where the spacing between adjacent circuit patterns is large, the remaining metal layer can be largely removed.

[0023] Figures 1 and 2 are top views of a flexible circuit board according to the first embodiment.

[0024] Figures 3 and 4 are bottom views of a flexible circuit board according to the first embodiment.

[0025] Figures 5 to 16 are enlarged views of the chip mounting area and the lower surface opposite to the chip mounting area.

[0026] Figure 17 is an enlarged view of area A of Figure 1, and Figure 18 is an enlarged view of area B of Figure 3.

[0027] Fig. 19 is a top view of a flexible circuit board according to the third embodiment.

[0028] Fig. 20 is a bottom view of a flexible circuit board according to the fourth embodiment.

[0029] Figure 21 is an enlarged view of area A of Figure 19, and Figure 22 is an enlarged view of area B of Figure 19.

[0030] Figure 23 is an enlarged view of area C of Figure 20.

[0031] Figure 24 is an enlarged view of area D of Figure 20.

[0032] Figure 25 is an enlarged view of area E of Figure 19.

[0033] Figure 26 is an enlarged view of area F of Figure 20.

[0034] Figures 27 and 28 are cross-sectional views taken along the AA' area of ​​Figure 21.

[0035] Figures 29 to 31 are drawings illustrating a manufacturing process of a circuit pattern of a flexible circuit board according to an embodiment.

[0036] Figures 32 to 36 are cross-sectional views taken along the BB' area of ​​Figure 19.

[0037] Figure 37 is a cross-sectional view taken along the CC' area of ​​Figure 21.

[0038] Figure 38 is a cross-sectional view taken along the DD' area of ​​Figure 23.

[0039] Figure 39 is a cross-sectional view taken along the EE' area of ​​Figure 21.

[0040] Figure 40 is an enlarged view of area G of Figure 19.

[0041] Figure 41 is a cross-sectional view taken along the FF' area of ​​Figure 40.

[0042] Figure 42 is another enlarged view of area G of Figure 19.

[0043] Figure 43 is a cross-sectional view taken along the GG' area of ​​Figure 42.

[0044] FIG. 44 is a top view of a fingerprint sensor module according to one embodiment.

[0045] FIG. 45 is a drawing illustrating a fingerprint recognition card according to one embodiment.

[0046] Figure 46 is a drawing for explaining the connection of a COF module and other members according to an embodiment.

[0047] FIGS. 47 to 49 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0048] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0049] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0050] In addition, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0051] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0052] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0053] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0054] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0055]

[0056] Hereinafter, a flexible circuit board according to an embodiment will be described with reference to the drawings.

[0057] However, before describing the embodiments, it should be noted that the flexible circuit board described below may be a fingerprint sensor board on which a fingerprint sensor for fingerprint recognition is placed. Alternatively, the flexible circuit board described below may be a driver chip board on which a driver chip is placed. In other words, the flexible circuit board described below may be applicable to various products depending on the type of chip mounted thereon.

[0058]

[0059] FIGS. 1 and 2 are top views of a flexible circuit board according to a first embodiment, FIGS. 3 and 4 are bottom views of a flexible circuit board according to the first embodiment, FIGS. 5 to 16 are enlarged views of a chip mounting area and a bottom surface opposite to the chip mounting area, FIG. 17 is an enlarged view of area A of FIG. 1, and FIG. 18 is an enlarged view of area B of FIG. 3.

[0060] Referring to FIGS. 1 to 4, a flexible circuit board (1000) includes a substrate (100), a sensing electrode, a wiring electrode, a dummy electrode, and a protective layer.

[0061] The above-described substrate (100) includes a first surface (1S) and a second surface (2S) opposite to the first surface (1S). The first surface (1S) is the upper surface of the flexible circuit board. The second surface (2S) is the lower surface of the flexible circuit board.

[0062] The above substrate (100) includes a cutting line (CL). The flexible circuit board (1000) is cut along the cutting line (CL). In detail, the sensing electrode, the wiring electrode, the dummy electrode, the protective layer, and the chip are arranged on the substrate (100). Subsequently, the substrate (100) is cut along the cutting line (CL). At this time, the chip may be a fingerprint sensor. Accordingly, as the substrate (100) is cut based on the cutting line (CL), a fingerprint sensor module (2000) may be manufactured accordingly. However, the embodiment is not limited thereto. For example, the chip may be a driver IC, and thus a COF module (to be described later) may be manufactured. However, for the convenience of explanation, the following description will assume that the mounted chip is a fingerprint sensor, and accordingly, the flexible circuit board (1000) is a fingerprint sensor substrate for mounting a fingerprint sensor.

[0063] The above description (100) includes a valid area and an ineffective area. The valid area and the ineffective area are separated by the cutting line (CL). Specifically, the valid area is an area inside the cutting line (CL). In addition, the ineffective area is an area outside the cutting line (CL).

[0064] The sensing electrode, the wiring electrode, the dummy electrode, the protective layer (600), and the chip are arranged in the effective area. In addition, a dummy pattern and a sprocket hole (SH) are arranged in the ineffective area. The dummy pattern increases the strength of the substrate (100). In addition, the flexible circuit board (1000) is rolled or unrolled in a roll-to-roll manner by the sprocket hole (SH).

[0065] The above-described substrate (100) includes a chip mounting area (CHA). The chip mounting area (CHA) is disposed on the first surface (1S). The chip mounting area (CHA) is disposed in the effective area. The chip is disposed in the chip mounting area (CHA). In addition, the pad portions of the wiring electrode are disposed within the chip mounting area (CHA).

[0066] The substrate (100) comprises a flexible material. For example, the substrate (100) may comprise polyimide (PI). However, the embodiment is not limited thereto. The substrate (100) may comprise a polymer material, such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board can be folded in one direction. Accordingly, the flexible circuit board can be arranged in a small area within the IC card.

[0067] The substrate (100) has a set thickness. For example, the thickness of the substrate (100) may be 20 μm to 100 μm, or 25 μm to 50 μm, or 30 μm to 40 μm. If the thickness of the substrate (100) exceeds 100 μm, the thickness of the flexible circuit board increases. This reduces the flexible characteristics of the flexible circuit board. In addition, if the thickness of the substrate (100) is less than 20 μm, the substrate (100) may be damaged by heat and pressure applied to the substrate when the chip is mounted on the flexible circuit board.

[0068] The above sensing electrode is placed on the substrate (100). The sensing electrode includes a first sensing electrode (210) and a second sensing electrode (220).

[0069] The first sensing electrode (210) is disposed on the first surface (1S). The first sensing electrode (210) is disposed in the effective area. The first sensing electrode (210) extends in one direction. For example, the first sensing electrode (210) extends in the first direction (1D). The first sensing electrode (210) includes a plurality of first pattern electrodes. The plurality of first pattern electrodes are spaced apart in the second direction (2D). The first direction (1D) and the second direction (2D) may be perpendicular.

[0070] The second sensing electrode (220) is disposed on the second surface (2S). The second sensing electrode (220) is disposed in the effective area. The second sensing electrode (220) extends in another direction. For example, the second sensing electrode (220) extends in the second direction (2D). The second sensing electrode (220) includes a plurality of second pattern electrodes. The plurality of second pattern electrodes are spaced apart in the first direction (1D).

[0071] Accordingly, the first sensing electrode (210) and the second sensing electrode (220) are arranged on different surfaces and intersect each other. Accordingly, the first sensing electrode (210) and the second sensing electrode (220) form an intersection area. The flexible circuit board can sense a fingerprint by a change in electrostatic capacitance of the intersection area.

[0072] The sensing electrode (210, 22O) may include a metal material having excellent electrical conductivity. Specifically, the sensing electrode (210, 22O) may include copper (Cu). However, the embodiment is not limited thereto. The sensing electrode (210, 22O) may include at least one metal selected from the group consisting of copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti), and alloys thereof.

[0073] The above sensing electrode may include a plurality of dummy portions. Specifically, a first dummy portion (710) and a second dummy portion (720) may be arranged on the substrate (100). The first dummy portion (710) may be arranged on the first surface (1S). The second dummy portion (720) may be arranged on the second surface (2S).

[0074] The first dummy portion (710) and the second dummy portion (720) are connected. In detail, the first dummy portion (710) and the second dummy portion (720) can be connected through a fifth via (V5).

[0075] The first dummy portion (710) and the second dummy portion (720) are not connected to the wiring electrode. The first dummy portion (710) and the second dummy portion (720) may be ground electrodes.

[0076] The above wiring electrode is placed on the substrate (100). The above wiring electrode includes a first wiring electrode (310), a second wiring electrode, and a third wiring electrode (330).

[0077] The first wiring electrode (310) is disposed on the first surface (1S). The first wiring electrode (310) is disposed in the effective area. The first wiring electrode (310) extends to the chip mounting area (CHA). The first wiring electrode (310) is connected to the first sensing electrode (210). In addition, the first wiring electrode (310) is connected to the first pad portion (410). The first pad portion (410) is disposed inside the chip mounting area (CHA). Accordingly, the first sensing electrode (210) is electrically connected to the chip by the first wiring electrode (310).

[0078] The above second wiring electrode includes a 2-1 wiring electrode (321) and a 2-2 wiring electrode.

[0079] The above 2-1 wiring electrode (321) is disposed on the second surface (2S). The 2-1 wiring electrode (321) is disposed in an effective area. The 2-1 wiring electrode (321) is directly connected to the second sensing electrode. At least one first via (V1) is disposed on the second surface (2S). The 2-1 wiring electrode (321) extends to the first via (V1).

[0080] The above 2-2 wiring electrode is arranged on the first surface (2S). The 2-2 wiring electrode includes a 2-2a wiring electrode (322a) and a 2-2b wiring electrode (322b).

[0081] The above-mentioned 2-2a wiring electrode (322a) is connected to the first via (V1) on the first surface (1S). The above-mentioned 2-2a wiring electrode (322a) extends to the chip mounting area (CHA). The above-mentioned 2-2a wiring electrode (322a) is connected to the second pad portion (420). The above-mentioned second pad portion (420) is disposed inside the chip mounting area (CHA). Accordingly, at least one of the second sensing electrodes (220) is electrically connected to the chip by the first via (V1), the 2-1 wiring electrode (321), and the above-mentioned 2-2a wiring electrode (322a).

[0082] At least one second via (V2) is arranged on the second surface (2S). The second via (V2) is arranged in an area overlapping the second sensing electrode (220). The 2-2b wiring electrode (322b) is connected to the second via (V2) on the first surface (1S). The 2-2b wiring electrode (322b) extends to the chip mounting area (CHA). The 2-2b wiring electrode (322b) is connected to the second pad portion (420). The second pad portion (420) is arranged inside the chip mounting area (CHA). Accordingly, at least one of the second sensing electrodes (220) is electrically connected to the chip by the second via (V2) and the 2-2b wiring electrode (322b).

[0083] The third wiring electrode (330) is disposed on the first surface (1S). The third wiring electrode (330) is disposed in the effective area. The third wiring electrode (330) extends to the chip mounting area (CHA). The third wiring electrode (310) is connected to an external power source. The third wiring electrode (330) is connected to the 3-1 pad portion (431) inside the chip mounting area (CHA) and the third pad portion (432) outside the chip mounting area (CHA). Accordingly, power is supplied to the chip by the third wiring electrode (330).

[0084] The above dummy electrode is placed on the substrate (100). The dummy electrode includes a first dummy electrode (510) and a second dummy electrode (520). The first dummy electrode (510) and the second dummy electrode (520) are not connected to the chip.

[0085] The first dummy electrode (510) is disposed on the first surface (1S). The first dummy electrode is disposed in the chip mounting area (CHA). The first dummy electrode is disposed spaced apart from the pad portions.

[0086] Referring to FIG. 5, the first dummy electrode (510) includes a plurality of first open areas (OA1). The first open areas (OA1) extend in one direction, for example, the first open areas (OA1) may extend in the first direction (1D). The first dummy electrode is not positioned in the first open areas (OA1). Therefore, the first surface (1S) is exposed in the first open areas (OA1).

[0087] The first dummy electrode is divided into a plurality of electrodes by the first open area (OA1). For example, the first dummy electrode may include a first-first dummy electrode and a first-second dummy electrode (512).

[0088] The above-mentioned 1-1 dummy electrode includes a first dummy pattern (511a) arranged at the bottom, a second dummy pattern (511b) arranged at the top, and a third dummy pattern (511c) arranged at the side. The first dummy pattern (511a) and the second dummy pattern (511b) are connected to each other by the third dummy patterns (511c). Accordingly, the first dummy electrode forms a border electrode by the 1-1 dummy electrode.

[0089] The above first-second dummy electrodes (512) are placed between adjacent first open areas (OA1). Therefore, the first-second dummy electrodes (512) are spaced apart from each other by the first open areas (OA1).

[0090] The first dummy electrode extends in multiple directions by the first-first dummy electrode and the first-second dummy electrode (512). The first-first dummy electrode extends in multiple directions. For example, the first-first dummy electrode may extend in the first direction (1D) and the second direction (2D). For example, the first dummy pattern (511a) and the second dummy pattern (511b) extend in the second direction (2D). In addition, the third dummy pattern (511c) extends in the first direction (1D).

[0091] In addition, the first-second dummy electrode (512) extends in one direction. Specifically, the first-second dummy electrode (512) extends in the same direction as the first open area (OA1). For example, the first-second dummy electrode (512) extends in the first direction (1D).

[0092] The chip is placed in the chip mounting area (CHA). The fingerprint sensor module generates heat by the chip during operation. The heat moves to the first dummy electrode. The first dummy electrode includes the first-first dummy electrode and the first-second dummy electrode extending in multiple directions. Therefore, the heat can be easily dissipated through the first dummy electrode. Therefore, an increase in the temperature of the flexible circuit board can be prevented.

[0093] The first dummy electrode includes a via. Specifically, a third via (V3) is arranged on the first dummy electrode. The third via (V3) may be arranged on the first dummy pattern (511a). The first dummy electrode (510) and the second dummy electrode (520) are electrically connected by the third via (V3). The first dummy pattern (511a) includes a region having a wider width. Accordingly, the third via (V3) can be easily arranged on the first dummy pattern (511a).

[0094] The first dummy electrode (510) includes at least one open portion (OP). The open portion (OP) is formed in at least one corner region of the first dummy electrode (510). The first dummy electrode is not disposed on the open portion (OP). The open portion (OP) is formed for an alignment mark (M) described below. In detail, the alignment mark (M) can be identified on the first surface (1S) by the open portion (OP).

[0095] The second dummy electrode (520) is placed on the second surface (2S). The second dummy electrode (520) is placed in an area (CHA1) that overlaps the chip mounting area.

[0096] Referring to Fig. 6, the second dummy electrode includes a plurality of second open areas (OA2). The second open areas (OA2) extend in one direction, and the second open areas (2A) may extend in the same direction as the first open areas (OA1). For example, the second open areas (OA2) may extend in the first direction (1D).

[0097] The first open area (OA1) and the second open area (OA2) may overlap. For example, the first open area (OA1) and the second open area (OA2) may completely overlap. Alternatively, the first open area (OA1) and the second open area (OA2) may partially overlap. Accordingly, the stress difference between the first surface and the second surface corresponding to the chip mounting area may be reduced.

[0098] In addition, the first open area (OA1) and the second open area (OA2) may not overlap. For example, the first open area (OA1) and the second open area (OA2) may be alternately arranged. Accordingly, the heat moving in the first dummy electrode (510) and the second dummy electrode (520) does not overlap. Accordingly, it is possible to prevent a large amount of heat from moving in one area of ​​the chip mounting area.

[0099] The second dummy electrode (520) is not positioned in the second open area (OA2). Therefore, the second surface (2S) is exposed in the second open area (OA2).

[0100] The second dummy electrode is divided into a plurality of electrodes by the second open area (OA2). For example, the second dummy electrode may include a second-first dummy electrode and a second-second dummy electrode (522).

[0101] The above 2-1 dummy electrode includes a fourth dummy pattern (521a) arranged at the bottom, a fifth dummy pattern (521b) arranged at the top, and a sixth dummy pattern (521c) arranged at the side. The fourth dummy pattern (521a) and the fifth dummy pattern (521b) are connected by the sixth dummy patterns (521c). Accordingly, the second dummy electrode forms a border electrode by the 2-1 dummy electrode.

[0102] The above 2-2 dummy electrodes (522) are placed between adjacent 2nd open areas (OA2). Therefore, the 2-2 dummy electrodes (522) are spaced apart by the 2nd open areas (OA2).

[0103] The second dummy electrode (520) extends in multiple directions by the second-first dummy electrode and the second-second dummy electrode (522). The second-first dummy electrode extends in multiple directions. For example, the second-first dummy electrode may extend in the first direction (1D) and the second direction (2D). For example, the fourth dummy pattern (521a) and the fifth dummy pattern (521b) extend in the second direction (2D). In addition, the sixth dummy pattern (521c) extends in the first direction (1D).

[0104] In addition, the second-second dummy electrode (522) extends in one direction. Specifically, the second-second dummy electrode (512) extends in the same direction as the second open area (OA2). For example, the second-second dummy electrode (522) extends in the second direction (2D).

[0105] The chip is placed in the chip mounting area (CHA). The fingerprint sensor module generates heat by the chip during operation. The heat moves to the second dummy electrode. The second dummy electrode includes the second-first dummy electrode and the second-second dummy electrode extending in multiple directions. Therefore, the heat can be easily dissipated through the second dummy electrode. Therefore, an increase in the temperature of the flexible circuit board can be prevented.

[0106] The second dummy electrode includes a via. Specifically, a third via (V3) is disposed on the second-first dummy electrode. The third via (V3) is disposed on the fourth dummy pattern (521a). Accordingly, the first dummy pattern (511a) and the fourth dummy pattern (521a) are connected by the third via (V3). Accordingly, the first dummy electrode (510) and the second dummy electrode (520) are connected. Accordingly, the heat can move through the first dummy electrode (510) and the second dummy electrode (520).

[0107] A plurality of alignment marks (M) are arranged on the above 2-1 dummy electrode (521). The alignment marks (M) can be formed by etching the 2-1 dummy electrode. That is, the alignment marks (M) are portions where the second surface (2S) is exposed. The chip and the pad portion are aligned by the alignment marks (M).

[0108] The second dummy electrode (520) may further include at least one third open area (OA3). In addition, the second dummy electrode (520) may further include at least one second-third dummy electrode (523). The second-third dummy electrode (523) is disposed between adjacent third open areas (OA3). The second-third dummy electrode (523) is disposed below the fourth dummy pattern (521a). The second-third dummy electrode (523) is connected to the fourth dummy pattern (521a). The second-third dummy electrode (523) is formed integrally with the fourth dummy pattern (521a).

[0109] The second dummy electrode (520) is connected to a fourth dummy electrode on the second surface that does not correspond to the chip mounting area by the second-third dummy electrode (523). Accordingly, noise generated in the chip moves to the fourth dummy electrode via the second-third dummy electrode (523).

[0110] The above-mentioned 2-3 dummy electrode (523) includes a plurality of pattern electrodes spaced apart from each other. Accordingly, the noise is dispersed through the plurality of pattern electrodes. Accordingly, the noise can be prevented from being concentrated in one area of ​​the 2-3 dummy electrode (523).

[0111] A protective layer is disposed on each of the first surface (1S) and the second surface (2S).

[0112] A first protective layer (610) is disposed on the first surface (1S). The first protective layer (610) is disposed on an area excluding the chip mounting area (CHA). The first protective layer (610) is disposed on the first sensing electrode (210) and the first wiring electrode (310). In addition, the first protective layer (610) is not disposed on the pad portions and vias.

[0113] A second protective layer (620) is disposed on the second surface (2S). The second protective layer (620) is disposed on an area excluding the via. The second protective layer (620) is disposed on the second sensing electrode (220) and the second wiring electrode. In addition, the second protective layer (620) is not disposed on the via.

[0114] At least one of the first protective layer (610) and the second protective layer (620) may include solder paste. For example, at least one of the first protective layer (610) and the second protective layer (620) may include solder paste containing a thermosetting resin, a thermoplastic resin, a filler, a curing agent, or a curing accelerator.

[0115] A flexible circuit board according to an embodiment includes dummy electrodes. Specifically, a first dummy electrode is disposed in the chip mounting area of ​​the first surface. In addition, a second dummy electrode is disposed in the second surface corresponding to the chip mounting area.

[0116] The first dummy electrode and the second dummy electrode each include an open area. Accordingly, the first dummy electrode and the second dummy electrode extend in multiple directions. Accordingly, the path of heat moving from the first dummy electrode and the second dummy electrode increases. Accordingly, the heat dissipation effect through the first dummy electrode and the second dummy electrode increases.

[0117] Additionally, the first dummy electrode and the second dummy electrode are connected through a via. Accordingly, the heat dissipation area of ​​the flexible circuit board increases.

[0118] Therefore, when the fingerprint sensor module is operated, the temperature of the fingerprint sensor module can be prevented from increasing.

[0119]

[0120] Below, various arrangements of dummy electrodes are described with reference to FIGS. 7 to 14.

[0121] Referring to FIGS. 7 and 8, the size or length of at least one of the open areas may be different from the size or length of the other open areas.

[0122] Referring to FIG. 7, the first open area includes outermost first open areas (EOA1). The outermost first open areas (EOA1) face each other in the second direction (2D). The width of the outermost first open area (EOA1) may be different from the width of the other first open areas (OA1). For example, the width of the outermost first open area (EOA1) may be smaller than the width of the other first open areas (OA1).

[0123] Accordingly, the widths of the first and second dummy electrodes can be made uniform. The first dummy electrode is arranged in the chip mounting area (CHA). A plurality of pad portions are arranged in the chip mounting area (CHA), and the first dummy electrode is spaced apart from the pad portions. Accordingly, by making the sizes of the outermost first open regions among the plurality of first open regions different, the sizes of the plurality of first and second dummy electrodes can be made uniform. Accordingly, a reduction in the heat dissipation effect in the outermost region can be prevented.

[0124] Referring to Fig. 8, the second open area includes outermost second open areas (EOA2). The outermost second open areas (EOA2) face each other in the second direction (2D). The length of the outermost second open area (EOA1) may be different from the length of the other second open areas (OA2). For example, the length of the outermost second open area (EOA2) may be shorter than the length of the other second open areas (OA2).

[0125] The alignment mark (M) is arranged on the second dummy electrode. The alignment mark (M) is arranged in a corner region of the second dummy electrode. By forming the length of the outermost second open areas (EOA2) short, the alignment mark (M) can be easily formed. In other words, overlapping of the alignment mark (M) and the second open area can be prevented.

[0126] Referring to FIGS. 9 and 10, the shape of at least one of the open areas may be different from the shapes of the other open areas.

[0127] Referring to Fig. 9, the first dummy electrode includes an open portion (OP). In addition, the first open area includes at least one corner first open area (COA1) facing a corner of the open portion (OP).

[0128] The shape of the first corner open area (COA1) may be different from the shape of the other first open areas (OA1). Specifically, the first corner open area (COA1) may include a slope. Alternatively, the first corner open area (COA1) may include a narrowing area.

[0129] The corner area of ​​the above-mentioned open portion (OP) may include a curved surface or an inclined surface. Accordingly, the corner first open area may also form an inclined surface or a curved surface according to the shape of the corner area. Accordingly, etching uniformity may be improved.

[0130] Referring to FIG. 10, the second open area includes a corner second open area (COA2) arranged in an area corresponding to the corner first open area (COA1).

[0131] The shape of the second corner open area (COA2) may be different from the shape of the other second open areas (OA2). Specifically, the second corner open area (COA2) may include a slope. Alternatively, the second corner open area (COA2) may include a narrowing area.

[0132] Accordingly, the shapes of the overlapping first corner open area and the second corner open area can be made similar. Accordingly, the heat dissipation characteristics of the first surface and the second surface can be made uniform.

[0133] Referring to FIGS. 11 and 12, at least one open area among the first open area (OA1) and the second open area (OA2) can extend in a direction different from the first direction (1D).

[0134] For example, at least one of the first open area (OA1) and the second open area (OA2) may extend in a diagonal direction between the first direction (1D) and the second direction (2D). Alternatively, at least one of the first open area (OA1) and the second open area (OA2) may extend in the second direction (2D).

[0135] Accordingly, heat can be effectively dissipated depending on the characteristics of the chip placed in the chip mounting area. Specifically, in the case of a chip that generates a lot of heat in the first direction, the open areas can extend in the first direction. Alternatively, in the case of a chip that generates a lot of heat in the second direction, the open areas can extend in the second direction. Alternatively, in the case of a chip that generates a lot of heat in the diagonal direction, the open areas can extend in the diagonal direction. Accordingly, the heat can be effectively dissipated.

[0136] Referring to FIGS. 13 to 16, the size of at least one dummy electrode among the first-second dummy electrode and the second-second dummy electrode may vary while extending in one direction.

[0137] Referring to FIG. 13, the size of the first-second dummy electrode (512) may vary as it extends from the central region to the outer region. Specifically, the width of the first-second dummy electrode (512) may increase as it extends from the central region to the outer region.

[0138] Referring to FIG. 14, the size of the second-second dummy electrode (522) may vary as it extends from the central region to the outer region. Specifically, the width of the second-second dummy electrode (522) may increase as it extends from the central region to the outer region.

[0139] Accordingly, the area of ​​the dummy electrode in the outer portion of the chip mounting area becomes larger than the area of ​​the dummy electrode in the central portion.

[0140] Accordingly, the heat generated from the chip can gradually increase as it disperses to the periphery. Accordingly, heat can be prevented from being concentrated in the central portion of the chip mounting area.

[0141] Referring to FIG. 15, the size of the first-second dummy electrode (512) may vary as it extends from the central region to the outer region. Specifically, the width of the first-second dummy electrode (512) may decrease as it extends from the central region to the outer region.

[0142] Referring to FIG. 16, the size of the second-second dummy electrode (522) may vary as it extends from the central region to the outer region. Specifically, the width of the second-second dummy electrode (522) may decrease as it extends from the central region to the outer region.

[0143] Accordingly, the area of ​​the dummy electrode in the central portion of the chip mounting area becomes larger than the area of ​​the dummy electrode in the outer portion.

[0144] The heat generated from the chip may be greatest in the central portion of the chip mounting area. Furthermore, the heat may decrease as it extends toward the outer portion of the chip mounting area. Accordingly, the area of ​​the dummy electrode is formed to be larger as it extends from the central portion to the outer portion.

[0145] Therefore, the heat generated from the chip can be efficiently dissipated.

[0146] Referring to FIGS. 17 and 18, the flexible circuit board further includes a fourth via (V4).

[0147] The flexible circuit board includes a third dummy electrode (530) and a fourth dummy electrode (540). The third dummy electrode (530) is disposed on the first surface (1S). The third dummy electrode (530) is disposed outside the chip mounting area (CHA). The third dummy electrode (530) is spaced apart from the first dummy electrode (510). The third dummy electrode (530) may be a ground electrode.

[0148] The fourth dummy electrode (540) is disposed on the second surface (2S). The fourth dummy electrode (540) is disposed outside an area (CHA1) corresponding to the chip mounting area. The fourth dummy electrode (540) is connected to the second dummy electrode (520).

[0149] The fourth via (V4) is positioned on the third dummy electrode (530) and the fourth dummy electrode (540). The third dummy electrode (530) and the fourth dummy electrode (540) are connected by the fourth via (V4).

[0150] Accordingly, the second dummy electrode (520) is connected to the third dummy electrode (530) by the fourth dummy electrode (530) and the fourth via (V4).

[0151] Therefore, noise entering the second dummy electrode (520) moves to the third dummy electrode (530) along the fourth dummy electrode (530) and the fourth via (V4).

[0152] Accordingly, the flexible circuit board can easily block the noise. Accordingly, interference between the signal of the chip and noise is prevented, thereby improving the operating characteristics of the fingerprint sensor module.

[0153]

[0154] Meanwhile, the above-described flexible circuit board may be a COF module, which is placed between a display panel and an external circuit board, rather than a fingerprint sensor, and in which a driver chip is placed. When the above-described flexible circuit board is used as a COF module, the sensing electrodes placed on the above-described substrate may be circuit patterns. In addition, when the above-described flexible circuit board is used as a COF module, the arrangement structure of the circuit patterns placed on the substrate may be different from the flexible circuit board described with reference to FIGS. 1 to 18.

[0155] In addition, the grooves provided in the flexible circuit board applied to the COF module described below can be provided in the same manner in the substrate (100) of the flexible circuit board provided in the fingerprint sensor module illustrated in FIGS. 1 to 18.

[0156] FIG. 19 is a top view of a flexible circuit board according to a third embodiment, FIG. 20 is a bottom view of a flexible circuit board according to a fourth embodiment, FIG. 21 is an enlarged view of area A of FIG. 19, FIG. 22 is an enlarged view of area B of FIG. 19, FIG. 23 is an enlarged view of area C of FIG. 20, FIG. 24 is an enlarged view of area D of FIG. 20, FIG. 25 is an enlarged view of area E of FIG. 19, FIG. 26 is an enlarged view of area F of FIG. 20, FIGS. 27 and 28 are cross-sectional views taken along the line AA' of FIG. 21, and FIGS. 29 to 31 are drawings illustrating a manufacturing process of a circuit pattern of a flexible circuit board according to an embodiment, FIGS. 32 to 36 are cross-sectional views taken along the line BB' of FIG. 19, FIG. 37 is a cross-sectional view taken along the line CC' of FIG. 21, and FIG. 38 is FIG. 23 is a cross-sectional view taken along the DD' region, FIG. 39 is a cross-sectional view taken along the EE' region of FIG. 21, FIG. 40 is an enlarged view of the G region of FIG. 19, FIG. 41 is a cross-sectional view taken along the FF' region of FIG. 40, FIG. 42 is another enlarged view of the G region of FIG. 19, and FIG. 43 is a cross-sectional view taken along the GG' region of FIG. 42.

[0157] A flexible circuit board (3000) includes a substrate (3100), and a circuit pattern may be arranged on the substrate (3100). At this time, the circuit pattern may include a first circuit pattern (3210), a second circuit pattern (3220), a third circuit pattern (3230), and a fourth circuit pattern (3240). In addition, the protective layer includes a first protective layer (3310) and a second protective layer (3320).

[0158] Referring to FIGS. 19 and 21, the first circuit pattern (3210) is disposed on the first surface (1S). The first circuit pattern (3210) includes a first wiring portion (3211), a first pad portion (3212a), and a second pad portion (3212b). The first wiring portion (3211), the first pad portion (3212a), and the second pad portion (3212b) include the same material. In addition, the first wiring portion (3211), the first pad portion (3212a), and the second pad portion (3212b) are formed integrally.

[0159] The first pad portion (3212a) is positioned within the chip mounting area (CHA). Accordingly, the first pad portion (3212a) is connected to the terminal of the chip. As a result, the first circuit pattern (3210) and the chip are connected.

[0160] In addition, the second pad portion (3212b) is positioned outside the chip mounting area (CHA). The second pad portion (3212b) is connected to a terminal of a circuit board. Thus, the first circuit pattern (3210) and the circuit board can be connected. The circuit board may include a printed circuit board such as a main board.

[0161] The second pad portion (3212b) may include a first test pad portion. Specifically, the first circuit pattern (3210) may be tested before connecting the circuit board and the second pad portion (3212b). For example, whether the first circuit pattern is open or shorted may be checked through the second pad portion (3212b).

[0162] The first wiring portion (3211) is positioned between the first pad portion (3212a) and the second pad portion (3212b). The first wiring portion (3211) connects the first pad portion (3212a) and the second pad portion (3212b). Accordingly, the chip and the circuit board are connected. Accordingly, a signal generated from the chip is transmitted to the circuit board.

[0163] The first protective layer (3310) is disposed on the first circuit pattern (3210). In detail, the first protective layer (3310) is disposed on an area excluding the first pad portion (3212a) and the second pad portion (3212b).

[0164] Referring to FIGS. 19, 20, 22, and 23, the second circuit pattern (3220) may be disposed on the first surface (1S) and the second surface (2S). The second circuit pattern (3220) includes a second wiring portion (3221a, 3221b), a third pad portion (3222a), a fourth pad portion (3222b), and a first via (V1). The second wiring portion (3221a, 3221b), the third pad portion (3222a), and the fourth pad portion (3222b) include the same material. In addition, the second wiring portion (3221a, 3221b), the third pad portion (3222a), and the fourth pad portion (3222b) are formed integrally.

[0165] The third pad portion (3222a) is positioned on the first surface (1S). The third pad portion (3222a) is positioned within the chip mounting area (CHA). Accordingly, the third pad portion (3222a) is connected to the terminal of the chip. As a result, the second circuit pattern (3220) and the chip are connected.

[0166] Additionally, the fourth pad portion (3222b) is positioned on the second surface (2S). The fourth pad portion (3222b) is connected to a terminal of the display panel. Thus, the second circuit pattern (3220) and the display panel can be connected.

[0167] The second wiring section includes a second-first wiring section (3221a) and a second-second wiring section (3221b). The second-first wiring section (3221a) is disposed on the first surface (1S). The second-second wiring section (3221b) is disposed on the second surface (2S).

[0168] The second wiring section connects the third pad section (3222a) and the fourth pad section (3222b). Specifically, the second-first wiring section (3221a) is connected to the third pad section (3222a). In addition, the second-second wiring section (3221b) is connected to the fourth pad section (3222b).

[0169] Accordingly, the chip and the display panel are connected. Accordingly, signals generated from the chip are transmitted to the display panel.

[0170] The first protective layer (3310) and the second protective layer (3320) are disposed on the second circuit pattern (3220). In detail, the first protective layer (3310) is disposed on the second circuit pattern (3220) on the first surface (1S). In addition, the second protective layer (3320) is disposed on the second circuit pattern (3220) on the second surface (2S). The first protective layer (3310) and the second protective layer (3320) are disposed on an area excluding the third pad portion (3222a) and the fourth pad portion (3222b).

[0171] The above 2-1 wiring portion (3221a) and the 2-2 wiring portion (3221b) are connected. In detail, the 2-1 wiring portion (3221a) and the 2-2 wiring portion (3221b) are connected by the first via (V1). The first via (V1) is arranged on the first surface (1S) and the second surface (2S). The first via (V1) on the first surface (1S) and the first via (V1) on the second surface (2S) are arranged at positions corresponding to each other.

[0172] The first via (V1) includes a first via land (VL1) and a first via hole (VH1) formed in the first via land (VL1). A conductive material is disposed in the first via hole (VH1). Accordingly, the 2-1 wiring portion (3221a) and the 2-2 wiring portion (3221b) are electrically connected.

[0173] The second circuit pattern (3220) may include a second test pad portion (TP2). The second test pad portion (TP2) may be disposed on the second surface (2S). The second test pad portion (TP2) may be disposed in the unactive area (UA). In addition, a second protective layer (3320) is not disposed on the second test pad portion (TP2). The second test pad portion (TP2) may be connected to the 2-2 wiring portion (3221b). In detail, the second test pad portion (TP2) may be formed integrally with the 2-2 wiring portion (3221b).

[0174] The second circuit pattern (3220) can be tested before connecting the display panel and the fourth pad portion (3222b). For example, whether the second circuit pattern is open or shorted can be checked through the second test pad portion (TP2).

[0175] Referring to FIGS. 19, 20, 21, and 24, the third circuit pattern (3230) is disposed on the first surface (1S) and the second surface (2S). The third circuit pattern (3230) includes a third wiring portion (3231), a fifth pad portion (3232a), a sixth pad portion (3232b), and a second via (V2). The third wiring portion (3231), the fifth pad portion (3232a), and the sixth pad portion (3232b) include the same material. In addition, the third wiring portion (3231), the fifth pad portion (3232a), and the sixth pad portion (3232b) are formed integrally.

[0176] The fifth pad portion (3232a) is positioned on the first surface (1S). The fifth pad portion (3232a) is positioned within the chip mounting area (CHA). Accordingly, the fifth pad portion (3232a) is connected to the terminal of the chip. As a result, the third circuit pattern (3230) and the chip are connected.

[0177] Additionally, the sixth pad portion (3232b) is positioned on the second surface (2S). The sixth pad portion (3232b) is connected to a terminal of the display panel. As a result, the third circuit pattern (3230) and the display panel are connected.

[0178] The third wiring portion (3231) is arranged on the second surface (2S). The third wiring portion (3231) connects the fifth pad portion (3232a) and the sixth pad portion (3232b). Accordingly, the chip and the display panel are connected. Accordingly, signals generated from the chip are transmitted to the display panel.

[0179] The second protective layer (3320) is disposed on the third circuit pattern (3230). Specifically, the second protective layer (3320) is disposed on the third circuit pattern (3230) on the second surface (2S). The second protective layer (3320) is disposed on an area excluding the sixth pad portion (3232b).

[0180] The fifth pad portion (3232a) and the third wiring portion (3231) are connected. In detail, the fifth pad portion (3232a) and the third wiring portion (3231) are connected through the second via (V2). The second via (V2) is arranged on the first surface (1S) and the second surface (2S). The second via (V2) on the first surface (1S) and the second via (V2) on the second surface (2S) are arranged at positions corresponding to each other.

[0181] The second via (V2) includes a second via land (VL2) and a second via hole (VH2) formed in the second via land (VL2). A conductive material is disposed in the second via hole (VH2). Accordingly, the fifth pad portion (3232a) and the third wiring portion (3231) are electrically connected.

[0182] The third circuit pattern (3230) may include a third test pad portion (TP3). The third test pad portion (TP3) may be disposed on the second surface (2S). The third test pad portion (TP3) may be disposed in the unactive area (UA). In addition, a second protective layer (3320) is not disposed on the third test pad portion (TP3). The third test pad portion (TP3) may be connected to the third wiring portion (3231). In detail, the third test pad portion (TP3) may be formed integrally with the third wiring portion (3231).

[0183] The third circuit pattern (3230) can be tested before connecting the display panel and the sixth pad portion (3232b). For example, whether the third circuit pattern is open or shorted can be checked through the third test pad portion (TP3).

[0184] Referring to FIG. 19, FIG. 25, and FIG. 26, the fourth circuit pattern (3240) is disposed on the first surface (1S) and the second surface (2S). The fourth circuit pattern (3240) includes a fourth wiring portion (3241a, 3241b), a seventh pad portion (3242a), an eighth pad portion (3242b), and a third via (V3). The fourth wiring portion (3241a, 3241b), the seventh pad portion (3242a), and the eighth pad portion (3242b) include the same material. In addition, the fourth wiring portion (3241a, 3241b), the seventh pad portion (3242a), and the eighth pad portion (3242b) are formed integrally.

[0185] The seventh pad portion (3242a) is positioned on the first surface (1S). The seventh pad portion (3242a) is positioned adjacent to the first pad portion (3212a). The seventh pad portion (3242a) is connected to a terminal of the circuit board. As a result, the fourth circuit pattern (3220) and the circuit board are connected.

[0186] The eighth pad portion (3242b) is positioned on the second surface (2S). The eighth pad portion (3242b) is connected to a terminal of the display panel. Thus, the fourth circuit pattern (3240) and the display panel are connected.

[0187] The fourth wiring section includes a fourth-first wiring section (3241a) and a fourth-second wiring section (3241b). The fourth wiring section connects the seventh pad section (3242a) and the eighth pad section (3242b). Specifically, the fourth-first wiring section (3241a) is connected to the seventh pad section (3242a). In addition, the fourth-second wiring section (3241b) is connected to the eighth pad section (3242b).

[0188] Accordingly, the circuit board and the display panel are connected. Accordingly, the circuit board and the display panel can exchange signals.

[0189] The first protective layer (3310) and the second protective layer (3320) are disposed on the fourth circuit pattern (3240). In detail, the first protective layer (3310) is disposed on the fourth circuit pattern (3240) on the first surface (1S). In addition, the second protective layer (3320) is disposed on the fourth circuit pattern (3240) on the second surface (2S). The first protective layer (3310) and the second protective layer (3320) are disposed on an area excluding the seventh pad portion (3242a) and the eighth pad portion (3242b).

[0190] The above 4-1 wiring portion (3241a) and the 4-2 wiring portion (3241b) are connected. In detail, the 4-1 wiring portion (3241a) and the 4-2 wiring portion (3241b) are connected by the third via (V3). The third via (V3) is arranged on the first surface (1S) and the second surface (2S). The third via (V3) on the first surface (1S) and the third via (V3) on the second surface (2S) are arranged at positions corresponding to each other.

[0191] The third via (V3) includes a third via land (VL3) and a third via hole (VH3) formed in the third via land (VL3). A conductive material is disposed in the third via hole (VH3). Accordingly, the 4-1 wiring portion (3241a) and the 4-2 wiring portion (3241b) are electrically connected.

[0192] Figures 27 and 28 are drawings for explaining the layer structure of a circuit pattern. Figures 27 and 28 illustrate a first circuit pattern as an example. Here, the first circuit pattern described below may refer to the layer structure of the first sensing electrode (210) described in Figures 1 to 18.

[0193] Referring to Fig. 27, the first circuit pattern is formed in multiple layers. In detail, the first wiring portion (3211), the first pad portion (3212a), and the second pad portion (3212b) include a buffer layer (3205), a metal layer (3201), and a bonding layer (3203).

[0194] The buffer layer (3205) may include multiple layers. Specifically, the buffer layer (3205) includes a first buffer layer (3205a) and a second buffer layer (3205b). The first buffer layer (3205a) is disposed on the substrate (3100). The second buffer layer (3205b) is disposed on the first buffer layer (3205a).

[0195] The first buffer layer (3205a) includes a material having good adhesion to the substrate (3100). For example, the first buffer layer (3205a) may include nickel (Ni). In addition, the second buffer layer (3205b) includes a material having good adhesion to the first circuit pattern. For example, the second buffer layer (3205b) may include chromium (Cr).

[0196] The above buffer layer (3205) may have a thin film thickness in nanometer units. For example, the above buffer layer (3205) may have a thickness of 20 nm or less.

[0197] The adhesion between the substrate (3100) and the first circuit pattern is improved by the buffer layer (3205).

[0198] The metal layer (3201) is disposed on the buffer layer (3205). Specifically, the metal layer (3201) is disposed on the second buffer layer (3205b). The metal layer (3201) includes a metal material. For example, the metal layer (3201) may include copper (Cu).

[0199] The above metal layer (3201) may be formed by electroplating using the buffer layer as a seed layer. That is, the metal layer (3201) may be a plating layer. The thickness of the metal layer (3201) may be 10 μm to 30 μm.

[0200] The above bonding layer (3203) is disposed on the metal layer (3201). The bonding layer (3203) is disposed on the side and upper surface of the metal layer (3201). For example, the bonding layer (3203) may be disposed to surround the metal layer (3201). The bonding layer (3203) includes a metal. For example, the bonding layer (3203) may include tin (Sn).

[0201] The thickness of the bonding layer (3203) may be 0.3 μm to 0.7 μm. The tin content may increase as it extends from the lower surface of the bonding layer (3203) toward the upper surface. That is, the bonding layer (3203) is in contact with the metal layer (3201). Therefore, the tin content increases as it extends from the lower surface of the bonding layer (3203) toward the upper surface. In addition, the copper content decreases as it extends from the lower surface of the bonding layer (3203) toward the upper surface. Accordingly, pure tin may remain in a thickness range of 0.1 μm to 0.3 μm from the upper surface of the bonding layer (3203).

[0202] The above pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer (3203). For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0203] Referring to FIG. 28, the metal layer (3201) may include a first metal layer (3201a) and a second metal layer (3201b). The first metal layer (3201a) is disposed on the buffer layer (3205). The second metal layer (3201b) is disposed on the first metal layer (3201a).

[0204] The thickness of the first metal layer (3201a) may be smaller than the thickness of the second metal layer (3201b). For example, the thickness of the first metal layer (3201a) may be 0.7 μm to 2 μm, and the thickness of the second metal layer (3201b) may be 10 μm to 25 μm. The first metal layer (3201a) and the second metal layer (3201b) may include the same metal material. For example, the first metal layer (3201a) and the second metal layer (3201b) may include copper (Cu). The first metal layer (3201a) and the second metal layer (3201b) may be formed through a plating process. For example, the first metal layer (3201a) is formed thinly on the buffer layer (3205). Next, the second metal layer (3201b) can be formed using the first metal layer (3201a) as a seed layer.

[0205] In addition, the bonding layer (3203) may include a first bonding layer (3203a) and a second bonding layer (3203b). The first bonding layer (3203a) is disposed on the metal layer (3201). Specifically, the first bonding layer (3203a) is disposed on the first wiring portion (3211), the first pad portion (3212a), and the second pad portion (3212b). The second bonding layer (3203b) is disposed on the first bonding layer (3203a). Specifically, the second bonding layer (3203b) is disposed on the first pad portion (3212a) and the second pad portion (3212b).

[0206] Accordingly, the first wiring portion (3211) includes the buffer layer (3205), the metal layer (3201), and the first bonding layer (3203a). In addition, the first pad portion (3212a) and the second pad portion (3212b) include the buffer layer (3205), the metal layer (3201), the first bonding layer (3203a), and the second bonding layer (3203b).

[0207] Accordingly, the layer structure of the first wiring portion (3211) is different from the layer structures of the first pad portion (3212a) and the second pad portion (3212b).

[0208] The first bonding layer (3203a) and the second bonding layer (3203b) include metal. Specifically, the first bonding layer (3203a) and the second bonding layer (3203b) may include tin (Sn). The first bonding layer (3203a) and the second bonding layer (3203b) are arranged with different thicknesses. Specifically, the thickness of the second bonding layer (3203b) is greater than the thickness of the first bonding layer (3203a). For example, the first bonding layer (3203a) has a thickness of 0.02 μm to 0.06 μm. Additionally, the second bonding layer (3203b) has a thickness of 0.2 μm to 0.6 μm. Accordingly, the thickness of the first wiring portion (3211) is reduced. Therefore, when bending the flexible circuit board, cracking of the first wiring portion (3211) can be prevented.

[0209] The thickness of the first circuit pattern may be 2 μm to 25 μm. Specifically, the thickness of the first circuit pattern may be 5 μm to 20 μm. Specifically, the thickness of the first circuit pattern may be 7 μm to 15 μm. When the thickness of the first circuit pattern is less than 2 μm, the resistance of the first circuit pattern may increase. When the thickness of the first circuit pattern exceeds 25 μm, it becomes difficult to implement a fine pattern.

[0210] Referring to FIGS. 29 to 31, the circuit patterns are formed by an etching process.

[0211] Referring to Fig. 29, the buffer layer (3205), the metal layer (3201), and the bonding layer (3203) are disposed on the substrate (3100). Next, a photosensitive layer (PR) is disposed on the bonding layer (3203). The photosensitive layer (PR) is disposed in a photosensitive pattern. The photosensitive pattern is disposed on an area where the circuit pattern is formed.

[0212] Referring to Fig. 30, the buffer layer (3205), the metal layer (3201), and the bonding layer (3203) are etched. Accordingly, the buffer layer (3205), the metal layer (3201), and the bonding layer (3203) in the area where the photosensitive pattern is not arranged are etched.

[0213] The above etching process is performed in two steps. First, the metal layer (3201) and the bonding layer (3203) are etched for the first time. Next, the buffer layer (3205) is etched for the second time. However, during the etching process, a portion of the buffer layer (3205) may remain on the substrate (3100).

[0214] Referring to FIG. 31, at least one of the first buffer layer (3205a) and the second buffer layer (3205b) may remain on the substrate (3100). As a result, a residual buffer layer (3206) may be formed. The first buffer layer (3205a) and the second buffer layer (3205b) may be spaced apart from the circuit pattern. However, migration may occur in adjacent circuit patterns due to the residual buffer layer (3206). Accordingly, adjacent circuit patterns may be short-circuited.

[0215] Alternatively, adjacent circuit patterns may be electrically connected by the residual buffer layer (3206). Accordingly, adjacent circuit patterns may be short-circuited. Consequently, the electrical and driving characteristics of the flexible circuit board may deteriorate. Accordingly, the flexible circuit board according to the embodiment forms a groove by partially removing the substrate (3100). Accordingly, the remaining buffer layer may be removed or reduced.

[0216] Referring to FIGS. 32 to 34, the substrate (3100) may include a groove. Specifically, the groove may include a first groove (G1) and a second groove (G2). The first groove (G1) is disposed on the first surface (1S). The first groove (G1) is disposed between adjacent first circuit patterns (3210), between adjacent second circuit patterns (3220), and / or between adjacent third circuit patterns (3230). The second groove (G2) is disposed on the second surface (2S). The second groove (G2) is disposed between adjacent second circuit patterns (3220) and / or between adjacent third circuit patterns (3230). In the case of the embodiments of FIGS. 1 to 18, a groove (not shown) formed on the first surface (1S) of the substrate (100) may be provided between a plurality of first sensing electrodes (210), and a groove (not shown) formed on the second surface (2S) of the substrate (100) may be provided between a plurality of second sensing electrodes (220).

[0217] The buffer layer (3205) between adjacent circuit patterns can be almost or completely removed by the first groove (G1) and the second groove (G2). Specifically, the substrate (3100) is partially etched during the second etching process for etching the buffer layer (3205). Accordingly, the buffer layer (3205) on the first surface (1S) and the second surface (2S) can be (almost) removed. Accordingly, the migration phenomenon of the circuit pattern can be prevented. In addition, short circuiting of adjacent circuit patterns can be prevented.

[0218] The first protective layer (3310) is disposed within the first groove (G1). In addition, the second protective layer (3320) is disposed within the second groove (G2). Accordingly, it is possible to prevent an air layer from forming within the first groove (G1) and the second groove (G2). In addition, it is possible to prevent impurities from penetrating through the first groove (G1) and the second groove (G2).

[0219] The first groove (G1) and the second groove (G2) may have a set depth. For example, the depth of the first groove (G1) and the second groove (G2) may be 10% or less of the thickness of the substrate (3100). In detail, the depth of the first groove (G1) and the second groove (G2) may be 1% to 10%, 2% to 8%, or 3% to 5% of the thickness of the substrate (3100).

[0220] If the depth of the first groove (G1) and the second groove (G2) exceeds 10% of the thickness of the substrate (3100), the strength of the substrate (3100) may decrease. In addition, an area where the protective layer (310, 320) is not disposed may be formed within the groove (G1, G2). Accordingly, the reliability of the flexible circuit board may decrease.

[0221] The thickness of the substrate (3100) varies depending on the position due to the first groove (G1) and the second groove (G2). Specifically, the thickness (T1) of the substrate (3100) in the area overlapping the grooves (G1, G2) may be smaller than the thickness (T2) of the substrate (3100) in the area not overlapping the grooves (G1, G2).

[0222] Referring to FIGS. 32 to 34, the first groove (G1) and the second groove (G2) may overlap or not overlap in the thickness direction of the substrate (3100).

[0223] Referring to FIGS. 32 and 33, the first groove (G1) and the second groove (G2) may overlap in the thickness direction of the substrate (3100). Referring to FIG. 32, the first groove (G1) and the second groove (G2) overlap in the thickness direction of the substrate (3100). Referring to FIG. 15, the first groove (G1) and the second groove (G2) partially overlap in the thickness direction of the substrate (3100).

[0224] Referring to FIG. 34, the first groove (G1) and the second groove (G2) do not overlap in the thickness direction of the substrate (3100).

[0225] Alternatively, the flexible circuit board may include an area where the first groove (G1) and the second groove (G2) overlap and an area where the first groove (G1) and the second groove (G2) do not overlap. That is, the flexible circuit board may include both an area where the grooves overlap and an area where the grooves do not overlap.

[0226] Referring to FIGS. 33 and 34, the first groove (G1) and the second groove (G2) partially overlap or do not overlap in the thickness direction of the substrate (3100). Accordingly, the thickness difference of the substrate (3100) can be reduced. In addition, the thickness of a specific region of the substrate (3100) can be prevented from becoming smaller than that of other regions. Accordingly, the strength of a specific region of the substrate (3100) can be prevented from decreasing.

[0227] Referring to Fig. 35, the first groove (G1) and the second groove (G2) may have different sizes. Specifically, the depth (D1) of the first groove (G1) and the depth (D2) of the second groove (G2) facing each other may be different.

[0228] For example, the depth (D1) of the first groove (G1) facing in the thickness direction of the substrate may be greater than the depth (D2) of the second groove (G2). Alternatively, the depth (D2) of the second groove (G2) may be greater than the depth (D1) of the first groove (G1).

[0229] Accordingly, when the first groove (G1) and the second groove (G2) overlap in the thickness direction of the substrate (3100), the thickness of a specific region of the substrate (3100) can be prevented from becoming smaller than that of other regions. Accordingly, the strength of a specific region of the substrate (3100) can be prevented from decreasing.

[0230] Referring to Fig. 36, the second groove (G2) may not be formed on the second surface (2S) that faces the first groove (G1) in the thickness direction of the substrate. Alternatively, the first groove (G1) may not be formed on the first surface (1S) that faces the second groove (G2) in the thickness direction of the substrate. Accordingly, the thickness of a specific region of the substrate (3100) can be prevented from becoming smaller than other regions. Accordingly, the strength of a specific region of the substrate (3100) can be prevented from decreasing.

[0231] Referring to FIGS. 37 to 39, the first groove (G1) and the second groove (G2) may have different sizes. The spacing between the wiring portions may be different. Alternatively, the spacing between the pad portions may be different.

[0232] Referring to Fig. 37, the second pad portion (3212b) and the third circuit pattern (3230) may face each other. In detail, the second pad portion (3212b) may be arranged on the first surface (1S), and the third wiring portion (3231) may be arranged on the second surface (2S).

[0233] The spacing between adjacent second pad portions (3212b) and adjacent third wiring portions (3231) may be different. Specifically, the spacing between adjacent second pad portions (3212b) is greater than the spacing between adjacent third wiring portions (3231).

[0234] The depth (D1-2) of the first groove (G1) and the depth (D2-1) of the second groove (G2) may be different. In detail, the depth (D1-2) of the first groove (G1) may be greater than the depth (D2-1) of the second groove (G2).

[0235] That is, since the spacing of the second pad portions (3212b) is greater than the spacing of the third wiring portions (3231), the etching time for removing the buffer layer (3205) may be prolonged. Accordingly, the depth (D1-2) of the first groove (G1) becomes greater than the depth (D2-1) of the second groove (G2), and the buffer layer between adjacent second pad portions (3212b) can be (almost) removed.

[0236] Referring to Fig. 38, the 2-1 wiring portion (3221a) and the 4th pad portion (3222b) may face each other. Specifically, the 2-1 wiring portion (3221a) may be arranged on the 1st surface (1S), and the 4th pad portion (3222b) may be arranged on the 2nd surface (2S).

[0237] The spacing between adjacent 2-1 wiring portions (3221a) and the spacing between adjacent 4th pad portions (3222b) may be different. Specifically, the spacing between adjacent 2-1 wiring portions (3221a) is greater than the spacing between adjacent 4th pad portions (3222b).

[0238] The depth (D1-1) of the first groove (G1) and the depth (D2-2) of the second groove (G2) may be different. In detail, the depth (D1-1) of the first groove (G1) may be greater than the depth (D2-2) of the second groove (G2).

[0239] That is, since the spacing of the 2-1 wiring portion (3221a) is greater than the spacing of the 4th pad portion (3222b), the etching time for removing the buffer layer (3205) may be prolonged. Accordingly, the depth (D1-1) of the first groove (G1) becomes greater than the depth (D2-2) of the second groove (G2), and the buffer layer between adjacent 2-1 wiring portions (3221a) can be (almost) removed.

[0240] Referring to Fig. 39, the first pad portion (3212a) and the dummy pattern (3250) may face each other. Specifically, the first pad portion (3212a) may be arranged on the first surface (1S), and the dummy pattern (3250) may face each other on the second surface (2S).

[0241] The above dummy pattern (3250) is placed on the second surface (2S) corresponding to the chip mounting area. Accordingly, the strength of the chip mounting area can be improved by the dummy pattern (3250). In addition, the dummy pattern (3250) can serve as a heat dissipation pattern.

[0242] The spacing between adjacent first pad portions (3212a) and the spacing between adjacent dummy patterns (3250) may be different. Specifically, the spacing between adjacent dummy patterns (3250) may be greater than the spacing between adjacent first pad portions (3212a).

[0243] The depth of the first groove (G1) and the depth of the second groove (G2) may be the same or different. For example, the depth of the first groove (G1) may be greater than the depth of the second groove (G2). Alternatively, the depth of the first groove (G1) may be less than the depth of the second groove (G2). Alternatively, the depth of the first groove (G1) and the depth of the second groove (G2) may be the same or similar.

[0244] The above dummy patterns (3250) are not connected to the chip, circuit board, and display panel. Accordingly, even if adjacent dummy patterns (3250) are electrically connected, the driving characteristics of the flexible circuit board are not affected. Accordingly, a groove may not be formed between adjacent dummy patterns (3250). Alternatively, a buffer layer may remain between adjacent dummy patterns. Alternatively, the buffer layer may be (almost) removed between adjacent dummy patterns.

[0245] Referring to FIGS. 40 to 43, a metal pattern (3260) may be arranged on the non-effective area (UA). The metal pattern (3260) is arranged adjacent to the sprocket hole (SH). Specifically, the metal pattern (3260) is arranged spaced apart from the sprocket hole (SH). For example, as shown in FIG. 40, the metal pattern (3260) extends in the direction in which the sprocket hole (SH) extends.

[0246] The flexible circuit board can be transported by a roller by the metal pattern (3260). That is, the metal pattern (3260) may be a transport pattern. The metal pattern (3260) may include the same material as the circuit pattern. In detail, the metal pattern (3260) may be formed simultaneously with the formation of the circuit patterns.

[0247] The metal pattern (3260) may be disposed on at least one surface of the substrate (3100). For example, as shown in FIG. 41, the metal pattern (3260) may be disposed on the first surface (1S) and the second surface (2S). The metal pattern may include a first metal pattern (3261) and a second metal pattern (3262). The first metal pattern (3261) is disposed on the first surface (1S). The second metal pattern (3262) is disposed on the second surface (2S).

[0248] The first metal pattern (3261) and the second metal pattern (3262) may not overlap in the thickness direction of the substrate. Accordingly, wear of the metal pattern by the transport roller may be reduced.

[0249] The distance between the sprocket hole (SH) and the metal pattern (3260) may be smaller than the width of the metal pattern (3260). Accordingly, the sprocket hole (SH) portion may be prevented from being torn by the transport roller. That is, if the sprocket hole (SH) and the metal pattern (3260) are attached, the metal pattern may be worn by the transport roller. Accordingly, foreign substances generated from the worn metal pattern may penetrate into the effective area during the process. Accordingly, a defect in the circuit pattern may occur.

[0250] A groove may be formed between adjacent metal patterns (3260). For example, a first groove (G1) is formed between adjacent first metal patterns (3261). In addition, a second groove (G2) is formed between adjacent second metal patterns (3262). Accordingly, the buffer layer between adjacent metal patterns (3260) can be (almost) removed. Accordingly, the adjacent metal patterns (3260) can be prevented from being connected. Accordingly, the flexible circuit board can be easily rolled or unrolled by the sprocket hole (SH) and the metal pattern (3260).

[0251] As shown in Fig. 42, the metal pattern (3260) may be arranged to surround the sprocket hole (SH). In addition, as shown in Fig. 43, the metal pattern (3260) may be arranged on the first surface (1S) or the second surface (2S).

[0252] A flexible circuit board according to an embodiment includes a substrate and a circuit pattern on the substrate. The substrate includes a groove. The groove is disposed on first and second surfaces of the substrate. The groove is disposed between adjacent circuit patterns. Accordingly, when forming the circuit patterns, any metal layer that may remain between the circuit patterns can be removed.

[0253] Therefore, short-circuiting of adjacent circuit patterns can be prevented. Consequently, the reliability and operating characteristics of the flexible circuit board are improved.

[0254] Additionally, the grooves arranged on the first side and the second side may partially overlap in the thickness direction of the substrate. Alternatively, the grooves arranged on the first side and the second side may not overlap in the thickness direction of the substrate.

[0255] Accordingly, the difference in thickness between the overlapping region of the grooves and other regions is reduced. Consequently, the strength of the substrate is enhanced. Furthermore, bending of the flexible circuit board in specific regions of the substrate can be prevented.

[0256] Additionally, the depth of the groove can vary depending on the spacing between adjacent circuit patterns. Specifically, the groove depth can be large in areas where the spacing between circuit patterns is large. Accordingly, even in areas where the spacing between adjacent circuit patterns is large, the remaining metal layer can be largely removed.

[0257] Meanwhile, the previous description focused on a flexible circuit board. Furthermore, a fingerprint sensor can be mounted on the aforementioned flexible circuit board and provided as a fingerprint sensor package.

[0258]

[0259] FIG. 44 is a top view of a fingerprint sensor module according to one embodiment, and FIG. 45 is a drawing illustrating a fingerprint recognition card according to one embodiment.

[0260] Referring to Fig. 44, the flexible circuit board described above can be provided as a fingerprint sensor module. That is, a chip (C) is placed on the flexible circuit board. The chip (C) is placed on the chip mounting area (CHA). The terminals of the chip (C) are connected to the pad portions of the wiring electrode. The flexible circuit board is cut along the cutting line (CL). Accordingly, the ineffective area is removed. Accordingly, the fingerprint sensor module (2000) is manufactured.

[0261] Referring to FIG. 45, the fingerprint recognition card (4000) includes a card body (4100), a circuit board (4200), a chip (4300), a microcontroller unit (MCU, 4400), a connection circuit pattern (4350), a fingerprint sensor package (4500), an antenna (4600), and a battery (4700).

[0262] The circuit board (4200) is accommodated in the card body (4100). In detail, the card body (4100) includes an opening (G). The circuit board (4200) is accommodated in the opening (G). Accordingly, the circuit board (4200) is inserted into and bonded to the opening (G).

[0263] Accordingly, the contact surface of the circuit board (4200) is exposed to the outside of the IC card. The circuit board (4200) mounts an IC chip. The connection circuit pattern (4350) electrically connects the chip (4300) and the micro control unit (4400).

[0264] The above fingerprint recognition card includes the fingerprint sensor module (4500). The fingerprint sensor module (4500) recognizes the user's fingerprint. It also matches the fingerprint with the fingerprint information stored in the chip (4300).

[0265] The above chip (4300) stores fingerprint information of a predetermined user. The fingerprint recognized by the fingerprint sensor module (4500) is matched with the fingerprint information stored in the chip (4300).

[0266] For example, when a user's finger comes into contact with the fingerprint sensor module (4500), the micro control unit (4300) is powered by the battery (4700). The fingerprint sensor module (4500) is powered by the micro control unit (4300). As a result, the fingerprint sensor module (4500) is driven.

[0267] Next, the microcontrol unit (4300) receives fingerprint information recognized by the fingerprint sensor module (4500). In addition, it performs an authentication process for the recognized fingerprint information.

[0268] If the recognized fingerprint matches the fingerprint information stored in the chip (4300), the circuit board (4200) is activated. Accordingly, the fingerprint recognition card is activated.

[0269] If the recognized fingerprint does not match the fingerprint information stored in the chip (4300), the circuit board (4200) is not activated. Accordingly, the fingerprint recognition card is not activated.

[0270] The fingerprint recognition card may include an antenna (4600). Accordingly, the fingerprint recognition card may operate as a contactless card. However, the embodiment is not limited thereto. The fingerprint recognition card may not include an antenna (4600). Accordingly, the fingerprint recognition card may operate as a contact card.

[0271]

[0272] FIG. 46 is a drawing for explaining the connection of a COF module and other members according to an embodiment, and FIGS. 47 to 49 are drawings for an electronic device including a flexible circuit board according to an embodiment.

[0273] Referring to FIG. 46, a flexible circuit board according to an embodiment can be cut along a cutting line (CL), and a chip placed on the flexible circuit board can be a driver IC, through which a COF module (2000) can be manufactured.

[0274] One end of the COF module (2000) may be connected to the display panel (6000), and the other end opposite to the one end may be connected to the circuit board (5000). For example, the display panel (6000) may be disposed on one surface of the COF module (2000), and the circuit board (5000) may be disposed on the other surface opposite to the one surface of the COF module (2000). However, the embodiment is not limited thereto, and the display panel (6000) and the circuit board (5000) may be disposed on the same surface of the COF module (2000).

[0275] Since the COF module (2000) includes a flexible substrate, it can have both a rigid shape and a bent shape between the display panel (3000) and the circuit board (5000). That is, the COF module (2000) can include a bending area (BA).

[0276] The COF module (2000) can be connected in a curved manner between the display panel (6000) and the circuit board (5000), which are arranged to face each other, thereby reducing the thickness of the electronic device. Furthermore, the degree of freedom in design can be improved. Furthermore, the COF module (2000) including the flexible substrate does not have wires that break even when bent. Accordingly, the reliability of the electronic device including the COF module can be improved.

[0277] Since the above COF module is flexible, it can be used in various electronic devices.

[0278] For example, referring to FIG. 47, the COF module may be incorporated into a flexible touch window. Accordingly, a touch device device including the COF module may be a flexible touch device. Accordingly, the touch device device may be bent or folded by a user's hand. Such a flexible touch window may be applied to wearable touch devices, etc.

[0279] Referring to Fig. 48, the COF module can be included in various wearable touch devices including curved displays. Accordingly, an electronic device including the COF module can be slimmed down or made lighter.

[0280] Referring to Fig. 49, the COF module can be used in various electronic devices having a display portion, such as a TV, monitor, or laptop. In this case, the COF module can also be used in an electronic device having a curved display portion.

[0281] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0282] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A substrate comprising a first side and a second side opposite to the first side; A first sensing electrode disposed on the first surface and extending in the first direction A second sensing electrode disposed on the second surface and extending in a second direction different from the first direction; a first wiring electrode connected to the first sensing electrode; and including a second wiring electrode connected to the second sensing electrode; The first surface above includes a chip mounting area, The second surface includes an overlapping area overlapping the chip mounting area along the thickness direction of the substrate, It includes a first dummy electrode arranged in the chip mounting area and a second dummy electrode arranged in the overlapping area, A flexible circuit board, wherein at least one of the first dummy electrode and the second dummy electrode comprises a plurality of dummy electrodes extending in a plurality of different directions.

2. In paragraph 1, The first dummy electrode includes a plurality of first open areas, The above first dummy electrode includes a 1-1 dummy electrode and a 1-2 dummy electrode, The above 1-1 dummy electrode extends in the first direction and the second direction, The above first and second dummy electrodes are flexible circuit boards extending in the first direction.

3. In paragraph 2, The above 1-1 dummy electrode First dummy pattern below; Second dummy pattern on top; and Including a third dummy pattern connecting the first dummy pattern and the second dummy pattern, A flexible circuit board in which the first and second dummy electrodes are placed between the first open areas adjacent to each other.

4. In paragraph 1, A flexible circuit board comprising an open portion formed in at least one corner region of the dummy electrode.

5. In paragraph 3, The second dummy electrode includes a plurality of second open areas, The second dummy electrode includes a 2-1 dummy electrode and a 2-2 dummy electrode, The above 2-1 dummy electrode extends in the first direction and the second direction, The above 2-2 dummy electrode is a flexible circuit board extending in the first direction.

6. In paragraph 5, The above 2-1 dummy electrode The fourth dummy pattern below; The fifth dummy pattern on top; and Including a sixth dummy pattern on the side connecting the fourth dummy pattern and the fifth dummy pattern, The above 2-2 dummy electrode is a flexible circuit board arranged between the second open areas adjacent to each other.

7. In paragraph 6, Further comprising a via penetrating the first side and the second side of the above-described substrate, The above via overlaps the first dummy pattern and the fourth dummy pattern along the thickness direction of the substrate, A flexible circuit board in which the first dummy electrode and the second dummy electrode are connected through the via.

8. In paragraph 5, The second dummy electrode further includes a plurality of third open areas, The second dummy electrode further includes a second-third dummy electrode between the third open areas adjacent to each other, A flexible circuit board in which the second dummy electrode is connected to a fourth dummy electrode arranged in a non-overlapping area excluding the overlapping area by the second-third dummy electrode.

9. In paragraph 6, The first open area includes outermost first open areas facing in the second direction, The second open area includes outermost second open areas facing in the second direction, The width of the first outermost open area is smaller than the width of the other first open areas, A flexible circuit board wherein the length of the outermost second open area is shorter than the length of the other second open areas.

10. In paragraph 6, The shape of at least one of the first open areas is different from the shape of the other first open areas, A flexible circuit board wherein the shape of at least one of the second open areas is different from the shape of the other first open areas.

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