Deep learning accelerator chip parametric design method and system

Abstract

Disclosed in the present invention are a deep learning accelerator chip parametric design method and system. The method comprises the following steps: S1, initializing an accelerator chip design condition, the accelerator chip design condition comprising an accelerator chip architecture design space and load characteristic data; S2, on the basis of the accelerator chip architecture design space and the load characteristic data, obtaining optimal design parameters of an accelerator chip architecture; and S3, on the basis of the optimal design parameters of the accelerator chip architecture, executing accelerator architecture design. By means of the parametric method for an automatic search for deep learning load characteristics, the present invention optimizes the accelerator design, reduces the time cost and the labor cost for the accelerator design, and solves a series of problems, such as long design cycles, high costs and difficulty in making adaptive adjustments according to application characteristics, in existing accelerator chip design.

Description

A parametric design method and system for deep learning accelerator chips Technical Field

[0001] The present invention relates to the field of computer and electronic technologies, in particular to the field of parametric design of deep learning accelerator chips, and specifically to a parametric design method and system for deep learning accelerator chips. Background Art

[0002] In recent years, deep learning algorithms such as recurrent neural networks and convolutional neural networks have demonstrated increasing influence in a wide range of fields, with applications in all aspects of social life. With the continuous development of deep learning algorithms, especially the introduction and application of large models, the demand for hardware computing power has gradually increased, posing new challenges to chip design.

[0003] Currently, there are three main types of chips that can be used for deep learning algorithm calculations: (1) Central Processing Unit (CPU) chips. General-purpose processor chips are instruction-driven and can execute various applications through software programming. They can handle tasks in most scenarios and have very high flexibility. However, when processing large-scale parallel computing-intensive tasks in complex deep learning algorithms, they have problems such as excessive power consumption and insufficient performance, and low energy efficiency. (2) Graphics Processing Unit (GPU) chips. Graphics processor chips contain specialized graphics and image acceleration components and computing acceleration components that can be used for large-scale simple parallel computing tasks. In addition to being used for specialized graphics and image computing, they can also support highly parallel artificial intelligence algorithm acceleration. This type of chip undertakes large-scale parallel computing-intensive tasks sent by general-purpose processors, achieving high computing throughput while also consuming very high power and still having a low energy efficiency. (3) Deep learning-specific accelerator chips. Deep learning-specific accelerator chips are hardware circuits specially designed to improve the performance of deep learning algorithms. They can achieve very high energy efficiency in specific application scenarios and have become a hot topic of research in academia and industry.

[0004] Dedicated deep learning accelerator chips can be implemented using application-specific integrated circuits (ASICs). Specifically designed and tape-out hardware circuits are tailored to specific applications. These chips offer excellent performance and high energy efficiency, but support limited application scenarios and lack flexibility. Alternatively, they can be implemented using field-programmable gate arrays (FPGAs). Depending on the algorithm being used, the hardware can be modified internally, achieving performance similar to that of an ASIC, while also offering high energy efficiency and flexibility. Consequently, academia and industry are focusing their attention on reconfigurable deep learning accelerators. FPGA-based deep learning accelerator chips can be configured with pre-designed parameters to construct a specific chip logic structure to perform specific tasks. When the chip's task undergoes significant changes, the parameter configuration can be modified to reconstruct the chip logic structure adapted to the new task. This reconfigurable chip design model has been gradually applied and implemented in the field of deep learning accelerators. However, current deep learning accelerator chip design typically relies on extensive manual tuning to achieve optimal chip design parameters, which is time-consuming and costly. Furthermore, manual tuning makes it difficult to verify whether there is room for improvement in chip performance.

[0005] In summary, deep learning accelerator chips are increasingly receiving attention from academia and industry. However, the parameterized design of existing deep learning accelerator chips is just getting started and cannot meet the demand for quickly outputting accelerator chip designs based on application characteristics.

[0006] Summary of the Invention

[0007] In response to the shortcomings of the existing technology, the present invention proposes a parametric design method and system for deep learning accelerator chips. Its purpose is to optimize the accelerator design through a parametric method that automatically searches for deep learning load characteristics, reduce the time and labor costs of accelerator design, and solve a series of problems such as the long design cycle, high cost, and difficulty in adaptive adjustment according to application characteristics of existing accelerator chips.

[0008] To achieve the above object, the present invention provides the following solutions:

[0009] A parameterized design method for a deep learning accelerator chip includes the following steps:

[0010] S1: Initializing accelerator chip design conditions, wherein the accelerator chip design conditions include: accelerator chip architecture design space and load characteristic data;

[0011] S2: Based on the accelerator chip architecture design space and load characteristic data, the optimal design parameters of the accelerator chip architecture are obtained;

[0012] S3: Complete the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture.

[0013] Preferably, in S1, the method for initializing the accelerator chip design conditions includes:

[0014] S101: Pre-analyze the deep learning application load characteristics to obtain load characteristic data;

[0015] S102: Pre-designing a deep learning accelerator chip infrastructure template based on the load characteristic data, parameterizing the tunable hardware architecture, and obtaining an accelerator chip architecture design space;

[0016] S103: Initializing design parameter weights based on the accelerator chip architecture design space.

[0017] Preferably, in S2, the method for obtaining the optimized design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and the load characteristic data includes:

[0018] S201: Select a set of design parameter samples based on the accelerator chip architecture design space;

[0019] S202: Based on the design parameter sample, using an evaluation component, evaluate the accelerator chip design parameters and load characteristic data to obtain an evaluation component calculation score;

[0020] S203: Calculating scores based on the evaluation components and calculating weight gradients of design parameters;

[0021] S204: Based on the weight gradient and the optimization rate, modify the weights of corresponding parameters in the design space;

[0022] S205: Iteratively optimize S201 to S204 to obtain optimized design parameters of the accelerator chip architecture.

[0023] Preferably, in S202, the method of using an evaluation component to evaluate the accelerator chip design parameters and load characteristic data based on the design parameter sample to obtain a calculation score of the evaluation component includes:

[0024] S202-1: Calculate the energy consumption of the accelerator chip using the energy evaluation component;

[0025] S202-2: Calculating the accelerator chip operation time using a delay evaluation component based on the accelerator chip operation energy consumption;

[0026] S202-3: Based on the accelerator chip operation time and the preset weight ratio, comprehensively calculate the performance score of the accelerator chip design parameters, that is, the evaluation component calculation score.

[0027] Preferably, in S3, the method for completing the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture includes:

[0028] By optimizing the accelerator chip design parameters and making adjustments on the preset accelerator chip architecture template, the computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic are maximized to improve the performance of the accelerator chip when calculating the input deep learning application load, and finally complete the parametric design of the deep learning accelerator chip.

[0029] The present invention also provides a parameterized design system for a deep learning accelerator chip, comprising: an initialization module, an optimization module, and a design module;

[0030] The initialization module is used to initialize the accelerator chip design conditions, wherein the accelerator chip design conditions include: accelerator chip architecture design space and load characteristic data;

[0031] The optimization module is used to obtain the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and load characteristic data;

[0032] The design module is used to complete the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture.

[0033] Preferably, in the initialization module, the process of initializing the accelerator chip design conditions includes:

[0034] S101: Pre-analyze the deep learning application load characteristics to obtain load characteristic data;

[0035] S102: Pre-designing a deep learning accelerator chip infrastructure template based on the load characteristic data, parameterizing the tunable hardware architecture, and obtaining an accelerator chip architecture design space;

[0036] S103: Initializing design parameter weights based on the accelerator chip architecture design space.

[0037] Preferably, in the optimization module, the process of obtaining the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and the load characteristic data includes:

[0038] S201: Select a set of design parameter samples based on the accelerator chip architecture design space;

[0039] S202: Based on the design parameter sample, using an evaluation component, evaluate the accelerator chip design parameters and load characteristic data to obtain an evaluation component calculation score;

[0040] S203: Calculating scores based on the evaluation components and calculating weight gradients of design parameters;

[0041] S204: Based on the weight gradient and the optimization rate, modify the weights of corresponding parameters in the design space;

[0042] S205: Iteratively optimize S201 to S204 to obtain optimized design parameters of the accelerator chip architecture.

[0043] Preferably, in S202, the process of evaluating the accelerator chip design parameters and load characteristic data using an evaluation component based on the design parameter sample to obtain a calculation score of the evaluation component includes:

[0044] S202-1: Calculate the energy consumption of the accelerator chip using the energy evaluation component;

[0045] S202-2: Calculating the accelerator chip operation time using a delay evaluation component based on the accelerator chip operation energy consumption;

[0046] S202-3: Based on the accelerator chip operation time and the preset weight ratio, comprehensively calculate the performance score of the accelerator chip design parameters, that is, the evaluation component calculation score.

[0047] Preferably, in the design module, the process of completing the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture includes:

[0048] By optimizing the accelerator chip design parameters and making adjustments on the preset accelerator chip architecture template, the computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic are maximized to improve the performance of the accelerator chip when calculating the input deep learning application load, and finally complete the parametric design of the deep learning accelerator chip.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] The present invention proposes a parametric design method and system for a deep learning accelerator chip. The method parameterizes the tunable portion of the accelerator chip architecture to obtain a design parameter space. Differentiable sampling and gradient descent methods are then used to search for optimal design parameters within the design parameter space. The parametric design of the deep learning accelerator chip is then completed based on these design parameters. The present invention can automatically search for the optimal accelerator design based on deep learning load characteristics, significantly reducing the time and labor costs of accelerator design. It can also evaluate deep learning accelerator chips, ensuring that the performance of the searched design architecture meets certain standards. The core algorithm is highly scalable and can be applied to the parametric design of large-scale, industrial-grade deep learning accelerator chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] FIG1 is a schematic diagram showing the implementation process of the parameterized design method for a deep learning accelerator chip;

[0053] FIG2 is a schematic diagram showing the implementation process of initializing chip design conditions for parameterized design of a deep learning accelerator chip;

[0054] FIG3 is a schematic diagram showing a specific implementation process of a deep learning accelerator chip design parameter search component;

[0055] FIG4 is a schematic diagram showing a specific implementation process of a deep learning accelerator chip design parameter evaluation component;

[0056] FIG5( a ) is a schematic diagram showing the energy consumption evaluation process of the accelerator architecture by the energy evaluation component;

[0057] FIG5( b ) is a schematic diagram showing the process of delay evaluation of the accelerator architecture by the delay evaluation component;

[0058] FIG6 is a schematic diagram showing a specific implementation device of the parameterized design method for a deep learning accelerator chip. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] Example 1

[0062] The present invention proposes a parameterized design method for a deep learning accelerator chip. The specific implementation process includes the following steps (as shown in Figure 1):

[0063] Step S1. Initialize the accelerator chip design conditions.

[0064] Step S2: Based on the accelerator chip architecture design space and load characteristic data, search and obtain the optimal design parameters.

[0065] Step S3: Complete the accelerator architecture design based on the accelerator chip architecture design parameters.

[0066] In this embodiment, step S1 initializes the accelerator chip design conditions, and the specific implementation process is as follows (as shown in FIG2 ):

[0067] S101: Pre-analyze the deep learning application load characteristics to obtain load characteristic data, including:

[0068] 1) Number of layers in the deep learning model;

[0069] 2) Layer type;

[0070] 3) Layer size.

[0071] The layer size includes: input feature width, output feature width, convolution kernel size, number of channels, number of convolution kernels, step size, padding length, and number of bits after quantization.

[0072] S102: Pre-design a deep learning accelerator chip infrastructure template, parameterize the tunable hardware architecture, and obtain the accelerator chip architecture design space;

[0073] 1) Computational array size, computational unit interconnection method, global register capacity, computational unit local register size, computational unit processing bit width, and computational unit additional computational logic;

[0074] 2) Assign equal weights to all parameters before the search begins, indicating that all parameters have equal priority in the current search;

[0075] S103: Initializing the design parameter weights. Initializing the weights of all design parameters to equal values ​​means that all parameters have equal priorities before the search begins.

[0076] In this embodiment, step S2 searches for optimal design parameters based on the accelerator chip architecture design space and load characteristic data. The specific implementation process is as follows (as shown in FIG3 ):

[0077] S201: Based on the parameterized design space of the accelerator chip architecture, a set of design parameter samples is selected. Based on the weights of each parameter in the parameterized design space of the accelerator chip architecture, a differentiable sampling method is used to facilitate the subsequent calculation of gradient optimization parameter weights. This ensures that high-weight parameters are more likely to be sampled and maintains a certain degree of randomness. The closer the parameter weights, the greater the randomness. This feature can prevent the search results from falling into local optimality. The specific implementation method is as follows:

[0078] Each parameter in the accelerator chip architecture parameterized design space is assigned a weight in step S1. Based on the weight of each parameter, a set of parameter samples is selected using the Gumbel sampling algorithm. The Gumbel function is defined as follows:

[0079] Here, x is the value of a random variable, and μ and β are parameters of the random distribution. The Gumbel function's characteristics make the sampling process differentiable, facilitating the subsequent calculation of gradient optimization parameter weights. Furthermore, the sampling results are very close to those of argmax sampling. Furthermore, Gumbel sampling retains a certain amount of random fluctuation compared to argmax sampling. The closer the parameter weights are, the greater the randomness. This characteristic prevents search results from falling into local optima.

[0080] S202: Evaluate the accelerator chip design parameters and load characteristic data using an evaluation component. The evaluation component includes an energy evaluation component and a delay evaluation component. The specific evaluation process is as follows (as shown in FIG4 ):

[0081] Step 202-1. The energy evaluation component (as shown in Figure 5(a)) calculates the runtime computing and memory access energy consumption for each network layer based on the accelerator chip design parameters and the deep learning application load characteristic data. The memory access energy consumption includes multiple levels such as registers, cache, and main memory. Finally, the energy consumption of all network layers is accumulated to obtain the energy consumption of the entire network.

[0082] An energy assessment component is used to segment the accelerator architecture and calculate the energy consumption of the required operation steps. Specifically, the inputs to the energy assessment component include: accelerator chip architecture parameters, deep learning load characteristic data, and an energy reference table. Accelerator chip architecture parameters include: computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic. Load characteristic data includes: the number of deep learning model layers, layer type, and layer size, including: input feature width, output feature width, convolution kernel size, number of channels, number of convolution kernels, stride, padding length, and number of bits after quantization. The energy reference table provides an energy reference for each operation. By calculating the number of operations in the current network layer and searching the energy reference, the computational energy consumption of this layer can be obtained. Memory access energy consumption calculation includes register energy consumption. The specific implementation method uses the number of processing unit calculations to represent the number of register accesses, and distinguishes between reads and writes when calculating energy consumption. Cache energy consumption and main memory energy consumption must be considered separately when calculating the energy consumption of the required operation steps. Cache energy consumption, based on the amount of network layer weight data and the cache size in the accelerator chip design parameters, additionally calculates the access pattern and number of accesses, and calculates the energy consumption based on this; main memory energy consumption, in the specific implementation method, according to the network layer weights and input data, only one read from the memory is needed for calculation.

[0083] Step 202-2. The latency evaluation component (as shown in Figure 5(b)) calculates the runtime computation and memory access latency for each network layer based on the accelerator chip design parameters and the deep learning application load characteristic data. The memory access latency includes multiple levels such as registers, cache, and main memory. Finally, the latency calculated by all network layers is accumulated to obtain the computation latency of the entire network.

[0084] The latency evaluation component uses a latency parameter table to calculate the runtime of each network layer. Specifically, the latency evaluation component's inputs include accelerator chip architecture parameters, deep learning load signature data, and a latency reference table. Accelerator chip architecture parameters include: compute array size, compute unit interconnection, global register capacity, compute unit local register size, compute unit processing bit width, and compute unit additional computational logic. Load signature data includes: the number of deep learning model layers, layer type, and layer size, including: input feature width, output feature width, convolution kernel size, number of channels, number of convolution kernels, stride, padding length, and number of bits after quantization. The latency reference table relies on the physical process used during chip fabrication and the implementation of components such as compute and memory access. It must be manually specified and remains unchanged throughout the accelerator chip design parameter search process. Latency calculation includes: memory access delay, which is calculated based on the cache strategy and storage structure space at each level in the design parameters, as well as the data volume of the network layer, to obtain the hit rate of each level of storage structure, and the memory access delay of the network layer is obtained based on the access delay of different storage structures; calculation delay, in each round of calculation, the time length of different calculations is obtained by looking up the delay reference table. In the specific implementation method, the longest calculation delay in each calculation batch is superimposed as the network layer calculation delay.

[0085] Step 202-3. Based on the preset weight ratios, a comprehensive performance score for the accelerator chip design parameters is calculated, i.e., the evaluation component calculation score. Considering that both energy consumption and latency are negatively correlated with the degree of optimization, deep learning accelerator chip designs with lower energy consumption and latency are preferred. In this specific implementation, the product of energy consumption and latency, i.e., the energy-delay product, is used as the design parameter score, with design parameters with lower scores being preferred.

[0086] S203: Based on the score calculated by the evaluation component, the gradient of the design parameter weight is calculated. In the specific implementation method, the design parameter score calculated by the evaluation component is used as the starting point. The back propagation algorithm is used to gradually calculate the partial differentials of the score of each calculated data during the operation of the evaluation component. Finally, the gradient of the score corresponding to the weight of each design parameter sampled in step S201 is obtained by reverse deduction.

[0087] S204: Based on the weight gradient and optimization rate, the weights of the corresponding parameters in the design space are corrected. In the specific implementation method, for each design parameter sampled in step S201, a corresponding gradient value is calculated in step S203. The weight of the above design parameter is subtracted from the product of the gradient value and the preset weight optimization rate to obtain the weight correction.

[0088] S205: Iterative Optimization. In a specific implementation, this involves returning to step S201, re-performing Gumbel sampling using the design parameter space weights modified in step S204, and completing subsequent steps. As the iterations proceed, the weights of parameters that are more suitable for the deep learning application workload analyzed in step S1 will increase, while those that are less suitable will decrease. The iterative optimization process ends when the searched design parameters meet the preset performance requirements or when the maximum number of iterations has been reached.

[0089] In this embodiment, step S3 completes the accelerator architecture design based on the accelerator chip architecture design parameters. The specific implementation process is as follows:

[0090] Using the optimized accelerator chip design parameters obtained through the search, adjustments are made to the preset accelerator chip architecture template, ensuring that all searched parameters, including the computing array size, computing unit interconnection structure, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computational logic, maximize the accelerator chip's performance when computing deep learning application loads. The final accelerator chip can be implemented through various methods, including FPGAs and simulators, ultimately completing the parameterized design of a deep learning accelerator chip.

[0091] Example 2

[0092] The present invention also provides a parameterized design system for a deep learning accelerator chip, comprising: an initialization module, an optimization module, and a design module;

[0093] The initialization module is used to initialize the accelerator chip design conditions, wherein the accelerator chip design conditions include: accelerator chip architecture design space and load characteristic data;

[0094] The optimization module is used to obtain the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and load characteristic data;

[0095] The design module is used to complete the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture.

[0096] In this embodiment, in the initialization module, the process of initializing the accelerator chip design conditions includes:

[0097] S101: Pre-analyze the deep learning application load characteristics to obtain load characteristic data;

[0098] S102: Based on the load characteristic data, a deep learning accelerator chip infrastructure template is pre-designed, and the tunable hardware architecture is parameterized to obtain the accelerator chip architecture design space;

[0099] S103: Initializing design parameter weights based on the accelerator chip architecture design space.

[0100] In this embodiment, in the optimization module, the process of obtaining the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and load characteristic data includes:

[0101] S201: Selecting a set of design parameter samples based on the parameterized design space of the accelerator chip architecture;

[0102] S202: Based on the design parameter sample, using the evaluation component, evaluate the accelerator chip design parameters and load characteristic data to obtain an evaluation component calculation score;

[0103] S203: Calculating scores based on the evaluation components and calculating weight gradients of design parameters;

[0104] S204: Based on the weight gradient and the optimization rate, modify the weights of the corresponding parameters in the design space;

[0105] S205: Iteratively optimize S201 to S204 to obtain the optimal design parameters of the accelerator chip architecture.

[0106] In this embodiment, in S202, the process of evaluating the accelerator chip design parameters and load characteristic data using the evaluation component based on the design parameter sample to obtain the evaluation component calculation score includes:

[0107] S202-1: Calculate the energy consumption of the accelerator chip using the energy evaluation component;

[0108] S202-2: Calculating the accelerator chip operation time using a delay evaluation component based on the accelerator chip operation energy consumption;

[0109] S202-3: Based on the running time of the accelerator chip and the preset weight ratio, comprehensively calculate the performance score of the accelerator chip design parameters.

[0110] In this embodiment, in the design module, the process of completing the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture includes:

[0111] By optimizing the accelerator chip design parameters and making adjustments on the preset accelerator chip architecture template, the computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic are maximized to improve the performance of the accelerator chip when calculating the input deep learning application load, and finally complete the parametric design of the deep learning accelerator chip.

[0112] Example 3

[0113] The present invention also provides a specific implementation device of the parameterized design method of a deep learning accelerator chip (as shown in Figure 6), which includes a search component and an evaluation component.

[0114] The search component is used to search for deep learning accelerator architecture design parameters. Its input is the deep learning accelerator architecture design space, and its output is the optimal accelerator design parameters.

[0115] The search component includes the design parameter sampling component and the iteration control component:

[0116] A design parameter sampling component, configured to select a design parameter sample from the deep learning accelerator architecture design space, wherein the input of the design parameter sampling component is the deep learning accelerator architecture design space, and the output is a set of accelerator design parameters;

[0117] The iterative control component is used to control the cyclic iterative process in the operation of the search component. The input is the accelerator parameter performance score. If the score shows that the accelerator performance does not meet the standard, the iterative control component controls the sampling component to sample again and start a new round of iteration; if the score shows that the accelerator performance meets the standard, it means that the search has obtained the optimal design parameters, then the iterative component controls the search component to output the current design parameters.

[0118] The evaluation component is used to perform performance evaluation on the deep learning accelerator design parameters output by the design parameter sampling component. Its input is the accelerator design parameters and deep learning application load characteristic data. The output is the accelerator parameter performance score, which is used as the input of the iterative control component.

[0119] The evaluation components include energy evaluation component, delay evaluation component and comprehensive evaluation component:

[0120] An energy evaluation component is used to calculate the energy consumption of the accelerator operation. The input is the aforementioned accelerator design parameters and deep learning application load characteristic data. The output is the energy consumption data calculated based on the input data.

[0121] The latency evaluation component is used to calculate the accelerator runtime latency. The input is the aforementioned accelerator design parameters and deep learning application load characteristic data. The output is the latency data calculated based on the input data.

[0122] The comprehensive evaluation component is used to calculate the comprehensive performance score of the accelerator design parameters. The input is the energy consumption data calculated by the energy evaluation component and the delay data calculated by the delay evaluation component. The output is the accelerator parameter performance score, which is used as the input of the aforementioned iterative control component.

[0123] The present invention provides a parametric design method for a deep learning accelerator chip. The method parameterizes the tunable portion of the accelerator chip architecture to obtain a design parameter space. The method uses differentiable sampling and gradient descent methods to search for optimal design parameters in the design parameter space. The parametric design of the deep learning accelerator chip is completed based on the design parameters. The present invention can automatically search for the optimal accelerator design based on the deep learning load characteristics, greatly reducing the time and labor costs of accelerator design; it can complete the evaluation of deep learning accelerator chips and ensure that the performance of the searched design architecture meets certain standards; the method has good scalability and can be applied to the parametric design of large-scale industrial-grade deep learning accelerator chips.

[0124] The deep learning accelerator chip parameterized design search component proposed in the present invention can flexibly search for the optimal design parameters in a given design parameter space based on the input deep learning application load, which can effectively reduce the time and labor costs of tuning during the accelerator chip design process.

[0125] The deep learning accelerator chip design parameter evaluation component proposed in the present invention can calculate the design parameter score based on the accelerator design parameters and deep learning load characteristic data, quickly evaluate the optimization degree of the current design parameters, and effectively point out the direction of the next search by calculating the gradient.

[0126] Based on this process, the present invention can develop a specific parameterized design method for a deep learning accelerator chip.

[0127] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A parameterized design method for a deep learning accelerator chip, characterized in that: The following steps are involved: S1: Initializing accelerator chip design conditions, wherein the accelerator chip design conditions include: accelerator chip architecture design space and load characteristic data; S2: Based on the accelerator chip architecture design space and load characteristic data, the optimal design parameters of the accelerator chip architecture are obtained; S3: Complete the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture.

2. The parameterized design method of a deep learning accelerator chip according to claim 1, characterized in that: In S1, the method for initializing the accelerator chip design conditions includes: S101: pre-analyze the deep learning application load characteristics to obtain load characteristic data; S102: Based on the load characteristic data, pre-design a deep learning accelerator chip infrastructure template, parameterize the tunable hardware architecture, and obtain an accelerator chip architecture design space; S103: Initializing design parameter weights based on the accelerator chip architecture design space.

3. The parameterized design method of a deep learning accelerator chip according to claim 1, characterized in that: In S2, the method for obtaining the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and the load characteristic data includes: S201: Select a set of design parameter samples based on the accelerator chip architecture design space; S202: Based on the design parameter sample, using an evaluation component, evaluating the accelerator chip design parameters and load characteristic data to obtain an evaluation component calculation score; S203: Calculating scores based on the evaluation components and calculating weight gradients of design parameters; S204: Based on the weight gradient and the optimization rate, modify the weight of the corresponding parameter in the design space; S205: Iteratively optimize S201 to S204 to obtain optimal design parameters of the accelerator chip architecture.

4. The parameterized design method of a deep learning accelerator chip according to claim 3, characterized in that: In S202, based on the design parameter sample, using the evaluation component to evaluate the accelerator chip design parameters and load characteristic data, the method for obtaining the evaluation component calculation score includes: S202-1: Calculate the energy consumption of the accelerator chip using the energy evaluation component; S202-2: Based on the energy consumption of the accelerator chip, use a delay evaluation component to calculate the accelerator chip operation time; S202-3: Based on the running time of the accelerator chip and the preset weight ratio, a performance score of the accelerator chip design parameters is comprehensively calculated, that is, the evaluation component calculation score.

5. The parameterized design method of a deep learning accelerator chip according to claim 2, characterized in that: In S3, based on the optimized design parameters of the accelerator chip architecture, the method for completing the accelerator architecture design includes: By using the optimized accelerator chip design parameters, adjustments are made on the preset accelerator chip architecture template to maximize the performance of the accelerator chip when calculating the input deep learning application load, including the computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic. This ultimately completes the parametric design of the deep learning accelerator chip.

6. A parameterized design system for a deep learning accelerator chip, characterized in that: include: Initialization module, optimization module and design module; The initialization module is used to initialize the accelerator chip design conditions, wherein the accelerator chip design conditions include: accelerator chip architecture design space and load characteristic data; The optimization module is used to obtain the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and load characteristic data; The design module is used to complete the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture.

7. The parameterized design system for a deep learning accelerator chip according to claim 6, characterized in that: In the initialization module, the process of initializing the accelerator chip design conditions includes: S101: pre-analyze the deep learning application load characteristics to obtain load characteristic data; S102: Based on the load characteristic data, pre-design a deep learning accelerator chip infrastructure template, parameterize the tunable hardware architecture, and obtain an accelerator chip architecture design space; S103: Initializing design parameter weights based on the accelerator chip architecture design space.

8. The parameterized design system for a deep learning accelerator chip according to claim 6, characterized in that: In the optimization module, the process of obtaining the optimal design parameters of the accelerator chip architecture based on the accelerator chip architecture design space and load characteristic data includes: S201: Select a set of design parameter samples based on the accelerator chip architecture design space; S202: Based on the design parameter sample, using an evaluation component, evaluating the accelerator chip design parameters and load characteristic data to obtain an evaluation component calculation score; S203: Calculating scores based on the evaluation components and calculating weight gradients of design parameters; S204: Based on the weight gradient and the optimization rate, modify the weight of the corresponding parameter in the design space; S205: Iteratively optimize S201 to S204 to obtain optimal design parameters of the accelerator chip architecture.

9. The parameterized design system for a deep learning accelerator chip according to claim 8, characterized in that: In S202, based on the design parameter sample, using the evaluation component to evaluate the accelerator chip design parameters and load characteristic data, and obtaining the evaluation component calculation score includes: S202-1: Calculate the energy consumption of the accelerator chip using the energy evaluation component; S202-2: Based on the energy consumption of the accelerator chip, use a delay evaluation component to calculate the accelerator chip operation time; S202-3: Based on the accelerator chip running time and the preset weight ratio, comprehensively calculate the accelerator chip The performance score of the chip design parameters, that is, the evaluation component calculation score.

10. The parameterized design system for a deep learning accelerator chip according to claim 7, characterized in that: In the design module, the process of completing the accelerator architecture design based on the optimized design parameters of the accelerator chip architecture includes: By using the optimized accelerator chip design parameters, adjustments are made on the preset accelerator chip architecture template to maximize the performance of the accelerator chip when calculating the input deep learning application load, including the computing array size, computing unit interconnection method, global register capacity, computing unit local register size, computing unit processing bit width, and computing unit additional computing logic. This ultimately completes the parametric design of the deep learning accelerator chip.

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