Electroencephalography signal acquisition and processing device and method

Abstract

The present application provides an electroencephalography signal acquisition and processing device and method. The device comprises: an analog front-end processing circuit which comprises an analog front-end chip used for carrying out electroencephalography signal acquisition by taking a clock signal of a first clock frequency of an external clock as a clock input to obtain an electroencephalography analog signal, converting the electroencephalography analog signal into an electroencephalography digital signal, and transmitting the electroencephalography digital signal to a control unit; a frequency division circuit which is connected to the external clock with the first clock frequency and is used for carrying out N-times frequency division on a clock crystal oscillator of the external clock to obtain a clock signal with the clock frequency being a target clock frequency, wherein N is an even multiple of 2, and is equal to f1 / fg, f1 represents the first clock frequency, and fg represents the target clock frequency; and the control unit used for carrying out data processing on the electroencephalography digital signal from the analog front-end chip by taking, as a clock input, the clock signal of the target clock frequency obtained after frequency division of the frequency division circuit.

Description

EEG signal acquisition and processing device and method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 26, 2023, with application number 202311255915.2 and application name “Electroencephalogram Signal Acquisition and Processing Device and Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of signal processing technology, and more specifically to an apparatus and method for collecting and processing electroencephalogram (EEG) signals. Background Art

[0003] The most important neuroelectrophysiological signals include EEG (electroencephalography) signals collected from the scalp surface, EMG (electromyography) signals, local field potentials collected in the brain, and spike signals directly corresponding to neural activity. These signals have different characteristics, such as different amplitudes and frequency bands, and the electrodes that collect them also have many different properties, such as different impedances and different electrode polarization voltages, which also result in different biases.

[0004] The development of high-precision analog-to-digital converters (ADCs) has led to the acquisition of these neurophysiological signals being generally performed by analog front-end (AFE) chips. The recommended external clock for many high-precision AFE (or analog integrated front-end) chips is 2.048 MHz, which corresponds to a sampling rate of 250 Hz.

[0005] In the process of implementing the present application, the applicant discovered that in some applications, it is necessary to perform synchronous acquisition (such as multi-channel synchronous acquisition) and processing of multiple physiological signals. For example, it is necessary not only to acquire EEG signals, but also to acquire physiological signals such as EDA (Electrodermal Activity, skin electrode activity) signals, PPG (Photo Plethysmo Graphy, photoplethysmography) signals, eye movements, heart rate and / or fNIRS (functional near-infrared spectroscopy, functional near-infrared spectroscopy) signals. The sampling rates usually used for the acquisition of these physiological signals are 8Hz, 16Hz, 64Hz, 128Hz or 256Hz, so the processing of these signals requires a data processing unit (main control chip) with a sampling rate of 256Hz or an integer multiple of 256Hz. However, the main control chip with a sampling rate of 256Hz or an integer multiple of 256Hz cannot be used in conjunction with an analog front-end chip with a sampling rate of 250Hz. This is because the sampling rate required by the main control chip MCU is 256Hz or an integer multiple of 256Hz. When using an analog front-end chip with a sampling rate of 250Hz to collect data in conjunction with the selected main control chip, only a sampling rate of 250Hz and an integer multiple of 250Hz can be achieved for EEG signals, making it difficult for the main control chip to process data. If the 256Hz sampling rate is forced to be used for collection, there will be a phenomenon of mismatch between the analog front-end chip and the main control unit clock, resulting in abnormal physiological signal data collection. Therefore, EEG signals cannot be processed synchronously with other physiological signals by the same main control chip clock.

[0006] Therefore, how to solve the clock asynchrony and coordinated processing between data acquisition and data processing is an urgent problem to be solved.

[0007] Application Contents

[0008] In view of this, the present application proposes an EEG signal acquisition and processing device and a frequency division circuit to achieve coordinated acquisition and time synchronization between the analog front-end chip and the main control chip with a 256Hz sampling rate.

[0009] In one aspect of the present application, a device for collecting and processing electroencephalogram (EEG) signals is provided, the device comprising:

[0010] An analog front-end processing circuit, comprising an analog front-end chip, the analog front-end chip being configured to use a clock signal having a first clock frequency of an external clock as a clock input, collect EEG signals at a first sampling rate matching the first clock frequency, obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to a control unit; wherein a default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate;

[0011] a frequency dividing circuit, connected to an external clock of the first clock frequency, configured to divide a clock crystal of the external clock by a factor of N to obtain a clock signal having a target clock frequency, wherein N is an even multiple of 2, and N=f1 / fg, where f1 represents the first clock frequency and fg represents the target clock frequency; and

[0012] The control unit is used to use the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

[0013] In some embodiments of the present application, the device also includes: a power supply circuit for supplying power to the analog front-end chip and the main control chip, the power supply circuit includes a main power supply module and a sub-power supply module, the main power supply module includes an analog circuit power supply circuit and a digital circuit power supply circuit; the analog circuit power supply circuit includes a low voltage difference regulator for providing a first voltage for powering the analog circuit of the EEG signal acquisition device; the digital circuit power supply circuit includes a step-down circuit for providing a first voltage for powering the digital circuit of the EEG signal acquisition device; the sub-circuit module separates a second voltage from the voltage provided by the analog circuit power supply circuit to power the analog front-end chip.

[0014] In some embodiments of the present application, the first clock frequency ranges from 1.5M to 2.25 MHz, and the first sampling rate is F, satisfying: F=f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048 or 4096.

[0015] In some embodiments of the present application, the first clock frequency is 2.097 MHz, N is 64, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the target clock frequency is 32.768 KHz.

[0016] In some embodiments of the present application, the frequency division circuit includes: a first frequency division sub-circuit, connected to the external clock of the first clock frequency, for dividing the clock crystal oscillator of the external clock by M times, where M is an even multiple of 2; and a second frequency division sub-circuit, for further dividing the signal after the M-fold frequency division of the first frequency division circuit by L times to obtain a clock signal of the target clock frequency, where L is an even multiple of 2 and L=N / M.

[0017] In some embodiments of the present application, the frequency division circuit includes: a first frequency division sub-circuit, connected to the external clock of the first clock frequency, for dividing the clock crystal oscillator of the external clock by 4 times; a second frequency division sub-circuit, for further dividing the signal after 4 times division by the first frequency division circuit by 4 times by 4 times; and a third frequency division sub-circuit, for further dividing the signal after 4 times division by the second frequency division circuit by 4 times by 4 times to obtain a 32.768KHz clock signal.

[0018] In some embodiments of the present application, the analog front-end processing circuit further includes: an electrostatic protection circuit, which is arranged at the EEG signal input end for electrostatic protection.

[0019] In some embodiments of the present application, the analog front-end processing circuit further includes: a low-pass filtering circuit, which is arranged at the EEG signal input end and is used to filter out high-frequency electromagnetic waves and high-frequency crosstalk.

[0020] In some embodiments of the present application, the analog front-end chip includes a multi-channel EEG signal MUX switching module for polling and collecting EEG signals.

[0021] In some embodiments of the present application, the first voltage ranges from 1.8 to 3.6 V, preferably 3.0 V; the second voltage is expressed as AVDD: AVDD = AVDD+ - AVDD-, where AVDD+ and AVDD- represent the high voltage and low voltage of the analog front-end chip, respectively, and the range of AVDD is 4.75 to 5.25 V.

[0022] Another aspect of the present application provides a method for collecting and processing EEG signals, the method comprising the following steps:

[0023] The analog front-end chip uses a clock signal of a first clock frequency of an external clock as a clock input, collects EEG signals at a first sampling rate that matches the first clock frequency, obtains an EEG analog signal, converts the EEG analog signal into an EEG digital signal, and transmits the EEG digital signal to a control unit; wherein the default sampling rate of the analog front-end chip is a second sampling rate that is different from the first sampling rate;

[0024] An external clock having the first clock frequency is connected via a frequency dividing circuit, and is configured to divide the clock crystal oscillator of the external clock by a factor of N to obtain a clock signal having a target clock frequency, wherein N is an even multiple of 2, and N=f1 / fg, where f1 represents the first clock frequency and fg represents the target clock frequency; and

[0025] The control unit uses the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

[0026] In some embodiments of the present application, the external clock connected to the first clock frequency through the frequency dividing circuit is used to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: connecting the external clock with the first clock frequency, dividing the clock crystal oscillator of the external clock by M times, where M is an even multiple of 2; and further dividing the signal after M times division by the first frequency dividing circuit by L times to obtain the clock signal of the target clock frequency, where L is an even multiple of 2 and L=N / M.

[0027] In some embodiments of the present application, the external clock connected to the first clock frequency through the frequency division circuit is used to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: connecting the external clock of the first clock frequency to divide the clock crystal oscillator of the external clock by 4 times for the first time; further dividing the signal after the first 4-fold division by 4 times for the second time; and further dividing the signal after the second 4-fold division by 4 times for the third time to obtain the clock signal of the target clock frequency.

[0028] The EEG signal acquisition and processing device and method of the present application can realize the coordinated acquisition of the analog front-end chip and the main control chip, so that the same main control chip with a selected sampling rate (such as 256Hz) can realize the synchronous processing of multiple physiological signals including EEG signals, greatly expanding the application scenarios of physiological signals.

[0029] Additional advantages, purposes, and features of the present application will be described in part in the following description and will become apparent to those skilled in the art upon study of the following or may be learned from practice of the present application. The purposes and other advantages of the present application may be achieved and obtained by the structures specifically pointed out in the specification and drawings.

[0030] Those skilled in the art will understand that the purposes and advantages that can be achieved by the present application are not limited to the above specific description, and the above and other purposes that can be achieved by the present application will be more clearly understood based on the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide further understanding of the present application, constitute a part of the present application, and do not constitute a limitation of the present application.

[0032] FIG1 is a schematic diagram of an apparatus for collecting and processing EEG signals in one embodiment of the present application.

[0033] FIG2 is a schematic diagram of an EEG signal acquisition and processing device in another embodiment of the present application.

[0034] FIG3 is a schematic diagram of an external clock circuit.

[0035] FIG4 is a schematic diagram of a frequency division circuit in an embodiment of the present application.

[0036] FIG5 is a flow chart of a method for collecting and processing EEG signals in one embodiment of the present application.

[0037] FIG6 is a schematic structural diagram of an analog front-end processing circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail in conjunction with the embodiments and drawings. Here, the illustrative embodiments of this application and their descriptions are used to explain this application, but are not intended to limit this application.

[0039] It should also be noted here that in order to avoid obscuring the present application due to unnecessary details, the accompanying drawings only show structures and / or processing steps that are closely related to the scheme according to the present application, while other details that are not closely related to the present application are omitted.

[0040] It should be emphasized that the term "include / comprises" when used herein refers to the existence of features, elements, steps or components, but does not exclude the existence or addition of one or more other features, elements, steps or components.

[0041] As mentioned above, when using an analog front-end chip with a 250Hz sampling rate and a main control chip (MCU) with a 256Hz sampling rate for data collection, only 250Hz and integer multiples of 250Hz can be achieved for EEG signal sampling rates, making it difficult for the main control chip to process data. If the analog front-end chip is forced to use a 256Hz sampling rate for data collection, there will be a phenomenon of mismatch between the analog front-end chip and the main control unit clock, resulting in abnormal physiological signal data collection. As a result, EEG signals cannot be processed synchronously with other physiological signals by the same main control chip clock.

[0042] In addition, for analog front-end chips whose default or fixed sampling rate is neither 250 Hz or its multiples nor 256 Hz or its multiples, the same problem also exists when converting to a sampling rate of 256 Hz for sampling.

[0043] To address this technical problem, the present application proposes an improved EEG signal acquisition and processing device, which converts the fixed 250Hz sampling rate of the analog integrated front end (or other sampling rates different from 256Hz and its multiples) into a custom 256Hz sampling rate by changing the external input clock. This device can achieve coordinated acquisition between the analog front-end chip and the main control chip, so that the main control chip with a 256Hz sampling rate can achieve synchronous processing of multiple physiological signals including EEG signals, so that multiple physiological signals can be used for collaborative judgment of the subject's physiological state, greatly expanding the application scenarios of physiological signals.

[0044] The analog front-end chip allows the input of an external clock. Taking an analog front-end chip with a sampling rate of 250Hz as an example, the allowed input range of the external clock is 1.5MHz to 2.25MHz, and the recommended external clock input is 2.048Mhz (the sampling rate of 250Hz is based on (2.048MHz / 2 / 4096)). Within this allowed range, this application does not adopt the recommended external clock input of 2.048Mhz, but chooses to adopt a 2.097MHz clock. The 2.097MHz clock is an integer multiple of 32.768KHz, and 32.768KHz happens to be the clock of the main control chip. Therefore, by modifying the external input clock of the analog front-end chip to 2.097MHz, the analog integrated front-end with a fixed sampling rate of 250Hz can be converted to a sampling rate of 256Hz. However, while changing the external input clock to 2.097MHz to enable the analog integrated front end to sample at a sampling rate of 256Hz, a defect is caused, that is, the problem of clock asynchrony between the analog integrated front end and the main control chip due to frequency deviation will occur, that is, clock deviation will also occur between the analog integrated front end and the main control chip due to clock asynchrony. In this regard, the present application further, in order to eliminate clock deviation and ensure clock synchronization between the analog integrated front end and the main control chip, not only 2.097MHz is used as the clock input of the analog integrated front end, but also a frequency division circuit is designed to divide 2.097MHz by 64 to obtain 32.768KHz as the clock input of the main control chip, replacing the original 32.768KHz clock of the main control chip, thereby achieving a unified clock source and then achieving clock synchronization. In this way, the purpose of clock synchronization between the analog integrated front end and the main control chip can be achieved while the analog integrated front end adopts a 256Hz sampling rate to collect EEG signals.

[0045] For other analog front-end chips whose default or fixed sampling rate is neither 250Hz or its multiples, nor 256Hz or its multiples, this application also needs to convert to sampling using a custom sampling rate (such as 256Hz), and also choose to change the clock frequency of the external clock of the analog front-end chip from a fixed or default clock frequency to a clock frequency that matches the target sampling rate, so that EEG signals can be collected at a first sampling rate that matches the external input clock frequency to obtain an EEG simulation signal. Accordingly, in order to achieve clock synchronization between the analog integrated front-end and the main control chip, the external input clock frequency is divided by a frequency division circuit to obtain a target clock frequency consistent with the main control chip and input to the main control chip.

[0046] Figure 1 is a schematic structural diagram of an EEG signal acquisition and processing device in one embodiment of the present application. As shown in Figure 1 , the EEG signal acquisition and processing device includes: an analog front-end processing circuit, a frequency division circuit, and a main control chip (MCU).

[0047] The analog front-end processing circuit includes an analog front-end chip, which is used to use a clock signal of a first clock frequency of an external clock as a clock input, collect EEG signals at a first sampling rate matching the first clock frequency, obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to a control unit; wherein the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate.

[0048] In an embodiment of the present application, the range of the first clock frequency f1 is 1.5M~2.25MHz, and the first sampling rate F that matches the first clock frequency is: F=f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048 and 4096. As an example, the first clock frequency is 2.097MHz, the first sampling rate is 256Hz or a multiple of 256Hz, and the second sampling rate is 250Hz or a multiple of 250Hz. At this time, the analog front-end chip is used to use the 2.097MHz clock signal of the external clock as the clock input to collect EEG signals, obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to the control unit (i.e., the main control chip MCU).

[0049] The frequency dividing circuit is connected to an external clock of a first clock frequency, and is used to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency equal to the target clock frequency, where N is an even multiple of 2, and N=f1 / fg, f1 represents the first clock frequency, and fg represents the target clock frequency.

[0050] When the first clock frequency is 2.097 MHz and the first sampling rate is 256 Hz or a multiple of 256 Hz, the target clock frequency is 32.768 kHz and N is 64. At this time, the frequency division circuit is connected to the 2.097 MHz external clock to divide the 2.097 MHz clock crystal oscillator by 64 times to obtain a 32.768 kHz clock signal.

[0051] The main control chip MCU is used to use the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

[0052] In other embodiments of the present application, the EEG signal acquisition and processing device further includes a power supply circuit for supplying power to the analog front-end chip and the main control chip.

[0053] The power supply circuit can provide digital circuit power at a first voltage and analog circuit power at a first voltage and a second voltage, respectively, to provide the required voltages to the digital circuits and analog circuits in the components of the EEG signal acquisition and processing device, including the analog front-end chip and the main control chip. The first voltage ranges from 1.8 to 3.6V, preferably 3.0V; the second voltage can be expressed as AVDD: AVDD = AVDD+ - AVDD-, where AVDD+ and AVDD- represent the high voltage and low voltage of the analog front-end chip, respectively. AVDD ranges from 4.75 to 5.25V, preferably 5V. As an example, the power supply circuit may include a main power supply module and a sub-power supply module. The main power supply module includes a power management chip, which includes an analog circuit power supply circuit and a digital circuit power supply circuit. The analog circuit power supply circuit includes a low-dropout regulator (LDO) for providing a 3.0V supply voltage to the analog circuit of the EEG signal acquisition device; the digital circuit power supply circuit includes a step-down circuit (BUCK circuit) for providing a 3.0V supply voltage to the digital circuit of the EEG signal acquisition device.

[0054] The sub-circuit module can separate ±2.5V from the voltage provided by the analog circuit power supply circuit to provide ±2.5V power supply voltage for the analog front-end chip, that is, AVDD+ is +2.5V and AVDD- is -2.5V. For example, the provided 3.0V analog circuit power supply voltage is first boosted to 5V, and the 5V is output as a 2.5V power supply voltage through the step-down chip; the -2.5V power supply voltage is obtained by converting the 5V to -5V, and then converting the -5V to -2.5V.

[0055] Since the power supply circuit can be implemented using an existing circuit that can provide 3.0V digital circuit power supply and 3.0V and ±2.5V analog circuit power supply, it will not be described in detail here.

[0056] In some embodiments of the present application, as shown in FIG6 , the analog front-end processing circuit may include, in addition to the analog front-end chip, an ESD (Electrostatic Protection) circuit. This ESD circuit is provided at the EEG signal input terminal and provides electrostatic protection for each acquisition channel. When the device receives a lightning surge, ESD electrostatic discharge, or other transient voltage, the circuit can be protected from damage by transient lightning surges and ESD static electricity.

[0057] In some embodiments of the present application, as shown in FIG6 , the analog front-end processing circuit may further include a low-pass filter circuit, which is provided at the EEG signal input end and is used to:

[0058] (1) Each acquisition channel filters out high-frequency electromagnetic waves. When there is a conducting current on the wire, the higher the frequency of the current, the easier it is to radiate, thus generating stronger radiation interference. Therefore, filtering out these high-frequency noises will effectively reduce cable radiation.

[0059] (2) Filtering high-frequency crosstalk in each acquisition channel. Due to the distributed capacitance and mutual inductance between wires or cables, crosstalk will occur. This interference is mainly high-frequency, so low-pass filtering can remove this interference.

[0060] In some embodiments of the present application, the analog front-end chip includes:

[0061] Multi-channel EEG signal MUX switching module (such as 8 channels or 16 channels, etc., this application is not limited to this), programmable gain module, analog-to-digital signal conversion module and right leg drive module (right leg drive circuit), etc.

[0062] The EEG signals measured by the analog front-end chip can be either 8-channel or 16-channel. After entering the analog front-end chip, data acquisition is not performed simultaneously. Instead, the signals are collected in a round-robin fashion via the multiplexing (MUX) switching module. The programmable gain module can amplify the EEG signals by 1x, 2x, 4x, 6x, 8x, 12x, or 24x, respectively. The amplified analog signals are then converted to digital signals by the analog-to-digital signal conversion module, which then communicates with the main control chip (MCU) via the SPI protocol and transmits the digital signals to the MCU. Furthermore, the right leg drive module is used to reduce common-mode interference. After amplification, the common-mode components of the EEG signals are extracted by the programmable gain module and fed into the right leg drive module, where they are then returned to the human body, thereby reducing interference. Since the multi-channel EEG signal multiplexing (MUX) switching module, programmable gain module, analog-to-digital signal conversion module, and right leg drive module are already internal to the existing analog front-end chip, they will not be described in detail here.

[0063] In some embodiments of the present application, the frequency division circuit may include two, three or more frequency division sub-circuits. For example, the frequency division circuit may include:

[0064] a first frequency division sub-circuit, connected to an external clock of a first clock frequency, for dividing the clock crystal oscillator of the external clock by a factor of M, where M is an even multiple of 2; and

[0065] The second frequency dividing sub-circuit is used to further divide the signal divided by M times by the first frequency dividing circuit by L times to obtain a clock signal of a target clock frequency, wherein L is an even multiple of 2 and L=N / M.

[0066] When N=64, and the 64-fold frequency division circuit includes two frequency division sub-circuits, the 64-fold frequency division circuit may include:

[0067] The first frequency division sub-circuit is connected to the 2.097 MHz external clock and is used to divide the 2.097 MHz clock crystal oscillator by M times, where M is an even multiple of 2, preferably, M is 4, 8 or 16.

[0068] The second frequency dividing sub-circuit is used to further divide the signal divided by M times by the first frequency dividing circuit by L times to obtain a 32.768KHz clock signal, wherein L=64 / M.

[0069] That is, the 2.097Mhz crystal oscillator can be divided by 16 times first, and then divided by 4 times on the basis of the 16-fold division, a total of 64-fold division is achieved, and finally 32.768KHz is output as the input clock of the MCU, which is the input clock of the same source as the analog integrated front-end; the 2.097Mhz crystal oscillator can be divided by 8 times first, and then divided by 8 times on the basis of the 8-fold division, a total of 64-fold division is achieved, and finally 32.768KHz is output as the input clock of the analog integrated front-end; the 2.097Mhz crystal oscillator can be divided by 4 times first, and then divided by 16 times on the basis of the 4-fold division, a total of 64-fold division is achieved, and finally 32.768KHz is output as the input clock of the analog integrated front-end.

[0070] In the case where the 64-fold frequency division circuit includes three frequency division sub-circuits, the 64-fold frequency division circuit may include:

[0071] A first frequency division sub-circuit, connected to the 2.097 MHz external clock, is used to divide the 2.097 MHz clock crystal oscillator by 4 times;

[0072] a second frequency dividing sub-circuit, configured to further divide the frequency of the signal divided by 4 by the first frequency dividing circuit by 4; and

[0073] The third frequency dividing sub-circuit is used to further divide the signal divided by 4 by the second frequency dividing circuit by 4 to obtain a 32.768KHz clock signal.

[0074] That is, the first frequency division sub-circuit, the second frequency division sub-circuit and the third frequency division sub-circuit are the same 4-divide-by-4 frequency division circuit.

[0075] In some other embodiments of the present application, more frequency division sub-circuits may be included, with a frequency division multiple of 2 to 16, which are not listed here one by one.

[0076] FIG3 is a schematic diagram of an external clock circuit in one embodiment of the present application. FIG4 is a schematic diagram of a frequency division circuit in one embodiment of the present application. As shown in FIG3 , pin 3 of clock circuit X1 outputs a 2.097 MHz clock. One direction is output to the analog front-end chip as the clock source of the analog front-end chip, and the other direction is output to pin 2 of the first frequency division sub-circuit (chip U6, a 16-fold frequency division circuit) as the main input of the frequency division circuit. Then, after being divided by 16 by chip U6, the 16-fold frequency division clock is output from pin 11. Then, it is input from pin 3 of the second frequency division sub-circuit (chip U8, a 4-fold frequency division circuit). After being divided by 4 by chip U8, the desired 32.768 kHz clock is output from pin 11. This clock is given to the main control chip MCU as the clock signal of the MUC. This not only enables the analog front-end chip to collect EEG signals at 256 Hz, but also enables clock synchronization between the analog front-end chip and the main control chip.

[0077] In some embodiments of the present application, the main control chip MCU is a chip that integrates Bluetooth and wired. After the ADC of the analog front-end chip transmits the data (digital signal) to the MCU through the SPI protocol, the MCU processes the data and further transmits the processed data to the host computer through the Bluetooth protocol or wired transmission.

[0078] The main control chip MCU mainly includes:

[0079] Indicator light circuit control module, which can be used to control the charging indicator light and Bluetooth indicator light, etc.

[0080] Analog integrated front-end EEG signal data receiving and processing module, used for receiving and processing EEG digital signals from the analog integrated front-end;

[0081] The power circuit control module is used to monitor power consumption and charge detection, and perform corresponding charging control;

[0082] Lead off switching control (shedding detection control) module, used for round-robin detection of multi-channel impedance connection degree;

[0083] EEG signal switching control module, used for round-robin detection of multi-channel EEG signals;

[0084] Two-channel BIO signal receiving and processing module for physiological signal detection.

[0085] The main control chip MCU can be implemented by using an existing MCU chip, or a self-developed chip that can achieve similar functions can be used.

[0086] From the above, it can be seen that the present application uses hardware to convert an analog integrated front-end with a fixed sampling rate of 250Hz to a sampling rate of 256Hz, and solves the problem of clock asynchrony caused by changing the sampling rate through a frequency division circuit. As a result, the same main control chip with a sampling rate of 256Hz can achieve synchronous processing of multiple physiological signals including EEG signals, greatly expanding the application scenarios of physiological signals.

[0087] Corresponding to the above-mentioned device, the present application also provides a method for collecting and processing EEG signals, as shown in FIG5 , the method comprising the following steps:

[0088] In step S110, the analog front-end chip uses the clock signal of the first clock frequency of the external clock as the clock input, collects the EEG signal at a first sampling rate that matches the first clock frequency, obtains an EEG analog signal, converts the EEG analog signal into an EEG digital signal, and transmits the EEG digital signal to the control unit; wherein the default sampling rate of the analog front-end chip is a second sampling rate that is different from the first sampling rate.

[0089] In the foregoing example, the first clock frequency is 2.097 MHz, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the second sampling rate is 250 Hz.

[0090] Step S120, connecting the external clock of the first clock frequency through a frequency dividing circuit, for dividing the clock crystal oscillator of the external clock by N times, to obtain a clock signal with a clock frequency of the target clock frequency, wherein N is an even multiple of 2, and N=f1 / fg, f1 represents the first clock frequency, and fg represents the target clock frequency.

[0091] In the previous example, the target clock frequency is 32.768KHz and N is 64.

[0092] In step S130 , the control unit uses the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

[0093] As an example, the external clock connected to the first clock frequency through the frequency dividing circuit is used to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: connecting the external clock with the first clock frequency, dividing the clock crystal oscillator of the external clock by M times, where M is an even multiple of 2; and further dividing the signal after M times division by the first frequency dividing circuit by L times to obtain a 32.768KHz clock signal, where L is an even multiple of 2 and L=N / M.

[0094] As another example, when the first clock frequency is 2.097 MHz, N is 64, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the target clock frequency is 32.768 kHz, the external clock of the first clock frequency is connected through the frequency division circuit to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: connecting a 2.097 MHz external clock to divide the 2.097 MHz clock crystal oscillator by 4 times for the first time; further dividing the signal after the first 4-fold division by 4 times by 4 times for the second time; and further dividing the signal after the second 4-fold division by 4 times by 4 times for the third time to obtain a 32.768 kHz clock signal.

[0095] It should be understood by those skilled in the art that the various exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is specifically performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of this application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0096] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0097] In this application, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or replace features of other embodiments.

[0098] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Those skilled in the art will appreciate that various modifications and variations of the present embodiment are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. An electroencephalogram signal acquisition and processing device, characterized in that: The device includes: An analog front-end processing circuit, comprising an analog front-end chip, the analog front-end chip is used to use a clock signal of a first clock frequency of an external clock as a clock input, collect EEG signals at a first sampling rate matching the first clock frequency, obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to a control unit; wherein the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate; a frequency dividing circuit connected to an external clock of the first clock frequency, and used to divide the clock crystal of the external clock by N times to obtain a clock signal having a clock frequency of a target clock frequency, wherein N is an even multiple of 2, and N=f1 / fg, f1 represents the first clock frequency, and fg represents the target clock frequency; and The control unit is used to use the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

2. The device according to claim 1, characterized in that The device also includes: A power supply circuit, used to supply power to the analog front-end chip and the main control chip, the power supply circuit includes a main power supply module and a sub-power supply module, the main power supply module includes an analog circuit power supply circuit and a digital circuit power supply circuit; the analog circuit power supply circuit includes a low voltage dropout regulator, used to provide a first voltage for powering the analog circuit of the EEG signal acquisition device; the digital circuit power supply circuit includes a step-down circuit, used to provide a first voltage for powering the digital circuit of the EEG signal acquisition device; The circuit division module divides a second voltage from a first voltage provided by the analog circuit power supply circuit to power the analog front-end chip.

3. The device according to claim 1, characterized in that The first clock frequency ranges from 1.5M to 2.25 MHz, and the first sampling rate is F, satisfying: F=f1 / 2 / k, wherein k is selected from 64, 128, 256, 512, 1024, 2048 or 4096.

4. The device according to any one of claims 1 to 3, characterized in that The frequency division circuit comprises: A first frequency division sub-circuit, connected to an external clock of the first clock frequency, for dividing the clock crystal oscillator of the external clock by M times, where M is an even multiple of 2; and The second frequency division sub-circuit is used to further divide the signal divided by M times by the first frequency division circuit by L times to obtain a clock signal of a target clock frequency, wherein L is an even multiple of 2 and L=N / M.

5. The device according to claim 3, characterized in that N is 64, and the frequency division circuit includes: A first frequency division sub-circuit, connected to an external clock of the first clock frequency, for dividing the clock crystal of the external clock by 4 times; a second frequency division sub-circuit, which is used to further divide the frequency of the signal divided by 4 by the first frequency division circuit by 4; and The third frequency division sub-circuit is used to further divide the signal divided by 4 by the second frequency division circuit by 4 to obtain a clock signal of a target clock frequency.

6. The device according to claim 1, characterized in that The analog front-end processing circuit also includes: an electrostatic protection circuit, which is arranged at the EEG signal input end for electrostatic protection; and A low-pass filter circuit is arranged at the EEG signal input end to filter out high-frequency electromagnetic waves and high-frequency crosstalk.

7. The device according to claim 2, characterized in that The analog front-end chip includes a multi-channel EEG signal MUX switching module for polling and collecting EEG signals; The first voltage ranges from 1.8 to 3.6 V; The second voltage is expressed as AVDD: AVDD=AVDD+-AVDD-, wherein AVDD+ and AVDD- represent the high voltage and low voltage of the analog front-end chip respectively, and the range of AVDD is 4.75-5.25V.

8. A method for collecting and processing electroencephalogram signals, characterized in that: The method comprises the following steps: The analog front-end chip uses a clock signal of a first clock frequency of an external clock as a clock input, collects EEG signals at a first sampling rate matching the first clock frequency, obtains an EEG analog signal, converts the EEG analog signal into an EEG digital signal, and transmits the EEG digital signal to a control unit; wherein the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate; An external clock of the first clock frequency is connected through a frequency dividing circuit, and is used to divide the clock crystal of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, wherein N is an even multiple of 2, and N=f1 / fg, f1 represents the first clock frequency, and fg represents the target clock frequency; and The control unit uses the clock signal of the target clock frequency obtained after the frequency division by the frequency division circuit as the clock input to perform data processing on the EEG digital signal from the analog front-end chip.

9. The method according to claim 8, characterized in that The external clock connected to the first clock frequency through the frequency dividing circuit is used to divide the clock crystal of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: An external clock of a first clock frequency is connected, and a clock crystal oscillator of the external clock is divided by M times, wherein M is an even multiple of 2; and The signal divided by the first frequency division circuit by M times is further divided by L times to obtain a clock signal of the target clock frequency, wherein L is an even multiple of 2 and L=N / M.

10. The method according to claim 8, characterized in that The first clock frequency ranges from 1.5M to 2.25MHz, N is 64, and the first sampling rate is F, satisfying: F=f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048 or 4096; The external clock of the first clock frequency is connected through a frequency dividing circuit, and the clock crystal oscillator of the external clock is divided by N times to obtain a clock signal with a clock frequency of the target clock frequency, including: An external clock connected to the first clock frequency is used to perform a first 4-fold frequency division on the clock crystal oscillator of the external clock; Further performing a second 4-fold frequency division on the signal after the first 4-fold frequency division; and The signal after the second 4-fold frequency division is further divided by 4 for a third time to obtain a clock signal of the target clock frequency.

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