Data mapping method and related apparatus

Abstract

Disclosed in the embodiments of the present application are a data mapping method and a related apparatus, which can obtain higher encoding gains while keeping good compatibility, and can also guarantee the capability to resist channel burst errors. Specifically, a first data stream that has been subjected to outer code encoding is acquired; afterwards, inner code encoding is performed on the first data stream to obtain a second data stream, wherein the second data stream comprises L codewords that have been subjected to second FEC encoding, L is an integer multiple of 8, each codeword comprises n bits, and n is an odd number greater than 1; and then, interleaved mapping is performed on the L codewords to obtain n×L / 8 DP-16 QAM symbols, wherein any one of an X-polarization-direction I-path component, an X-polarization-direction Q-path component, a Y-polarization-direction I-path component and a Y-polarization-direction Q-path component of each DP-16 QAM symbol is obtained by mapping two bits in the L codewords, and each DP-16 QAM symbol is obtained by mapping eight bits respectively from eight codewords.

Description

A data mapping method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number 202311294686.5 and invention name “A data mapping method and related device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of optical communications, and in particular to a data mapping method and related devices. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing toward high capacity and ultra-high speeds. Forward error correction (FEC) is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0004] In 400G ZR scenarios, concatenated-FEC (CFEC) is used in optical modules as an error correction scheme. Staircase codes are used for the outer code, and two-bit extended Hamming codes are used for the inner code. Before the inner-coded data stream is sent to the transmission medium, symbol mapping and channel interleaving are performed to enhance cFEC's resilience to channel burst errors. The existing channel interleaving scheme is designed based on an inner codeword length that is a multiple of 8. In the future 1.6T ZR scenario, due to the significant increase in transmission rates, the performance of the existing CFEC scheme will not meet the link budget. Therefore, a more performant codeword and corresponding channel interleaving scheme are urgently needed.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a data mapping method and related devices, which can achieve higher coding gain while maintaining good compatibility and at the same time ensure resistance to channel burst errors.

[0007] In the first aspect, an embodiment of the present application provides a data mapping method. First, a first data stream that has been encoded by a first forward error correction (FEC) code is obtained, and the first FEC code can be regarded as an outer code code. Afterwards, a second FEC code is performed on the first data stream to obtain a second data stream, and the second FEC code can be regarded as an inner code code. The second data stream includes L codewords that have been encoded by the second FEC, where L is an integer multiple of 8, each codeword includes n bits, and n is an odd number greater than 1. Furthermore, the L codewords are interleaved and mapped to obtain n×L / 8 dual-polarization (DP)-16QAM symbols, and any one of the X-polarization direction I component, X-polarization direction Q component, Y-polarization direction I component, and Y-polarization direction Q component of each DP-16QAM symbol is mapped from 2 bits in the L codewords, and each DP-16QAM is mapped from 8 bits from 8 codewords respectively.

[0008] In this embodiment, the inner code word designed by this scheme includes an odd number of bits, and a BCH code or its extended code with an error correction capability of 2 bits can be used to improve the performance of the inner code coding. For example, a coding method such as (135,119) coding or (137,119) coding can be used instead of the existing (128,119) coding, which can achieve a higher coding gain while maintaining good compatibility. Since the inner code code word length used in this scheme is no longer a multiple of 8, the method of independently mapping each inner code code word to a DP-16QAM symbol in the existing interleaving mapping scheme is no longer applicable. Therefore, this application specifically designs an interleaving mapping method, that is, each DP-16QAM symbol is obtained by mapping 8 bits from 8 code words respectively, which can also ensure the ability to resist channel burst errors.

[0009] In some possible implementations, the L codewords include L / 2 first-category codewords and L / 2 second-category codewords. bits are mapped to the most significant bits (MSBs) of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the least significant bit (LSB) of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the MSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in n×L / 8 DP-16QAM symbols. Indicates rounding down. Indicates rounding up. This means that the bits in each codeword are mapped as evenly as possible to the MSBs and LSBs of the four polarization components in n × L / 8 DP-16QAM symbols. Because the MSB and LSB have different noise immunity capabilities, evenly mapping the bits in each inner codeword to the MSB and LSB maximizes coding performance.

[0010] In some possible implementations, the number of bits from any codeword among the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is w. That is, the number of bits from any codeword in the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is as close or identical as possible, which helps to reduce performance degradation caused by continuous errors.

[0011] In some possible implementations, the number of bits of each codeword mapped to any polarization component in n×L / 8 DP-16QAM symbols is r. That is, the number of bits of each codeword mapped to any polarization component in the n×L / 8 DP-16QAM symbols is as close or identical as possible, which is beneficial to reducing performance degradation caused by continuous errors.

[0012] In some possible implementations, each consecutive L / 8 DP-16QAM symbols in n×L / 8 DP-16QAM symbols are mapped to L bits from L codewords respectively. In scenarios where L is greater than 8, this interleaved mapping method can also be well compatible with the inner codewords provided in the embodiments of the present application.

[0013] In some possible implementations, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained. Among them, It represents the lth pulse amplitude modulation PAM4 symbol component of the I-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. It represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. a%b represents a modulo b, and a^b represents the exclusive OR of a and b. This implementation provides an exclusive OR shift method for interleaving mapping, which enhances the practicality of this solution.

[0014] In some possible implementations, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained. Among them, Indicates the lth PAM4 symbol component of the I-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. It represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. This implementation provides a cyclic shift method for interleaving mapping, which improves the flexibility of the solution.

[0015] In some possible implementations, the number of information bits in the codeword is k=119, n=133, 135, or 137. On the basis of compatibility with 400G ZR, a BCH code or its extended code with an error correction capability of 2 bits can be used, which is beneficial to improving the performance of inner code encoding.

[0016] In some possible implementations, the first FEC encoding uses staircase (512, 510) encoding, which has better practical effects.

[0017] In some possible implementations, the first data stream is bit-stuffed after the first FEC encoding, which facilitates better synchronization of the inner code and the outer code at the receiving end, wherein the number of the padded bits is greater than or equal to 1.

[0018] In some possible implementations, the first data stream undergoes convolutional interleaving after undergoing the first FEC encoding.

[0019] In some possible implementations, before obtaining the first data stream after the first FEC encoding, the method further includes: distributing the input data stream to obtain four distributed data streams, wherein each consecutive four bits in the input data stream are distributed to the four distributed data streams; and performing the first FEC encoding on each distributed data stream. This data method facilitates compatibility with throughput scenarios such as 1.6T, 800G, and 400G.

[0020] In a second aspect, an embodiment of the present application provides a data mapping device. The data mapping device includes an acquisition unit, an encoding unit, and an interleaving mapping unit. The acquisition unit is configured to acquire a first data stream that has undergone a first FEC encoding. The encoding unit is configured to perform a second FEC encoding on the first data stream to obtain a second data stream. The second data stream includes L codewords that have undergone a second FEC encoding, where L is an integer multiple of 8, each codeword includes n bits, and n is an odd number greater than 1. The interleaving mapping unit is configured to interleave and map the L codewords to obtain n×L / 8 DP-16QAM symbols. Each DP-16QAM symbol is mapped from two bits in the L codewords to obtain any of the following components: the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction. Each DP-16QAM symbol is mapped from eight bits from eight codewords.

[0021] In some possible implementations, the L codewords include L / 2 first-category codewords and L / 2 second-category codewords. bits are mapped to the MSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the MSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in n×L / 8 DP-16QAM symbols. Indicates rounding down. Indicates rounding up. This means that the bits in each codeword are mapped as evenly as possible to the MSBs and LSBs of the four polarization components in n × L / 8 DP-16QAM symbols. Because the MSB and LSB have different noise immunity capabilities, evenly mapping the bits in each inner codeword to the MSB and LSB maximizes coding performance.

[0022] In some possible implementations, the number of bits from any codeword among the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is w. That is, the number of bits from any codeword in the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is as close or identical as possible, which helps to reduce performance degradation caused by continuous errors.

[0023] In some possible implementations, the number of bits of each codeword mapped to any polarization component in n×L / 8 DP-16QAM symbols is r. That is, the number of bits of each codeword mapped to any polarization component in the n×L / 8 DP-16QAM symbols is as close or identical as possible, which is beneficial to reducing performance degradation caused by continuous errors.

[0024] In some possible implementations, each consecutive L / 8 DP-16QAM symbols in the n×L / 8 DP-16QAM symbols are mapped to L bits from L codewords respectively.

[0025] In some possible implementations, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained. Among them, It represents the lth pulse amplitude modulation PAM4 symbol component of the I-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. It represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. a%b represents a modulo b, and a^b represents the exclusive OR of a and b. This implementation provides an exclusive OR shift method for interleaving mapping, which enhances the practicality of this solution.

[0026] In some possible implementations, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained, By The first codeword bits and The first codeword Bit mapping is obtained. Among them, Indicates the lth PAM4 symbol component of the I-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the X polarization direction among n×L / 8 DP-16QAM symbols. It represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. Indicates the lth PAM4 symbol component of the Q-path component in the Y polarization direction among n×L / 8 DP-16QAM symbols. This implementation provides a cyclic shift method for interleaving mapping, which improves the flexibility of the solution.

[0027] In some possible implementations, the number of information bits in the codeword is k=119, n=133, 135, or 137. On the basis of compatibility with 400G ZR, a BCH code or its extended code with an error correction capability of 2 bits can be used, which is beneficial to improving the performance of inner code encoding.

[0028] In some possible implementations, the first FEC encoding uses staircase (512, 510) encoding, which has better practical effects.

[0029] In some possible implementations, the first data stream is bit-stuffed after the first FEC encoding, which facilitates better synchronization of the inner code and the outer code at the receiving end, wherein the number of the padded bits is greater than or equal to 1.

[0030] In some possible implementations, the first data stream undergoes convolutional interleaving after undergoing the first FEC encoding.

[0031] In some possible embodiments, the data mapping device further includes a processing unit, which, before obtaining the first data stream that has undergone the first FEC encoding, is used to: perform data distribution on the input data stream to obtain 4 distribution data streams, wherein every 4 consecutive bits in the input data stream are distributed to 4 distribution data streams respectively; and perform the first FEC encoding on each distribution data stream.

[0032] In a third aspect, an embodiment of the present application provides a chip comprising a processor and a memory, the memory and the processor being interconnected via lines, instructions being stored in the memory, and the processor being used to execute the method described in any embodiment of the first aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any embodiment of the first aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding on the received data.

[0034] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the method described in any embodiment of the first aspect is implemented.

[0035] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0036] In this embodiment, the inner code word designed by this scheme includes an odd number of bits, and a BCH code or its extended code with an error correction capability of 2 bits can be used to improve the performance of the inner code coding. For example, a coding method such as (135,119) coding or (137,119) coding can be used instead of the existing (128,119) coding, which can achieve a higher coding gain while maintaining good compatibility. Since the inner code code word length used in this scheme is no longer a multiple of 8, the method of independently mapping each inner code code word to a DP-16QAM symbol in the existing interleaving mapping scheme is no longer applicable. Therefore, this application specifically designs an interleaving mapping method, that is, each DP-16QAM symbol is obtained by mapping 8 bits from 8 code words respectively, which can also ensure the ability to resist channel burst errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0038] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application;

[0039] FIG3 is a schematic diagram of an implementation method of data processing at the sending end and data processing at the receiving end in accordance with an embodiment of the present application;

[0040] FIG4 is a flow chart of a data mapping method provided in an embodiment of the present application;

[0041] FIG5 is a schematic diagram of a first application scenario of interleaving mapping in an embodiment of the present application;

[0042] FIG6 is a schematic diagram of a second application scenario of interleaving mapping in an embodiment of the present application;

[0043] FIG7 is a schematic diagram of a third application scenario of interleaving mapping in an embodiment of the present application;

[0044] FIG8 is a schematic diagram of a fourth application scenario of interleaving mapping in an embodiment of the present application;

[0045] FIG9 is a schematic diagram of a fifth application scenario of interleaving mapping in an embodiment of the present application;

[0046] FIG10 is a schematic diagram of a sixth application scenario of interleaving mapping in an embodiment of the present application;

[0047] FIG11 is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in an embodiment of the present application;

[0048] FIG12 is a schematic diagram of an implementation method of data distribution in an embodiment of the present application;

[0049] FIG13 is a schematic structural diagram of a data mapping device according to an embodiment of the present application;

[0050] FIG14 is another structural diagram of the data mapping device in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application provide a data mapping method and related devices that can achieve a higher coding gain while maintaining good compatibility, and at the same time ensure resistance to channel burst errors. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or sequence. It should be understood that the above terms can be interchangeable where appropriate so that the embodiments described in this application can be implemented in an order other than that described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0052] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in FIG1 , the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also referred to as a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also referred to as a client-side chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also referred to as a client-side device (host device). The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module may be an 800ZR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in the communication system may support bidirectional transmission or unidirectional transmission, without limitation herein.

[0053] FIG2 is a schematic diagram of another communication system used in an embodiment of the present application. As shown in FIG2 , at the transmitting end, a signal source provides a data stream to be transmitted; a transmitting data processor receives the data stream and performs data processing including encoding, interleaving, and modulation on it to obtain a symbol data stream, which is then sent to a transmitting signal processor for framing. The signal is then transmitted through a channel to a receiving device. After receiving a distorted signal caused by noise or other damage in the channel, the receiving device sends it to a receiving signal processor for dispersion compensation, synchronization, phase recovery, and other operations. The signal is then sent to a receiving data processor for demodulation, deinterleaving, and decoding. The original data is then recovered and sent to the destination. The transmitting data processing and transmitting signal processing shown in FIG2 can be applied to the transmitting processing module 02 shown in FIG1 , and the receiving data processing and receiving signal processing shown in FIG2 can be applied to the receiving processing module 04 shown in FIG1 .

[0054] FIG3 is a schematic diagram of an implementation of transmitting-end data processing and receiving-end data processing in an embodiment of the present application. As shown in FIG3 , the transmitting-end data processing operations include performing outer code encoding, inner code encoding, symbol mapping, and channel interleaving on the input data stream. The receiving-end data processing operations include performing symbol inverse mapping, channel deinterleaving, inner code decoding, and outer code decoding on the input data stream. In some possible scenarios, the transmitting-end data processing may also perform operations such as padding bit insertion, scrambling, and convolution interleaving between outer code encoding and inner code encoding. In this case, the receiving-end data processing also requires performing corresponding inverse transform operations.

[0055] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operations and the channel transmission medium. The entity performing the inner code operations is closer to the channel transmission medium, while the entity performing the outer code operations is farther away. In the embodiment of this application, using Figure 1 as an example, the transmitting processing module 02 encodes the data twice before sending it to the channel transmission medium. The data encoded first by the transmitting processing module 02 is farther away from the channel transmission medium, while the data encoded later by the transmitting processing module 02 is closer to the channel transmission medium. Therefore, the data encoded first by the transmitting processing module 02 is referred to as outer-coded data, while the data encoded later by the transmitting processing module 02 is referred to as inner-coded data. Correspondingly, the data decoded first by the receiving processing module 04 is referred to as inner-coded data, while the data decoded later by the receiving processing module 04 is referred to as outer-coded data. In one possible implementation, both the inner and outer codes described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting end processing module 02 may use staircase code for outer code encoding, use Hamming code for inner code encoding, or use Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding.

[0056] It should be noted that the above content is an exemplary description of the application scenario of the data mapping method provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the data mapping method. A person skilled in the art will know that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one. The following mainly introduces the data mapping method applied to the data sending end. The data inverse mapping method applied to the receiving end can be understood as the inverse operation of the data mapping method of the sending end. On the basis of the determination of the data mapping method of the sending end, the data inverse mapping method of the receiving end is also clear. This application will no longer provide a detailed introduction to the data inverse mapping method of the receiving end.

[0057] Figure 4 is a schematic flow chart of a data mapping method provided in an embodiment of the present application. The data mapping method includes the following steps, which are described in detail below. It should be understood that, for ease of explanation, the first FEC encoding described below can be considered the outer code encoding described above, and the second FEC encoding described below can be considered the inner code encoding described above. The following description can be understood based on this.

[0058] 101. Obtain a first data stream that has undergone first FEC encoding.

[0059] It should be understood that this application does not limit the specific implementation of the outer code encoding. As an example, the outer code encoding can specifically adopt staircase (512, 510) encoding. In some possible scenarios, the first data stream after outer code encoding can also be called an encoded data frame, and the bits in the encoded data frame are distributed in rows and columns.

[0060] 102. Perform second FEC encoding on the first data stream to obtain a second data stream.

[0061] In an embodiment of the present application, the second data stream encoded by the inner code includes L inner codewords, where L is an integer multiple of 8. Each codeword includes k information bits and nk check bits, totaling n bits, where n is not divisible by 8. Each codeword includes r bit subsets, each bit subset includes d bits, and the number of bits included in each codeword is n = r × d. Specifically, d can be the greatest common divisor of n and 8, for example, d = 1, 2, or 4.

[0062] In a possible implementation manner, the inner code encoding of the embodiment of the present application may specifically adopt GF(2 m ) BCH coding or extended BCH coding with error correction of t=2 bits increases the error correction capability of the inner code word to t=2 bits, that is, an inner code word can correct errors of t=2 bits at most, thus improving the performance of concatenated coding. GF refers to a finite field, also known as a Galois field, 2 m Indicates the order of the finite field. The nk parity bits in the inner codeword using BCH encoding do not include the cyclic redundancy check (CRC) extended check bit. In the inner codeword using extended BCH encoding, the nk parity bits include a 1-bit or 2-bit CRC extended check bit. If the nk parity bits do not include the CRC extended check bit, then nk = m × t; if the nk parity bits include a 1-bit CRC extended check bit, then nk = m × t + 1; if the nk parity bits include a 2-bit CRC extended check bit, then nk = m × t + 2.

[0063] As an example, taking k=119 as an example, if d=1, that is, the length of the inner code word is an odd number of bits, the following Table 1 provides several possible inner code encoding schemes. Among them, n represents the length of the inner code word, k represents the information sequence length of the inner code word, the no extension in the note means that there is no CRC extension check bit in the check sequence, the single-bit extension in the note means that there is a 1-bit CRC extension check bit in the check sequence, and the double-bit extension in the note means that there are 2-bit CRC extension check bits in the check sequence. Schemes 1 and 2 in Table 1 are built on GF(2 8 ), Schemes 3 and 4 in Table 1 are constructed on GF(2 7 )superior.

[0064] Table 1

[0065] As another example, taking k=119 as an example, if d=2, the length n of the inner code word can be 134, and there is a 1-bit CRC extended check bit in the check sequence. This scheme is built on GF(2 7 )superior.

[0066] 103. Interleave and map the L codewords to obtain n×L / 8 DP-16QAM symbols.

[0067] It should be understood that the symbol mapping method includes but is not limited to Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM), and further polarization symbol division is performed to obtain dual-polarization (DP) symbols, such as DP-QPSK, DP-8QAM, DP-16QAM, DP-32QAM, and DP-64QAM. The embodiment of the present application is mainly introduced using DP-16QAM symbols as an example.

[0068] Specifically, any one of the X-polarization direction I-phase component, the X-polarization direction Q-phase component, the Y-polarization direction I-phase component, and the Y-polarization direction Q-phase component of each DP-16QAM symbol is mapped from two bits in the L codewords, and each DP-16QAM symbol is mapped from eight bits from eight codewords. The X-polarization direction and the Y-polarization direction are orthogonal to each other, and any one component of the DP-16QAM symbol can also be referred to as a PAM4 symbol component.

[0069] In the embodiment of the present application, a bit subset of d bits is used as the minimum granularity for interleaving mapping in order to minimize the implementation complexity of interleaving. That is, when the length n of the inner code word is a multiple of 4, the interleaving mapping is performed with d = 4 bits or the equivalent of one 16QAM symbol as the minimum granularity. When the length n of the inner code word is a multiple of 2, the interleaving mapping is performed with d = 2 bits or the equivalent of one PAM4 symbol as the minimum granularity. When the length n of the inner code word is an odd number, that is, when d = 1, the interleaving mapping is performed with a single bit as the minimum granularity.

[0070] It should be noted that the interleaving mapping mentioned here can actually be a single operation. Alternatively, the interleaving mapping can also include multiple operations. For example, the interleaving mapping includes symbol mapping, polarization division, and interleaving operations. In one possible implementation, the L codewords are first interleaved to disrupt the order of the L codewords, and then the interleaved L codewords are symbol mapped and polarization divided to obtain the required n×L / 8 DP-16QAM symbols. In another possible implementation, the L codewords are symbol mapped and polarization divided, and then interleaved to obtain the required n×L / 8 DP-16QAM symbols.

[0071] It should be noted that the interleaving mapping designed in the embodiment of the present application mainly considers two aspects. The first consideration is to map the bits in each codeword as evenly as possible to the most significant bit (MSB) and the least significant bit (LSB) of the four polarization components in the n×L / 8 DP-16QAM symbols. Since the MSB and LSB have different abilities to resist noise, mapping the bits in each inner codeword to the MSB and LSB on average can maximize the performance of the encoding and decoding. The second consideration is that the number of bits from any codeword in the 2×n×L / 8 bits included in any polarization component in the n×L / 8 DP-16QAM symbols is as close or identical as possible, and the number of bits of each codeword mapped to any polarization component in the n×L / 8 DP-16QAM symbols is as close or identical as possible, which is conducive to reducing the performance degradation caused by continuous errors. The following further introduces these two considerations in detail.

[0072] Regarding the first aspect, L / 2 of the L inner code words can be recorded as first-category code words, and the other L / 2 of the L inner code words can be recorded as second-category code words. bits are mapped to the MSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the MSBs of the four polarization components in n×L / 8 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in n×L / 8 DP-16QAM symbols. Indicates rounding down. It should be understood that in the scenario where d=2 or 4, that is, n is an even number, the above and are equal to

[0073] For the second consideration, the number of bits from any codeword in the 2×n×L / 8 bits included in any polarization component of n×L / 8 DP-16QAM symbols is recorded as w, and the number of bits mapped from each codeword to any polarization component of n×L / 8 DP-16QAM symbols is recorded as r. In the scenario of d=1, In the scenario where d=2, or or In the scenario where d=4, or or

[0074] The following provides several specific interleaving mapping methods based on different values ​​of d. It should be understood that the following interleaving mapping methods are all introduced based on L=8 as an example. Indicates the lth PAM4 symbol component of the I-path component in the X polarization direction among n DP-16QAM symbols, Indicates the lth PAM4 symbol component of the Q-path component in the X polarization direction among n DP-16QAM symbols, Indicates the lth PAM4 symbol component of the I-path component in the Y polarization direction among n DP-16QAM symbols, Represents the lth PAM4 symbol component of the Q-path component in the Y polarization direction among n DP-16QAM symbols, 0≤l≤n-1, a%b represents a modulo b, and a^b represents the XOR of a and b. The solid and dotted boxes in Figures 5-8 below are used to distinguish the bits mapped to the MSB and LSB of the 4 polarization components in the DP-16QAM symbol, and the different shaded areas in Figures 5-8 are used to distinguish the bits of the 4 polarization components in the DP-16QAM symbol. It should also be understood that for the conditions satisfied by the interleaving mapping methods of XOR shift and cyclic shift introduced in the following application scenarios, the conditions provided in the embodiments of the present application are only one possible implementation method. In addition, those skilled in the art can also flexibly transform the conditions provided in the embodiments of the present application to achieve the effects after interleaving mapping shown in Figures 5-8, which will not be listed one by one here.

[0075] FIG5 is a schematic diagram of the first application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG5 , taking n=135 as an example, an XOR shift method is used for interleaving mapping in a scenario where d=1. Specifically, the XOR shift interleaving mapping satisfies the following conditions:

[0076] Obtained by mapping the lth bit of the 0^(l%8)th codeword and the lth bit of the 1^(l%8)th codeword;

[0077] Obtained by mapping the lth bit of the 2^(l%8)th codeword and the lth bit of the 3^(l%8)th codeword;

[0078] Obtained by mapping the lth bit of the 4^(l%8)th codeword and the lth bit of the 5^(l%8)th codeword;

[0079] Obtained by mapping the lth bit of the 6^(l%8)th codeword and the lth bit of the 7^(l%8)th codeword.

[0080] FIG6 is a schematic diagram of a second application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG6 , taking n=135 as an example, cyclic shift is used for interleaving mapping in a scenario where d=1. Specifically, the cyclic shift interleaving mapping satisfies the following conditions:

[0081] Obtained by mapping the lth bit of the (0+1)%8th codeword and the lth bit of the (1+1)%8th codeword;

[0082] Obtained by mapping the lth bit of the (2+1)%8th codeword and the lth bit of the (3+1)%8th codeword;

[0083] Obtained by mapping the lth bit of the (4+1)%8th codeword and the lth bit of the (5+1)%8th codeword;

[0084] It is obtained by mapping the lth bit of the (6+1)%8th codeword and the lth bit of the (7+1)%8th codeword.

[0085] It should be noted that, in the embodiments shown in FIG. 5 and FIG. 6 , X I ,X Q ,Y I ,Y Q Of the 2×135=270 bits corresponding to each signal, the number of bits from any codeword is 33 or 34, satisfying From the perspective of codewords, the number of bits in each codeword that are ultimately mapped to any one of the four components is 33 or 34. In addition, the first type of codewords bits are mapped to the MSB of the four polarization components in 135 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in 135 DP-16QAM symbols. bits are mapped to the MSB of the four polarization components in 135 DP-16QAM symbols. The bits are mapped to the LSBs of the four polarization components in the 135 DP-16QAM symbols.

[0086] FIG7 is a schematic diagram of the third application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG7 , taking n=134 as an example, an XOR shift method is used for interleaving mapping in a scenario where d=2. Specifically, the XOR shift interleaving mapping satisfies the following conditions:

[0087] By The first codeword bits and Bit mapping is obtained;

[0088] By The first codeword bits and Bit mapping is obtained;

[0089] By The first codeword bits and Bit mapping is obtained;

[0090] By The first codeword bits and The bit map is obtained.

[0091] FIG8 is a schematic diagram of the fourth application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG8 , taking n=134 as an example, cyclic shift is used for interleaving mapping in the scenario of d=2. Specifically, the cyclic shift interleaving mapping satisfies the following conditions:

[0092] By The first codeword bits and Bit mapping is obtained;

[0093] By The first codeword bits and Bit mapping is obtained;

[0094] By The first codeword bits and Bit mapping is obtained;

[0095] By The first codeword bits and The bit map is obtained.

[0096] It should be noted that, in the embodiments shown in FIG. 7 and FIG. 8 , X I ,X Q ,Y I ,Y Q Among the 2×134=268 bits corresponding to each signal in , the number of bits from any codeword is or From the perspective of codewords, the number of bits in each codeword that are ultimately mapped to any one of the four components is or In addition, each codeword bits are mapped to the MSBs of the four polarization components in 134 DP-16QAM symbols. The bits are mapped to the LSBs of the four polarization components in the 135 DP-16QAM symbols.

[0097] For the scenario where d=4, no further figures are provided. Based on the above Figures 5-8, the transformation can be performed according to the actual value of n. The interleaving mapping provided here uses a cyclic shift method. As for the interleaving mapping using an XOR shift method, the transformation can be based on the embodiments shown in Figures 5 or 7. Specifically, the cyclic shift interleaving mapping meets the following conditions:

[0098] By The first codeword bits and Bit mapping is obtained;

[0099] By The first codeword bits and Bit mapping is obtained;

[0100] By The first codeword bits and Bit mapping is obtained;

[0101] By The first codeword bits and The bit map is obtained.

[0102] Figures 5-8 above provide several implementations of interleaving mapping in the scenario where L = 8. Below is an implementation of interleaving mapping in the scenario where L = 16, taking d = 1 as an example. Implementations with other values ​​for L and d can be flexibly modified based on the embodiments provided in this application, and will not be described in detail here.

[0103] FIG9 is a schematic diagram of the fifth application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG9 , taking n=135 as an example, an XOR shift method is used for interleaving mapping in the scenario of d=1. Specifically, the XOR shift interleaving mapping satisfies the following conditions:

[0104] By The first codeword bits and The first codeword Bit mapping is obtained;

[0105] By The first codeword bits and The first codeword Bit mapping is obtained;

[0106] By The first codeword bits and The first codeword Bit mapping is obtained;

[0107] By The first codeword bits and The first codeword The bit map is obtained.

[0108] FIG10 is a schematic diagram of the sixth application scenario of interleaving mapping in an embodiment of the present application. As shown in FIG10 , taking n=135 as an example, cyclic shift is used for interleaving mapping in the scenario of d=1. Specifically, the cyclic shift interleaving mapping satisfies the following conditions:

[0109] By The first codeword bits and The first codeword Bit mapping is obtained;

[0110] By The first codeword bits and The first codeword Bit mapping is obtained;

[0111] By The first codeword bits and The first codeword Bit mapping is obtained;

[0112] By The first codeword bits and The first codeword The bit map is obtained.

[0113] It should be noted that, in the embodiments shown in FIG. 9 and FIG. 10 , X I ,X Q ,Y I ,Y Q Each signal corresponds to bits, the number of bits from any codeword is 33 or 34. From the perspective of codewords, the number of bits in each codeword that are ultimately mapped to any one of the four components is 33 or 34, satisfying In addition, the first type of codewords bits are mapped to the MSBs of the four polarization components in the 270 DP-16QAM symbols. bits are mapped to the LSBs of the four polarization components in the 270 DP-16QAM symbols. bits are mapped to the MSBs of the four polarization components in the 270 DP-16QAM symbols. The bits are mapped to the LSBs of the four polarization components in 540 DP-16QAM symbols.

[0114] It should be noted that in the embodiments of the present application, in addition to steps 101-103 described above, other operations may be performed between outer code encoding and inner code encoding. For example, at least one padding bit may be added to the data stream after outer code encoding. The specific number of padding bits depends on the actual application and is not limited here. For another example, after adding padding bits, the data stream may be scrambled. The specific scrambling method depends on the actual application and is not limited here. For another example, after scrambling, the data stream may be convolutionally interleaved. The specific convolutional interleaving method depends on the actual application and is not limited here.

[0115] The above describes the data mapping method provided in the embodiments of the present application. It should be understood that in some possible scenarios, considering the potential need for FEC schemes to be compatible with throughput rates such as 1.6T, 800G, and 400G, as well as the issue of hardware implementation at ultra-high throughput, a multi-channel parallel data processing solution can also be proposed based on the aforementioned embodiments. Figure 11 is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in the embodiments of the present application. As shown in Figure 11, the input data stream is first distributed to obtain four data streams, and then each distributed data stream is processed according to the data processing method shown in Figure 3.

[0116] Figure 12 is a schematic diagram of an implementation method of data distribution in an embodiment of the present application. As shown in Figure 12, first obtain continuous 4×119×10280 bits of data, and then poll and distribute them according to the granularity of h bits to obtain 4 data frames. The bits in each data frame are arranged into 119 rows and 10280 columns. The 4 data frames are respectively outer-coded to obtain 4 coded data frames, and then each coded data frame is subsequently processed in the manner shown in Figure 3. It should be understood that 10280% (4×h) = 0, for example, h = 1, 257, 514 or 1285. This solution can be well compatible with throughput rates such as 1.6T, 800G, and 400G. As an example, when the input data frame is a 1.6T service, the data frame can be distributed into 4 channels for processing as shown in Figure 10. As another example, when the input data frame is an 800G service, the data frame can be distributed into 2 channels for processing, and the other 2 channels can be turned off to save power consumption. As another example, when the input data frame is a 400G service, data frame distribution can be omitted, and the data frame can be directly processed as shown in Figure 3, and the other three paths can be turned off to save power consumption.

[0117] Figure 13 is a structural diagram of a data mapping device in an embodiment of the present application. As shown in Figure 13, the data mapping device includes an acquisition unit 201, an encoding unit 202 and an interleaving mapping unit 203. The acquisition unit 201 is used to perform the operation of the above-mentioned step 101, the encoding unit 202 is used to perform the operation of the above-mentioned step 102, and the interleaving mapping unit 203 is used to perform the operation of the above-mentioned step 103. It should be understood that the data mapping device provided by the present application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or can be independent physical units, or two or more functional units can be integrated into a processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0118] Figure 14 is another structural diagram of the data mapping device in an embodiment of the present application. As shown in Figure 14, the data mapping device includes a processor 301 and a transceiver 302. The processor 301 and the transceiver 302 are interconnected via a line. Specifically, the transceiver 302 is used to perform data transmission and reception operations, and the processor 301 is used to perform other operations besides data transmission and reception. In one possible embodiment, the processor 301 may include the encoding unit 202 and the interleaving mapping unit 203 shown in Figure 13 above, and the transceiver 302 includes the acquisition unit 201 shown in Figure 13 above. Optionally, the data mapping device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0119] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 301 described above. When the chip integrates memory, it can perform the method steps of any one or more of the aforementioned embodiments. When the chip does not integrate memory, it can be connected to an external memory via an interface. The chip implements the actions performed by the transmitting device or receiving device in the aforementioned embodiments based on program code stored in the external memory.

[0120] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data mapping method, characterized in that: include: Acquire a first data stream that has been encoded by a first forward error correction (FEC); Performing a second FEC encoding on the first data stream to obtain a second data stream, the second data stream comprising L codewords subjected to the second FEC encoding, L being an integer multiple of 8, each of the codewords comprising n bits, and n being an odd number greater than 1; The L codewords are interleaved and mapped to obtain n×L / 8 dual-polarization DP-16QAM symbols, and any one of the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of each DP-16QAM symbol is obtained by mapping 2 bits in the L codewords, and each DP-16QAM is obtained by mapping 8 bits from 8 of the codewords respectively.

2. The method according to claim 1, characterized in that: The L code words include L / 2 first-category code words and L / 2 second-category code words, each of which has bits are mapped to the high-order bits MSB of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the first codewords bits are mapped to the low-order bits LSB of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the second-category codewords bits are mapped to the MSBs of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the second type of codewords bits are mapped to the LSBs of the 4 polarization components in the n×L / 8 DP-16QAM symbols, where: Indicates rounding down. Indicates rounding up.

3. The method according to claim 1 or 2, characterized in that: The number of bits from any codeword among the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is w, 4. The method according to any one of claims 1 to 3, characterized in that The number of bits of each codeword mapped to any polarization component in the n×L / 8 DP-16QAM symbols is r, 5. The method according to any one of claims 1 to 4, characterized in that Each consecutive L / 8 DP-16QAM symbols in the n×L / 8 DP-16QAM symbols are mapped by L bits respectively from the L codewords.

6. The method according to any one of claims 1 to 5, characterized in that By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word Bit mapping is obtained; in, represents the lth pulse amplitude modulation PAM4 symbol component of the I-path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, a%b means a modulo b, and a^b means the exclusive OR of a and b.

7. The method according to any one of claims 1 to 5, characterized in that By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word Bit mapping is obtained; in, represents the lth PAM4 symbol component of the I-path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, 8. The method according to any one of claims 1 to 7, characterized in that The number of information bits in the codeword is k=119, n=133, 135 or 137.

9. The method according to any one of claims 1 to 8, characterized in that The first FEC coding adopts staircase (512, 510) coding.

10. The method according to any one of claims 1 to 9, characterized in that The first data stream is bit-filled after being encoded by the first FEC, wherein the number of filled bits is greater than or equal to 1.

11. The method according to any one of claims 1 to 10, characterized in that The first data stream is also subjected to convolution interleaving after being encoded by the first FEC.

12. The method according to any one of claims 1 to 11, characterized in that Before acquiring the first data stream encoded by the first FEC, the method further includes: Performing data distribution on the input data stream to obtain 4 distribution data streams, wherein every 4 consecutive bits in the input data stream are distributed to the 4 distribution data streams respectively; The first FEC encoding is performed on each of the distribution data streams.

13. A data mapping device, characterized in that: The data mapping device comprises: an acquisition unit, an encoding unit and an interleaving mapping unit; The acquisition unit is used to: acquire a first data stream that has been encoded by a first forward error correction (FEC); The encoding unit is used to: perform second FEC encoding on the first data stream to obtain a second data stream, the second data stream includes L code words encoded by the second FEC, L is an integer multiple of 8, each of the code words includes n bits, and n is an odd number greater than 1; The interleaving and mapping unit is used to: interleave and map the L codewords to obtain n×L / 8 dual-polarization DP-16QAM symbols, wherein any one of the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of each DP-16QAM symbol is obtained by mapping 2 bits in the L codewords, and each DP-16QAM is obtained by mapping 8 bits from 8 of the codewords respectively.

14. The data mapping device according to claim 13, characterized in that: The L code words include L / 2 first-category code words and L / 2 second-category code words, each of which has bits are mapped to the high-order bits MSB of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the first codewords bits are mapped to the low-order bits LSB of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the second-category codewords bits are mapped to the MSBs of the four polarization components in the n×L / 8 DP-16QAM symbols, and each of the second type of codewords bits are mapped to the LSBs of the 4 polarization components in the n×L / 8 DP-16QAM symbols, where: Indicates rounding down. Indicates rounding up.

15. The data mapping device according to claim 13 or 14, characterized in that: The number of bits from any codeword among the 2×n×L / 8 bits included in any polarization component of the n×L / 8 DP-16QAM symbols is w, 16. The data mapping device according to any one of claims 13 to 15, characterized in that: The number of bits of each codeword mapped to any polarization component in the n×L / 8 DP-16QAM symbols is r, 17. The data mapping device according to any one of claims 13 to 16, characterized in that: Each consecutive L / 8 DP-16QAM symbols in the n×L / 8 DP-16QAM symbols are mapped by L bits respectively from the L codewords.

18. The data mapping device according to any one of claims 13 to 17, characterized in that: By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word Bit mapping is obtained; in, represents the lth pulse amplitude modulation PAM4 symbol component of the I-path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, a%b means a modulo b, and a^b means the exclusive OR of a and b.

19. The data mapping device according to any one of claims 13 to 17, characterized in that: By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word The bit mapping is obtained. By The code word bits and The code word Bit mapping is obtained; in, represents the lth PAM4 symbol component of the I-path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q path component in the X polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the I-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, represents the lth PAM4 symbol component of the Q-path component in the Y polarization direction among the n×L / 8 DP-16QAM symbols, 20. The data mapping device according to any one of claims 13 to 19, characterized in that: The number of information bits in the codeword is k=119, n=133, 135 or 137.

21. The data mapping device according to any one of claims 13 to 20, characterized in that: The first FEC coding adopts staircase (512, 510) coding.

22. The data mapping device according to any one of claims 13 to 21, characterized in that: The first data stream is bit-filled after being encoded by the first FEC, wherein the number of filled bits is greater than or equal to 1.

23. The data mapping device according to any one of claims 13 to 22, characterized in that: The first data stream is also subjected to convolution interleaving after being encoded by the first FEC.

24. The data mapping device according to any one of claims 13 to 23, characterized in that: The data mapping device further includes a processing unit, which is used to: Performing data distribution on the input data stream to obtain 4 distribution data streams, wherein every 4 consecutive bits in the input data stream are distributed to the 4 distribution data streams respectively; The first FEC encoding is performed on each of the distribution data streams.

25. A chip, characterized in that: The chip includes a processor and a memory, wherein the memory and the processor are connected to each other via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 12.

Images