Method and apparatus for predicting memory fault, and chip, device and storage medium

Abstract

Disclosed are a method and apparatus for predicting a memory fault, and a chip, a device and a storage medium, which belong to the technical field of computers. The method comprises: acquiring an error position distribution of an error correction unit associated with a memory, wherein the memory comprises at least one memory module, the error correction unit comprises a plurality of data bits obtained from a plurality of storage units of the memory by means of a plurality of continuous burst reads, each data bit corresponding to one storage unit in the memory, the error position distribution is used for indicating the positions of error data bits among the plurality of data bits, and the error position distribution causes the occurrence of a CE in the memory; acquiring a memory fault model, wherein the memory fault model comprises at least one reference position distribution, the reference position distribution being associated with a UCE of the memory; and on the basis of the similarity between the error position distribution and the at least one reference position distribution, outputting a prediction result, wherein the prediction result is used for indicating the probability of the UCE occurring in the memory. The method facilitates an improvement in the timeliness of memory fault prediction.

Description

Memory failure prediction method, device, chip, equipment and storage medium

[0001] This application claims priority to Chinese patent application No. 202311286869.2 filed on September 28, 2023, entitled “Method and device, chip, equipment and storage medium for predicting memory failures,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a memory failure prediction method and apparatus, chip, device, and storage medium. Background Art

[0003] With the development of Internet technology, server memory capacity is increasing. Memory failure is one of the main causes of server failure. To ensure normal server operation, it is necessary to predict memory failures before they occur.

[0004] In the related art, memory fault prediction can adopt the following method: based on multiple correctable error (CE) information of the memory of the device under test within a set time period, determine the memory fault characteristics of the device under test at multiple memory granularities, where the memory granularity includes the whole machine memory granularity, memory bar granularity, physical array granularity and memory particle granularity; based on the resource static information of the device under test and the memory fault characteristics at various memory granularities, predict the probability of uncorrectable error (UCE) of the device under test.

[0005] Since this method needs to collect multiple CE information within a set time period first, the CE information collection process is long, resulting in poor timeliness of the memory fault prediction method.

[0006] Summary of the Invention

[0007] The present application provides a memory fault prediction method and apparatus, chip, device and storage medium, which are conducive to improving the timeliness of memory fault prediction.

[0008] In a first aspect, the present application provides a method for predicting memory faults. The method includes: obtaining an error location distribution of an error correction unit associated with a memory, wherein the memory includes at least one memory cell, each memory cell includes multiple storage cells arranged in an array, the error correction unit includes multiple data bits obtained from the multiple storage cells of the at least one memory cell through multiple consecutive burst reads, each of the multiple data bits corresponding to one of the multiple storage cells of the at least one memory cell. That is, each data bit corresponds to one storage cell, and different data bits correspond to different storage cells. The error location distribution indicates the location of an erroneous data bit among the multiple data bits, and the error location distribution causes the memory to experience a correctable error (CE); obtaining a memory fault model, wherein the memory fault model includes at least one reference location distribution, wherein the reference location distribution is associated with an uncorrectable error (UCE) of the memory; and outputting a prediction result based on the similarity between the error location distribution and at least one reference location distribution, wherein the prediction result indicates the probability of the memory experiencing an UCE.

[0009] In this application, since the reference position distribution is associated with UCE, the similarity between the error position distribution when a memory error code (CE) occurs and at least one of the reference position distributions is correlated with the probability of a memory error code (UCE) occurring, and can reflect the probability of a memory error code occurring. The higher the similarity between the error position distribution and the reference position distribution, the higher the probability of a memory error code occurring. Conversely, the lower the similarity between the error position distribution of the error correction unit and the reference position distribution, the lower the probability of a memory error code occurring. Therefore, the probability of a memory error code occurring can be predicted based on the similarity between the error position distribution when a memory error code occurs and at least one of the reference position distributions. On the one hand, as soon as a memory error code occurs, memory faults can be predicted based on the error position distribution of the error correction unit corresponding to the CE, without having to wait for the collection of a large amount of CE information. This improves the timeliness of memory fault prediction. On the other hand, predicting memory faults based on the error position distribution of the error correction unit, that is, based on the mechanism of UCE generation, helps improve the accuracy of memory fault prediction. This prediction method can be combined with other fault prediction methods in related technologies to further improve the accuracy of memory fault prediction.

[0010] Optionally, associating the reference location distribution with a memory UCE means that the reference location distribution is the error location distribution when the memory UCE occurs, or the reference location distribution is the error location distribution corresponding to CEs that occurred within a set time period before the memory UCE occurred. If a CE appeared within a set time period before the memory UCE occurred, it indicates that the CE may subsequently evolve into a UCE. Therefore, the error location distribution corresponding to the CE can be used as the reference location distribution.

[0011] Optionally, outputting a prediction result based on the similarity between the error position distribution and at least one of the reference position distributions may be performed in either of the following two ways:

[0012] The first approach involves calculating the similarity between the error location distribution and each reference location distribution, and outputting the prediction result based on the calculated similarities. For example, the highest similarity among the calculated similarities can be determined, and then the prediction result can be output based on the highest similarity. Another example is that, for each calculated similarity, the probability of a UCE occurring corresponding to each reference location distribution can be determined. The determined probabilities can then be fused to obtain a fused result, and finally, the prediction result can be output based on the fused result.

[0013] In the first approach, the error position distribution is compared with each reference position distribution to obtain the similarity between the error position distribution and each reference position distribution, which is beneficial to improving the accuracy of the fault prediction result.

[0014] The second method is to calculate the similarity between the error position distribution and each reference position distribution in the memory fault model in sequence; when the calculated similarity is higher than the similarity threshold, stop calculating the similarity and output the prediction result based on the similarity higher than the similarity threshold.

[0015] In the second method, it may be possible to obtain a prediction result without calculating the similarities corresponding to all reference position distributions, which is beneficial to improving fault prediction efficiency.

[0016] Optionally, the error position distribution of the error correction unit is represented by a plurality of first elements, the plurality of first elements corresponding one-to-one to the plurality of data bits, and each first element is used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a plurality of second elements, the plurality of first elements corresponding one-to-one to the plurality of second elements. Calculating the similarity between the error position distribution and any of the reference position distributions in the memory fault model includes: counting the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity; or counting the number of first elements in the error position distribution that are the same as the corresponding second element to obtain the similarity.

[0017] Optionally, the similarity between the error position distribution and a reference position distribution may be calculated in either of the following two ways.

[0018] In a first approach, the error position distribution is represented by a first binary sequence, where the first binary sequence includes multiple first data bits, each of which is a first element. The reference position distribution is represented by a second binary sequence, where the second binary sequence includes multiple second data bits, each of which is a second element. The Hamming distance between the first binary sequence and the second binary sequence is used as the similarity between the error position distribution and the reference position distribution.

[0019] The first method is used to calculate the similarity, which is simple and helps to simplify the process of memory fault prediction and improve the efficiency of memory fault prediction.

[0020] The second way is that the error position distribution is represented by a first graphic, which includes a plurality of first units arranged in an array, and the plurality of first units correspond one-to-one to the plurality of data bits, and each first unit is used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a second graphic, which includes a plurality of second units arranged in an array. The plurality of second units correspond one-to-one to the plurality of first units. The degree of overlap between the first graphic and the second graphic is determined, and the degree of overlap is used as the similarity between the error position distribution and the reference position distribution. The degree of overlap is proportional to the number of first fault units in the first graphic that have the same position as the second fault unit in the second graphic. The first fault unit is a first unit indicating that the corresponding data bit is an error data bit, and the second fault unit is a second unit indicating that the corresponding data bit is an error data bit.

[0021] Using the first graph and the second graph to represent the error position distribution and the reference position distribution respectively can facilitate determining the position relationship between each data bit in an error correction unit, such as being in the same burst or the same data queue (DQ).

[0022] In this second method, the overlap calculation methods can be divided into two categories. The first category is to calculate the overlap based on the number of first faulty cells in the first graph that have the same position as the second faulty cell in the second graph; the second category is to calculate the overlap based on the number of first faulty cells in the first graph that have the same position as the second faulty cell in the second graph and the number of first non-faulty cells in the first graph that have the same position as the second non-faulty cell.

[0023] These two types of overlap calculation methods correspond to two different calculation methods, so there are at least four overlap calculation methods:

[0024] The first method is to determine the overlap degree according to the number of first faulty units in the first graph that have the same position as the second faulty units in the second graph, and the number of second faulty units in the second graph.

[0025] For example, the overlap ratio can be determined as the ratio of the number of first faulty cells in the first graph that have the same position as the second faulty cells in the second graph to the number of second faulty cells in the second graph. The calculation logic is simple and easy to implement.

[0026] The second method is to determine the degree of overlap based on the number of first fault units in the first graphic that have the same position as the second fault unit in the second graphic, the relative positions of the first non-fault units in the first graphic that have the same position as the second fault unit in the second graphic and the first fault unit in the second graphic, and the number of second fault units in the second graphic.

[0027] Exemplarily, the number of first fault units in the first graph that have the same position as the second fault unit in the second graph is first determined; then, based on the relative positions of the first non-fault units in the first graph that have the same position as the second fault unit in the second graph and the first fault units in the second graph, the number of first fault units in the first graph that have the same position as the second fault unit in the second graph is adjusted to obtain an adjusted number; then, the ratio of the adjusted number to the number of second fault units in the second graph is determined as the degree of overlap.

[0028] According to the relative positions of the first non-faulty units in the first graph that are at the same position as the second faulty units in the second graph and the first faulty units in the second graph, the number of the first faulty units in the first graph that are at the same position as the second faulty units in the second graph is adjusted, so that the finally calculated overlap degree can better reflect the similarity between the error position distribution and the reference position distribution, making the memory fault prediction result more accurate.

[0029] The third method is to determine the degree of overlap based on the number of overlapping units in the first graphic and the second graphic, and the number of first units in the first graphic, wherein the overlapping units include the first faulty unit in the first graphic that is in the same position as the second faulty unit in the second graphic and the first non-faulty unit in the first graphic that is in the same position as the second non-faulty unit.

[0030] Exemplarily, the ratio of the number of overlapping units to the number of second faulty units in the second graph may be determined as the overlap degree.

[0031] The fourth method is to determine the degree of overlap based on the number of overlapping units in the first graphic and the second graphic, the relative position of the first non-faulty unit in the first graphic that is the same as the second faulty unit in the second graphic and the first faulty unit in the second graphic, and the number of first units in the first graphic.

[0032] Exemplarily, the number of overlapping units is first determined; then, based on the relative position of the first non-faulty unit in the first graph that is the same as the position of the second faulty unit in the second graph and the first faulty unit in the second graph, the number of overlapping units is adjusted to obtain an adjusted number; then, the ratio of the adjusted number to the number of second faulty units in the second graph is determined as the degree of overlap.

[0033] In the second and fourth methods, first, a first non-faulty unit is identified from the first graph, which has the same position as the second faulty unit in the second graph and whose corresponding data bits belong to the same data queue and / or the same burst. An adjustment value is determined based on the identified first non-faulty unit and a set value. The corresponding quantity is adjusted using the adjustment value, for example, by adding the corresponding quantity to the adjustment value to obtain an adjusted quantity. The set value represents the probability of an error in the identified first non-faulty unit. The adjustment value is equal to the sum of the set values ​​corresponding to the identified first non-faulty units.

[0034] Since when a data bit corresponding to a first unit is erroneous, the non-erroneous data bits located in the same DQ and / or burst are more likely to be erroneous, therefore, once the data bit that is about to be erroneous is erroneous, the corresponding first unit will overlap with the second faulty unit in the second graph. Therefore, a value (i.e., the aforementioned set value) can be set for the first non-faulty storage unit corresponding to this type of data bit to indicate its possibility of error, and the number of overlapping units can be adjusted according to the set value.

[0035] In some examples, the prediction result can be the aforementioned similarity. In other examples, the prediction result can be a risk level, which indicates the probability of a memory UCE. A higher risk level indicates a greater probability of a memory UCE; conversely, a lower risk level indicates a lower probability of a memory UCE.

[0036] When similarity is represented by Hamming distance, the risk level corresponding to the distance interval to which the Hamming distance belongs can be output based on the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level. The correspondence includes N distance intervals and N risk levels, with different distance intervals corresponding to different risk levels, where N is an integer greater than 1.

[0037] The larger the Hamming distance, the lower the similarity between the error position distribution and the reference position distribution, and the smaller the possibility of UCE. Conversely, the smaller the Hamming distance, the higher the similarity between the error position distribution and the reference position distribution, and the greater the possibility of UCE.

[0038] When the similarity is expressed by overlap, the risk level corresponding to the overlap interval to which the overlap belongs can be output based on the overlap interval to which the overlap belongs and the correspondence between the overlap interval and the risk level. The correspondence includes M overlap intervals and M risk levels, and different overlap intervals correspond to different risk levels, where M is an integer and M is greater than 1.

[0039] The greater the overlap, the higher the similarity between the error position distribution and the reference position distribution, and the greater the possibility of UCE. Conversely, the smaller the overlap, the lower the similarity between the error position distribution and the reference position distribution, and the smaller the possibility of UCE.

[0040] Optionally, the number of risk levels can be set according to actual needs, for example, it can be divided into three risk levels: high, medium and low.

[0041] In a second possible implementation, the memory fault model is a neural network model. The neural network model is trained using first and second samples. The first samples are the error location distribution of the error correction unit corresponding to a memory device that only experiences CE when a CE occurs, and the second samples are the error location distribution of the error correction unit corresponding to a memory device that experiences UCE when a CE occurs before a UCE occurs. The neural network model is used to process the error location distribution to obtain the prediction result.

[0042] The neural network model is used to predict memory faults without the need to obtain the error location distribution when the memory UCE occurs in advance, and has a wide range of applications.

[0043] In the second possible implementation, the prediction result may be a probability value of UCE occurring in the memory or a risk level indicating the probability value of UCE occurring in the memory.

[0044] In a second aspect, the present application provides a memory failure prediction device. This memory failure prediction device has the function of implementing the method described in the first aspect or any optional embodiment of the first aspect. This function can be implemented through hardware or through hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-mentioned functions.

[0045] In a third aspect, an electronic device is provided. The electronic device includes a processor and a memory. The memory is used to store software programs and modules. The processor implements the method of the first aspect or any possible implementation of the first aspect by running or executing the software programs and / or modules stored in the memory.

[0046] Optionally, there are one or more processors and one or more memories.

[0047] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0048] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated on the same chip as the processor or be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0049] In a fourth aspect, a computer program product is provided, wherein the computer program product includes computer program code, and when the computer program code is executed by a computer, the computer executes the method in the first aspect or any possible implementation of the first aspect.

[0050] In a fifth aspect, the present application provides a computer-readable storage medium, which is used to store program codes executed by a processor, wherein the program codes include instructions for implementing the method in any possible implementation of the first aspect.

[0051] In a sixth aspect, the present application provides a chip comprising a logic circuit and a power supply circuit, wherein the logic circuit is used to execute the method in any possible implementation of the first aspect above, and the power supply circuit is used to supply power to the logic circuit.

[0052] In a seventh aspect, the present application provides another chip. The chip includes an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected via an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to perform the method of any possible implementation of the first aspect described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a schematic diagram of the hardware structure of a server provided in an embodiment of the present application;

[0054] FIG2 is a flow chart of a method for predicting memory failures according to an embodiment of the present application;

[0055] FIG3 is a schematic diagram of an error correction unit provided in an embodiment of the present application;

[0056] FIG4 is a flow chart of another memory failure prediction method provided in an embodiment of the present application;

[0057] FIG5 is a graphical comparison diagram of error position distribution and reference position distribution;

[0058] FIG6 is a flow chart of another memory failure prediction method provided in an embodiment of the present application;

[0059] FIG7 is a block diagram of a memory failure prediction device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] FIG1 is a schematic diagram of the hardware structure of a server provided in an embodiment of the present application. As shown in FIG1 , the server 10 includes at least a processor 110, a memory 120, a basic input / output system (BIOS) 130, and a baseboard management controller (BMC) 140. The processor 110 and the memory 120 are connected via a bus 150. The BMC 140 and the processor 110 are respectively connected to the BIOS 130.

[0062] The processor 110 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits. Optionally, the number of processors 110 may be one or more. When the processor 110 is a CPU, the CPU may have one or more CPU cores.

[0063] The memory 120 can be used to temporarily store computer executable program code and data. The memory 120 has the characteristics of fast data read and write speed and can be used as temporary data storage space for running applications. The memory 120 can adopt one or more of the following types of memory: dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM) (DDR for short), low power DDR (LPDDR), high bandwidth memory (HBM), phase change memory (PCM), resistive random access memory (RRAM or ReRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FeRAM), nano random access memory (NRAM) or static random access memory (SRAM). In actual applications, the server 10 may include one or more memories 120. When the server 10 is configured with multiple memories 120 , the multiple memories 120 may be of the same type or different types.

[0064] In some examples, the processor 110 includes a memory controller 1101. The memory controller 1101 is used to manage the memory 120 and communicate with the processor 110. In the server 10, the processor 110 and the memory 120 exchange data through the memory controller 1101. For example, when the memory controller 1101 receives a data write request from the processor 110, it saves the data in the data write request in the memory 120. For another example, when the memory controller 1101 receives a data read request from the processor 110, it reads data from the memory 120 according to the memory address carried in the data read request and returns the read data to the processor 110.

[0065] Memory controller 1101 can detect whether errors have occurred in memory 120. Upon detecting an error in memory 120, memory controller 1101 reports the error to BIOS 130, which then reports the error to BMC 140 for processing. BMC 140 then processes the error and feeds the result back to BIOS 130. BIOS 130 then issues a command to trigger processor 110 to perform the corresponding operation. BIOS 130 then accesses memory 120 through memory controller 1101.

[0066] BMC 140 is also called an out-of-band controller. BMC 140 stores the program code of the present application solution. By executing the program code, the memory failure prediction method provided by the embodiment of the present application can be implemented. In some examples, BMC 140 can be an independent chip.

[0067] In one possible implementation, the chip may include a processor and a memory, and the processor is used to call and run the program code stored in the memory from the memory, so that the electronic device equipped with the chip executes the memory failure prediction method provided in the embodiment of the present application.

[0068] In another possible embodiment, the chip includes a logic circuit and a power supply circuit, the logic circuit is used to implement the memory failure prediction method provided in the embodiment of the present application, and the power supply circuit is electrically connected to the logic circuit for powering the logic circuit. Exemplarily, the logic circuit can be implemented by a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a discrete gate or transistor logic device, a discrete hardware component, etc. The PLD can be a complex programmable logical device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC) or any combination thereof.

[0069] The bus 150 may include a path for transmitting information between various components of the server 10 (eg, the processor 110 and the memory 120 ).

[0070] It should be noted that the memory controller 1101 in FIG. 1 is provided in the processor 110 . In other possible implementations, the memory controller 1101 may also be a device external to the processor 110 and connected to the processor 110 via a bus.

[0071] It should also be noted that the structure shown in FIG1 does not constitute a specific limitation on the server. In other embodiments of the present application, the server may include more or fewer components than shown in the figure. For example, the server may also include an external memory (such as a hard disk), or the server may combine or split certain components, or adopt a different component arrangement.

[0072] The embodiment of the present application does not limit the architecture of the server. For example, the server 10 can be an X86 architecture server or a non-X86 architecture server. The embodiment of the present application does not limit the form of the server. For example, it can be a blade server, a high-density server, a rack server, or a high-performance server.

[0073] The physical granularity of memory, from largest to smallest, is as follows: memory stick (also known as dual inline memory module (DIMM)), memory rank, memory chip (also known as memory device), memory array (bank), row or column, and memory unit (cell).

[0074] Each memory bank has at least one memory column, and each memory column can include multiple memory chips. When a memory bank has multiple memory columns, each memory column contains the same number of memory chips. The number of memory chips in each memory column varies depending on the data bit width of the memory chip. The product of the data bit width and the number of memory chips is the memory bit width. Each memory chip can be divided into multiple storage arrays. When the memory chip stores data, the data is written to the storage array in units of bits. In addition, multiple storage arrays can be divided into a storage array group (bank group). The storage array includes multiple storage cells arranged in a two-dimensional matrix. A storage cell in the storage array can be located by row and column, and each storage cell is used to store one bit of data. The smallest unit of memory failure is a storage cell in the storage array.

[0075] During the operation of the server 10, the memory 120 may malfunction. For example, in a DRAM, a memory cell is typically composed of a transistor and a capacitor. The amount of charge carried by the capacitor determines whether the memory cell is 1 or 0. Due to external environmental influences or hardware defects in the transistor, memory errors, i.e., memory failures, may occur.

[0076] When a memory failure occurs, error correction algorithms (such as error checking and correcting (ECC)) are used to correct the error. If the error is corrected, it is called error correction (CE). If the error exceeds the error correction capability of the error correction algorithm, it cannot be corrected, which is called error correction (UCE). UCE can cause problems such as device downtime. Therefore, it is necessary to predict the possibility of UCE before it occurs, that is, to perform memory failure prediction, to reduce the occurrence of device downtime and minimize the losses caused by memory failure.

[0077] FIG2 is a flow chart of a memory fault prediction method provided in an embodiment of the present application. The method can be executed by the BMC in FIG1 . As shown in FIG2 , the method includes the following steps:

[0078] 201. Obtain error position distribution of an error correction unit associated with a memory.

[0079] The memory includes at least one memory chip. That is, the memory here can refer to a single memory chip or a memory bar including multiple memory chips. Each memory chip includes multiple storage cells arranged in an array.

[0080] An error correction unit (ECU) is the minimum error correction unit required by the error correction algorithm used by the memory. A memory-associated ECU is composed of data burst-read from a portion of the memory's storage cells. Each ECU includes multiple data bits obtained through multiple consecutive burst reads from multiple storage cells in each memory chip of the memory. These multiple data bits each correspond to a storage cell in the memory. That is, each data bit corresponds to a storage cell, and different data bits correspond to different storage cells. Here, a data bit is a single bit of data read from the corresponding storage cell.

[0081] Each error correction unit includes multiple bursts, each containing multiple data bits, which correspond one-to-one to multiple data channels in the memory. For example, the number of bursts in an error correction unit can be equal to half the burst length. A burst refers to the continuous transmission of data between adjacent memory cells in the same row. The number of consecutive transmission cycles is the burst length.

[0082] For example, as shown in Figure 3, assume that a memory bank includes a memory rank, and the memory rank includes 18 memory chips, of which 16 memory chips (chips 0-15) are used to store valid data, 1 memory chip is used to store parity data, and 1 memory chip is used to store cyclic redundancy check (CRC) data.

[0083] For a single memory access, the memory generates multiple bursts in batches (i.e., a single memory access generates multiple burst reads, each corresponding to a burst). Each burst typically consists of multiple data bits (for example, 64 data bits in Figure 3). The number of data bits contained in each burst is equal to the sum of the number of DQs (Directional Response Queues) across all memory chips in the memory. Here, each DQ represents a data transmission channel in a memory chip, and each data transmission channel corresponds to a data transmission pin on a memory chip. Different bit positions in each burst correspond to different DQs, and the same bit positions in different bursts share a single DQ. In Figure 3, the data corresponding to each burst includes 64 bits of valid data (i.e., D0-D63), 4 bits of parity data (i.e., P0-P3), and 4 bits of CRC data (i.e., C0-C3). If the burst length is 8, the data corresponding to the four bursts constitute an error correction unit, and each error correction unit contains 288 bits of data. For example, the data corresponding to bursts 0-4 constitutes an error correction unit, and the data corresponding to bursts 4-7 constitutes an error correction unit. Here, valid data refers to data other than check data.

[0084] The error position distribution is used to indicate positions of erroneous data bits among all data bits of the error correction unit, and the error position distribution causes CE to occur in the memory.

[0085] Due to the IO characteristics of DRAM, data bits related to a burst or a DQ are prone to errors together. When the locations of the erroneous data bits in multiple data bits corresponding to the same memory chip in an error correction unit are distributed over multiple bursts and / or multiple DQ errors, UCE may occur in the memory chip.

[0086] When a data bit corresponding to a memory chip in an error correction unit is erroneous, the BIOS will report the fault information to the BMC. The fault information includes the fault location, fault time, and error location distribution. The fault location refers to the physical address where the memory fault occurs. For example, the physical address is used to indicate the bank, row and / or column, memory chip, memory column, and memory bar where the storage unit corresponding to the erroneous data bit is located. The fault time refers to the time when the memory fault occurs. During implementation, the error location distribution may only include the locations of all data bits corresponding to a memory chip where the erroneous data bit is located in an error correction unit, and the other data bits of the error correction unit are considered to be free of errors. Therefore, the error location distribution can describe the location of the erroneous data bits of each data bit of an error correction unit.

[0087] During implementation, the error location distribution may be represented by a portion of the value of a register used to record memory error information.

[0088] For example, in Figure 3, the first box from top to bottom represents error correction unit 0, and the second box represents error correction unit 1. If memory cell 0 has an error in error correction unit 0, the error position distribution is used to indicate the position of the erroneous data bit of memory cell 0 among the 16 data bits in error correction unit 0.

[0089] 202 : Obtain a memory fault model, where the memory fault model includes at least one reference position distribution, and the at least one reference position distribution is associated with a UCE of the memory.

[0090] In a first possible implementation manner, the association between the reference position distribution and the UCE of the memory means that the reference position distribution is an error position distribution that may cause the UCE to occur in the memory.

[0091] Each reference location distribution can be determined through fault injection testing. For example, test data is written into memory using error correction units (ECUs). During this process, a fault injection tool is used to tamper with specific locations within the test data, causing errors in the memory data. If an error code (UCE) occurs in the memory after a certain test data write, the corresponding error location distribution is determined as the reference location distribution. During implementation, all possible error location combinations can be traversed to obtain all possible reference location distributions, thereby generating a memory fault model.

[0092] In a second possible implementation, the reference location distribution is associated with the UCE of the memory, and refers to the error location distribution corresponding to the CE associated with the UCE. The CE associated with the UCE means that after the error location distribution corresponding to the CE appears, the memory will experience the UCE, or the probability of the memory experiencing the UCE is high.

[0093] In this second possible implementation, the reference location distribution can be obtained by training a neural network model. For example, the error location distribution of CE in a memory device experiencing UCE within a set period of time before the UCE is used as positive samples, and the error location distribution of CE in a memory device experiencing only CE is used as negative samples. The initial neural network model is trained to obtain a memory fault model. This memory fault model can represent at least one reference location distribution.

[0094] Alternatively, the error position distribution of CEs that occurred within a set time period before the occurrence of the UCE in the memory where the UCE occurred is statistically analyzed. For example, the error position distribution of CEs that occurred within a set time period before the occurrence of the UCE in the memory where the UCE occurred can be sorted in descending order of frequency, and the first X error position distributions are used as reference position distributions, where X is a positive integer and a set value.

[0095] 203 : Output a prediction result based on the similarity between the error position distribution and at least one reference position distribution, where the prediction result is used to indicate the probability of UCE occurring in the memory.

[0096] In a second possible implementation, the memory fault model is a neural network model, and the error position distribution of the error correction unit is used as the input of the memory fault model. The output of the memory fault model is used to indicate the probability of UCE occurring in the memory.

[0097] The method can be executed each time a CE is detected in the memory, or when the number of CEs in the memory reaches a threshold, or can be executed periodically. When the method is executed periodically, the length of the period can be set according to actual needs and can be in seconds, minutes, hours, etc., and the embodiments of the present application do not limit this.

[0098] In the embodiments of the present application, since the reference location distribution is associated with UCE, the similarity between the error location distribution when a memory CE occurs and at least one of the reference location distributions is correlated with the probability of a memory UCE occurring, reflecting the probability of a memory UCE occurring. The higher the similarity between the error location distribution and the reference location distribution, the higher the probability of a memory UCE occurring; conversely, the lower the similarity between the error location distribution and the reference location distribution, the lower the probability of a memory UCE occurring. Therefore, the probability of a memory UCE occurring can be predicted based on the similarity between the error location distribution when a memory CE occurs and at least one of the reference location distributions. On the one hand, when a memory CE occurs, memory faults can be predicted based on the error location distribution of the error correction unit corresponding to the CE, without having to wait for the collection of a large amount of CE information. Therefore, memory fault prediction is more timely. On the other hand, predicting memory faults based on the similarity between the error location distribution of the error correction unit and the reference location distribution, that is, based on the mechanism of UCE generation, helps improve the accuracy of memory fault prediction. This prediction method can be combined with other fault prediction methods in the related art to further improve the accuracy of memory fault prediction.

[0099] The first possible implementation manner described above will be described in detail below with reference to FIG. 4 .

[0100] FIG4 is a flow chart of a memory failure prediction method provided in an embodiment of the present application. As shown in FIG4 , the method includes:

[0101] 401. Obtain error position distribution of an error correction unit associated with a memory.

[0102] For related content, please refer to 301 and detailed description is omitted here.

[0103] In a possible implementation, the error position distribution is represented by a plurality of first elements, which correspond one-to-one to a plurality of data bits, and each first element is used to indicate whether a corresponding data bit is an error data bit.

[0104] In some examples, the error position distribution is represented by a first binary sequence comprising a plurality of first data bits, each of which is used to indicate whether a data bit in the error correction unit is erroneous, that is, each first data bit is a first element.

[0105] The number of first data bits in the first binary sequence is equal to the number of data bits in an error correction unit, or the number of first data bits in the first binary sequence is equal to the number of data bits corresponding to the same memory chip in an error correction unit. To facilitate similarity calculation, the following description will mainly use the example of the number of first data bits in the first binary sequence being equal to the number of data bits corresponding to the same memory chip in an error correction unit.

[0106] Each first data bit uniquely corresponds to a data bit in the error correction unit and is used to indicate whether the corresponding data bit is an error. Optionally, when the first data bit is a first value, it indicates that the corresponding data bit is an error, and when the first data bit is a second value, it indicates that the corresponding data bit is not an error. In some examples, the first value is 0 and the second value is 1. In other examples, the first value is 1 and the second value is 0.

[0107] In other examples, the error location distribution is represented by a first graph, which includes a plurality of first units arranged in an array, each first unit being used to indicate whether a data bit in an error correction unit is erroneous, that is, each first unit is a first element. The number of first units in the first graph is equal to the number of data bits contained in an error correction unit, or the number of first units in the first graph is equal to the number of data bits corresponding to the same memory chip in an error correction unit. To facilitate the calculation of similarity, the following description will mainly take the example of the number of first units in the first graph being equal to the number of data bits corresponding to the same memory chip in an error correction unit.

[0108] The row of the first graphic represents a burst, and the column of the first graphic represents a DQ. In the first graphic, a data bit can be indexed by a row and a column. The first graphic is a binary graphic, and each first unit can be composed of one or more pixels. When each first unit is composed of multiple pixels, it can be square or circular, etc. When the first unit is the third value, it means that the corresponding data bit is erroneous, and when the first unit is the fourth value, it means that the data of the corresponding data bit is not erroneous. Here, the third value and the fourth value can be pixel values ​​(such as grayscale values). In some examples, the third value is 0 and the fourth value is 255. In other examples, the third value is 255 and the fourth value is 0.

[0109] 402 : Obtain a memory fault model, where the memory fault model includes at least one reference location distribution.

[0110] Each reference position distribution is an error position distribution that may cause UCE in the memory.

[0111] 403 , respectively calculating the similarity between the error position distribution and each reference position distribution.

[0112] Each reference position distribution includes a plurality of second elements, each second element is used to indicate whether a data bit is erroneous. The plurality of first elements and the plurality of second elements correspond one to one, and the corresponding first elements and second elements are related to the same data bit.

[0113] When the error position distribution is represented by a first binary sequence, the reference position distribution is represented by a second binary sequence. The second binary sequence includes multiple second data bits, each of which is used to indicate whether a data bit is erroneous, i.e., each second data bit is a second element. Similar to the first binary sequence, when a second data bit is a first value, it indicates that the corresponding data bit is erroneous, and when the second data bit is a second value, it indicates that the corresponding data bit is not erroneous. The i-th second data bit in the second binary sequence and the i-th first data bit in the first binary sequence correspond to the same data bit in an error correction unit. Here, i is an integer.

[0114] When the error location distribution is represented by a first binary sequence and the reference location distribution is represented by a second binary sequence, step 402 includes calculating the Hamming distance between the first binary sequence and the second binary sequence. This Hamming distance represents the similarity between the error location distribution and the reference location distribution. This simple calculation method simplifies the memory fault prediction process and improves the efficiency of memory fault prediction.

[0115] The first binary sequence and the second binary sequence are compared bit by bit, and the number of first data bits that are at the same data bit position as the second data bit but have different values ​​is determined as the Hamming distance between the first binary sequence and the second binary sequence.

[0116] For example, the error position distribution is 0x2270, and the corresponding first binary sequence is 0b 0010 0010 0111 0000; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline indicates a first data bit that has the same data bit position as the second data bit but a different value. There is only one first data bit that meets this condition. Therefore, the Hamming distance between the first and second binary sequences is 1.

[0117] For example, the error position distribution is 0x0070, and the corresponding first binary sequence is 0b 0000 0000 0111 0000; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline indicates a first data bit that has the same data bit position as the second data bit but a different value. There are three first data bits that meet this condition. Therefore, the Hamming distance between the first binary sequence and the second binary sequence is 3.

[0118] For another example, the error position distribution is 0x0884, and the corresponding first binary sequence is 0b 0000 1000 1000 0100; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline indicates a first data bit that has the same data bit position as the second data bit but a different value. There are eight first data bits that meet this condition. Therefore, the Hamming distance between the first and second binary sequences is 8.

[0119] In these examples, the error location distribution is part of the value of the register that records the memory error information.

[0120] It can be seen that the larger the Hamming distance is, the lower the similarity between the error position distribution and the reference position distribution is; conversely, the smaller the Hamming distance is, the higher the similarity between the error position distribution and the reference position distribution is.

[0121] Using the Hamming distance as the similarity measure involves counting the number of first elements in the error position distribution that differ from the corresponding second element, and using this number as the similarity measure. In other embodiments, the number of first elements in the error position distribution that are identical to the corresponding second element can also be used as the similarity measure. In this case, a larger number indicates a higher similarity, while a smaller number indicates a lower similarity.

[0122] If the number of first elements in the error position distribution that are identical to the corresponding second element is used as the similarity, the similarity can be obtained by adding the difference between the length of the first binary sequence and the Hamming distance and the number of data bits of other corresponding memory particles in the error correction unit; or, the difference between the length of the first binary sequence and the Hamming distance is used as the similarity.

[0123] In other embodiments, an array may be used to represent the error position distribution and the reference position distribution, where each number in the array representing the error position distribution is a first element and each number in the array representing the reference position distribution is a second element.

[0124] While the error position distribution is represented by the first graph, the reference position distribution is represented by the second graph. The second graph includes a plurality of second cells arranged in an array. Each second cell indicates whether a data bit in an error correction unit is erroneous. In other words, each second cell is a second element. Similar to the first graph, this second graph is also a binary graph. When the second cell has the third value, it indicates that the corresponding data bit has an error. When the second cell has the fourth value, it indicates that the corresponding data bit has not been erroneous.

[0125] When the error position distribution is represented by a first graph and the reference position distribution is represented by a second graph, step 402 includes: taking the degree of overlap between the first graph and the second graph as the similarity.

[0126] The first graph includes a first faulty unit and a first non-faulty unit. The first faulty unit is the first unit indicating a data bit error, and the first non-faulty unit is the first unit indicating no data bit error, that is, the first non-faulty unit is the first unit other than the first faulty unit.

[0127] The second graph includes a second faulty unit and a second non-faulty unit. The second faulty unit is a second unit indicating a data bit error, and the second non-faulty unit is a second unit indicating no data bit error, that is, the second non-faulty unit is a second unit other than the second faulty unit.

[0128] In the embodiment of the present application, the degree of overlap is proportional to the number of first faulty units in the first graph that have the same position as the second faulty units in the second graph.

[0129] In one possible implementation, the degree of overlap between the first and second graphs is calculated based on the number of first faulty cells in the first graph that are located in the same position as the second faulty cells in the second graph. For example, the first faulty cells in the plurality of first cells and the second faulty cells in the plurality of second cells may be determined separately; then, the degree of overlap is determined based on the number of first faulty cells that are located in the same position as the second faulty cell and the number of second faulty cells.

[0130] In some examples, the coincidence degree may be determined as a ratio of the number of first faulty cells co-located with the second faulty cell to the number of the second faulty cells.

[0131] In other examples, the number of first faulty units at the same position as the second faulty unit is adjusted based on the position of the first non-faulty unit and the position of the first faulty unit to obtain an adjusted number; then the ratio of the adjusted number to the number of the second faulty units is determined as the overlap.

[0132] Optionally, the number of first faulty cells co-located with the second faulty cell is adjusted based on the first non-faulty cells co-located with the second faulty cell and belonging to the same DQ and / or the same burst as the first faulty cell. This is because in an error correction unit, if a data bit is erroneous, the adjacent data bits in the same DQ and / or the same burst as the data bit are more likely to be erroneous.

[0133] The following describes a method for adjusting the number of first faulty units located at the same position as the second faulty unit.

[0134] In some examples, if a data bit in an error correction unit is erroneous, the adjacent data bits in the same DQ as the data bit are more likely to be erroneous. Therefore, the number of first cells in the first unit other than the first faulty cell that are in the same position as the second faulty cell and belong to the same DQ as the first faulty cell is adjusted to a set value; then the number of first faulty cells in the same position as the second faulty cell is added to the sum of all set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value can be 0.1, 0.2, 0.3, etc. Adjusting the number of fifth cells based on the number of data bits that are not currently erroneous but are more likely to be erroneous helps to make the calculated overlap more accurate.

[0135] In other examples, if a data bit in an error correction unit is erroneous, the adjacent data bits in the same burst as the data bit are more likely to be erroneous. Therefore, the number of first cells in the first cells other than the first faulty cell that are in the same position as the second faulty cell and belong to the same burst as the first faulty cell is adjusted to a set value. The number of first faulty cells in the same position as the second faulty cell is then added to the sum of all the set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value can be 0.1, 0.2, 0.3, etc.

[0136] In some other examples, the number of first cells, excluding the first faulty cell, that have the same position as the second faulty cell and belong to the same DQ as the first faulty cell is adjusted to a set value, and the number of first cells, excluding the first faulty cell, that have the same position as the second faulty cell and belong to the same burst as the first faulty cell is adjusted to a set value; then, the number of first faulty cells at the same position as the second faulty cell is added to the sum of all the set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value may be 0.1, 0.2, 0.3, etc.

[0137] The following examples illustrate the first and second methods for calculating the overlap degree, using Figure 5. In Figure 5, in each of the first and second graphs, black rectangles represent corresponding erroneous data bits, while white rectangles represent intact data bits. That is, in the first graph, each rectangle represents a first unit, and the black rectangle represents a first faulty unit; in the second graph, each rectangle represents a second unit, and the black rectangle represents a second faulty unit. There are a total of six second faulty units in the second graph.

[0138] The first method for calculating the coincidence degree is to use the ratio of the number of first faulty units having the same position as the second faulty unit to the number of second faulty units as the coincidence degree.

[0139] In the first first figure, there are 5 first faulty cells, and the positions of all first faulty cells are the same as the positions of the second faulty cells in the second figure. Therefore, the number of first faulty cells with the same position as the second faulty cell is 5, and the overlap is 0.83. In the second first figure, there are 3 first faulty cells, and the positions of all first faulty cells are the same as the positions of the second faulty cells in the second figure. Therefore, the number of first faulty cells with the same position as the second faulty cell is 3, and the overlap is 0.5. In the third first figure, there are 4 first faulty cells, and the positions of all first faulty cells are different from the positions of the second faulty cells in the second figure. Therefore, the number of fifth cells is 0, and the overlap is 0.

[0140] The second method of calculating the coincidence degree is as follows: based on the first non-faulty unit that is at the same position as the second faulty unit and belongs to the same DQ as the first faulty unit, the number of first faulty units at the same position as the second faulty unit is adjusted, and the ratio of the adjusted number to the number of second faulty units is used as the coincidence degree.

[0141] In the first graph, there are five first faulty cells. The positions of all first faulty cells are identical to those of the second faulty cells in the second graph. Therefore, the number of first faulty cells with the same position as the second faulty cell is 5. Among all first non-faulty cells (i.e., those in the white rectangles), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is also the second faulty cell. Therefore, the first cell corresponding to DQ1, burst1 corresponds to the set value. Assuming the set value is 0.3, the adjusted number is 5.3, with an overlap of 0.88.

[0142] In the second first graph, the number of first faulty cells that share the same position as the second faulty cell is 3. Among all first non-faulty cells (i.e., within the white rectangles), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is the second faulty cell. The first non-faulty cell corresponding to DQ2, burst1 is adjacent to the first faulty cell corresponding to DQ2, burst2, and the second cell corresponding to DQ2, burst1 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst1 and the first cell corresponding to DQ2, burst1 correspond to the set value. Assuming the set value is 0.3, the adjusted number is 3.6, with an overlap of 0.6.

[0143] In the third first graph, the number of first faulty cells in the same position as the second faulty cell is 0. Among all first non-faulty cells (i.e., in the white rectangles), the first non-faulty cell corresponding to DQ1, burst2 is adjacent to the first faulty cell corresponding to DQ1, burst3, and the second cell corresponding to DQ1, burst2 is the second faulty cell. The first non-faulty cell corresponding to DQ2, burst2 is adjacent to the first faulty cell corresponding to DQ2, burst3, and the second cell corresponding to DQ2, burst2 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst2 and the first cell corresponding to DQ2, burst2 correspond to the set value. Assuming the set value is 0.3, the adjusted number is 0.6, and the overlap is 0.1.

[0144] In another possible implementation, the degree of overlap between the first and second graphs is calculated based on the number of first faulty cells in the first graph that are located at the same position as the second faulty cell in the second graph, and the number of first non-faulty cells in the first graph that are located at the same position as the second non-faulty cell in the second graph. Specifically, the overlap is calculated based on the number of overlapping cells in the first and second graphs, where the overlapping cells include the first faulty cell located at the same position as the second faulty cell and the first non-faulty cell located at the same position as the second non-faulty cell.

[0145] For example, the number of first faulty units at the same position as the second faulty unit and the number of first non-faulty units at the same position as the second non-faulty unit can be determined, that is, the number of overlapping units can be determined; and the degree of overlap can be determined based on the number of overlapping units and the number of first units.

[0146] In some examples, the overlap ratio can be determined as the ratio of the number of overlapping cells to the number of first cells. In other examples, the number of overlapping cells is first adjusted based on the position of the first non-faulty cell and the position of the first faulty cell that are co-located with the second faulty cell to obtain an adjusted number of overlapping cells; and then, the overlap ratio is determined as the ratio of the adjusted number of overlapping cells to the number of first cells.

[0147] The method for adjusting the number of overlapping units refers to the aforementioned method for adjusting the number of first faulty units at the same position as the second faulty unit, and detailed description is omitted here.

[0148] The following examples illustrate the third and fourth methods for calculating coincidence, using Figure 5. In Figure 5, in each of the first and second graphs, a black rectangle indicates an error in the corresponding data bit, while a white rectangle indicates a normal data bit. That is, in the first graph, each rectangle represents a first unit, with a black rectangle representing a first faulty unit and a white rectangle representing a first non-faulty unit. In the second graph, each rectangle represents a second unit, with a black rectangle representing a second faulty unit and a white rectangle representing a second non-faulty unit. The first graph includes 16 first units.

[0149] The third method for calculating the coincidence degree is as follows: the coincidence degree is determined as the ratio of the sum of the number of first faulty units having the same position as the second faulty unit and the number of first non-faulty units having the same position as the second non-faulty unit to the number of first units.

[0150] In the first first figure, the number of overlapping units is 15, and the overlap is equal to 0.94. In the second first figure, the number of overlapping units is 13, and the overlap is equal to 0.81. In the third first figure, the number of overlapping units is 6, and the overlap is equal to 0.38.

[0151] The fourth method for calculating the degree of overlap is to use the ratio of the number of adjusted overlapping units to the number of first units as the degree of overlap.

[0152] In the first graph, the number of overlapping cells is 15. Among all first non-faulty cells (i.e., those in the white rectangles), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is also the second faulty cell. Therefore, the first cell corresponding to DQ1, burst1 corresponds to the set value. Assuming the set value is 0.3, the adjusted number of overlapping cells is 15.3, and the overlap is 0.96.

[0153] In the second first graph, the number of overlapping cells is 13. Among all first non-faulty cells (i.e., those in the white rectangles), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is the second faulty cell. The first non-faulty cell corresponding to DQ2, burst1 is adjacent to the first faulty cell corresponding to DQ2, burst2, and the second cell corresponding to DQ2, burst1 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst1 and the first cell corresponding to DQ2, burst1 correspond to the set value. Assuming the set value is 0.3, the adjusted number of overlapping cells is 13.6, and the overlap is 0.85.

[0154] In the third first graph, the number of first faulty cells that share the same position as the second faulty cell is 6. Among all first non-faulty cells (i.e., those in the white rectangles), the first non-faulty cell corresponding to DQ1, burst2 is adjacent to the first faulty cell corresponding to DQ1, burst3, and the second cell corresponding to DQ1, burst2 is the second faulty cell. The first non-faulty cell corresponding to DQ2, burst2 is adjacent to the first faulty cell corresponding to DQ2, burst3, and the second cell corresponding to DQ2, burst2 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst2 and the first cell corresponding to DQ2, burst2 correspond to the set value. Assuming the set value is 0.3, the number of overlapping cells after adjustment is 6.6, and the overlap degree is 0.41.

[0155] It can be seen that the greater the overlap, the higher the similarity between the error position distribution and the reference feature distribution; conversely, the smaller the overlap, the lower the similarity between the error position distribution and the reference position distribution.

[0156] 404. Output the prediction result based on the calculated similarities.

[0157] The prediction result is used to indicate the probability of UCE occurring in the memory.

[0158] In one embodiment, the prediction result includes the highest similarity among all calculated similarities. In another embodiment, the prediction result includes the risk level corresponding to the highest similarity among all calculated similarities.

[0159] For example, when the similarity is expressed using the Hamming distance, the highest similarity is the minimum Hamming distance. Step 403 includes: outputting the risk level corresponding to the distance interval to which the minimum Hamming distance belongs based on the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level. The correspondence includes N distance intervals and N risk levels, and different distance intervals correspond to different risk levels, where N is an integer and N is greater than 1.

[0160] For example, N is equal to 3, that is, the risk level is divided into three risk levels: high, medium and low. Distance interval 1 corresponds to the high risk level, distance interval 2 corresponds to the medium risk level, and distance interval 3 corresponds to the low risk level.

[0161] The embodiments of the present application do not limit the division method of the distance intervals and can be adjusted according to actual needs. For example, distance interval 1 can be [1, a1), distance interval 2 can be [a1, a2), and distance interval 3 can be [a2, a3]. For example, a1 is equal to 3, a2 is equal to 10, and a3 is equal to the number of data bits contained in the error correction unit.

[0162] For another example, when the similarity is expressed by overlap, the highest similarity is the maximum overlap. Step 403 includes: outputting the risk level corresponding to the overlap interval to which the maximum overlap belongs according to the overlap interval to which the maximum overlap belongs and the correspondence between the overlap interval and the risk level. The correspondence includes M overlap intervals and M risk levels, and different overlap intervals correspond to different risk levels, where M is an integer and M is greater than 1.

[0163] For example, M is equal to 3, that is, the risk level is divided into three risk levels: high, medium and low. Coincidence interval 1 corresponds to the low risk level, coincidence interval 2 corresponds to the medium risk level, and coincidence interval 3 corresponds to the high risk level.

[0164] The embodiment of the present application does not limit the division method of the overlap interval and can be adjusted according to actual needs. For example, overlap interval 1 can be [0, b1), overlap interval 2 can be [b1, b2), and overlap interval 3 can be [b2, 1]. For example, b1 is equal to 0.4 and b2 is equal to 0.8.

[0165] It should be noted that when the memory fault model includes multiple reference position distributions, it is necessary to determine the probability of UCE occurrence corresponding to each reference position distribution and obtain the prediction result based on the probability corresponding to each reference position distribution.

[0166] In one possible implementation, the prediction result may indicate the maximum probability among the probabilities corresponding to all reference position distributions. In another possible implementation, the probabilities corresponding to the reference position distributions may be fused to obtain a fusion result, and the prediction result is used to indicate the fusion result.

[0167] For example, the fusion result can be calculated using the following formula (1):

[0168] p=1-(1-p1)*(1-p2)……*(1-px) (1),

[0169] Among them, p represents the fusion result, p1 represents the probability corresponding to the first reference position distribution, px represents the probability corresponding to the xth reference position distribution, and x represents the number of all reference position distributions.

[0170] Through steps 403 and 404 , it is possible to output a prediction result based on the similarity between the error position distribution and at least one reference position distribution, where the prediction result is used to indicate the probability of UCE occurring in the memory.

[0171] Alternatively, in other embodiments, steps 403 and 404 can be replaced by: sequentially calculating the similarity between the error location distribution and each reference location distribution; when the calculated similarity is higher than a similarity threshold, stopping calculating the similarity between the error location distribution and the remaining reference location distributions, and outputting a prediction result based on the similarity higher than the similarity threshold. For example, assuming that the memory fault model includes Y reference location distributions, first calculate the similarity between the error location distribution and the jth reference location distribution. If the similarity is higher than the similarity threshold, stop calculating and output a prediction result based on the similarity; if the similarity is lower than or equal to the similarity threshold, calculate the similarity between the error location distribution and the j+1th reference location distribution, until a similarity higher than the similarity threshold is calculated or until the similarities corresponding to all reference location distributions are calculated. If the similarities corresponding to all reference location distributions are calculated, the prediction result can be output based on the highest similarity among the calculated similarities. Wherein, j is a positive integer, and j is less than or equal to Y.

[0172] If the similarity is higher than the threshold, the probability of a UCE occurring in the memory is very high. In this case, the prediction result can be obtained without further calculating the similarity with other reference location distributions. Therefore, during the fault prediction process, it is possible to obtain a prediction result without calculating the similarity with all reference location distributions, which helps improve fault prediction efficiency.

[0173] The first possible implementation method is described in detail below with reference to FIG6 . FIG6 is a flow chart of a memory failure prediction method provided by an embodiment of the present application. As shown in FIG6 , the method includes:

[0174] 601, obtaining error position distribution of an error correction unit associated with a memory.

[0175] 602, obtaining a neural network model.

[0176] The neural network model is trained using the first and second types of samples. The first type of samples is the error position distribution of the error correction unit corresponding to the memory where only CE appears when CE appears. The second type of samples is the error position distribution of the error correction unit corresponding to the memory where UCE appears when CE appears before UCE appears.

[0177] 603, using a neural network model to process the error position distribution to obtain a prediction result.

[0178] In the embodiments of the present application, the neural network model includes but is not limited to a convolutional neural network (CNN) model, a recurrent neural network (RNN) model, or a long short-term memory (LSTM) model.

[0179] Optionally, before executing step 601, the method further includes training the neural network model. The training process may be as follows: for memory in which only CE occurs, the error location distribution corresponding to CE that occurred in a first time period is obtained as a first-category sample (negative sample); for memory in which UCE occurs, the error location distribution corresponding to CE that occurred in a second time period before the UCE occurs is obtained as a second-category sample (positive sample); the neural network model is trained using the first-category samples and the second-category samples as training sets, and the trained neural network model is the memory fault model.

[0180] In this embodiment, the error position distribution, the first type of samples and the second type of samples are all represented by graphs. For the content of the graphs, please refer to the first graph and the second graph in the aforementioned embodiment, and detailed description is omitted here.

[0181] For example, the first time period can be 24 hours long. The second time period can also be 24 hours long. Optionally, a first label, such as 0, can be added to the first category of samples, indicating that the actual probability of UCE occurrence corresponding to the first category of samples is 0, and a second label, such as 1, can be added to the second category of samples, indicating that the actual probability of UCE occurrence corresponding to the second category of samples is 1.

[0182] Taking the CNN model as an example, a neural network model consists of a series of layers: convolutional layers, downsampling layers (also known as pooling layers), fully connected layers, and an output layer. The convolutional layers extract features from the input image and feed these features into the downsampling layers. The downsampling layers reduce feature dimensionality to reduce computational complexity. The fully connected layers generate predicted probabilities based on the outputs of the downsampling layers. The output layer outputs these predicted probabilities.

[0183] The output of the neural network model can be a predicted probability of a UCE occurring in memory. The loss function of the neural network model can be determined based on the error between the predicted probability output by the neural network model and the actual probability of a UCE occurring in memory. The error between the predicted probability output by the neural network model and the actual probability of a UCE occurring in memory can be represented by the mean squared error or cross entropy between the predicted and actual probabilities.

[0184] Thus, after training is complete, the neural network model can characterize at least one reference position distribution. This reference position distribution is the error position distribution corresponding to the CE associated with the UCE. Here, the CE associated with the UCE means that if the memory exhibits the error position distribution corresponding to the CE, the memory is likely to exhibit the UCE.

[0185] In one embodiment, the prediction result is the output of the neural network model, that is, the output of the neural network model is output as the prediction result.

[0186] In another embodiment, the prediction result is a risk level corresponding to the probability value, and step 603 includes: outputting the risk level corresponding to the probability interval to which the probability value belongs according to the probability interval to which the probability value belongs and the correspondence between the probability interval and the risk level.

[0187] For example, the risk level is still divided into three risk levels: high, medium and low. Probability interval 1 corresponds to the low risk level, probability interval 2 corresponds to the medium risk level, and probability interval 3 corresponds to the high risk level.

[0188] The present embodiment does not limit the division method of the probability intervals and can be adjusted according to actual needs. For example, probability interval 1 can be [0, c1), probability interval 2 can be [c1, c2), and probability interval 3 can be [c2, 1]. For example, c1 is equal to 0.4 and c2 is equal to 0.8.

[0189] In the embodiments of the present application, the method of outputting the prediction results includes one or more of the following methods: outputting the prediction results on a display device; or outputting the prediction results through a voice device; or recording the prediction results in an alarm log. In this way, the staff can promptly learn the prediction results of the memory failure. When the probability of UCE in the memory is high, relevant protective measures can be taken in a timely manner, such as migrating data or performing redundancy processing on the memory (for example, copying the data in the memory to redundant memory) and replacing the memory, etc., to reduce the losses caused by downtime.

[0190] Optionally, the method may further include: automatically executing some protection measures, such as memory chip isolation, etc., according to the prediction result and based on a set memory protection policy.

[0191] The following describes the memory failure prediction method provided in the embodiment of the present application with reference to specific examples.

[0192] Example 1

[0193] Given a reference position distribution of 0x2670 and four CEs in memory, the corresponding error positions for each CE are 0x0010, 0x0030, 0x0020, and 0x0010, respectively. Calculated Hamming distances between the first binary sequence corresponding to each CE and the second binary sequence corresponding to the reference position distribution are 5, 4, 5, and 5, respectively. With a1 = 3 and a2 = 10, the risk levels of memory UCEs caused by the error position distributions corresponding to these four CEs are medium, medium, medium, and medium, respectively.

[0194] Example 2

[0195] Given a reference position distribution of 0x2670 and four CEs in memory, the corresponding error positions for each CE are 0x2400, 0x2500, 0x2510, and 0x2610, respectively. Calculated Hamming distances between the first binary sequence corresponding to each CE and the second binary sequence corresponding to the reference position distribution are 4, 5, 4, and 2, respectively. Furthermore, a1 = 3 and a2 = 10. Therefore, the risk levels of memory UCEs caused by the error position distributions corresponding to these four CEs are medium, medium, medium, and high, respectively.

[0196] Example 3

[0197] Given a reference position distribution of 0x2670 and four CEs in memory, the corresponding error positions for each CE are 0x700F, 0x500F, 0x700E, and 0x500D, respectively. Calculated Hamming distances between the first binary sequences corresponding to the four CEs and the second binary sequence corresponding to the reference position distribution are 11, 12, 10, and 11, respectively. Furthermore, a1 = 3 and a2 = 10. Therefore, the risk levels of memory UCEs caused by the error position distributions corresponding to these four CEs are low, low, low, and low, respectively.

[0198] Example 4

[0199] The reference position distribution is known to be 0x2670, and four CEs appear in the memory. The error positions corresponding to each CE are 0x2401, 0x2410, 0x2630, and 0x2500, respectively. After visualization and calculation, the overlap between the first graphs corresponding to the four CEs and the second graph corresponding to the reference position distribution is 69%, 81%, 94%, and 69%, respectively. b1 = 40%, b2 = 80%. Therefore, the error position distribution corresponding to these four CEs leads to a UCE risk level of medium, high, high, and medium, respectively.

[0200] Example 5

[0201] For the case where there is no known reference location distribution, the dataset contains 19,763 error location distributions of memory devices with only CE occurrences, and 4,255 error location distributions of memory devices with UCE occurrences. A memory fault model was obtained by training a CNN model. The error location distributions corresponding to CEs, 0x700F, 0x0030, 0x2630, and 0x2500, were input for testing. The probabilities of memory UCE occurrences were 0.12, 0.35, 0.92, and 0.73, respectively. With c1 = 0.4 and c2 = 0.8, the risk levels of memory UCE occurrences due to the error location distributions corresponding to these CEs are low, low, high, and medium, respectively.

[0202] FIG7 is a schematic diagram of the structure of a memory fault prediction device provided by the present application. The prediction device can be implemented as part or all of a computer device by software, hardware, or a combination of both. As shown in FIG7 , the device 700 includes: a first acquisition unit 701, a second acquisition unit 702, and a prediction unit 703. The first acquisition unit 701 is used to obtain an error location distribution of an error correction unit associated with a memory. The memory includes at least one memory chip, each memory chip includes multiple storage cells arranged in an array, and the error correction unit includes multiple data bits obtained from multiple storage cells of the at least one memory chip through multiple consecutive burst reads. Each of the multiple data bits corresponds to a storage cell of the memory. The error location distribution is used to indicate the location of the erroneous data bits in the multiple data bits, and the error location distribution causes the memory to have a correctable error (CE). The second acquisition unit 702 is used to obtain a memory fault model. The memory fault model includes at least one reference location distribution, which is associated with an uncorrectable error (UCE) of the memory. The prediction unit 703 is used to output a prediction result based on the similarity between the error location distribution and the at least one reference location distribution. The prediction result is used to indicate the probability of the memory having an UCE.

[0203] In one possible implementation, the prediction unit 703 includes a calculation subunit 7031 and an output subunit 7032. In some examples, the calculation subunit 7031 is configured to calculate the similarity between the error position distribution and each reference position distribution; the output subunit 7032 is configured to output a prediction result based on the calculated similarities. In other examples, the calculation subunit 7031 is configured to sequentially calculate the similarity between the error position distribution and each reference position distribution; and the output subunit 7032 is configured to, when the calculated similarity exceeds a similarity threshold, output a prediction result based on the similarity exceeding the similarity threshold.

[0204] Optionally, the error position distribution is represented by multiple first elements, each of which corresponds one-to-one to multiple data bits, and each first element is used to indicate whether a corresponding data bit is an error bit; the reference position distribution is represented by multiple second elements, each of which indicates whether a data bit is an error, and the multiple first elements and the multiple second elements correspond one-to-one. Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: counting the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity; or counting the number of first elements in the error position distribution that are the same as the corresponding second element to obtain the similarity.

[0205] In some examples, the error position distribution is represented by a first binary sequence, where the first binary sequence includes multiple first data bits, each of which is a first element. The reference position distribution is represented by a second binary sequence, where the second binary sequence includes multiple second data bits, each of which is a second element. The calculation subunit 7031 is configured to calculate the Hamming distance between the first binary sequence and the second binary sequence.

[0206] Optionally, the output sub-unit 7032 is used to determine the risk level to which the possibility of UCE occurring in the memory belongs based on the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level, where the correspondence includes N distance intervals and N risk levels, and different distance intervals correspond to different risk levels, where N is an integer and N is greater than 1.

[0207] In other examples, the error position distribution is represented by a first graph, the first graph including a plurality of first units arranged in an array, the plurality of first units corresponding one-to-one to a plurality of data bits, and each first unit being used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a second graph including a plurality of second units arranged in an array, the plurality of second units corresponding one-to-one to a plurality of first units. The calculation subunit 7031 is used to use the degree of overlap between the first graph and the second graph as the similarity, the degree of overlap being proportional to the number of first error units in the first graph that are in the same position as the second error unit in the second graph, the first error unit being the first unit indicating that the corresponding data bit is an error data bit, and the second error unit being the second unit indicating that the corresponding data bit is an error data bit.

[0208] Optionally, the calculation subunit 7031 is used to determine the degree of overlap based on the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, and the number of second fault units in the second graph; or, determine the degree of overlap based on the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, the relative position of the first non-fault unit in the first graph that has the same position as the second fault unit in the second graph and the first fault unit in the second graph, and the number of second fault units in the second graph; or, determine the degree of overlap based on the number of overlapping units in the first graph and the second graph, and the number of first units in the first graph, where the overlapping units include the first fault unit in the first graph that has the same position as the second fault unit in the second graph and the first non-fault unit in the first graph that has the same position as the second non-fault unit; or, determine the degree of overlap based on the number of overlapping units in the first graph and the second graph, the relative position of the first non-fault unit in the first graph that has the same position as the second fault unit in the second graph and the first fault unit in the second graph, and the number of first units in the first graph.

[0209] Optionally, the output sub-unit 7032 is used to determine the risk level to which the possibility of UCE occurring in the memory belongs based on the overlap interval to which the overlap belongs and the correspondence between the overlap interval and the risk level. The correspondence includes M overlap intervals and M risk levels, and different overlap intervals correspond to different risk levels, where M is an integer and M is greater than 1.

[0210] In another possible embodiment, the memory fault model is a neural network model, which is trained using first-category samples and second-category samples. The first-category samples are the error position distribution of the error correction unit corresponding to the memory where only CE occurs when CE occurs, and the second-category samples are the error position distribution of the error correction unit corresponding to the memory where UCE occurs when CE occurs before UCE occurs. The prediction unit 703 is used to process the error position distribution of the error correction unit using the neural network model to obtain a prediction result.

[0211] It should be noted that the memory fault prediction device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate memory fault prediction. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the memory fault prediction device provided in the above embodiment and the memory fault prediction method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0212] The division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0213] If the integrated module is implemented in the form of hardware, it can be implemented through a chip, a CPU, an ASIC, or a PLD.

[0214] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a terminal device (which can be a personal computer, mobile phone, or communication device, etc.) or a processor to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0215] The descriptions of the processes corresponding to the above figures have different focuses. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0216] In an embodiment of the present application, a computer-readable storage medium is further provided, which stores computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by a computer device, the computer device executes the memory failure prediction method provided above.

[0217] In an embodiment of the present application, a computer program product including instructions is further provided. When the computer program product is run on a computer device, the computer device executes the memory failure prediction method provided above.

[0218] In an embodiment of the present application, a chip is also provided, which includes a processor and a power supply circuit, the power supply circuit is used to power the processor, and the processor is used to execute the memory failure prediction method shown in Figure 2 or Figure 4 or Figure 6.

[0219] In some examples, the chip further includes a memory storing computer instructions, and the processor is configured to execute the computer instructions stored in the memory to implement the memory failure prediction method shown in FIG. 2 , FIG. 4 , or FIG. 6 .

[0220] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meaning understood by persons of ordinary skill in the field to which this application belongs. The words "first", "second", "third" and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprising" mean that the elements or objects appearing before "include" or "comprising" cover the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. The multiple involved in the embodiments of this application refers to two or more. A and / or B means that there are three situations: A; B; and A and B.

[0221] The above is only an embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A memory failure prediction method, characterized in that: include: Obtaining an error position distribution of an error correction unit associated with a memory, wherein the memory includes at least one memory cell, each of the memory cells includes a plurality of storage cells arranged in an array, the error correction unit includes a plurality of data bits obtained from a plurality of storage cells of the at least one memory cell by continuous burst reading, the plurality of data bits respectively corresponding to one storage cell among the plurality of storage cells of the at least one memory cell, the error position distribution is used to indicate a position of an error data bit in the plurality of data bits, and the error position distribution causes a correctable error CE to occur in the memory; Acquire a memory fault model, wherein the memory fault model includes at least one reference position distribution, and the reference position distribution is associated with an uncorrectable error (UCE) of the memory; According to the similarity between the error position distribution and at least one of the reference position distributions, a prediction result is output, where the prediction result is used to indicate the probability of UCE occurring in the memory.

2. The method according to claim 1, characterized in that Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: respectively calculating the similarity between the error position distribution and each of the reference position distributions; outputting the prediction result according to the calculated similarity; or, Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: Calculating the similarity between the error position distribution and each reference position distribution in sequence; When the calculated similarity is higher than the similarity threshold, a prediction result is output according to the similarity higher than the similarity threshold.

3. The method according to claim 2, characterized in that The error position distribution is represented by a plurality of first elements, the plurality of first elements correspond to the plurality of data bits one by one, and each of the first elements is used to indicate whether a corresponding data bit is an error data bit; The reference position distribution is represented by a plurality of second elements, and the plurality of first elements correspond to the plurality of second elements in a one-to-one manner; Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: Counting the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity; or, The number of first elements in the error position distribution that are identical to the corresponding second element is counted to obtain the similarity.

4. The method according to claim 3, characterized in that: The error position distribution is represented by a first binary sequence, wherein the first binary sequence includes a plurality of first data bits, and one first data bit is one first element; The reference position distribution is represented by a second binary sequence, the second binary sequence includes a plurality of second data bits, and one second data bit is one second element; The counting of the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity includes: A Hamming distance between the first binary sequence and the second binary sequence is calculated.

5. The method according to claim 2, characterized in that: The error position distribution is represented by a first graph, the first graph includes a plurality of first units arranged in an array, the plurality of first units correspond to the plurality of data bits one by one, and each of the first units is used to indicate whether a corresponding data bit is an error data bit; The reference position distribution is represented by a second graphic, wherein the second graphic includes a plurality of second units arranged in an array, and the plurality of second units correspond one-to-one to the plurality of first units; Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: The degree of overlap between the first graph and the second graph is taken as the similarity, and the degree of overlap is proportional to the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, the first fault unit is a first unit indicating that the corresponding data bit is an erroneous data bit, and the second fault unit is a second unit indicating that the corresponding data bit is an erroneous data bit.

6. The method according to claim 5, characterized in that The taking the overlap degree between the first graphic and the second graphic as the similarity includes: determining the overlap degree according to the number of first faulty units in the first graph having the same position as the second faulty units in the second graph and the number of second faulty units in the second graph; or, According to the number of first faulty units in the first graph having the same position as the second faulty units in the second graph, the first graph The overlap degree is determined based on the relative positions of the first non-faulty unit in the second graph and the first faulty unit in the second graph, and the number of the second faulty units in the second graph; or, Determine the overlap degree according to the number of overlapped units in the first graph and the second graph and the number of first units in the first graph, wherein the overlapped units include the first faulty unit in the first graph having the same position as the second faulty unit in the second graph and the first non-faulty unit in the first graph having the same position as the second non-faulty unit in the second graph; or, The overlap degree is determined based on the number of overlapping units in the first graph and the second graph, the relative position of the first non-faulty unit in the first graph that is the same position as the second faulty unit in the second graph and the first faulty unit in the second graph, and the number of first units in the first graph.

7. The method according to claim 1, characterized in that The memory fault model is a neural network model, and the neural network model is trained by using the first type of samples and the second type of samples, wherein the first type of samples is the error position distribution of the error correction unit corresponding to the memory where only CE occurs when CE occurs, and the second type of samples is the error position distribution of the error correction unit corresponding to the memory where UCE occurs when CE occurs before UCE occurs; Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: The neural network model is used to process the error position distribution to obtain the prediction result.

8. A memory failure prediction device, characterized in that: include: A first acquisition unit is used to acquire an error position distribution of an error correction unit associated with a memory, wherein the memory includes at least one memory cell, each of the memory cells includes a plurality of storage cells arranged in an array, the error correction unit includes a plurality of data bits obtained from a plurality of storage cells of the at least one memory cell by continuous burst reading, the plurality of data bits respectively corresponding to one storage cell among the plurality of storage cells of the at least one memory cell, the error position distribution is used to indicate a position of an error data bit among the plurality of data bits, and the error position distribution causes a correctable error CE to occur in the memory; A second acquisition unit, configured to acquire a memory fault model, wherein the memory fault model includes at least one reference position distribution, and the reference position distribution is associated with an uncorrectable error UCE of the memory; The prediction unit is used to output a prediction result according to the similarity between the error position distribution and at least one reference position distribution, wherein the prediction result is used to indicate the probability of an uncorrectable error UCE occurring in the memory.

9. A chip, characterized in that: The chip comprises a logic circuit and a power supply circuit, the logic circuit is used to execute the method according to any one of claims 1 to 7, and the power supply circuit is used to supply power to the logic circuit.

10. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store a software program, and the processor runs or executes the software program stored in the memory so that the electronic device implements the method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes executed by a processor, wherein the program codes include instructions for implementing the method according to any one of claims 1 to 7.

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