Apparatus and method for accessing memory, and chip and storage medium

Abstract

An apparatus and method for accessing a memory, and a medium and an electronic device. The apparatus comprises an MEM input interface, an APB input interface, an interface conversion module, a caching module and a control module, such that a first MEM interface signal and an APB interface signal for requesting access to a memory can be simultaneously received, and the APB interface signal can be converted into a corresponding second MEM interface signal. When there is an access conflict between the two MEM interface signals, the control module performs arbitration to determine an access priority of the first MEM interface signal and an access priority of the second MEM interface signal, controls the output and caching of the first MEM interface signal and the second MEM interface signal on the basis of an arbitration result by means of preferentially outputting the MEM interface signal with a higher access priority to the memory and sending the MEM interface signal with a lower access priority to the caching module for caching.

Description

Device and method for accessing memory, chip, and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on September 25, 2023, with application number 202311234650.8 and invention name “A device for accessing a memory, method thereof, chip, and storage medium”. The entire contents of the patent application are incorporated into this application by reference. Technical Field

[0003] The present application relates to the field of memory technology, and in particular to a device for accessing a memory, a method thereof, a chip, and a storage medium. Background Art

[0004] The memory is provided with a MEM interface. Currently, there are two ways to access the memory: one is to connect the APB (Advanced Peripheral Bus) bus to the MEM interface of the memory through an interface conversion module to realize the APB interface to MEM interface access to the memory; the other is to access the memory directly through the MEM interface;

[0005] Since the above interface conversion module will occupy the memory interface of the memory, the above two methods are incompatible.

[0006] Summary of the Invention

[0007] According to various embodiments of the present application, a device for accessing a memory, a method thereof, a chip, and a storage medium are proposed.

[0008] According to a first aspect of the present application, there is provided a device for accessing a memory, the device comprising a MEM input interface, an APB input interface, an interface conversion module, a cache module, and a control module;

[0009] The MEM input interface is used to receive a first MEM interface signal requesting access to the memory;

[0010] The APB input interface is used to receive an APB interface signal requesting access to a memory;

[0011] The interface conversion module is used to convert the APB interface signal into a corresponding second MEM interface signal;

[0012] The control module is used to determine whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, arbitration is performed according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and the MEM interface signal with a higher access priority is preferentially output to the memory, and the MEM interface signal with a lower access priority is sent to the cache module for caching.

[0013] In some embodiments, the control module is further configured to determine whether the memory has completed responding to the MEM interface signal with a higher access priority; if so, outputting the MEM interface signal with a lower access priority cached by the cache module to the memory.

[0014] In some embodiments, the cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal.

[0015] In some embodiments, the control module is further configured to control the MEM input interface to pause receiving a next MEM interface signal when the first MEM interface signal is sent to the MEM register for buffering, and to control the MEM input interface to start receiving a next MEM interface signal when the first MEM interface signal buffered by the MEM register is output to the memory;

[0016] The control module is further configured to control the interface conversion module to pause outputting the next MEM interface signal when the second MEM interface signal is sent to the APB register for caching, and to control the interface conversion module to start outputting the next MEM interface signal when the MEM interface signal cached by the APB register is output to the memory.

[0017] In some embodiments, the apparatus further comprises an APB output interface and an address verification module;

[0018] The address checking module is used to check whether the APB address in the APB interface signal is within the accessible range. If so, the APB interface signal is sent to the interface conversion module; if not, the APB interface signal is output through the APB output interface.

[0019] In some embodiments, the preset arbitration logic uses RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

[0020] In some embodiments, the interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit, a write data cache unit, and a read data cache unit;

[0021] The conversion unit is used to convert n APB interface signals received in sequence into a corresponding MEM interface signal, wherein the n APB interface signals are used to request the memory to perform a write operation, and the one MEM interface signal includes a write enable signal, a write address, and data to be written; wherein n = memory data bit width / APB bus data bit width;

[0022] The conversion unit is further configured to convert an APB interface signal into a corresponding MEM interface signal; the APB interface signal is used to request the memory to perform a read operation, and the MEM interface signal includes a read enable signal and a read address;

[0023] The write data cache unit is used to cache the data to be written;

[0024] The address cache unit is used to cache the write address or the read address;

[0025] The receiving unit is used to receive the APB interface signal and the read data returned by the memory;

[0026] The read data cache unit is used to cache the read data returned by the memory;

[0027] The output unit is used to output the converted MEM interface signal and the read data cached by the read data cache unit.

[0028] In some embodiments, the device includes at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces and the at least two MEM output interfaces correspond one to one with the at least two memories;

[0029] The control module is further configured to output a MEM interface signal received by any MEM input interface to a corresponding memory through a MEM output interface corresponding to the any MEM input interface if there is no access conflict between the MEM interface signal and the second MEM interface signal;

[0030] The control module is further configured to output the second MEM interface signal to the corresponding memory through the corresponding MEM output interface if there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface.

[0031] An embodiment of the present application provides a method for accessing a memory, which is implemented based on the above-mentioned device and includes:

[0032] The MEM input interface receives a first MEM interface signal requesting access to the memory;

[0033] The APB input interface receives an APB interface signal requesting access to the memory;

[0034] The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal;

[0035] The control module determines whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, the control module performs arbitration according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and outputs the MEM interface signal with a higher access priority to the memory first, and sends the MEM interface signal with a lower access priority to the cache module for caching.

[0036] In some embodiments, the method further comprises:

[0037] The control module determines whether the memory completes the response action to the MEM interface signal with a higher access priority. If so, the cache module outputs the MEM interface signal with a lower access priority cached by the cache module to the memory.

[0038] In some embodiments, the cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal;

[0039] The method further comprises:

[0040] When the first MEM interface signal is sent to the MEM register for buffering, the control module controls the MEM input interface to pause receiving the next MEM interface signal; and when the first MEM interface signal buffered by the MEM register is output to the memory, the control module controls the MEM input interface to start receiving the next MEM interface signal;

[0041] When the second MEM interface signal is sent to the APB register for caching, the control module controls the interface conversion module to pause outputting the next MEM interface signal; and when the MEM interface signal cached by the APB register is output to the memory, the control module controls the interface conversion module to start outputting the next MEM interface signal.

[0042] In some embodiments, the apparatus further comprises an APB output interface and an address verification module;

[0043] The address checking module checks whether the APB address in the APB interface signal is within an accessible range. If so, the APB interface signal is sent to the interface conversion module. If not, the APB interface signal is output through the APB output interface.

[0044] In some embodiments, the preset arbitration logic uses RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

[0045] In some embodiments, the interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit, and a write data cache unit;

[0046] The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal, specifically including:

[0047] The receiving unit sequentially receives n APB interface signals; the n APB interface signals are used to request the memory to perform a write operation;

[0048] The conversion unit converts the n APB interface signals into a corresponding MEM interface signal, where the MEM interface signal includes a write enable signal, a write address, and data to be written; wherein n = memory data bit width / APB bus data bit width;

[0049] The write data cache unit caches the data to be written;

[0050] The address cache unit caches the write address;

[0051] The output unit outputs the converted MEM interface signal.

[0052] In some embodiments, the conversion unit converts the n APB interface signals into a corresponding MEM interface signal, specifically including:

[0053] Each time an APB interface signal is received, the write address and offset address contained in the APB interface signal are obtained, and whether the data to be written has been received is determined based on the offset address. If so, the output unit outputs all the data to be written cached by the write data cache unit, the write address cached by the address cache unit, and the write enable signal. If not, the data to be written is sent to the write data cache unit cache, and continues to wait for receiving the next APB interface signal.

[0054] In some embodiments, the interface conversion module further includes a read data cache unit;

[0055] The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal, and specifically further includes:

[0056] The receiving unit receives an APB interface signal; the APB interface signal is used to request the memory to perform a read operation;

[0057] The conversion unit converts the APB interface signal into a corresponding MEM interface signal; the MEM interface signal includes a read enable signal and a read address;

[0058] The receiving unit receives the read data returned by the memory;

[0059] A read data cache unit caches the read data returned by the memory;

[0060] The output unit outputs the read data cached by the read data cache unit; wherein the output unit outputs the read data of the APB bus data bit width each time.

[0061] In some embodiments, the device includes at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces and the at least two MEM output interfaces correspond one to one with the at least two memories;

[0062] The method specifically includes:

[0063] If there is no access conflict between a MEM interface signal received by any MEM input interface and the second MEM interface signal, the control module outputs the MEM interface signal to a corresponding memory through a MEM output interface corresponding to the any MEM input interface;

[0064] If there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface, the control module outputs the second MEM interface signal to the corresponding memory through the corresponding MEM output interface.

[0065] According to a second aspect of the present application, a chip is provided, comprising the above-mentioned device.

[0066] According to a third aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0067] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0069] FIG1 is a schematic diagram of a device for accessing a memory according to an embodiment of the present application.

[0070] FIG2 is a schematic diagram of an interface conversion module in one embodiment of the present application.

[0071] FIG3 is a schematic diagram of an interface conversion module in a specific embodiment of the present application.

[0072] FIG4 is a flowchart of a memory access method in another embodiment of the present application. DETAILED DESCRIPTION

[0073] The detailed description of the accompanying drawings is intended to serve as an illustration of the presently preferred embodiment of the present application, and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.

[0074] One embodiment of the present application provides a device for accessing a memory, referring to FIG1 , wherein the device includes a MEM input interface, an APB input interface, an interface conversion module, a cache module, and a control module;

[0075] The MEM input interface is used to receive a first MEM interface signal input by a peripheral device requesting access to the memory; the first MEM interface signal can be directly output to the memory for access;

[0076] The APB input interface is used to receive an APB interface signal input by a peripheral device requesting access to a memory;

[0077] The interface conversion module is used to convert the APB interface signal into a corresponding second MEM interface signal; specifically, the APB interface signal cannot be directly output to the memory for access and needs to be converted into a corresponding second MEM interface signal;

[0078] The control module is used to determine whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, arbitration is performed according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and the MEM interface signal with a higher access priority is preferentially output to the memory for reading or writing access to the memory, and the MEM interface signal with a lower access priority is sent to the cache module for caching, so as to be output to the memory next time for reading or writing access to the memory.

[0079] Specifically, the memory is a SPRAM (Single-Port Random Access Memory). In the same clock cycle, the SPRAM can only perform a read operation or a write operation.

[0080] It should be noted that the first MEM interface signal and the second MEM interface signal are only used to distinguish different MEM interface signals and facilitate description. "first" and "second" do not constitute a limitation on a specific MEM interface signal. The first MEM interface signal and the second MEM interface signal can be writing or reading different addresses of different memories.

[0081] The device of this embodiment is used as an intermediate device between a peripheral device and a memory to be compatible with different access modes. The device is provided with a MEM input interface and an APB input interface, respectively, for receiving a first MEM interface signal and an APB interface signal requesting access to the memory. The APB interface signal is then converted into a corresponding second MEM interface signal by an interface conversion module. Since there may be an access conflict between the first MEM interface signal and the second MEM interface signal, that is, in the same clock cycle, the first MEM interface signal and the second MEM interface signal request access to the same memory, when there is an access conflict, the control module arbitrates according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and controls the output and caching of the first MEM interface signal and the second MEM interface signal based on the arbitration result, preferentially outputting the MEM interface signal with a higher access priority to the memory and sending the MEM interface signal with a lower access priority to the cache module for caching. Based on the above description, it can be seen that the embodiment of the present application can achieve compatibility between the MEM interface access mode and the APB interface access mode.

[0082] In some embodiments, the control module is further configured to determine whether the memory has completed responding to the MEM interface signal with a higher access priority; if so, outputting the MEM interface signal with a lower access priority cached by the cache module to the memory.

[0083] Specifically, the response action refers to the memory executing a read or write operation in response to a MEM interface signal sent by the device. In this embodiment, the control module can determine whether the memory has completed reading or writing a MEM interface signal through, for example, a polling or interrupt mechanism, depending on the communication protocol and hardware design between the control module and the memory. A polling mechanism means that the control module can continuously query (or poll) the memory status to determine whether the operation has been completed. After sending a read or write request, the control module will query the memory status at fixed intervals. When the memory status indicates that the operation has been completed, the control module will be informed that the read or write operation has been completed. An interrupt mechanism means that after sending a read or write request, the control module will continue to perform other tasks without continuously querying the memory status. When the memory completes the operation, an interrupt signal is triggered to notify the control module that the read or write operation has been completed. It should be understood that the polling mechanism is relatively simple but wastes a certain amount of processor resources. The interrupt mechanism can more efficiently utilize processor resources, but requires that the control module and memory support interrupt functionality. The choice of which mechanism to use depends on the system design requirements and hardware support.

[0084] In some embodiments, the cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal.

[0085] In some embodiments, the control module is further used to control the MEM input interface to pause receiving the next MEM interface signal when the first MEM interface signal is sent to the MEM register for caching; and to control the MEM input interface to start receiving the next MEM interface signal when the first MEM interface signal cached by the MEM register is output to the memory.

[0086] Specifically, in order to save the circuit area of ​​the device, the MEM register in this embodiment can only store one MEM interface signal. When the device has cached a MEM interface signal, the MEM input interface can no longer receive the next MEM interface signal because there is still a MEM interface signal that has not been sent. It should be noted that in this embodiment, the first MEM interface signal cached by the MEM register is output to the memory, and the MEM input interface is controlled to start receiving the next MEM interface signal. These two control actions are performed within the same clock cycle. The purpose is to avoid the generation of bubbles, so that the read and write operations on the memory are continuous. While the first MEM interface signal cached by the MEM register can be output to the memory in the current clock cycle, the peripheral device is notified that the MEM input interface is ready to receive the next MEM interface signal.

[0087] The control module is further configured to control the interface conversion module to pause outputting the next MEM interface signal when the second MEM interface signal is sent to the APB register for caching; and to control the interface conversion module to start outputting the next MEM interface signal when the MEM interface signal cached by the APB register is output to the memory.

[0088] Specifically, in order to save the circuit area of ​​the device, the APB register in this embodiment can only store one MEM interface signal. When the device has cached a MEM interface signal, the interface conversion module can no longer output the next MEM interface signal because there is still a MEM interface signal that has not been sent. It should be noted that in this embodiment, the second MEM interface signal cached by the APB register is output to the memory, and the interface conversion module is controlled to pause outputting the next MEM interface signal. These two control actions are performed within the same clock cycle. The purpose is to avoid the generation of bubbles, so that the read and write operations on the memory are continuous. While the second MEM interface signal cached by the APB register can be output to the memory in the current clock cycle, the interface conversion module is notified that the next MEM interface signal can be output.

[0089] In some embodiments, the apparatus further comprises an APB output interface and an address verification module;

[0090] The address checking module is used to check whether the APB address in the APB interface signal is within the accessible range. If so, the APB interface signal is sent to the interface conversion module; if not, the APB interface signal is output through the APB output interface.

[0091] Specifically, after receiving the APB interface signal, the device of this embodiment needs to verify the address of the APB interface signal to determine whether the APB address is within the accessible range. If it is not within the accessible range, the APB interface signal needs to be transparently transmitted out; if it is within the accessible range, the APB interface signal is sent to the interface conversion module for conversion to obtain the corresponding MEM interface signal.

[0092] In some embodiments, the preset arbitration logic uses RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

[0093] Specifically, the RR polling is to provide fair processing time for the MEM input interface and the APB input interface. For example, the MEM interface signal input to the MEM input interface last time is processed first, and the MEM interface signal converted from the APB interface signal input to the APB input interface this time is processed first.

[0094] The default access priority of the first MEM interface signal is higher means that when the MEM interface signal input by the MEM input interface and the MEM interface signal obtained by converting the APB interface signal input by the APB input interface send an access conflict, the MEM interface signal input by the MEM input interface is output first, and the MEM interface signal obtained by converting the APB interface signal input by the APB input interface is cached;

[0095] The default higher access priority of the second MEM interface signal means that when the MEM interface signal input by the MEM input interface and the MEM interface signal converted from the APB interface signal input by the APB input interface send an access conflict, the MEM interface signal converted from the APB interface signal input by the APB input interface is output first, and the MEM interface signal input by the MEM input interface is cached.

[0096] In some embodiments, referring to FIG2 , the interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit, a write data cache unit, and a read data cache unit;

[0097] The conversion unit is used to convert n APB interface signals received in sequence into a corresponding MEM interface signal, wherein the n APB interface signals are used to request the memory to perform a write operation, and the one MEM interface signal includes a write enable signal, a write address, and data to be written; wherein n = memory data bit width / APB bus data bit width;

[0098] The conversion unit is further configured to convert an APB interface signal into a corresponding MEM interface signal; the APB interface signal is used to request the memory to perform a read operation, and the MEM interface signal includes a read enable signal and a read address;

[0099] The write data cache unit is used to cache the data to be written;

[0100] The address cache unit is used to cache the write address or the read address;

[0101] The receiving unit is used to receive the APB interface signal and the read data returned by the memory;

[0102] The read data cache unit is used to cache the read data returned by the memory;

[0103] The output unit is used to output the converted MEM interface signal and the read data cached by the read data cache unit.

[0104] Figure 3 is a circuit structure of an interface conversion module in a specific embodiment. Referring to Figure 3, the APB interface signals include psel (Peripheral Select), penable (Peripheral Enable), pwrite (Peripheral Write), paddr (Peripheral Address), pwdata (Peripheral Write Data) and other signals, wherein psel is used to select a specific peripheral and send a request to the memory; penable is used to enable the peripheral, indicating that a read and write operation is to be performed; pwrite is used to indicate a write operation, when pwrite is high, it indicates a write operation, otherwise it indicates a read operation; paddr is used to transmit the memory address, specifying the location of the memory unit to be read and written; pwdata is used to transmit the data to be written to the memory; the receiving unit includes multiple input ports, which are respectively used to receive psel, penable, pwrite, paddr, and pwdata.

[0105] When the APB input interface requests the memory to perform a write operation, the conversion unit is used to convert the input psel, penable, and pwrite into the corresponding write enable wen; and parse paddr, extract the write address and offset address (offset_addr) from paddr, and the write address is cached in the address cache unit (for example, a register), and subsequently output as ram_addr; the offset address indicates which write data this is. Assuming that the APB bus data bit width is 32 bits and the memory data bit width is 128 bits, then n=128bit / 32bit=4; the interface conversion module can only receive a 32-bit write data at a time, such as pwdata[31:0], and cache it in the write data cache unit wr data buffer. It is necessary to splice 4 32-bit write data to obtain a 128-bit write data ram_wdata, and then output the 128-bit write data ram_wdata to the memory. Therefore, whether the offset_addr is equal to apb write num is used to determine whether the data has been received. num is n=128bit / 32bit=4. If they are equal, a wr_done=1 is output to the AND gate circuit. If they are not equal, a wr_done=0 is output to the AND gate circuit. The AND gate circuit also receives apb ready and write enable wen. apb ready is returned by the control module to the interface conversion module. When apb ready=1, it means that the interface conversion module can output the MEM interface signal. When apb ready=0, it means that the interface conversion module cannot output the MEM interface signal. The write enable wen is obtained by conversion. When wr_done=1&wen=1&apb ready=1, ram_wen (write enable signal), ram_wdata (write data) and ram_addr (write address) are output to the memory, that is, n APB interface signals are converted into a corresponding MEM interface signal including ram_wen, ram_wdata and ram_addr. The output unit includes multiple output ports, which are used to output ram_wen, ram_wdata and ram_addr respectively.

[0106] When the APB input interface requests the memory to perform a read operation, the conversion unit is used to convert the input psel, penable, and pwrite into corresponding read enable ren; and parse paddr to extract the read address from paddr, which is cached in the address cache unit (for example, a register) and subsequently output as ram_addr; since the read operation does not require the transmission of write data, there is only one APB interface signal. After completing the conversion of this APB interface signal, the corresponding ram_ren (read enable signal) and ram_addr (read address) can be output to the memory, that is, an APB interface signal is converted into a corresponding MEM interface signal including ram_ren and ram_addr; further, after completing the read operation, the memory will return the read data. Assuming that the APB bus data bit width is 32 bits and the memory data bit width is 128 bits, then n=128bit / 32bit=4; the memory returns a 128-bit ram_rdata (read data) to the interface conversion module, and the read data cache unit rd data The buffer caches this 128-bit ram_rdata. Since the APB bus data width is 32 bits, this 128-bit ram_rdata needs to be split into 4 records and returned to the corresponding peripheral (the sender of the APB interface signal) in 4 times, each time returning a 32-bit read data, such as prdata[31:0].

[0107] In some embodiments, the device includes at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces and the at least two MEM output interfaces correspond one to one with the at least two memories;

[0108] The control module is further configured to output a MEM interface signal received by any MEM input interface to a corresponding memory through a MEM output interface corresponding to the any MEM input interface if there is no access conflict between the MEM interface signal and the second MEM interface signal;

[0109] The control module is further configured to output the second MEM interface signal to the corresponding memory through the corresponding MEM output interface if there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface.

[0110] Specifically, the one-to-one correspondence between the at least two MEM input interfaces, the at least two MEM output interfaces, and the at least two memories means that, assuming that the device is used to access k memories, k MEM input interfaces, k MEM output interfaces, and one APB input interface need to be set accordingly, the k MEM input interfaces are respectively a k1-MEM input interface, a k2-MEM input interface, and a k3-MEM input interface, the k MEM output interfaces are respectively a k1-MEM output interface, a k2-MEM output interface, and a k3-MEM output interface, and the k memories are respectively a k1-SPRAM, a k2-SPRAM, and a k3-SPRAM; the k1-MEM input interface, the k1-MEM output interface, and the k1-SPRAM have a one-to-one correspondence, and the MEM interface signal input by the k1-MEM input interface can only be transmitted through the k The 1-MEM output interface outputs to the k1-SPRAM; the k2-MEM input interface and the k2-MEM output interface correspond one-to-one to the k2-SPRAM, and the MEM interface signal input by the k2-MEM input interface can only be output to the k2-SPRAM through the k2-MEM output interface; the k3-MEM input interface and the k3-MEM output interface correspond one-to-one to the k3-SPRAM, and the MEM interface signal input by the k3-MEM input interface can only be output to the k3-SPRAM through the k3-MEM output interface; and the MEM interface signal obtained by converting the APB interface signal input by the APB input interface can be output to the k1-SPRAM through the k1-MEM output interface, or output to the k2-SPRAM through the k2-MEM output interface, or output to the k3-SPRAM through the k3-MEM output interface.

[0111] Based on the above description, it can be seen that the device of this embodiment has the following advantages: the APB interface signal and the MEM interface signal can access the memory at the same time. When the two interface signals conflict in access, bubble-free transmission is possible, and the memory with a data bit width greater than the APB bus (32 bits) can be read and written.

[0112] Another embodiment of the present application provides a method for accessing a memory. The method is implemented based on the apparatus described in the above embodiment. Referring to FIG4 , the method includes the following steps:

[0113] Step S10, the MEM input interface receives a first MEM interface signal requesting access to the memory;

[0114] Step S20, the APB input interface receives an APB interface signal requesting access to the memory;

[0115] Step S30: The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal;

[0116] In step S40, the control module determines whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, the control module performs arbitration according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal. The MEM interface signal with a higher access priority is preferentially output to the memory, and the MEM interface signal with a lower access priority is sent to the cache module for caching.

[0117] In some embodiments, the method further comprises:

[0118] In step S50 , the control module determines whether the memory has completed the response action to the MEM interface signal with a higher access priority. If so, the cache module caches a MEM interface signal with a lower access priority and outputs it to the memory.

[0119] In some embodiments, the cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal;

[0120] The step S40 further includes:

[0121] When the first MEM interface signal is sent to the MEM register for buffering, the control module controls the MEM input interface to pause receiving the next MEM interface signal; and when the first MEM interface signal buffered by the MEM register is output to the memory, the control module controls the MEM input interface to start receiving the next MEM interface signal;

[0122] When the second MEM interface signal is sent to the APB register for caching, the control module controls the interface conversion module to pause outputting the next MEM interface signal; and when the MEM interface signal cached by the APB register is output to the memory, the control module controls the interface conversion module to start outputting the next MEM interface signal.

[0123] In some embodiments, the apparatus further comprises an APB output interface and an address verification module;

[0124] The step S20 further includes:

[0125] The address checking module checks whether the APB address in the APB interface signal is within an accessible range. If so, the APB interface signal is sent to the interface conversion module. If not, the APB interface signal is output through the APB output interface.

[0126] In some embodiments, the preset arbitration logic uses RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

[0127] In some embodiments, the interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit, and a write data cache unit;

[0128] The step S30 specifically includes:

[0129] Step S311: The receiving unit sequentially receives n APB interface signals; the n APB interface signals are used to request the memory to perform a write operation;

[0130] Step S312: The conversion unit converts the n APB interface signals into a corresponding MEM interface signal, where the MEM interface signal includes a write enable signal, a write address, and data to be written; wherein n = memory data bit width / APB bus data bit width;

[0131] Step S313: the write data cache unit caches the data to be written;

[0132] Step S314, the address cache unit caches the write address;

[0133] Step S315 : the output unit outputs the converted MEM interface signal.

[0134] In some embodiments, step S312 specifically includes:

[0135] Each time an APB interface signal is received, the write address and offset address contained in the APB interface signal are obtained, and whether the data to be written has been received is determined based on the offset address. If so, the output unit outputs all the data to be written cached by the write data cache unit, the write address cached by the address cache unit, and the write enable signal. If not, the data to be written is sent to the write data cache unit cache, and continues to wait for receiving the next APB interface signal.

[0136] In some embodiments, the interface conversion module further includes a read data cache unit;

[0137] The step S30 specifically includes:

[0138] Step S321: The receiving unit receives an APB interface signal; the APB interface signal is used to request the memory to perform a read operation;

[0139] Step S322: The conversion unit converts the APB interface signal into a corresponding MEM interface signal; the MEM interface signal includes a read enable signal and a read address;

[0140] Step S323: The receiving unit receives the read data returned by the memory;

[0141] Step S324, the read data cache unit caches the read data returned by the memory;

[0142] Step S325 , the output unit outputs the read data cached by the read data cache unit; wherein the output unit outputs the read data of the APB bus data bit width each time.

[0143] In some embodiments, the device includes at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces and the at least two MEM output interfaces correspond one to one with the at least two memories;

[0144] The step S40 further includes:

[0145] If there is no access conflict between a MEM interface signal received by any MEM input interface and the second MEM interface signal, the control module outputs the MEM interface signal to a corresponding memory through a MEM output interface corresponding to the any MEM input interface;

[0146] If there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface, the control module outputs the second MEM interface signal to the corresponding memory through the corresponding MEM output interface.

[0147] It should be noted that the method described in this embodiment corresponds to the device described in the above embodiment. Therefore, the parts of the method described in this embodiment that are not described in detail can be obtained by referring to the contents of the device described in the above embodiment, so they will not be repeated here.

[0148] Another embodiment of the present application provides a chip including the device for accessing a memory as described in the above embodiment.

[0149] Another embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the memory access method described in the above embodiment is implemented.

[0150] Specifically, the computer-readable storage medium may include: any entity or recording medium that can carry the computer program instructions, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0151] While various embodiments of the present application have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many updates and modifications will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device for accessing a memory, characterized in that: The device includes a MEM input interface, an APB input interface, an interface conversion module, a cache module and a control module; The MEM input interface is used to receive a first MEM interface signal requesting access to the memory; The APB input interface is used to receive an APB interface signal requesting access to a memory; The interface conversion module is used to convert the APB interface signal into a corresponding second MEM interface signal; The control module is used to determine whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, arbitration is performed according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and a MEM interface signal with a higher access priority is preferentially output to the memory, and a MEM interface signal with a lower access priority is sent to the cache module for caching.

2. The device according to claim 1, characterized in that The control module is also used to determine whether the memory has completed the response action to the MEM interface signal with a higher access priority. If so, output a MEM interface signal with a lower access priority cached by the cache module to the memory.

3. The device according to claim 1, characterized in that The cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal.

4. The device according to claim 3, characterized in that The control module is further used to control the MEM input interface to pause receiving the next MEM interface signal when the first MEM interface signal is sent to the MEM register for buffering, and to control the MEM input interface to start receiving the next MEM interface signal when the first MEM interface signal buffered by the MEM register is output to the memory; The control module is also used to control the interface conversion module to pause outputting the next MEM interface signal when the second MEM interface signal is sent to the APB register for caching, and to control the interface conversion module to start outputting the next MEM interface signal when the MEM interface signal cached by the APB register is output to the memory.

5. The device according to claim 1, characterized in that The device also includes an APB output interface and an address verification module; The address checking module is used to check whether the APB address in the APB interface signal is within the accessible range. If so, the APB interface signal is sent to the interface conversion module. If not, the APB interface signal is output through the APB output interface.

6. The device according to claim 1, characterized in that The preset arbitration logic adopts RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

7. The device according to claim 1, characterized in that The interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit, a write data cache unit and a read data cache unit; The conversion unit is used to convert n APB interface signals received in sequence into a corresponding MEM interface signal, wherein the n APB interface signals are used to request the memory to perform a write operation, and the one MEM interface signal includes a write enable signal, a write address and data to be written; wherein n=memory data bit width / APB bus data bit width; The conversion unit is also used to convert an APB interface signal into a corresponding MEM interface signal; the APB interface signal is used to request the memory to perform a read operation, and the MEM interface signal includes a read enable signal and a read address; The write data cache unit is used to cache the data to be written; The address cache unit is used to cache the write address or the read address; The receiving unit is used to receive the APB interface signal and the read data returned by the memory; The read data cache unit is used to cache the read data returned by the memory; The output unit is used to output the converted MEM interface signal and the read data cached by the read data cache unit.

8. The device according to any one of claims 1 to 7, characterized in that The device comprises at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces, the at least two MEM output interfaces and the at least two memories correspond one to one; The control module is further configured to output a MEM interface signal received by any MEM input interface to a corresponding memory through a MEM output interface corresponding to the any MEM input interface if there is no access conflict between the MEM interface signal and the second MEM interface signal; The control module is further configured to output the second MEM interface signal to the corresponding memory through the corresponding MEM output interface if there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface.

9. A method for accessing a memory, characterized in that: The method is implemented based on the device described in any one of claims 1 to 8, and the method includes: The MEM input interface receives a first MEM interface signal requesting access to the memory; The APB input interface receives an APB interface signal requesting access to the memory; The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal; The control module determines whether there is an access conflict between the first MEM interface signal and the second MEM interface signal. If so, arbitration is performed according to a preset arbitration logic to determine the access priority of the first MEM interface signal and the second MEM interface signal, and a MEM interface signal with a higher access priority is preferentially output to the memory, and a MEM interface signal with a lower access priority is sent to the cache module for caching.

10. The method according to claim 9, characterized in that The method further comprises: The control module determines whether the memory has completed the response action to the MEM interface signal with a higher access priority. If so, the cache module caches a MEM interface signal with a lower access priority and outputs it to the memory.

11. The method according to claim 9, characterized in that The cache module includes a MEM register corresponding to the MEM input interface and an APB register corresponding to the APB input interface, the MEM register is used to cache the first MEM interface signal, and the APB register is used to cache the second MEM interface signal; The method further comprises: When the first MEM interface signal is sent to the MEM register for buffering, the control module controls the MEM input interface to pause receiving the next MEM interface signal; and when the first MEM interface signal buffered by the MEM register is output to the memory, the control module controls the MEM input interface to start receiving the next MEM interface signal; When the second MEM interface signal is sent to the APB register for caching, the control module controls the interface conversion module to pause outputting the next MEM interface signal; and when the MEM interface signal cached by the APB register is output to the memory, the control module controls the interface conversion module to start outputting the next MEM interface signal.

12. The method according to claim 9, characterized in that The device also includes an APB output interface and an address verification module; The address checking module checks whether the APB address in the APB interface signal is within the accessible range. If so, the APB interface signal is sent to the interface conversion module. If not, the APB interface signal is output through the APB output interface.

13. The method according to claim 9, characterized in that The preset arbitration logic adopts RR polling to determine the access priority of the first MEM interface signal and the second MEM interface signal, or defaults that the access priority of the first MEM interface signal is higher, or defaults that the access priority of the second MEM interface signal is higher.

14. The method according to claim 9, characterized in that The interface conversion module includes a receiving unit, an output unit, a conversion unit, an address cache unit and a write data cache unit; The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal, specifically including: The receiving unit sequentially receives n APB interface signals; the n APB interface signals are used to request the memory to perform a write operation; The conversion unit converts the n APB interface signals into a corresponding MEM interface signal, where the MEM interface signal includes a write enable signal, a write address and data to be written; wherein n=memory data bit width / APB bus data bit width; The write data cache unit caches the data to be written; The address cache unit caches the write address; The output unit outputs the converted MEM interface signal.

15. The method according to claim 9, characterized in that The conversion unit converts the n APB interface signals into a corresponding MEM interface signal, specifically including: Each time an APB interface signal is received, the write address and offset address contained in the APB interface signal are obtained, and whether the data to be written has been received is determined based on the offset address. If so, the output unit outputs all the data to be written cached by the write data cache unit, the write address cached by the address cache unit, and the write enable signal. If not, the data to be written is sent to the write data cache unit cache, and continues to wait for receiving the next APB interface signal.

16. The method according to claim 14, characterized in that The interface conversion module also includes a read data cache unit; The interface conversion module converts the APB interface signal into a corresponding second MEM interface signal, and specifically includes: The receiving unit receives an APB interface signal; the APB interface signal is used to request the memory to perform a read operation; The conversion unit converts the one APB interface signal into a corresponding one MEM interface signal; the one MEM interface signal includes a read enable signal and a read address; The receiving unit receives the read data returned by the memory; A read data cache unit caches the read data returned by the memory; The output unit outputs the read data cached by the read data cache unit; wherein the output unit outputs the read data of the APB bus data bit width each time.

17. The method according to any one of claims 9 to 16, characterized in that: The device comprises at least two MEM input interfaces and at least two MEM output interfaces, and the at least two MEM input interfaces, the at least two MEM output interfaces and the at least two memories correspond one to one; The method specifically comprises: If there is no access conflict between a MEM interface signal received by any MEM input interface and the second MEM interface signal, the control module outputs the MEM interface signal to a corresponding memory through a MEM output interface corresponding to the any MEM input interface; If there is no access conflict between the second MEM interface signal and other MEM interface signals received through the MEM input interface, the control module outputs the second MEM interface signal to the corresponding memory through the corresponding MEM output interface.

18. A chip, characterized in that: A device comprising any one of claims 1 to 8.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 9 to 17 is implemented.

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