Information processing device, quantum information processing program, quantum information processing method, and hybrid system

Abstract

A classic computer 110 acquires a quantum circuit generated on the basis of calculation information serving as a target, converts each gate included in the acquired quantum circuit into a gate which is predetermined to have fault tolerance and bias preservability, and outputs a post-conversion quantum circuit including the gate after conversion.

Description

Information processing device, quantum information processing program, quantum information processing method, and hybrid system

[0001] The disclosed technology relates to an information processing device, a quantum information processing program, a quantum information processing method, and a hybrid system.

[0002] Conventionally, methods of fault-tolerant quantum computing in the case where errors are biased have been known, with a specific type of quantum computer in mind.

[0003] J. Guillaud and M. Mirrahimi, Repetition cat qubits for fault-tolerant quantum computation, Physical Review X 9, 041053 (2019).

[0004] However, the above-mentioned Non-Patent Document 1 does not disclose how to obtain a quantum circuit that is fault-tolerant and bias-preserving by a method that does not depend on hardware.

[0005] The disclosed technology has been made in consideration of the above circumstances, and aims to provide an information processing device, a quantum information processing program, a quantum information processing method, and a hybrid system that can obtain a quantum circuit that is fault-tolerant and bias-preserving.

[0006] An information processing device of a first aspect of the present disclosure is an information processing device that acquires a quantum circuit generated based on target computational information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and outputs a converted quantum circuit that includes the converted gates.

[0007] A quantum information processing program according to a second aspect of the present disclosure is a quantum information processing program for causing a computer to execute a process of acquiring a quantum circuit generated based on target computational information, converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation properties, and outputting a converted quantum circuit that includes the converted gates.

[0008] A quantum information processing method according to a third aspect of the present disclosure is a quantum information processing method executed by a computer, which includes acquiring a quantum circuit generated based on target computational information, converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and outputting a converted quantum circuit that includes the converted gates.

[0009] A hybrid system according to a fourth aspect of the present disclosure is a hybrid system including a classical module that performs classical computation and a quantum module that performs quantum computation, wherein the classical module acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, transmits a converted quantum circuit including the converted gates to the quantum module, the quantum module executes the converted quantum circuit to acquire an execution result of the converted quantum circuit, transmits the execution result of the converted quantum circuit to the classical module, and the classical module acquires the execution result of the converted quantum circuit.

[0010] The disclosed technology has the effect of making it possible to obtain a quantum circuit that is fault-tolerant and bias-preserving in a hardware-independent manner.

[0011] 1 is a diagram showing an example of a schematic configuration of a hybrid system 100 of this embodiment. It is a schematic block diagram of computers functioning as a classical computer 110, a control device 121, and a user terminal 130. It is a diagram for explaining fault tolerance. It is a diagram for explaining bias preservation. It is a circuit diagram showing a logic X gate. It is a circuit diagram showing a logic Y gate. It is a circuit diagram showing a logic Z gate. It is a circuit diagram showing a logic CX gate. It is a circuit diagram showing a logic CZ gate. It is a circuit diagram showing a logic S gate. It is a circuit diagram showing a circuit that prepares a +1 eigenstate of a Y operator. It is a circuit diagram showing a logic H gate. It is a circuit diagram showing a circuit that prepares a +1 eigenstate of an X operator. It is a circuit diagram showing a circuit that performs measurement in the X basis. It is a circuit diagram showing a logic Rz gate. It is a diagram showing a response when data with an error is input to X, Y, and Z gates. It is a diagram showing a response when data with an error is input to an H gate. It is a diagram showing a response when data with an error is input to a CX gate. It is a diagram showing a response when data with an error is input to a CZ gate. It is a diagram showing a response when data with an error is input to a logic CZ gate. FIG. 1 is a diagram showing a response when data with an error is input to a logic CZ gate. FIG. 2 is a diagram showing a response when data with an error is input to a logic H gate. FIG. 3 is a circuit diagram showing an error correction circuit. FIG. 4 is a circuit diagram showing an error detection circuit of the error correction circuit. FIG. 5 is a diagram for explaining the operation of the error detection circuit of the error correction circuit. FIG. 6 is a diagram for explaining the operation of the error detection circuit of the error correction circuit. FIG. 7 is a diagram for explaining the operation of the error detection circuit of the error correction circuit. FIG. 8 is a diagram for explaining the operation of the error detection circuit of the error correction circuit. FIG. 9 is a circuit diagram showing an error correction circuit with fault tolerance. FIG. 10 is a diagram showing an example of a lookup table. FIG. 11 is a diagram showing an example of a sequence executed by the hybrid system 100 of the present embodiment.

[0012] Hereinafter, embodiments of the disclosed technology will be described in detail with reference to the drawings.

[0013] <Hybrid System 100 According to the Embodiment> Fig. 1 shows a hybrid system 100 according to the embodiment. The hybrid system 100 of the embodiment includes a classical computer 110, which is an example of an information processing device, a quantum computer 120, and a user terminal 130. As shown in Fig. 1, the classical computer 110, the quantum computer 120, and the user terminal 130 are connected via a computer network, such as an IP network, for example. The classical computer 110 is an example of a classical module (an information processing device having the function of performing classical computation), and the quantum computer 120 (an information processing device having the function of performing quantum computation) is an example of a quantum module.

[0014] In the hybrid system 100 of this embodiment, the quantum computer 120 performs a predetermined quantum computation in response to a request from the classical computer 110, and outputs the computation result of the quantum computation to the classical computer 110. The classical computer 110 outputs the computation result of the quantum computation to the user terminal 130. In this way, the predetermined computation process is executed by the hybrid system 100 as a whole.

[0015] The classical computer 110 includes a communication unit 111 such as a communication interface, a processing unit 112 such as a processor or a central processing unit (CPU), and an information storage unit 113 including a storage device or storage medium such as a memory or a hard disk, and is configured to execute programs for performing each process. The classical computer 110 may include one or more devices or servers. The program may include one or more programs, and may be recorded on a computer-readable storage medium to form a non-transitory program product.

[0016] As an example, quantum computer 120 generates an electromagnetic wave to be irradiated onto at least one of quantum bits in quantum bit group 123 based on information transmitted from classical computer 110. Then, quantum computer 120 executes a quantum circuit by irradiating at least one of quantum bits in quantum bit group 123 with the generated electromagnetic wave.

[0017] In the example of FIG. 1 , the quantum computer 120 includes a control device 121 that communicates with the classical computer 110, an electromagnetic wave generating device 122 that generates electromagnetic waves in response to requests from the control device 121, and a group of quantum bits 123 that receives electromagnetic wave irradiation from the electromagnetic wave generating device 122. The electromagnetic wave generating device 122 and the group of quantum bits 123 of the quantum computer 120 are also QPUs (Quantum Processing Units). Note that in this embodiment, the term "quantum computer" does not mean a computer that does not perform any operations using classical bits, but refers to a computer that includes operations using quantum bits or a computer that simulates the behavior of a quantum computer. An example of a computer that simulates the behavior of a quantum computer is a classical computer that performs quantum simulation. Furthermore, quantum computing is an operation using a quantum superposition state or an operation that simulates an operation using a quantum superposition state.

[0018] The control device 121 is a classical computer that performs operations using classical bits, and alternatively performs some or all of the processing described in this specification as being performed by the classical computer 110.

[0019] The user terminal 130 is a classical computer that performs calculations using classical bits. The user terminal 130 receives information input by a user and executes processing according to the information.

[0020] The classical computer 110, the control device 121, and the user terminal 130 can be realized, for example, by a computer 50 shown in FIG. 2 . The computer 50 includes a central processing unit (CPU) 51, a memory 52 serving as a temporary storage area, and a non-volatile storage unit 53. The computer 50 also includes an input / output interface (I / F) 54 to which external devices, output devices, etc. are connected, and a read / write (R / W) unit 55 that controls reading and writing of data from and to a recording medium. The computer 50 also includes a network I / F 56 that is connected to a network such as the Internet. The CPU 51, the memory 52, the storage unit 53, the input / output I / F 54, the R / W unit 55, and the network I / F 56 are connected to one another via a bus 57.

[0021] [Outline of this embodiment] Quantum computers perform various calculations using quantum bits (qubits), which are special elements that can assume a superposition state of 0 and 1. However, quantum bits are easily broken. If a quantum bit malfunction is left unattended, errors will occur in the calculation results. Therefore, a mechanism for automatically detecting and correcting quantum bit malfunctions is essential.

[0022] There are bit-flip errors and phase-flip errors in quantum computing, but to completely correct these requires a huge number of qubits, which is not realistic with the current state of technology. However, in real hardware, these do not occur with equal probability, and bias exists. Optical quantum computers are one example.

[0023] Therefore, we assume an environment in which only bit-flip errors occur. For example, we assume an environment in which the hardware is heavily biased and phase-flip errors can be ignored. This makes it possible to completely correct errors using bit-flip codes. Furthermore, bit-flip codes can be encoded using three quantum bits, which is easily achievable with current technology.

[0024] Furthermore, quantum bit calculations require various logical operations to be performed on the quantum bits, which necessitates fault-tolerant quantum computing that controls the logical operations so that errors do not accumulate.

[0025] Therefore, in this embodiment, assuming an environment in which only bit-flip errors occur, the classical computer 110 of the hybrid system 100 converts the input quantum circuit into a quantum circuit that enables quantum computation using bit-flip codes. Specifically, the classical computer 110 converts each gate included in the input quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation. Here, the gate before conversion will simply be called a "gate," and the gate after conversion will be called a "logic gate."

[0026] Furthermore, being fault-tolerant means that the probability that bit-flip errors occurring after three or more independent quantum bits pass through the quantum gate is more than half is sufficiently small and negligible compared to the probability that the error is less than half, as shown in Figure 3. In Figure 3, the left side represents the input and the right side represents the output. Figure 3 shows an example in which an error occurs in the first quantum bit after the logic gate has acted.

[0027] Since a bit-flip code is a code that detects bit-flip errors by majority vote of three or more quantum bits, it is necessary that the number of bit-flip errors that occur after, for example, three independent quantum bits pass through a logic gate is one or less. Note that although there is a probability that two errors will occur simultaneously in three quantum bits, this is ignored because the probability is low (the square of the probability of one error occurring).

[0028] As mentioned above, there are two different types of errors in quantum computing.

[0029] One is a bit inversion error, which is an error in which 0 changes to 1, and is hereinafter referred to as an X error.

[0030] The other is a phase inversion error, in which |0>+|1> changes to |0>-|1>, which will be referred to as a Z error hereinafter.

[0031] Some quantum gates (such as the H gate) have the property of converting X-errors into Z-errors. Therefore, even if we are considering an environment where only X-errors occur, it is possible that Z-errors may occur during calculations by converting X-errors into Z-errors through gate operation.

[0032] As shown in FIG. 4, a logic gate that keeps the X error as an X error is called a bias-preserving logic gate.

[0033] A bias-conserving logic gate is a circuit structure in which a Z error cannot occur, or in which a Z error can be detected if it does occur. The rules for converting each element into a bias-conserving logic gate are not uniform, but are determined for each element. Generally, when an error occurs in a gate, for example, an X error occurs in the first quantum bit of three quantum bits, or a Z error occurs in the first quantum bit. Here, if there is only one X error, the error can be corrected by fault tolerance. Therefore, a bias-conserving logic gate is a gate that keeps an X error as an X error.

[0034] A bit-flip code is a code that detects bit-flip errors by majority vote of three or more quantum bits. In the case of three quantum bits, if an X error occurs in two or more quantum bits, fault tolerance may not be maintained. However, since the probability of an X error occurring in one quantum bit is low to begin with and the probability of an X error occurring simultaneously in two or more quantum bits is a probability that can be discarded, three or more quantum bits are sufficient for fault-tolerant calculations.

[0035] In this embodiment, all logic gates are fault tolerant with respect to X errors, and are bias-preserving gates with respect to X errors.

[0036] Therefore, when the classical computer 110 of the hybrid system 100 of this embodiment converts each gate included in the quantum circuit, the gate is converted into a circuit that increases the number of quantum bits to three or more and includes a detection circuit that detects X errors for three or more quantum bits.

[0037] Specifically, the classical computer 110 converts the X gate included in the quantum circuit before conversion into a logical X gate as shown in Fig. 5. The logical X gate is a circuit that increases the number of quantum bits to three or more and executes the X gate for the three or more quantum bits.

[0038] Furthermore, the classical computer 110 converts the Y gate included in the quantum circuit before conversion into a logical Y gate as shown in Fig. 6. The logical Y gate is a circuit in which the number of quantum bits is increased to three or more, a Y gate is executed for the first quantum bit, and an X gate is executed for each of the second and subsequent quantum bits.

[0039] Furthermore, the classical computer 110 converts the Z gate included in the quantum circuit before conversion into a logical Z gate as shown in Fig. 7. The logical Z gate is a circuit in which the number of quantum bits is increased to three or more and a Z gate is executed for the first quantum bit.

[0040] Here, a circuit written by three non-intersecting lines such as a logic X gate, a logic Y gate, and a logic Z gate has fault tolerance.

[0041] Furthermore, the classical computer 110 converts the CX gate included in the quantum circuit before conversion into a logical CX gate as shown in Fig. 8. The logical CX gate is a circuit that increases the control bits to three or more, increases the target bits to three or more, and executes the CX gate for pairs of control bits and target bits.

[0042] Furthermore, the classical computer 110 converts the CZ (Controlled-Z) gate included in the pre-conversion quantum circuit into a logical CZ gate as shown in Fig. 9. The logical CZ gate is a circuit that increases the control bits to three or more and includes a first detection circuit SM that detects X errors for the three or more control bits, and a second detection circuit SM that increases the target bits to three or more and detects X errors for the three or more target bits.

[0043] When performing quantum computation, if an error is detected in either the first detection circuit SM or the second detection circuit SM, the computation is redone, or, after all computations have been completed, an event in which no error was detected in either the first detection circuit SM or the second detection circuit SM is post-selected.

[0044] In addition, the classical computer 110 converts the S gate included in the quantum circuit before conversion into a logical S gate as shown in Figure 10. The logical S gate is a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares a +1 eigenstate of the Y operator and three or more quantum bits, performs a measurement in the Z basis on the result of executing the logical CX gate, and executes a logical Y gate on three or more outputs of a circuit that prepares a +1 eigenstate of the Y operator |+i>L-prep. in accordance with the measurement value. In Figure 10, the gates connected by double lines indicate that they are executed only when the measurement value is 1.

[0045] As shown in FIG. 11, the circuit |+i>L-prep. for preparing the +1 eigenstate of the Y operator executes an H gate on the first of the three quantum bits, executes a CX gate on the execution result of the H gate and the second quantum bit, executes a CX gate on the execution result of the H gate and the third quantum bit, then executes an S gate on the execution result of the H gate, and detects an X error on the execution result of the S gate and the second quantum bit. １２ It is a circuit including:

[0046] When performing quantum computation, the detection circuit SM １２ When an error is detected, the calculation is redone, or after all the calculations are completed, the detection circuit SM １２ Events in which an error is detected are discarded, and events in which no error is detected are selected later.

[0047] The classical computer 110 also converts the H gate included in the pre-conversion quantum circuit into a logical H gate as shown in Fig. 12. The logical H gate is a circuit that increases the number of quantum bits to three or more, executes a logical CZ gate on the output of a circuit prep. |+>L that prepares a +1 eigenstate of the X operator, and the three or more quantum bits, measures the result of executing the logical CZ gate in the X basis, and executes an X logic circuit on the three or more outputs of the circuit that prepares the eigenstate of the X operator according to the measurement value, and includes a first detection circuit SM that detects an X error in the three or more outputs of the circuit that prepares the eigenstate of the X operator, and a second detection circuit SM that detects an X error in the result of executing the logical CZ gate.

[0048] When performing quantum computation, events in which an X error is detected by only one of the first detection circuit SM and the second detection circuit SM, i.e., events in which a Z error is detected, are excluded, and events in which a Z error is not detected are subsequently selected.

[0049] As shown in FIG. 13, the circuit prep. |+>L for preparing the eigenstate of the X operator is a circuit that executes an H gate on the first of three quantum bits, executes a CX gate on the execution result of the H gate and the second quantum bit, and executes a CX gate on the execution result of the H gate and the third quantum bit.

[0050] The circuit for performing measurements in the X base is the circuit shown in FIG. 14, and outputs the measured value.

[0051] Furthermore, the classical computer 110 converts the Rz gate included in the quantum circuit before conversion into a logical Rz gate shown in Fig. 15. The logical Rz gate is a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares a +1 eigenstate of the Z operator, operates an Rz gate on any one of the results of executing the logical CX gate, performs a measurement in the X basis, executes a logical Z gate on three or more quantum bits according to the measurement value, and includes a detection circuit that detects an X error in the result of operating the Rz gate on any one of the results of executing the logical CX gate.

[0052] Furthermore, the classical computer 110 converts the Ry gates included in the pre-conversion quantum circuit into logical Ry gates.

[0053] The logic Ry gate is a circuit that sequentially executes a logic S dagger gate, a logic H gate, a logic Rz gate, a logic H gate, and a logic S gate. The logic S dagger gate is a circuit that increases the number of quantum bits to three or more, executes a logic CX gate on the output of a circuit that prepares a −1 eigenstate of the Y operator and three or more quantum bits, measures the result of executing the logic CX gate in the Z basis, and executes a Y logic circuit on three or more outputs of the circuit that prepares a −1 eigenstate of the Y operator according to the measurement value.

[0054] The classical computer 110 may convert the Ry gate included in the quantum circuit before conversion into a circuit that sequentially executes an S-dagger gate, an H gate, an Rz gate, an H gate, and an S gate, and then converts each of these into a logic gate. Alternatively, the classical computer 110 may directly convert the Ry gate included in the quantum circuit before conversion into a circuit that sequentially executes a logical S-dagger gate, a logical H gate, a logical Rz gate, a logical H gate, and a logical S gate.

[0055] Furthermore, the classical computer 110 converts the Rx gates included in the pre-conversion quantum circuit into logical Rx gates. The logical Rx gate is a circuit that executes a logical H gate, a logical Rz gate, and a logical H gate in sequence.

[0056] The classical computer 110 may convert the Rx gate included in the quantum circuit before conversion into a circuit that executes an H gate, an Rz gate, and an H gate in sequence, and then convert each of these into a logic gate. Alternatively, the classical computer 110 may directly convert the Rx gate included in the quantum circuit before conversion into a circuit that executes a logical Rx gate, a logical H gate, a logical Rz gate, and a logical H gate in sequence.

[0057] By combining the various types of gates described above, any quantum computation can be performed.

[0058] A quantum circuit is expressed as a combination of gates such as the X gate, Y gate, Z gate, H gate, S gate, Rz gate, CX gate, and CZ gate. The response of each gate when erroneous data is input is known in advance.

[0059] For example, when erroneous data is input, the X gate, Y gate, and Z gate respond as shown in Figure 16. Figure 16 shows that when an X error occurs on the left side of the circuit (input state), it is transmitted directly to the right side of the circuit (output state).

[0060] Furthermore, when erroneous data is input, the H gate responds as shown in Figure 17. Figure 17 shows that if an X error occurs on the left side of the circuit, it changes to a Z error as it propagates to the right.

[0061] In addition, as shown in Figure 18, the response of the CX gate differs depending on whether an error occurs in the upper or lower stage. Figure 18 shows that when an X error occurs in the upper stage, the X error is propagated to both the upper and lower stages. Also, when an X error occurs in the lower stage, the X error is propagated to the lower stage.

[0062] Furthermore, when data with an error is input, the CZ gate responds as shown in Fig. 19. In Fig. 19, when an X error is input to the upper stage, the X error is propagated to the upper stage and changes to a Z error in the lower stage.

[0063] Furthermore, as shown in Figure 20, when an X error is input to a logic CZ gate, there is a possibility that a Z error will be generated, but since this always appears in pairs with an X error, the Z error can be indirectly detected by detecting the X error using the error detection circuit SM. Figure 20 shows an example in which the Z error that has changed in the lower stage can be indirectly detected by detecting the X error using the error detection circuit SM in the upper stage. If a Z error is detected, the calculation result can be removed by post-selection so that it will not be used.

[0064] 21, when an X error is input to the logic CZ gate, the X error is transmitted through the error detection circuit SM. In the final state, an X error occurs in only one of the three quantum bits, so this is fault-tolerant. Furthermore, even if an X error occurs in another location (for example, inside the error detection circuit SM), it can be seen that the system is similarly fault-tolerant.

[0065] Also, as shown in Figure 22, there is a possibility that a Z error may be generated inside a logic H gate, but since this always appears in pairs with an X error, the Z error can be indirectly detected by detecting the X error using the error detection circuit SM. Figure 22 shows an example in which the Z error that has changed in the upper stage can be indirectly detected by detecting the X error using the error detection circuit SM in the lower stage. If a Z error is detected, the calculation can be redone at that point, or the calculation result can be removed by post-selection so that it will not be used.

[0066] [Error Correction] The classical computer 110 of the hybrid system 100 of this embodiment may be further converted to insert an error correction circuit that executes an X gate operation in response to the detection result of the detection circuit that detects the X error into the quantum circuit.

[0067] Every gate has a certain probability of failure, and the failure probability accumulates according to the number of gate operations.

[0068] However, since the circuit scale of the error correction circuit is relatively large and the error correction circuit itself can be a cause of errors, it is better not to insert it unlimitedly.

[0069] Therefore, the classical computer 110 further determines the insertion position of the error correction circuit, and converts the quantum circuit so that the error correction circuit is inserted at the determined insertion position.

[0070] Here, the error correction circuit will be described.

[0071] The X operator is X ２ = 1 property, the error can be corrected by applying an X gate to the location where the X error occurred, as they cancel each other out.

[0072] 23, the error correction circuit executes an X gate operation in accordance with the detection result of an error detection circuit SM that detects an X error. More specifically, the error detection circuit SM can identify the position of a quantum bit in which an error has occurred, and the identified quantum bit is made to execute an X gate.

[0073] For example, as shown in Fig. 24, when no error is input to any quantum bit, the two measurement values ​​are (1, 1). Also, as shown in Fig. 25, when an X error is input to the first quantum bit, the two measurement values ​​are (-1, 1). Also, as shown in Fig. 26, when an X error is input to the second quantum bit, the two measurement values ​​are (-1, -1). Also, as shown in Fig. 27, when an X error is input to the third quantum bit, the two measurement values ​​are (1, -1).

[0074] However, since the error detection circuit SM itself can be a source of errors, the act of error correction itself must also be fault-tolerant.

[0075] In other words, in principle, the location of an error can be identified by a single error detection by the error detection circuit, but if we consider the possibility that the error detection circuit SM may become the source of the error, it may recognize the wrong location as the error location.

[0076] For example, as shown in Figure 28, suppose an X error occurs near the center of the error detection circuit. At this time, the error detection circuit determines that there is an error in the third quantum bit. If error correction is performed based on this, an X gate will be executed on the third quantum bit, and as a result, the error will be placed on the second and third quantum bits.

[0077] Therefore, in this embodiment, the error correction circuit is configured to perform error detection twice in succession using the error detection circuit, as shown in Figure 29. The error correction circuit has four measuring devices A to D, and there are 19 locations where X errors can occur (see numbers 1 to 19 in Figure 29).

[0078] Error correction is performed according to the lookup table shown in Figure 30. The first column of the lookup table indicates the location where the error occurred, and the second to fifth columns indicate the values ​​of measuring devices A to D at that time (taking two values: 1 and -1). The sixth column indicates the error correction operation. Xn means that an X gate is executed on the nth quantum bit. I means that nothing is done.

[0079] The measurement values ​​for the case where an error occurs in the second qubit (error location = 2, 5, 6) and the case where an error occurs in the second qubit but cannot be distinguished from a fault in the third qubit (error location = 13) are different, so the two can be separated. As a result, the risk of causing the wrong qubit to execute the X gate is reduced.

[0080] In this way, if an error detection circuit repeats error detection twice and identifies the location of the error based on the results, fault-tolerant error correction becomes possible.

[0081] In addition, in the conversion process to insert an error correction circuit, the conversion is performed so that an error correction circuit is inserted when the cumulative probability is greater than the error probability (noise probability) of the error correction circuit.

[0082] Specifically, when determining the insertion position of an error correction circuit, a predetermined error probability is cumulatively added from the input side of the quantum circuit according to the type of gate, and the position where the cumulative addition result exceeds a threshold is determined as the insertion position of the error correction circuit. For example, there is a table that lists the error probability to be added for each type of gate, and when the circuit is input, the error probability is added for each type of gate from left to right, and when a certain probability is exceeded, an error correction circuit is inserted. After insertion, the error probability is returned to a constant value, and the same operation is repeated from that point.

[0083] Alternatively, when determining the insertion position of the error correction circuit, the insertion position of the error correction circuit is determined based on the results of simulation of the quantum circuit for each of a plurality of patterns regarding the insertion position of the error correction circuit. For example, a numerical simulation is performed to determine the accuracy for each of a plurality of patterns in which a plurality of error correction circuits are inserted in the quantum circuit before insertion, and the pattern that results in the highest accuracy is determined as the insertion position of the error correction circuit.

[0084] [Operation of Hybrid System 100 of the Embodiment] Next, a specific operation of the hybrid system 100 of the embodiment will be described. Each device of the hybrid system 100 executes each process shown in FIG.

[0085] First, in step S100, the user terminal 130 transmits to the classical computer 110 computation target information, which is information about the computation target, and computation method information, which is information about the computation method, both input by the user.

[0086] The calculation target information includes, for example, information about the target system (e.g., information about the coefficient matrix when the equation of motion of the target system is expressed in matrix form) and quantum computer information (e.g., the type of quantum computer or pseudo-quantum computer used by the user).

[0087] Next, in step S102, the classical computer 110 receives the computation target information and computation method information transmitted from the user terminal 130.

[0088] In step S104, the classical computer 110 generates a quantum circuit based on information about the structure of the quantum circuit included in the calculation method information. The classical computer 110 also determines the initial state of the quantum based on information about the initial state included in the calculation method information.

[0089] In step S105, the classical computer 110 converts each gate included in the quantum circuit generated in step S104 into a gate that is predetermined to have fault tolerance and bias preservation properties.

[0090] Specifically, the information storage unit 113 of the classical computer 110 has a database that stores, for each type of gate, gates that have fault tolerance and bias preservation properties corresponding to the type of gate.

[0091] The classical computer 110 refers to the database held by the information storage unit 113 and performs a process of converting each gate included in the quantum circuit into a circuit that increases the number of quantum bits to three or more and includes a detection circuit that detects X errors for three or more quantum bits.

[0092] Furthermore, the classical computer 110 converts the quantum circuit so as to insert an error correction circuit. Specifically, the classical computer 110 further determines the insertion position of the error correction circuit, and converts the quantum circuit so as to insert the error correction circuit at the determined insertion position.

[0093] In step S106, the classical computer 110 transmits various pieces of information necessary for quantum computation to the quantum computer 120. Specifically, the classical computer 110 transmits to the quantum computer 120 the quantum initial state determined in step S104 and the transformed quantum circuit obtained in step S105.

[0094] In step S108, the control device 121 of the quantum computer 120 receives the various information transmitted from the classical computer 110 in step S104.

[0095] In step S110, the control device 121 of the quantum computer 120 causes the quantum computer 120 to perform quantum computation according to the various information received in step S108. Specifically, the quantum computer 120 executes the converted quantum circuit obtained in step S105 and obtains the execution result.

[0096] Specifically, quantum computer 120 generates an electromagnetic wave to be irradiated onto at least one of quantum bits in quantum bit group 123 in accordance with the control of control device 121. Then, quantum computer 120 irradiates the generated electromagnetic wave onto at least one of quantum bits in quantum bit group 123, thereby executing a quantum circuit. The gate operation of each quantum gate included in the quantum circuit is converted into a corresponding electromagnetic wave waveform, and the generated electromagnetic wave is irradiated onto quantum bit group 123 by electromagnetic wave generating device 122. Then, quantum computer 120 outputs the execution result of the quantum circuit.

[0097] In step S112, the control device 121 transmits the execution result obtained in step S110 to the classical computer 110.

[0098] In step S114, the classical computer 110 receives the execution result sent from the control device 121 in step S112.

[0099] In step S118, the classical computer 110 transmits the execution result obtained in step S114 to the user terminal 130.

[0100] In step S120, the user terminal 130 receives the results sent from the classical computer 110.

[0101] The user checks the results displayed on the display unit (not shown) of the user terminal 130 .

[0102] As described above, the classical computer of the hybrid system of the embodiment acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and outputs a converted quantum circuit including the converted gates. In this way, a quantum circuit with fault tolerance and bias preservation can be obtained.

[0103] Furthermore, the classical computer further converts the quantum circuit generated based on the target computation information so that an error correction circuit that executes the operation of the X gate is inserted according to the detection result of the detection circuit that detects the X error, thereby obtaining a quantum circuit that can perform quantum computation with high accuracy.

[0104] The classical computer also determines the insertion position of an error correction circuit for a quantum circuit generated based on the target computational information, and converts the quantum circuit so that the error correction circuit is inserted at the determined insertion position. This allows for error correction at the appropriate time, resulting in a quantum circuit that can perform quantum computation with high accuracy.

[0105] The technology of the present disclosure is not limited to the above-described embodiments and examples, and various modifications and applications are possible within the scope of the gist of the present invention.

[0106] For example, in the above embodiment, any method may be used to transmit and receive information between the classical computer 110 and the quantum computer 120. For example, transmission and reception of quantum circuit parameters and execution results between the classical computer 110 and the quantum computer 120 may be performed sequentially each time a predetermined calculation is completed, or may be performed after all calculations are completed.

[0107] Furthermore, in the above embodiment, an example has been described in which calculation target information is transmitted from the user terminal 130 to the classical computer 110, and the classical computer 110 executes calculations according to the calculation target information, but the present invention is not limited to this. The user terminal 130 may transmit the calculation target information to the classical computer 110 or a storage medium or storage device accessible to the classical computer 110 via a computer network such as an IP network, or may store the calculation target information in a storage medium or storage device and hand it over to the operator of the classical computer 110, who then inputs the calculation target information into the classical computer 110 using the storage medium or storage device.

[0108] Furthermore, in the above embodiment, the quantum circuit is executed by irradiating electromagnetic waves, but the present invention is not limited to this, and the quantum circuit may be executed by a different method.

[0109] In the above embodiment, the quantum computer 120 performs the calculations, but the present invention is not limited to this. For example, the calculations may be performed by a classical computer that simulates the behavior of a quantum computer.

[0110] Furthermore, although the above embodiment assumes that the classical computer 110 and the quantum computer 120 are managed by different organizations, the classical computer 110 and the quantum computer 120 may be managed as a single entity by the same organization. In this case, it is unnecessary to transmit various types of information from the classical computer 110 to the quantum computer 120 and to transmit execution results from the quantum computer 120 to the classical computer 110. In this case, it is also conceivable that the control device 121 of the quantum computer 120 will play the role of the classical computer 110 in the above description.

[0111] If a quantum computer exists that can replace part or all of the processing of the classical computer described in this embodiment, then part or all of the processing may be performed by the quantum computer.

[0112] It should be noted that in the above embodiments, unless there is a description of "only" such as "based on XX only," "depending only on XX," or "in the case of XX only," this specification assumes that additional information may also be taken into consideration. For example, the description "in the case of a, do b" does not necessarily mean "in the case of a, always do b," unless explicitly stated otherwise.

[0113] Furthermore, in the above embodiments, expressions such as "optimize" or "optimized parameters" are used, but it should be noted that these expressions of "optimization" mean approaching an optimal state. Therefore, when trying to obtain parameters that minimize a certain function, it should be noted that the parameters obtained by optimizing the function may be a local solution rather than a global solution that minimizes the function.

[0114] Furthermore, even if there is an aspect of a method, program, terminal, device, server, or system (hereinafter referred to as a "method, etc.") that performs an operation different from that described in this specification, each aspect of the disclosed technology is directed to an operation identical to one of the operations described in this specification, and the existence of an operation different from that described in this specification does not make the method, etc. outside the scope of each aspect of the disclosed technology.

[0115] Furthermore, although the present specification has been described as an embodiment in which the program is pre-installed, the program may also be provided by being stored on a computer-readable recording medium.

[0116] Furthermore, each component of the hybrid system of this embodiment does not have to be realized by a single computer or server, but may be realized in a distributed manner across multiple computers connected by a network.

[0117] For example, the processing performed by the classical computer of each of the above embodiments may be distributed among multiple classical computers connected by a network. Alternatively, the processing performed by the quantum computer of each of the above embodiments may be distributed among multiple quantum computers connected by a network. In this case, a hybrid system is formed by at least one classical computer and at least one quantum computer.

[0118] All publications, patent applications, and technical standards mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.

[0119] (Supplementary Notes) The following supplementary notes are provided regarding aspects of the present disclosure.

[0120] (Supplementary Note 1) An information processing device that acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and outputs a converted quantum circuit including the converted gates.

[0121] (Supplementary Note 2) The information processing device according to Supplementary Note 1, wherein when converting each gate included in the quantum circuit, the information processing device converts the gate into a circuit that increases the number of quantum bits to three or more and includes a detection circuit that detects X errors for the three or more quantum bits.

[0122] (Supplementary Note 3) The information processing device according to Supplementary Note 1 or 2, further comprising: a database storing, for each type of gate, gates having fault tolerance and bias preservation properties corresponding to the type of gate; and converting each gate included in the quantum circuit by referring to the database.

[0123] (Supplementary Note 4) The information processing device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the information processing device converts a CZ (Controlled-Z) gate included in the quantum circuit into a circuit including: a first detection circuit that increases the number of control bits to three or more and detects an X error for the three or more control bits; and a second detection circuit that increases the number of target bits to three or more and detects an X error for the three or more target bits.

[0124] (Supplementary Note 5) The information processing device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the information processing device converts the S gate included in the quantum circuit into a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares a +1 eigenstate of the Y operator and the three or more quantum bits, measures the result of executing the logical CX gate in the Z basis, and, depending on the measurement value, executes a logical Y gate on the three or more outputs of the circuit that prepares the +1 eigenstate of the Y operator.

[0125] (Supplementary Note 6) The information processing device according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the information processing device converts an H gate included in the quantum circuit into a circuit that increases the number of quantum bits to three or more, executes a logical CZ gate on an output of a circuit that prepares an eigenstate of an X operator and the three or more quantum bits, measures a result of executing the logical CZ gate in the X basis, and executes a logical X gate on the three or more outputs of the circuit that prepares the eigenstate of the X operator according to the measurement value, and includes a first detection circuit that detects an X error in the three or more outputs of the circuit that prepares the eigenstate of the X operator, and a second detection circuit that detects an X error in the result of executing the logical CZ gate.

[0126] (Supplementary Note 7) The information processing device according to any one of Supplementary Notes 1 to 6, wherein the Rz gate included in the quantum circuit is converted into a circuit including a detection circuit that detects an X error, the Rz gate increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares eigenstates of the Z operator, acts on any one of the results of executing the logical CX gate, and performs a measurement in the X basis by acting on the Rz gate, and executes a logical Z gate on the three or more quantum bits according to the measurement value, and the result of executing the logical CX gate and acting on any one of the results by acting on the Rz gate is converted into a circuit including a detection circuit that detects an X error.

[0127] (Supplementary Note 8) The information processing device converts the Ry gate included in the quantum circuit into a circuit that sequentially executes a logical S dagger gate, a logical H gate, a logical Rz gate, a logical H gate, and a logical S gate, and the logical S dagger gate is a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares a −1 eigenstate of the Y operator and the three or more quantum bits, measures the result of executing the logical CX gate in the Z basis, and executes a Y logic circuit on the three or more outputs of the circuit that prepares the −1 eigenstate of the Y operator according to the measurement value, the logic H gate is a circuit which increases the number of quantum bits to three or more, executes a logic CZ gate on the output of a circuit which prepares an eigenstate of the X operator and the three or more quantum bits, measures the result of executing the logic CZ gate in the X basis, and executes an X logic circuit on the three or more outputs of the circuit which prepares the eigenstate of the X operator according to the measurement value, and includes a first detection circuit which detects an X error in the three or more outputs of the circuit which prepares the eigenstate of the X operator, and a second detection circuit which detects an X error in the result of executing the logic CZ gate; the logic Rz gate is a circuit which increases the number of quantum bits to three or more, executes a logic CX gate on the output of a circuit which prepares an eigenstate of the Z operator, acts an Rz gate on any one of the results of executing the logic CX gate, measures the X basis, and executes a logic Z gate on the three or more quantum bits according to the measurement value, and includes a detection circuit which detects an X error in the result of executing the logic CX gate and acting on any one of the results; The logic S gate increases the number of quantum bits to three or more, executes a logic CX gate on the output of a circuit that prepares a +1 eigenstate of the Y operator and three or more quantum bits, performs a measurement in the Z basis on the result of executing the logic CX gate, and executes a Y logic circuit on three or more outputs of the circuit that prepares a +1 eigenstate of the Y operator according to the measurement value.

[0128] (Supplementary Note 9) The information processing device converts an Rx gate included in the quantum circuit into a circuit which sequentially executes a logical H gate, a logical Rz gate, and a logical H gate, and the logical H gate increases the number of quantum bits to three or more, executes a logical CZ gate on the output of a circuit which prepares an eigenstate of an X operator and the three or more quantum bits, measures the result of executing the logical CZ gate in the X basis, and executes an X logic circuit on the three or more outputs of the circuit which prepares the eigenstate of the X operator according to the measurement value, and includes a first detection circuit which detects an X error in the three or more outputs of the circuit which prepares the eigenstate of the X operator, and a second detection circuit which detects an X error in the result of executing the logical CZ gate, The logical Rz gate increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares an eigenstate of the Z operator, and acts on any one of the results of executing the logical CX gate to perform a measurement in the X basis, and executes a logical Z gate on three or more quantum bits according to the measurement value, and also includes a detection circuit that detects an X error in the result of acting on any one of the results of executing the logical CX gate and acting on the Rz gate.

[0129] (Supplementary Note 10) The information processing device according to any one of Supplementary Note 1 to Supplementary Note 9, further converting the quantum circuit so as to insert an error correction circuit that executes an operation of an X gate according to a detection result of a detection circuit that detects an X error.

[0130] (Supplementary Note 11) The information processing device according to Supplementary Note 10, wherein the error correction circuit executes an operation of an X gate in response to detection results of a plurality of detection circuits that detect X errors.

[0131] (Supplementary Note 12) The information processing device according to Supplementary Note 10, further comprising: determining an insertion position of the error correction circuit; and inserting the error correction circuit into the determined insertion position.

[0132] (Supplementary Note 13) The information processing device according to Supplementary Note 12, wherein when determining the insertion position of the error correction circuit, the information processing device cumulatively adds up error probabilities predetermined according to the type of gate from the input side of the quantum circuit, and determines the position where the cumulative addition result is equal to or greater than a threshold as the insertion position of the error correction circuit.

[0133] (Supplementary Note 14) The information processing device according to Supplementary Note 12, wherein when determining the insertion position of the error correction circuit, the information processing device determines the insertion position of the error correction circuit based on a simulation result for a quantum circuit in each of a plurality of patterns regarding the insertion position of the error correction circuit.

[0134] (Supplementary Note 15) A quantum information processing program for causing a computer to execute the following process: acquiring a quantum circuit generated based on target computation information; converting each gate included in the acquired quantum circuit into a predetermined gate that has fault tolerance and bias preservation properties; and outputting a converted quantum circuit including the converted gates.

[0135] (Supplementary Note 16) A quantum information processing method executed by a computer, comprising: acquiring a quantum circuit generated based on target computation information; converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation; and outputting a converted quantum circuit including the converted gates.

[0136] (Supplementary Note 17) A hybrid system including a classical module that performs classical computation and a quantum module that performs quantum computation, wherein the classical module acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and transmits a converted quantum circuit including the converted gates to the quantum module, the quantum module executes the converted quantum circuit to acquire an execution result of the converted quantum circuit and transmits the execution result of the converted quantum circuit to the classical module, and the classical module acquires the execution result of the converted quantum circuit.

[0137] (Supplementary Note 18) An information processing device including: a memory; and at least one processor connected to the memory, wherein the processor is configured to: acquire a quantum circuit generated based on target computation information; convert each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation; and output a converted quantum circuit including the converted gates.

[0138] (Supplementary Note 19) A non-transitory storage medium storing a program executable by a computer to perform information processing, wherein the information processing includes: acquiring a quantum circuit generated based on target computational information; converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation; and outputting a converted quantum circuit including the converted gates.

Claims

1. An information processing device that acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation properties, and outputs a converted quantum circuit including the converted gates.

2. The information processing device according to claim 1, wherein, when converting each gate included in the quantum circuit, the information processing device converts the gate into a circuit that increases the number of quantum bits to three or more and includes a detection circuit that detects X errors for the three or more quantum bits.

3. The information processing device according to claim 1, further comprising a database storing, for each type of gate, gates having fault tolerance and bias preservation properties corresponding to said type of gate, and converting each gate included in said quantum circuit by referring to said database.

4. The information processing device according to claim 1, wherein the information processing device converts a CZ (Controlled-Z) gate included in the quantum circuit into a circuit including: a first detection circuit that increases the control bits to three or more and detects an X error for the three or more control bits; and a second detection circuit that increases the target bits to three or more and detects an X error for the three or more target bits.

5. The information processing device according to claim 1, wherein the information processing device converts the S gate included in the quantum circuit into a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit preparing a +1 eigenstate of the Y operator and the three or more quantum bits, measures the result of executing the logical CX gate in the Z basis, and, depending on the measurement value, executes a logical Y gate on the three or more outputs of the circuit preparing the +1 eigenstate of the Y operator.

6. The information processing device according to claim 1, wherein the information processing device converts an H gate included in the quantum circuit into a circuit that increases the number of quantum bits to three or more, executes a logical CZ gate on the output of a circuit preparing an eigenstate of an X operator and the three or more quantum bits, measures a result of executing the logical CZ gate in the X basis, and executes a logical X gate on the three or more outputs of the circuit preparing an eigenstate of an X operator according to the measurement value, and includes a first detection circuit that detects an X error in the three or more outputs of the circuit preparing an eigenstate of an X operator, and a second detection circuit that detects an X error in the result of executing the logical CZ gate.

7. The information processing device according to claim 1, wherein the information processing device converts an Rz gate included in the quantum circuit into a circuit including a detection circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares an eigenstate of the Z operator, acts on any one of the results of executing the logical CX gate to perform a measurement in the X basis, executes a logical Z gate on three or more quantum bits according to the measurement value, and detects an X error in the result of acting on any one of the results of executing the logical CX gate and acting on the Rz gate.

8. The information processing device converts the Ry gate included in the quantum circuit into a circuit that sequentially executes a logical S dagger gate, a logical H gate, a logical Rz gate, a logical H gate, and a logical S gate, and the logical S dagger gate is a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares a -1 eigenstate of the Y operator and the three or more quantum bits, measures the result of executing the logical CX gate in the Z basis, and executes a Y logic circuit on the three or more outputs of the circuit that prepares the -1 eigenstate of the Y operator according to the measurement value, The logic H gate is a circuit which increases the number of quantum bits to three or more, executes a logic CZ gate on the output of a circuit preparing an eigenstate of an X operator and three or more quantum bits, measures the result of executing the logic CZ gate in the X basis, executes an X logic circuit on three or more outputs of the circuit preparing an eigenstate of an X operator according to the measured value, and includes a first detection circuit which detects an X error in the three or more outputs of the circuit preparing an eigenstate of an X operator, and a second detection circuit which detects an X error in the result of executing the logic CZ gate; the logic Rz gate is a circuit which increases the number of quantum bits to three or more, executes a logic CX gate on the output of a circuit preparing an eigenstate of a Z operator, operates an Rz gate on any one of the results of executing the logic CX gate, measures in the X basis, executes a logic Z gate on three or more quantum bits according to the measured value, and includes a detection circuit which detects an X error in the result of executing the logic CX gate and operates the Rz gate on any one of the results; The logic S gate is a circuit that increases the number of quantum bits to three or more, executes a logic CX gate on the output of a circuit that prepares a +1 eigenstate of the Y operator and the three or more quantum bits, measures the result of executing the logic CX gate in the Z basis, and executes a Y logic circuit on three or more outputs of the circuit that prepares the +1 eigenstate of the Y operator according to the measurement value.

9. The information processing device converts the Rx gate included in the quantum circuit into a circuit which sequentially executes a logical H gate, a logical Rz gate, and a logical H gate, and the logical H gate increases the number of quantum bits to three or more, executes a logical CZ gate on the output of a circuit which prepares an eigenstate of an X operator and the three or more quantum bits, measures the result of executing the logical CZ gate in the X basis, and executes an X logic circuit on the three or more outputs of the circuit which prepares an eigenstate of an X operator according to the measurement value, and includes a first detection circuit which detects an X error in the three or more outputs of the circuit which prepares an eigenstate of an X operator, and a second detection circuit which detects an X error in the result of executing the logical CZ gate, The logical Rz gate is a circuit that increases the number of quantum bits to three or more, executes a logical CX gate on the output of a circuit that prepares an eigenstate of the Z operator, and operates an Rz gate on any one of the results of executing the logical CX gate to perform a measurement in the X basis, executes a logical Z gate on three or more quantum bits according to the measurement value, and includes a detection circuit that detects an X error in the result of operating the Rz gate on any one of the results of executing the logical CX gate.

10. The information processing device according to claim 1, further comprising: a conversion circuit for converting said quantum circuit to insert an error correction circuit for executing an operation of an X gate in response to a detection result of a detection circuit for detecting an X error.

11. An information processing device according to claim 10, wherein said error correction circuit executes an X gate operation in response to detection results from a plurality of detection circuits which detect X errors.

12. The information processing device according to claim 10, further comprising: determining an insertion position of the error correction circuit; and inserting the error correction circuit into the determined insertion position.

13. The information processing device according to claim 12, when determining the insertion position of the error correction circuit, accumulates an error probability predetermined according to the type of gate from the input side of the quantum circuit, and determines the position where the accumulated addition result becomes equal to or exceeds a threshold value as the insertion position of the error correction circuit.

14. The information processing device according to claim 12, wherein when determining the insertion position of the error correction circuit, the information processing device determines the insertion position of the error correction circuit based on a simulation result for a quantum circuit in each of a plurality of patterns regarding the insertion position of the error correction circuit.

15. A quantum information processing program for causing a computer to execute the following process: acquiring a quantum circuit generated based on target computational information; converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation properties; and outputting a converted quantum circuit including the converted gates.

16. A quantum information processing method executed by a computer, comprising: acquiring a quantum circuit generated based on target computational information; converting each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation properties; and outputting a converted quantum circuit including the converted gates.

17. A hybrid system including a classical module that performs classical computation and a quantum module that performs quantum computation, wherein the classical module acquires a quantum circuit generated based on target computation information, converts each gate included in the acquired quantum circuit into a gate that is predetermined to have fault tolerance and bias preservation, and transmits a converted quantum circuit including the converted gates to the quantum module, the quantum module executes the converted quantum circuit to acquire an execution result of the converted quantum circuit, and transmits the execution result of the converted quantum circuit to the classical module, and the classical module acquires the execution result of the converted quantum circuit.

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