Multi-level inverter

Abstract

The present invention reduces the noise of a multi-level inverter. A multilevel inverter (100) comprises: a positive wiring part (4); a negative wiring part (5); a DC power supply part (3); a plurality of inverter circuits (1); a control device (6); and a noise filter (8). The DC power supply unit (3) has a first capacitor (C1) and a second capacitor (C2), and is connected in series between the positive wiring part (4) and the negative wiring part (5) in the order of the first capacitor (C1) and the second capacitor (C2) from the positive wiring part (4) side. The plurality of inverter circuits (1) are connected between the positive wiring part (4) and the negative wiring part (5), and are connected to an intermediate potential point (M1) between the first capacitor (C1) and the second capacitor (C2). The control device (6) controls the plurality of inverter circuits (1). The noise filter (8) is provided on a path (33) between the positive wiring part (4) and the negative wiring part (5) in the DC power supply part (3).

Description

Multilevel Inverter

[0001] The present disclosure relates to multilevel inverters, and more particularly to multilevel inverters having multiple capacitors connected in series between positive and negative wiring.

[0002] Patent Document 1 discloses a neutral point clamped multilevel converter (multilevel inverter).

[0003] The multilevel converter disclosed in Patent Document 1 includes a DC voltage link including a positive rail (positive wiring section) and a negative rail (negative wiring section), two capacitors connected in series across the DC voltage link, three legs each including four switches, and a controller.

[0004] US Patent Application Publication No. 2015 / 0318788

[0005] In a multilevel inverter, there are cases where it is required to reduce noise.

[0006] An object of the present disclosure is to provide a multilevel inverter capable of reducing noise.

[0007] A multilevel inverter according to one aspect of the present disclosure includes a positive wiring section, a negative wiring section, a DC power supply section, multiple inverter circuits, a control device, and a noise filter. The DC power supply section has a first capacitor and a second capacitor. In the DC power supply section, the first capacitor and the second capacitor are connected in series between the positive wiring section and the negative wiring section, with the first capacitor and the second capacitor arranged in this order from the positive wiring section side. The multiple inverter circuits are connected between the positive wiring section and the negative wiring section and are connected to an intermediate potential point between the first capacitor and the second capacitor. The control device controls the multiple inverter circuits. The noise filter is provided on a path between the positive wiring section and the negative wiring section in the DC power supply section.

[0008] The multilevel inverter of the present disclosure has the effect of making it possible to reduce noise.

[0009] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment. FIG. 2 is a more specific circuit diagram of a system including the multilevel inverter according to the first embodiment than FIG. 1 . FIG. 3 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a first switching state. FIG. 4 is an explanatory diagram of a discharge path and a charge path when a switching circuit in the multilevel inverter according to the first embodiment is in the first switching state. FIG. 5 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a second switching state. FIG. 6 is an explanatory diagram of a discharge path and a charge path when a switching circuit in the multilevel inverter according to the first embodiment is in the second switching state. FIG. 7 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the first embodiment is in a third switching state. FIG. 8 is an explanatory diagram of a discharge path and a charge path when a switching circuit in the multilevel inverter according to the first embodiment is in the third switching state. FIG. 9 is an explanatory diagram of a voltage command value for each phase in the multilevel inverter according to the first embodiment. FIG. 10 is an explanatory diagram of a group of voltage vectors related to the multilevel inverter according to the first embodiment. FIG. 11 is a more detailed explanatory diagram of a group of voltage vectors related to the multilevel inverter according to the first embodiment. FIG. 12 is a vector diagram for explaining the operation of a control unit in the multilevel inverter according to the first embodiment. FIG. 13 is a time chart of the switching states of each phase of the multilevel inverter according to the first embodiment. FIG. 14 is a time chart of the on / off states of first to fourth switching elements of the multilevel inverter according to the first embodiment. FIG. 15 is a circuit diagram used when measuring conducted noise generated when a noise filter is not provided in the multilevel inverter according to the first embodiment. FIG. 16 is an explanatory diagram of the path along which conducted noise generated when a noise filter is not provided in the multilevel inverter according to the first embodiment flows.17 is a graph showing frequency characteristics of noise voltage levels generated when a noise filter is not provided in the multilevel inverter according to the first embodiment and when a noise filter is provided in the load wiring section. FIG. 18 is a graph showing frequency characteristics of noise voltage levels when the capacitance of the third capacitor is changed in the multilevel inverter according to the first embodiment. FIG. 19 is a circuit diagram of a system including a multilevel inverter according to the second embodiment. FIG. 20 is a circuit diagram of a system including a multilevel inverter according to the third embodiment. FIG. 21 is a circuit diagram of a system including a multilevel inverter according to the fourth embodiment. FIG. 22 is a circuit diagram of a system including a multilevel inverter according to the fifth embodiment. FIG. 23 is a circuit diagram of a system including a multilevel inverter according to the sixth embodiment. FIG. 24 is an explanatory diagram of a current path when the switching circuit in the multilevel inverter according to the sixth embodiment is in a first switching state. FIG. 25 is an explanatory diagram of a discharge path when the switching circuit in the multilevel inverter according to the sixth embodiment is in a first switching state. FIG. 26 is an explanatory diagram of a current path when the switching circuit in the multilevel inverter according to the sixth embodiment is in a second switching state. Fig. 27 is an explanatory diagram of a discharge path when the switching circuit is in a second switching state in the multilevel inverter according to embodiment 6. Fig. 28 is an explanatory diagram of a current path when the switching circuit is in a third switching state in the multilevel inverter according to embodiment 6. Fig. 29 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in a third switching state in the multilevel inverter according to embodiment 6. Fig. 30 is an explanatory diagram of a current path when the switching circuit is in a second switching state in the multilevel inverter according to embodiment 6. Fig. 31 is a circuit diagram of a system including the multilevel inverter according to embodiment 7. Fig. 32 is a circuit diagram of a system including the multilevel inverter according to embodiment 8. Fig. 33 is a circuit diagram of a system including the multilevel inverter according to embodiment 9.

[0010] First Embodiment A multilevel inverter 100 according to a first embodiment will be described below with reference to FIGS. 1 to 14. FIG.

[0011] (1) Overall Configuration of Multilevel Inverter Fig. 1 is a circuit diagram of a system including a multilevel inverter 100 according to embodiment 1. As shown in Fig. 1, the multilevel inverter 100 includes, for example, a positive wiring section 4, a negative wiring section 5, a DC power supply section 3, a plurality of (three in the example of Fig. 1) inverter circuits 1, a control device 6, and a noise filter 8.

[0012] The DC power supply unit 3 has a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series between the positive wiring unit 4 and the negative wiring unit 5, with the first capacitor C1 and the second capacitor C2 arranged in this order from the positive wiring unit 4 side. The DC power supply unit 3 has an intermediate potential point M1. The "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive wiring unit 4 and the potential of the negative wiring unit 5. If the connection point of the DC power supply unit 3 with the positive wiring unit 4 is defined as a positive electrode P1 and the connection point of the DC power supply unit 3 with the negative wiring unit 5 is defined as a negative electrode N1, the "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0013] The plurality of inverter circuits 1 are connected between the positive wiring portion 4 and the negative wiring portion 5, and are connected to an intermediate potential point M1 between the first capacitor C1 and the second capacitor C2.

[0014] The control device 6 controls the plurality of inverter circuits 1 .

[0015] The noise filter 8 is provided on a path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3 .

[0016] The multilevel inverter 100 is a diode-clamped three-level, three-phase inverter. In the multilevel inverter 100, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the multiple (three in the example of FIG. 1 ) output terminals 41.

[0017] The AC load RA1 is, for example, a three-phase servo motor. In the multilevel inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0018] Each of the inverter circuits 1 includes a switching circuit 10, a first clamp diode D5, and a second clamp diode D6. In the multilevel inverter 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0019] (2) Details of the Multilevel Inverter The DC power supply unit 3 further has a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. The first DC terminal 31 is connected to the positive wiring unit 4. The second DC terminal 32 is connected to the negative wiring unit 5.

[0020] In the DC power supply unit 3, a first end of the first capacitor C1 is connected to the positive wiring portion 4, a second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the negative wiring portion 5. A DC voltage source E1, for example, is connected between the first DC terminal 31 and the second DC terminal 32. That is, the output voltage Vdc of the DC voltage source E1 is applied between the positive wiring portion 4 and the negative wiring portion 5. The series circuit of the first capacitor C1 and the second capacitor C2 forms a voltage divider circuit. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1. In this embodiment, the capacitance of each of the first capacitor C1 and the second capacitor C2 is, for example, 50 μF, but is not limited to 50 μF. From the viewpoint of stabilizing the potential of the intermediate potential point M1, the capacitance of each of the first capacitor C1 and the second capacitor C2 is preferably 50 μF or more.

[0021] The multilevel inverter 100 further includes a series circuit of two capacitors C11 and C12 connected between the positive wiring portion 4 and the negative wiring portion 5. Note that the two capacitors C11 and C12 are not shown in FIGS. 2 to 8. The connection point between the capacitors C11 and C12 is connected to ground. Each of the two capacitors C11 and C12 is a Y capacitor. The capacitance of each of the two capacitors C11 and C12 is, for example, 4700 pF.

[0022] Hereinafter, for convenience of explanation, with regard to the multiple switching circuits 10, the switching circuit 10 included in inverter circuit 1U may be referred to as switching circuit 10U, the switching circuit 10 included in inverter circuit 1V may be referred to as switching circuit 10V, and the switching circuit 10 included in inverter circuit 1W may be referred to as switching circuit 10W. Furthermore, of the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W may be referred to as output terminal 41W.

[0023] Each switching circuit 10 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, and a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4.

[0024] In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive wiring section 4 side to the negative wiring section 5 side in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0025] In each inverter circuit 1, the first diode D1 is connected in anti-parallel to the first switching element Q1, the second diode D2 is connected in anti-parallel to the second switching element Q2, the third diode D3 is connected in anti-parallel to the third switching element Q3, and the fourth diode D4 is connected in anti-parallel to the fourth switching element Q4.

[0026] In each inverter circuit 1, the first clamp diode D5 has its cathode connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2, and its anode connected to the intermediate potential point M1 via the wiring 2. In each inverter circuit 1, the second clamp diode D6 has its anode connected to a second connection point 12 between the third switching element Q3 and the fourth switching element Q4, and its cathode connected to the intermediate potential point M1 via the wiring 2.

[0027] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, respectively, a gate terminal, a collector terminal, and an emitter terminal.

[0028] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of a plurality of (three in the example of FIG. 1 ) first gate drivers 61 included in the control device 6. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of a plurality of (three in the example of FIG. 1 ) second gate drivers 62 included in the control device 6. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of a plurality of (three in the example of FIG. 1 ) third gate drivers 63 included in the control device 6. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of a plurality of (three in the example of FIG. 1 ) fourth gate drivers 64 included in the control device 6.

[0029] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to the positive wiring section 4, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to the negative wiring section 5.

[0030] In the inverter circuit 1U, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W. The third connection point 13 of the inverter circuit 1U is connected to, for example, the U-phase of the AC load RA1 via the output terminal 41U. The third connection point 13 of the inverter circuit 1V is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41V. The third connection point 13 of the inverter circuit 1W is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41W.

[0031] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0032] In each inverter circuit 1, the first diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In addition, in each inverter circuit 1, the second diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In addition, in each inverter circuit 1, the third diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In addition, in each inverter circuit 1, the fourth diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0033] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3 via a wiring 2. In the first embodiment, the intermediate potential point M1 is connected to ground, and therefore the potential of the intermediate potential point M1 is approximately 0 V. In this case, if the voltage between the positive wiring unit 4 and the negative wiring unit 5 (in other words, the voltage across both ends of the DC power supply unit 3) is Vdc, the potential of the positive wiring unit 4 and the positive electrode P1 is approximately Vdc / 2, and the potential of the negative wiring unit 5 and the negative electrode N1 is approximately −Vdc / 2.

[0034] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1 via the line 2. The anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0035] Fig. 2 is a more specific circuit diagram than Fig. 1 , relating to a system including the multilevel inverter 100 according to the first embodiment. As shown in Figs. 1 and 2 , the control device 6 includes the above-described plurality of first gate drivers 61 (three in the example of Fig. 1 ), a plurality of second gate drivers 62 (three in the example of Fig. 1 ), a plurality of third gate drivers 63 (three in the example of Fig. 1 ), and a plurality of fourth gate drivers 64 (three in the example of Fig. 1 ). As shown in Fig. 2 , the control device 6 also includes a plurality of bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality of second bootstrap circuits 72 (three in the example of Fig. 2 ), a plurality of third bootstrap circuits 73 (three in the example of Fig. 2 ), a power supply unit 9, and a control unit 60.

[0036] The plurality of first gate drivers 61 drive the first switching elements Q1 of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching elements Q2 of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching elements Q3 of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching elements Q4 of the plurality of inverter circuits 1.

[0037] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0038] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (see FIG. 3 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0039] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 3 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0040] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 3 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0041] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 3 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0042] The first bootstrap circuits 71 correspond one-to-one to the first gate drivers 61. Each of the first bootstrap circuits 71 supplies a voltage to a corresponding one of the first gate drivers 61. Each of the first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17). In each first bootstrap circuit 71, the anode of the diode D17 is connected to the positive terminal of the power supply unit 9 via diodes D27 and D37, and the cathode of the diode D17 is connected to a first end of the capacitor C17 via the resistor R17. The first end of the capacitor C17 is connected to a high-potential power supply terminal 61H (see FIG. 4 ) of the first gate driver 61, and the second end of the capacitor C17 is connected to a low-potential power supply terminal 61L (see FIG. 4 ) of the first gate driver 61. The first bootstrap circuit 71 supplies a voltage required to turn on the first switching element Q1 in the first gate driver 61 to the first gate driver 61. Each of the multiple first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.

[0043] The second bootstrap circuits 72 correspond one-to-one to the second gate drivers 62. Each of the second bootstrap circuits 72 supplies a voltage to a corresponding one of the second gate drivers 62. Each of the second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27). In each second bootstrap circuit 72, the anode of the diode D27 is connected to the positive terminal of the power supply unit 9 via a diode D37, and the cathode of the diode D27 is connected to a first end of the capacitor C27 via a resistor R27. The first end of the capacitor C27 is connected to a high-potential power supply terminal 62H (see FIG. 4 ) of the second gate driver 62, and the second end of the capacitor C27 is connected to a low-potential power supply terminal 62L (see FIG. 4 ) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with a voltage required to turn on the second switching element Q2 in the second gate driver 62. Each of the second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel to the capacitor C27.

[0044] The multiple third bootstrap circuits 73 correspond one-to-one to the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding one of the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (also referred to as a boost capacitor C37). In each third bootstrap circuit 73, the anode of the diode D37 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D37 is connected to a first end of the capacitor C37 via the resistor R37. The first end of the capacitor C37 is connected to a high-potential power supply terminal 63H (see FIG. 4 ) of the third gate driver 63, and the second end of the capacitor C37 is connected to a low-potential power supply terminal 63L (see FIG. 4 ) of the third gate driver 63. The third bootstrap circuit 73 supplies a voltage required to turn on the third switching element Q3 in the third gate driver 63 to the third gate driver 63. Each of the plurality of third bootstrap circuits 73 further includes a Zener diode Z37 connected in parallel to the capacitor C37.

[0045] The power supply unit 9 supplies voltages to the plurality (three) of first bootstrap circuits 71, the plurality (three) of second bootstrap circuits 72, the plurality (three) of third bootstrap circuits 73, and the plurality (three) of fourth gate drivers 64. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. A positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 64H (see FIG. 4) of each of the plurality of fourth gate drivers 64, and a negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 64L (see FIG. 4) of each of the plurality of fourth gate drivers 64.

[0046] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0047] 3 is an explanatory diagram of current paths when the switching circuit 10 is in a first switching state in the multilevel inverter 100 according to the first embodiment. The control unit 60 outputs a plurality of (three) first control signals S1 (see FIG. 3 ) for controlling a plurality of (three) first switching elements Q1, a plurality of (three) second control signals S2 (see FIG. 3 ) for controlling a plurality of (three) second switching elements Q2, a plurality of (three) third control signals S3 (see FIG. 3 ) for controlling a plurality of (three) third switching elements Q3, and a plurality of (three) fourth control signals S4 (see FIG. 3 ) for controlling a plurality of (three) fourth switching elements Q4. Note that FIG. 3 illustrates only one of the three inverter circuits 1 (see FIG. 1 ), and the remaining two inverter circuits 1 are not illustrated. 3 omits the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the power supply unit 9 shown in FIG. 2 . FIG. 4 is an explanatory diagram of the discharge path and the charge path when the switching circuit 10 is in the first switching state in the multilevel inverter 100 according to the first embodiment. In FIG. 4 , only one inverter circuit 1 of the three inverter circuits 1 (see FIG. 1 ) is shown, and the remaining two inverter circuits 1 are omitted. In addition, FIG. 4 omits the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, and the two third bootstrap circuits 73 shown in FIG. 2 .

[0048] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0049] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0050] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0051] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0052] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3 and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.

[0053] The first potential level is, for example, 0 V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.

[0054] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0055] In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0056] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the third connection point 13 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0057] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state and both the second switching element Q2 and the third switching element Q3 are in the on state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0058] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0059] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in FIG. 3, a current I1 flows through the path of the positive electrode P1 of the DC power supply unit 3, the first switching element Q1, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes approximately Vdc / 2.

[0060] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from capacitor C17 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, as shown in FIG. 4 , the charge in capacitor C17 of the first bootstrap circuit 71 is discharged through a discharge path Ru1 that connects capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61 to the low-potential power supply terminal 61L of the first gate driver 61 and then to capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across capacitor C17 decreases over time.

[0061] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the second gate driver 62 to turn on the second switching element Q2 is supplied from capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62. Therefore, the charge in capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that runs from capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 and back to capacitor C27. As a result, in the second bootstrap circuit 72, the voltage across capacitor C27 decreases over time.

[0062] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C17 is charged by the capacitor C27 if a first condition is met. As shown in FIG. 4 , if the voltages across the capacitor C17 are Vo1, Vo2, Vd1, VR1, and Vf2, respectively, the first condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). The charging path Ru21 along which the capacitor C17 is charged is the path of the capacitor C27, resistor R27, diode D17, resistor R17, capacitor C17, first node 11, second switching element Q2, and capacitor C27.

[0063] 5 is an explanatory diagram of a current path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the second switching state. When the switching circuit 10 in the inverter circuit 1 is in the second switching state and the polarity of the output current is positive, as shown in FIG. 5, a current I1 flows through a path (indicated by a thick solid arrow) from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5, the second switching element Q2, the third node 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, a current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5 of the inverter circuit 1U, the second switching element Q2 of the switching circuit 10U, the third node 13, and the output terminal 41.

[0064] 5, when the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is negative, a current I1 flows through a path (indicated by a thick dashed arrow) of the output terminal 41-the third node 13-the third switching element Q3-the second node 12-the second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, in the inverter circuit 1U, a current I1 flows through a path (indicated by a thick dashed arrow) of the output terminal 41-the third node 13-the third switching element Q3-the second node 12-the second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0.

[0065] 6 is an explanatory diagram of the discharge path and charge path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the second switching state. When the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the second switching element Q2 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62 by the second gate driver 62. Therefore, as shown in FIG. 6, the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that connects the capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62, the low-potential power supply terminal 62L of the second gate driver 62, and the capacitor C27. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the third switching element Q3 is supplied from the capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63 by the third gate driver 63. Therefore, the charge in the capacitor C37 of the third bootstrap circuit 73 is discharged through a discharge path Ru3 that runs from the capacitor C37 to the high potential power supply terminal 63H of the third gate driver 63 to the low potential power supply terminal 63L of the third gate driver 63 and back to the capacitor C37.

[0066] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C27 is charged by the capacitor C37 when the second condition is met, and the capacitor C17 is charged by the capacitor C27 when the third condition is met. As shown in Fig. 6, if the voltages across the capacitors C17, C27, and C37 are Vo1, Vo2, and Vo3, respectively, the voltages across the diodes D17 and D27 are Vd1 and Vd2, respectively, the voltages across the resistors R17 and R27 are VR1 and VR2, respectively, and the voltages across the second switching element Q2 and the third switching element Q3 are Vf2 and Vf3, respectively, the second condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The third condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). A charging path Ru32 through which the capacitor C27 is charged by the capacitor C37 is a path of the capacitor C37-resistor R37-diode D27-resistor R27-capacitor C27-third node 13-third switching element Q3-capacitor C37. A charging path Ru21 through which the capacitor C17 is charged by the capacitor C27 is a path of the capacitor C27-resistor R27-diode D17-resistor R17-capacitor C17-first node 11-second switching element Q2-capacitor C27.

[0067] FIG. 7 is an explanatory diagram of a current path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the third switching state. FIG. 8 is an explanatory diagram of a discharge path and a charge path when the switching circuit 10 in the multilevel inverter 100 according to the first embodiment is in the third switching state. When the switching circuit 10 in the inverter circuit 1 is in the third switching state, as shown in FIG. 7 , a current I1 flows through a path from the output terminal 41 to the third connection point 13, the third switching element Q3, the fourth switching element Q4, and the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 is approximately −Vdc / 2. When the switching circuit 10 in the inverter circuit 1 is in the third switching state, the capacitor C37 charges the capacitor C27 in the second bootstrap circuit 72 (see FIG. 2 ). Therefore, the voltage of the capacitor C27 increases over time, and the capacitor C27 reaches a fully charged state. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, a voltage required for the third gate driver 63 to turn on the third switching element Q3 is supplied from capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, the charge in capacitor C37 of the third bootstrap circuit 73 is discharged along a discharge path Ru3 that runs from capacitor C37 to the high-potential power supply terminal 63H of the third gate driver 63 to the low-potential power supply terminal 63L of the third gate driver 63 and then to capacitor C37. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, capacitor C37 is charged by the power supply unit 9 when a fourth condition is met, and capacitor C27 is charged by capacitor C37 when a fifth condition is met. 8 , if the voltage across the power supply unit 9 is Voo, the voltages across the capacitors C27 and C37 are Vo2 and Vo3, the voltages across the diodes D27 and D37 are Vd2 and Vd3, the voltages across the resistors R27 and R37 are VR2 and VR3, and the voltages across the third switching element Q3 and the fourth switching element Q4 are Vf3 and Vf4, respectively, the fourth condition is Voo > (Vo3 + Vd3 + VR3 + Vf4). The fifth condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3).A charging path Ru93 along which the capacitor C37 is charged by the power supply unit 9 is a path from the positive terminal of the power supply unit 9, diode D37, resistor R37, capacitor C37, second connection point 12, fourth switching element Q4, to the negative terminal of the power supply unit 9. A charging path Ru32 along which the capacitor C27 is charged by the capacitor C37 is a path from capacitor C37, resistor R37, diode D27, resistor R27, capacitor C27, third connection point 13, third switching element Q3, to capacitor C37.

[0068] In the multilevel inverter 100, the capacitance of the capacitor C17 of each of the plurality of first bootstrap circuits 71 is set to a value of 10 μF or more and 50 μF or less. Also, in the multilevel inverter 100, the capacitance of the capacitor C27 of each of the plurality of second bootstrap circuits 72 is set to a value of 10 μF or more and 50 μF or less. Also, in the multilevel inverter 100, the capacitance of the capacitor C37 of each of the plurality of third bootstrap circuits 73 is set to a value of 10 μF or more and 50 μF or less.

[0069] The control unit 60 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see FIG. 9) relating to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0070] FIG. 9 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter 100 according to the first embodiment. As shown in FIG. 9 , the voltage command Vu, voltage command Vv, and voltage command Vw are sinusoidal signals, each having a phase difference of 120°, and their respective values ​​(voltage command values) change over time. The voltage command Vu, voltage command Vv, and voltage command Vw have the same cycle length. The control unit 60 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 18 that detects the state of the AC load RA1. When the AC load RA1 is a three-phase servo motor, the information output from the detection unit 18 includes, for example, at least one of information on the detection results of a plurality of current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1 and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0071] Below, we will explain the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U). The operations of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W are similar to the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0072] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.

[0073] The voltage vector control by the control unit 60 will be described in more detail below.

[0074] The control unit 60 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of the potential levels of the connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3. ３ = 27 pieces.

[0075] 10 is an explanatory diagram of a group of voltage vectors related to the multilevel inverter 100 according to the first embodiment. As shown in FIG. 10, the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. The group of voltage vectors also includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of (2 / 3) １／２ The group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The magnitude of each of the voltage vectors is (2 / 3) １／２ The group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18 that are Vdc and have different directions. In Figure 10, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 10 is a vector diagram illustrating a group of voltage vectors on an orthogonal d-q coordinate system.

[0076] A group of voltage vectors can be expressed as shown in FIG. 11 by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating the U phase, V phase, and W phase in that order.

[0077] FIG. 11 is a more detailed explanatory diagram of a group of voltage vectors related to the multilevel inverter 100 according to the first embodiment. As shown in FIG. 11 , three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P," the switching state of the V-phase switching circuit 10V is "P," and the switching state of the W-phase switching circuit 10W is "P." For example, a voltage vector with a "p" appended, such as V10p, includes "P" but does not include "N." This applies hereinafter. Furthermore, a voltage vector with a "n" appended, such as V10n, includes "N" but does not include "P." This applies hereinafter. Furthermore, voltage vectors with "o" appended, such as V10o, include "0" but do not include "P" or "N." When the switching state of the switching circuit 10 is "P," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0078] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0079] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0080] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0081] The control unit 60 calculates the instantaneous value of the command voltage for each output voltage of the plurality of inverter circuits 1 as a command voltage vector V ＊ (See FIG. 12) to convert the command voltage vector V ＊ The d-axis component of the orthogonal d-q coordinate system is Vd, and the command voltage vector V ＊ If the q-axis component on the orthogonal d-q coordinate system is Vq, then the command voltage vector V ＊ can be calculated using equation (1).

[0082]

[0083] The control unit 60 selects a command voltage vector V ＊ 12 is a vector diagram for explaining the operation of the control unit 60 in the multilevel inverter 100 according to the first embodiment. In the example of FIG. 12, the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0084] Command voltage vector V ＊ The voltage vector closest to the ＊ The angle between them is less than 30 degrees.

[0085] The control unit 60 calculates the command voltage vector V within a predetermined control period Ts. ＊ The resultant vector of the vectors at the vertices of the equilateral triangle surrounding ＊ That is, the control unit 60 converts the resultant vector of the voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 12), the voltage vector V13[P0N], and the voltage vectors V7p[P00] and V7n[0NN] into the command voltage vector V ＊ The control period Ts is one period of the carrier signal. The frequency of the carrier signal (carrier frequency) is, for example, 6 kHz or more and 20 kHz or less. In the control unit 60, within the control period Ts, the switching state of only one of the U phase, V phase, and W phase in two voltage vectors arranged in time series changes between "P" and "0" or between "0" and "N," and the same voltage vector is output twice. FIG. 13 is a time chart of the switching state of each phase of the multilevel inverter 100 according to the first embodiment. In FIG. 13, the voltage vectors are output in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. 13 illustrates an example in which the allocation time of the voltage vectors V8p and V8n for the control period Ts is T0, the allocation time of the voltage vector V13 is T1, and the allocation time of the voltage vectors V7p and V7n is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding are Va, Vb, and Vc, and the command voltage vector V ＊ Assuming that the magnitude of the voltage V is V and the angle θ is θ, T0, T1, and T2 are determined so as to satisfy equations (2) and (3). "j" in equation (2) is an imaginary unit. In the example of FIG. 12, for example, the voltage vector Va is the voltage vector V8p[PP0] and V8n[00N], the voltage vector Vb is the voltage vector V13[P0N], and the voltage vector Vc is the voltage vector V7p[P00] and V7n[0NN].

[0086]

[0087]

[0088] In the example of Fig. 13, the on / off states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 within the control period Ts are as shown in Fig. 14. Fig. 14 is a time chart showing the on / off states of the first to fourth switching elements (Q1 to Q4) of the multilevel inverter 100 according to the first embodiment.

[0089] In addition, the command voltage vector V ＊ 12, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0090] As shown in FIG. 1, the noise filter 8 is provided on a path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3 .

[0091] FIG. 15 is a circuit diagram used to measure the conducted noise generated when a noise filter is not provided in the multilevel inverter 100 according to the first embodiment. In FIG. 15 , the ferrite core F8 is indicated by a two-dot chain line. This indicates that the ferrite core F8 is provided in either the positive wiring portion 4, the wiring portion 2, or the negative wiring portion 5 in FIG. 15 to measure the conducted noise. As shown in FIG. 15 , a pseudo power supply network 17 was provided in a multilevel inverter 100R that does not include the noise filter 8 in the multilevel inverter 100, and the noise voltage of the conducted noise generated in the multilevel inverter 100R was measured. In the circuit shown in FIG. 15 , a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32 of the multilevel inverter 100R via the pseudo power supply network 17. In the example of FIG. 15 , the pseudo power supply network 17 is a circuit network for stabilizing the power supply impedance of the DC voltage source E1 as viewed from the multilevel inverter 100R. 15, the noise voltage of the conducted noise was measured for each of the cases where the ferrite core F8 was attached to the positive wiring portion 4, where the ferrite core F8 was attached to the neutral wiring portion 2, and where the ferrite core F8 was attached to the negative wiring portion 5. The neutral wiring portion 2 is the wiring portion between the connection point between the first clamp diode D5 and the second clamp diode D6 and the midpoint potential point M1.

[0092] 16 is an explanatory diagram of the path through which the conducted noise generated when the noise filter is not provided in the multilevel inverter 100 according to the first embodiment flows. From the results of the above-described measurements, it was found that when the noise filter 8 of this embodiment is not provided, the conducted noise flows through the path shown by the dotted line in FIG. 16 (the path from the negative wiring portion 5 to the negative electrode N1, the second capacitor C2, the intermediate potential point M1, the first capacitor C1, the positive electrode P1, and the first DC terminal 31).

[0093] FIG. 17 is a graph showing the frequency characteristics of the noise voltage level generated when the multilevel inverter 100 according to the first embodiment does not include a noise filter (ferrite core F8) and when the noise filter (ferrite core F8) is included in the load wiring section 5. That is, FIG. 17 shows the frequency dependence of the noise voltage level when there is no ferrite core and when the ferrite core F8 is attached to the negative wiring section 5. A1 in FIG. 17 shows the measured value of the conducted noise when no ferrite core is attached. Furthermore, A2 in FIG. 17 shows the measured value of the conducted noise when the ferrite core F8 is attached to the negative wiring section 5. The horizontal axis in FIG. 17 represents the frequency of the conducted noise, and the vertical axis represents the voltage level of the conducted noise.

[0094] In the first embodiment, the noise filter 8 is provided on the path 332 between the intermediate potential point M1 and the first capacitor C1. The noise filter 8 includes an inductor. The inductor includes, for example, a ferrite core, a bead core, or a toroidal core.

[0095] The inductance of the inductor constituting the noise filter 8 is, for example, 5 μH or more. The inductance of the inductor constituting the noise filter 8 needs to be designed appropriately according to the frequency of the conducted noise that is not to be passed.

[0096] The noise filter 8 is not limited to an inductor, but may be a capacitor. In this case, the capacitance of the capacitor is preferably sufficiently smaller than the capacitance of each of the first capacitor C1 and the second capacitor C2 so that the combined capacitance of the first capacitor C1 and the capacitor of the noise filter 8 is approximately equal to the capacitance of the first capacitor C1. However, the capacitance of the capacitor of the noise filter 8 needs to be designed appropriately depending on the frequency of the conducted noise that is not to be passed.

[0097] Moreover, the multilevel inverter 100 according to the first embodiment further includes a noise-removing capacitor C3 connected between the intermediate potential point M1 and the ground.

[0098] 18 is a graph showing the frequency characteristics of the noise voltage level when the capacitance of the third capacitor (capacitor C3) is changed in the multilevel inverter 100 according to the first embodiment. That is, Fig. 18 shows the frequency dependence of the noise voltage level when the capacitance of the capacitor C3 is set to 2 nF, 5 nF, 10 nF, 20 nF, and 50 nF. In this case, from the viewpoint of making the capacitor C3 function as a high-pass filter that passes conducted noise of around 10 MHz, for example, the capacitance of the capacitor C3 is set to 5 nF or less.

[0099] (3) Advantages In the multilevel inverter 100 according to the first embodiment, the multiple inverter circuits 1 are connected between the positive wiring portion 4 and the negative wiring portion 5, and are connected to an intermediate potential point M1 between the first capacitor C1 and the second capacitor C2. The multilevel inverter 100 includes a noise filter 8 provided on the path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3.

[0100] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to block conducted noise flowing from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4 by the noise filter 8, thereby reducing noise.

[0101] Moreover, the multilevel inverter 100 according to the first embodiment further includes a noise-removing capacitor C3 connected between the intermediate potential point M1 and the ground.

[0102] According to the above configuration, a part of the noise can be released to the ground through the capacitor C3, and the noise can be further reduced.

[0103] Furthermore, in the multilevel inverter 100 according to the first embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73 .

[0104] According to the above configuration, it is possible to reduce the size of the multilevel inverter 100 while suppressing the voltage drop in each of the plurality of third bootstrap circuits 73 .

[0105] (Embodiment 2) A multilevel inverter 100A according to embodiment 2 will be described with reference to Fig. 19. Fig. 19 is a circuit diagram of a system including the multilevel inverter 100A according to embodiment 2. Regarding the multilevel inverter 100A according to embodiment 2, components similar to those of the multilevel inverter 100 according to embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and description thereof will be omitted.

[0106] (1) Configuration In the multilevel inverter 100A according to the second embodiment, the noise filter 8 is provided on the path 331 between the first capacitor C1 and the positive wiring portion 4.

[0107] (2) Advantages The multilevel inverter 100A according to the second embodiment, like the multilevel inverter 100 according to the first embodiment, includes a noise filter 8 provided on the path 33 between the positive wiring part 4 and the negative wiring part 5 in the DC power supply part 3.

[0108] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to block conducted noise flowing from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4 by the noise filter 8, thereby reducing noise.

[0109] (Embodiment 3) A multilevel inverter 100B according to embodiment 3 will be described with reference to Fig. 20. Fig. 20 is a circuit diagram of a system including the multilevel inverter 100B according to embodiment 3. Constituent elements of the multilevel inverter 100B according to embodiment 3 that are the same as those of the multilevel inverter 100A according to embodiment 2 (see Fig. 19) are denoted by the same reference numerals, and description thereof will be omitted.

[0110] (1) Configuration The multilevel inverter 100B according to the third embodiment differs from the multilevel inverter 100A according to the second embodiment in that it includes a noise-removing capacitor C4 connected between the path between the noise filter 8 and the first capacitor C1 and the ground. For example, in order to make the capacitor C4 function as a high-pass filter that passes conducted noise of around 10 MHz, the capacitance of the capacitor C4 is, for example, 5 nF or less.

[0111] (2) Advantages The multilevel inverter 100B according to the third embodiment includes the noise filter 8, similar to the multilevel inverter 100A according to the second embodiment. Therefore, the noise filter 8 can block the conduction noise that flows from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4, thereby reducing the noise.

[0112] Furthermore, since the multilevel inverter 100B according to the third embodiment includes the capacitor C4, it is possible to let a part of the noise escape to the ground through the capacitor C4, thereby further reducing the noise.

[0113] (Embodiment 4) A multilevel inverter 100C according to embodiment 4 will be described with reference to Fig. 21. Fig. 21 is a circuit diagram of a system including the multilevel inverter 100C according to embodiment 4. Regarding the multilevel inverter 100C according to embodiment 4, components similar to those of the multilevel inverter 100 according to embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and description thereof will be omitted.

[0114] (1) Configuration In the multilevel inverter 100C according to the fourth embodiment, the noise filter 8 is provided on the path 334 between the second capacitor C2 and the negative wiring portion 5.

[0115] (2) Advantages The multilevel inverter 100C according to the fourth embodiment, like the multilevel inverter 100 according to the first embodiment, includes a noise filter 8 provided on the path 33 between the positive wiring part 4 and the negative wiring part 5 in the DC power supply part 3.

[0116] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to block conducted noise flowing from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4 by the noise filter 8, thereby reducing noise.

[0117] Fifth Embodiment A multilevel inverter 100D according to a fifth embodiment will be described with reference to Fig. 22. Fig. 22 is a circuit diagram of a system including the multilevel inverter 100D according to the fifth embodiment. Constituent elements of the multilevel inverter 100D according to the fifth embodiment that are the same as those of the multilevel inverter 100C according to the fourth embodiment (see Fig. 21) are denoted by the same reference numerals, and description thereof will be omitted.

[0118] (1) Configuration The multilevel inverter 100D according to the fifth embodiment differs from the multilevel inverter 100C according to the fourth embodiment in that it includes a noise-removing capacitor C5 connected between the negative wiring portion 5 and the ground. For example, in order to make the capacitor C5 function as a high-pass filter that passes conducted noise of around 10 MHz, the capacitance of the capacitor C5 is, for example, 5 nF or less.

[0119] (2) Advantages The multilevel inverter 100D according to the fifth embodiment includes the noise filter 8, similar to the multilevel inverter 100C according to the fourth embodiment. Therefore, the noise filter 8 can block the conduction noise that flows from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4, thereby reducing the noise.

[0120] Furthermore, since the multilevel inverter 100D according to the fifth embodiment includes the capacitor C5, it is possible to let a part of the noise escape to the ground through the capacitor C5, thereby making it possible to further reduce the noise.

[0121] Sixth Embodiment A multilevel inverter 100E according to a sixth embodiment will be described below with reference to FIGS.

[0122] (1) Overall Configuration of Multilevel Inverter Fig. 23 is a circuit diagram of a system including a multilevel inverter 100E according to embodiment 6. As shown in Fig. 23 , the multilevel inverter 100E includes, for example, a positive wiring section 4, a negative wiring section 5, a DC power supply section 3, a plurality of (three in the example of Fig. 23 ) inverter circuits 1, a control device 6, and a noise filter 8.

[0123] The DC power supply unit 3 has a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series between the positive wiring unit 4 and the negative wiring unit 5, with the first capacitor C1 and the second capacitor C2 arranged in this order from the positive wiring unit 4 side. The DC power supply unit 3 has an intermediate potential point M1. The "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive wiring unit 4 and the potential of the negative wiring unit 5. If the connection point of the DC power supply unit 3 with the positive wiring unit 4 is defined as a positive electrode P1 and the connection point of the DC power supply unit 3 with the negative wiring unit 5 is defined as a negative electrode N1, the "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0124] The plurality of inverter circuits 1 are connected between the positive wiring portion 4 and the negative wiring portion 5, and are connected to an intermediate potential point M1 between the first capacitor C1 and the second capacitor C2.

[0125] The control device 6 controls the plurality of inverter circuits 1 .

[0126] The noise filter 8 is provided on a path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3 .

[0127] The multilevel inverter 100E is a T-type three-level three-phase inverter. In the multilevel inverter 100, each of the plurality of inverter circuits 1 has an output terminal 41. In the multilevel inverter 100E, AC loads RA1 are connected to the plurality of (three in the example of FIG. 23 ) output terminals 41.

[0128] The AC load RA1 is, for example, a three-phase servo motor. In the multilevel inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0129] (2) Details of the Multilevel Inverter The DC power supply unit 3 further has a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. The first DC terminal 31 is connected to the positive wiring unit 4. The second DC terminal 32 is connected to the negative wiring unit 5.

[0130] In the DC power supply unit 3, a first end of the first capacitor C1 is connected to the positive wiring portion 4, a second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the negative wiring portion 5. A DC voltage source E1, for example, is connected between the first DC terminal 31 and the second DC terminal 32. That is, the output voltage Vdc of the DC voltage source E1 is applied between the positive wiring portion 4 and the negative wiring portion 5. The series circuit of the first capacitor C1 and the second capacitor C2 forms a voltage divider circuit. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1. In this embodiment, the capacitance of each of the first capacitor C1 and the second capacitor C2 is, for example, 50 μF, but is not limited to 50 μF. From the viewpoint of stabilizing the potential of the intermediate potential point M1, the capacitance of each of the first capacitor C1 and the second capacitor C2 is preferably 50 μF or more.

[0131] Fig. 24 is an explanatory diagram of a current path when the switching circuit (inverter circuit 1) is in the first switching state in the multilevel inverter 100E according to the sixth embodiment. Fig. 25 is an explanatory diagram of a discharge path when the switching circuit (inverter circuit 1) is in the first switching state in the multilevel inverter 100E according to the sixth embodiment.

[0132] Each of the inverter circuits 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, as well as a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are connected in anti-parallel to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, respectively. In each of the inverter circuits 1, the first switching element Q1 and the second switching element Q2 are connected in series from the positive electrode P1 side to the negative electrode N1 side in the order of the first switching element Q1 and the second switching element Q2. That is, as shown in FIGS. 23 and 24 , a series circuit (first circuit 111) of the first switching element Q1 and the second switching element Q2 is connected between the positive electrode P1 and the negative electrode N1. In each of the inverter circuits 1, a series circuit (second circuit 112) of a third switching element Q3 and a fourth switching element Q4 is connected between an intermediate potential point M1 and an output point. The output point is a connection point 113 between the first switching element Q1 and the second switching element Q2. The second circuit 112 has a bidirectional switch including the third switching element Q3, the fourth switching element Q4, and the third and fourth diodes D3 and D4.

[0133] The control device 6 has a plurality of (three in the example of FIG. 23 ) first gate drivers 61, a plurality of (three in the example of FIG. 23 ) second gate drivers 62, a plurality of (three in the example of FIG. 23 ) third gate drivers 63, and a plurality of (three in the example of FIG. 23 ) fourth gate drivers 64. The control device 6 also has a plurality of (three in the example of FIG. 23 ) bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality of (three in the example of FIG. 23 ) second bootstrap circuits 72, a power supply unit 9, and a control unit 60.

[0134] The plurality of first gate drivers 61 drive the first switching elements Q1 of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching elements Q2 of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching elements Q3 of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching elements Q4 of the plurality of inverter circuits 1.

[0135] The multiple first bootstrap circuits 71 correspond one-to-one to the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies a voltage to a corresponding one of the multiple first gate drivers 61. The multiple second bootstrap circuits 72 correspond to a multiple third gate drivers 63 and a multiple fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 supplies a voltage to a corresponding one of the multiple third gate drivers 63 and a corresponding fourth gate driver 64. The power supply unit 9 supplies a voltage to the multiple second gate drivers 62.

[0136] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0137] A control terminal of the first switching element Q1 of each inverter circuit 1 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each inverter circuit 1 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each inverter circuit 1 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each inverter circuit 1 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0138] In each inverter circuit 1, the first main terminal of the first switching element Q1 is connected to the positive wiring section 4, the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2, and the second main terminal of the second switching element Q2 is connected to the negative wiring section 5.

[0139] In each inverter circuit 1, the first main terminal of the third switching element Q3 is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3 is connected to the second main terminal of the fourth switching element Q4, and the first main terminal of the fourth switching element Q4 is connected to the connection point 113. Therefore, the bidirectional switch of the second circuit 112 is a common-emitter bidirectional switch in which the second main terminals (emitter terminals) of the third switching element Q3 and the fourth switching element Q4 are connected to each other.

[0140] In the inverter circuit 1U, a connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41U. In the inverter circuit 1V, a connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41V. In the inverter circuit 1W, a connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41W. The connection point 113 of the inverter circuit 1U is connected to, for example, the U-phase of the AC load RA1 via the output terminal 41U. The connection point 113 of the inverter circuit 1V is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41V. The connection point 113 of the inverter circuit 1W is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41W.

[0141] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0142] In each inverter circuit 1, the first diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In addition, in each inverter circuit 1, the second diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In addition, in each inverter circuit 1, the third diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In addition, in each inverter circuit 1, the fourth diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0143] The multiple first gate drivers 61 correspond one-to-one to the multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to a control terminal of a corresponding one of the multiple first switching elements Q1. The multiple first gate drivers 61 drive the corresponding first switching element Q1. The multiple first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs multiple first control signals S1 (see FIG. 24 ) that correspond one-to-one to the multiple first gate drivers 61. Each of the multiple first gate drivers 61 controls the on / off of the first switching element Q1 based on the received first control signal S1.

[0144] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding one of the second switching elements Q2. The second gate drivers 62 drive the corresponding second switching element Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 24 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0145] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding one of the plurality of third switching elements Q3. The plurality of third gate drivers 63 drives the corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 24 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0146] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding one of the plurality of fourth switching elements Q4. The plurality of fourth gate drivers 64 drives the corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 24 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0147] The first bootstrap circuits 71 correspond one-to-one to the first gate drivers 61. Each of the first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. As shown in FIGS. 23 and 25 , each of the first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17). In each of the first bootstrap circuits 71, the anode of the diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D17 is connected to a first end of the capacitor C17 via the resistor R17. The first end of the capacitor C17 is connected to a high-potential power supply terminal 61H (see FIG. 25 ) of the first gate driver 61, and the second end of the capacitor C17 is connected to a low-potential power supply terminal 61L (see FIG. 25 ) of the first gate driver 61. The first bootstrap circuit 71 supplies a voltage required to turn on the first switching element Q1 in the first gate driver 61 to the first gate driver 61. Each of the multiple first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.

[0148] The second bootstrap circuits 72 correspond to the third gate drivers 63 and the fourth gate drivers 64. Each second bootstrap circuit 72 supplies a voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64. Each second bootstrap circuit 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27). In each second bootstrap circuit 72, the anode of the diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D27 is connected to a first end of the capacitor C27 via the resistor R27. A first end of the capacitor C27 is connected to the high-potential power supply terminal 63H (see FIG. 25 ) of the third gate driver 63 and the high-potential power supply terminal 64H (see FIG. 25 ) of the fourth gate driver 64, and a second end of the capacitor C27 is connected to the low-potential power supply terminal 63L (see FIG. 25 ) of the third gate driver 63 and the low-potential power supply terminal 64L (see FIG. 25 ) of the fourth gate driver 64. The second bootstrap circuit 72 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3 in the third gate driver 63, and supplies the fourth gate driver 64 with a voltage required to turn on the fourth switching element Q4 in the fourth gate driver 64. Each of the second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel to the capacitor C27.

[0149] The power supply unit 9 supplies voltage to a plurality of (three in the example of FIG. 23 ) first bootstrap circuits 71, a plurality of (three in the example of FIG. 23 ) second bootstrap circuits 72, and a plurality of (three in the example of FIG. 23 ) second gate drivers 62. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. A positive terminal of the power supply unit 9 is connected to a high-potential power supply terminal 62H (see FIG. 25 ) of each of the plurality of second gate drivers 62, and a negative terminal of the power supply unit 9 is connected to a low-potential power supply terminal 62L (see FIG. 25 ) of each of the plurality of second gate drivers 62.

[0150] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0151] The control unit 60 outputs a plurality of (three) first control signals S1 (see FIG. 24 ) for controlling a plurality of (three) first switching elements Q1, a plurality of (three) second control signals S2 (see FIG. 24 ) for controlling a plurality of (three) second switching elements Q2, a plurality of (three) third control signals S3 (see FIG. 24 ) for controlling a plurality of third switching elements Q3, and a plurality of (three) fourth control signals S4 (see FIG. 24 ) for controlling a plurality of (three) fourth switching elements Q4. Note that FIG. 24 illustrates only one of the three inverter circuits 1, and the remaining two inverter circuits 1 are not shown. Also, FIG. 24 does not illustrate a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, and the power supply unit 9. 25 illustrates only one of the three inverter circuits 1, omitting the illustration of the remaining two inverter circuits 1. Also, in FIG. 25 , the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, and the two second bootstrap circuits 72 is omitted.

[0152] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the inverter circuit 1U, a first control signal S1V that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal S1W that controls the first switching element Q1 of the inverter circuit 1W.

[0153] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the inverter circuit 1U, a second control signal S2V that controls the second switching element Q2 of the inverter circuit 1V, and a second control signal S2W that controls the second switching element Q2 of the inverter circuit 1W.

[0154] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the inverter circuit 1U, a third control signal S3V that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal S3W that controls the third switching element Q3 of the inverter circuit 1W.

[0155] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal S4V that controls the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal S4W that controls the fourth switching element Q4 of the inverter circuit 1W.

[0156] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) higher than the first potential level. The first potential level is, for example, 0 V, and the second potential level is a potential level higher than the gate threshold voltage of the IGBT. That is, in each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off a switching element corresponding to that control signal, and the second potential level is a potential level for turning on a switching element corresponding to that control signal.

[0157] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0158] In the multilevel inverter 100E, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100E, the switching state of each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that, with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0159] The first switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the ON state and both the second switching element Q2 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the connection point 113 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0160] The second switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the second switching state, the potential of the connection point 113 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0161] The third switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the OFF state and both the second switching element Q2 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the connection point 113 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0162] When the inverter circuit 1 is in the first switching state, as shown in FIG. 24, a current I1 flows through the path from the positive electrode P1 of the DC power supply unit 3 to the first switching element Q1, the connection point 113, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see FIG. 23) becomes approximately Vdc / 2.

[0163] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C17 of the first bootstrap circuit 71, and instead the capacitor C17 of the first bootstrap circuit 71 supplies to the first gate driver 61 a voltage necessary for the first gate driver 61 to turn on the first switching element Q1. Therefore, as shown in FIG. 25 , the charge in the capacitor C17 of the first bootstrap circuit 71 is discharged along a discharge path Ru1 that connects the capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61, the low-potential power supply terminal 61L of the first gate driver 61, and the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.

[0164] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C27 of the second bootstrap circuit 72, and instead supplies the voltage required for the third gate driver 63 to turn on the third switching element Q3 from the capacitor C27 of the second bootstrap circuit 72 to the third gate driver 63. Therefore, as shown in FIG. 25 , the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru3 that connects the capacitor C27 to the high-potential power supply terminal 63H of the third gate driver 63, the low-potential power supply terminal 63L of the third gate driver 63, and the capacitor C27. As a result, in the second bootstrap circuit 72, the voltage across the capacitor C27 decreases over time.

[0165] 26 is an explanatory diagram of a current path when the switching circuit (inverter circuit 1) in the multilevel inverter 100E according to the sixth embodiment is in the second switching state. When the inverter circuit 1 is in the second switching state (when it changes from the first switching state to the second switching state), for example, as shown in FIG. 26, a current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the third switching element Q3, the fourth switching element Q4, the connection point 113, and the output terminal 41 (see FIG. 23), and the voltage value of the output voltage to the AC load RA1 becomes approximately 0. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the third switching state, and the third switching state, respectively, a current flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the third switching element Q3 of the inverter circuit 1U to the fourth switching element Q4 of the inverter circuit 1U to the connection point 113 and the output terminal 41U.

[0166] 27 is an explanatory diagram of a discharge path when the switching circuit (inverter circuit 1) in the multilevel inverter 100E according to the sixth embodiment is in the second switching state. When the inverter circuit 1 is in the second switching state, a voltage required for turning on the third switching element Q3 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the third gate driver 63 by the third gate driver 63. Therefore, as shown in FIG. 27 , the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru3 that connects the capacitor C27 to the high-potential power supply terminal 63H of the third gate driver 63, the low-potential power supply terminal 63L of the third gate driver 63, and the capacitor C27. Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required for turning on the fourth switching element Q4 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the fourth gate driver 64 by the fourth gate driver 64. Therefore, the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged through a discharge path Ru4 from the capacitor C27 to the high potential side power supply terminal 64H of the fourth gate driver 64 to the low potential side power supply terminal 64L of the fourth gate driver 64 and back to the capacitor C27.

[0167] FIG. 28 is an explanatory diagram of a current path when the switching circuit (inverter circuit 1) in the multilevel inverter 100E according to the sixth embodiment is in the third switching state. FIG. 29 is an explanatory diagram of a discharge path and a charge path when the switching circuit (inverter circuit 1) in the multilevel inverter 100E according to the sixth embodiment is in the third switching state. When the inverter circuit 1 is in the third switching state, as shown in FIG. 28 , a current I1 flows through the path from the output terminal 41 to the connection point 113, the second switching element Q2, and the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 is approximately −Vdc / 2. Furthermore, when the inverter circuit 1 is in the third switching state, the power supply unit 9 charges the capacitor C17 of the first bootstrap circuit 71, so that the voltage of the capacitor C17 increases over time, and the capacitor C17 reaches a fully charged state. As shown in FIG. 29, a charging path Ru91 for charging the capacitor C17 by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 - diode D17 - resistor R17 - capacitor C17 - connection point 113 - second switching element Q2 - negative terminal of the power supply unit 9.

[0168] Furthermore, when the inverter circuit 1 is in the third switching state, the capacitor C27 of the second bootstrap circuit 72 is charged by the power supply unit 9. A charging path Ru92 along which the capacitor C27 is charged by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 to the diode D27, resistor R27, capacitor C27, fourth switching element Q4, node 113, second switching element Q2, and negative terminal of the power supply unit 9.

[0169] 30 is an explanatory diagram of a current path when the switching circuit (inverter circuit 1) in the multilevel inverter 100E according to the sixth embodiment is in the second switching state (when the switching state changes from the third switching state to the second switching state). When the inverter circuit 1 is in the second switching state (when the switching state changes from the third switching state to the second switching state), for example, as shown in FIG. 30, a current I1 flows through a path from the output terminal 41 to the node 113 to the fourth switching element Q4 to the third switching element Q3 to the intermediate potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the second switching state, and the first switching state, respectively, a current I1 flows through a path from the output terminal 41 of the inverter circuit 1U to the node 113 to the fourth switching element Q4 to the third switching element Q3 to the intermediate potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0.

[0170] When the inverter circuit 1 is in the second switching state, discharge occurs through the discharge paths Ru3 and Ru4 shown in FIG.

[0171] The control unit 60 generates, for example, first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W based on voltage commands Vu, Vv, and Vw (see FIG. 9) relating to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0172] As shown in FIG. 9 , the voltage commands Vu, Vv, and Vw are sinusoidal signals whose phases are, for example, 120° apart, and whose values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw have the same cycle length. The control unit 60 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 18 that detects the state of the AC load RA1. If the AC load RA1 is a three-phase servo motor, the information output from the detection unit 18 may include, for example, at least one of the following: information on the detection results of multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1; and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0173] Below, we will explain the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U). The operations of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W are similar to the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0174] The control unit 60 performs voltage vector control to control a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. The control unit 60 performs the same voltage vector control as in the first embodiment. The control unit 60 controls a command voltage vector V ＊ (See FIG. 12) The resultant vector of the vectors of the vertices of the equilateral triangle surrounding ＊ The first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 are controlled so that the voltage vectors match the voltages of the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64. The method of voltage vector control is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0175] In the multilevel inverter 100E, the capacitance of the capacitor C17 of each of the plurality of first bootstrap circuits 71 is set to a value not less than 10 μF and not more than 50 μF. Also, in the multilevel inverter 100E, the capacitance of the capacitor C27 of each of the plurality of second bootstrap circuits 72 is set to a value not less than 10 μF and not more than 50 μF.

[0176] As shown in FIG. 23, the noise filter 8 is provided on a path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3 .

[0177] In the sixth embodiment, the noise filter 8 is provided on the path 332 between the intermediate potential point M1 and the first capacitor C1. The noise filter 8 includes an inductor. The inductor includes, for example, a ferrite core, a bead core, or a toroidal core.

[0178] The inductance of the inductor constituting the noise filter 8 is, for example, 5 μH or more. The inductance of the inductor constituting the noise filter 8 needs to be designed appropriately according to the frequency of the conducted noise that is not to be passed.

[0179] The noise filter 8 is not limited to an inductor, but may be a capacitor. In this case, the capacitance of the capacitor is preferably sufficiently smaller than the capacitance of each of the first capacitor C1 and the second capacitor C2 so that the combined capacitance of the first capacitor C1 and the capacitor of the noise filter 8 is approximately equal to the capacitance of the first capacitor C1. However, the capacitance of the capacitor of the noise filter 8 needs to be designed appropriately depending on the frequency of the conducted noise that is not to be passed.

[0180] The multilevel inverter 100E according to the sixth embodiment further includes a noise-removing capacitor C3 connected between the intermediate potential point M1 and the ground. For example, the capacitance of the capacitor C3 is set to 5 nF or less, from the viewpoint of allowing the capacitor C3 to function as a high-pass filter that passes conducted noise of around 10 MHz.

[0181] (3) Advantages In the multilevel inverter 100E according to the sixth embodiment, the multiple inverter circuits 1 are connected between the positive wiring portion 4 and the negative wiring portion 5, and are connected to an intermediate potential point M1 between the first capacitor C1 and the second capacitor C2. The multilevel inverter 100 includes a noise filter 8 provided on the path 33 between the positive wiring portion 4 and the negative wiring portion 5 in the DC power supply portion 3.

[0182] The above configuration makes it possible to reduce noise. More specifically, the above configuration makes it possible to block conducted noise flowing from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4 by the noise filter 8, thereby reducing noise.

[0183] Moreover, the multilevel inverter 100E according to the sixth embodiment further includes a noise-removing capacitor C3 connected between the intermediate potential point M1 and the ground.

[0184] According to the above configuration, a part of the noise can be released to the ground through the capacitor C3, and the noise can be further reduced.

[0185] Furthermore, in the multilevel inverter 100E according to the sixth embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73 .

[0186] According to the above configuration, it is possible to reduce the size of the multilevel inverter 100E and suppress the voltage drop in each of the plurality of third bootstrap circuits 73.

[0187] Seventh Embodiment A multilevel inverter 100F according to a seventh embodiment will be described with reference to Fig. 31. Fig. 31 is a circuit diagram of a system including the multilevel inverter 100F according to the seventh embodiment. Concerning the multilevel inverter 100F according to the seventh embodiment, components similar to those of the multilevel inverter 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0188] (1) Configuration The multilevel inverter 100F according to the seventh embodiment differs from the multilevel inverter 100 according to the first embodiment in that a ground wiring G1 is provided instead of the noise-removing capacitor C3 connected between the intermediate potential point M1 and the ground.

[0189] (2) Advantages The multilevel inverter 100F according to the seventh embodiment includes the noise filter 8, similar to the multilevel inverter 100 according to the first embodiment. Therefore, the noise filter 8 can block the conduction noise that flows from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4, thereby reducing the noise.

[0190] Furthermore, since the multilevel inverter 100F according to the seventh embodiment includes the ground wiring G1, it is possible to let a part of the noise escape to the ground through the ground wiring G1, and it is possible to further reduce the noise. Furthermore, by providing the ground wiring G1 instead of the capacitor C3, it is not necessary to consider the withstand voltage of the capacitor C3.

[0191] Eighth Embodiment A multilevel inverter 100G according to an eighth embodiment will be described with reference to Fig. 32. Fig. 32 is a circuit diagram of a system including the multilevel inverter 100G according to the eighth embodiment. Concerning the multilevel inverter 100G according to the eighth embodiment, components similar to those of the multilevel inverter 100B according to the third embodiment (see Fig. 20) are denoted by the same reference numerals, and description thereof will be omitted.

[0192] (1) Configuration The multilevel inverter 100G according to the eighth embodiment differs from the multilevel inverter 100B according to the third embodiment in that it includes a ground wiring G2 instead of the noise-removing capacitor C4 connected between the ground and the path between the noise filter 8 and the first capacitor C1. The ground wiring G2 is provided on the intermediate potential point M1.

[0193] (2) Advantages The multilevel inverter 100G according to the eighth embodiment includes the noise filter 8, similar to the multilevel inverter 100B according to the third embodiment. Therefore, the noise filter 8 can block the conduction noise that flows from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4, thereby reducing the noise.

[0194] Furthermore, since the multilevel inverter 100G according to the eighth embodiment includes the ground wiring G2, a part of the noise can be released to the ground through the ground wiring G2, and the noise can be further reduced. Furthermore, by providing the ground wiring G2 instead of the capacitor C4, it is not necessary to consider the withstand voltage of the capacitor C4.

[0195] (Embodiment 9) A multilevel inverter 100H according to embodiment 9 will be described with reference to Fig. 33. Fig. 33 is a circuit diagram of a system including the multilevel inverter 100H according to embodiment 9. Constituent elements of the multilevel inverter 100H according to embodiment 9 that are the same as those of the multilevel inverter 100D according to embodiment 5 (see Fig. 22) are denoted by the same reference numerals, and description thereof will be omitted.

[0196] (1) Configuration The multilevel inverter 100H according to the ninth embodiment differs from the multilevel inverter 100D according to the fifth embodiment in that it includes a ground wiring G3 instead of the noise-removing capacitor C5 connected between the negative wiring section 5 and the ground.

[0197] (2) Advantages The multilevel inverter 100H according to the ninth embodiment includes the noise filter 8, similar to the multilevel inverter 100D according to the fifth embodiment. Therefore, the noise filter 8 can block the conduction noise that flows from the negative wiring portion 5 through the path 33 toward the positive wiring portion 4, thereby reducing the noise.

[0198] Furthermore, since the multilevel inverter 100H according to the ninth embodiment includes the ground wiring G3, it is possible to allow a portion of the noise to escape to the ground through the ground wiring G3, thereby further reducing the noise. Furthermore, by providing the ground wiring G3 instead of the capacitor C5, it is not necessary to consider the withstand voltage of the capacitor C5.

[0199] Other Embodiments In the multilevel inverter 100A according to the second embodiment (see FIG. 19 ), the noise filter 8 is provided on the path 331 between the positive electrode P1 and the capacitor C2. However, the present invention is not limited to this. The noise filter 8 may be provided on the path 332 between the capacitor C2 and the intermediate potential point M1, or on the path 333 between the intermediate potential point M1 and the capacitor C3.

[0200] In the multilevel inverter 100 according to the first embodiment (see FIG. 1 ), the multilevel inverter 100B according to the third embodiment (see FIG. 20 ), and the multilevel inverter 100D according to the fifth embodiment (see FIG. 22 ), the capacitor C3, the capacitor C4, or the capacitor C5, and the ground are preferably provided at positions with a lower potential than the noise filter 8, from the viewpoint of dissipating a portion of the noise to the ground. For example, in the case of the multilevel inverter 100 according to the first embodiment, the capacitor C3 and the ground are not limited to the case of FIG. 1 , and may be provided on the path 332, the path 333, the path 334, or the negative wiring portion 5 between the DC terminal 32 and the fourth switching element 4. However, in order to efficiently dissipate a portion of the noise to the ground, it is more preferable to provide the capacitor C3 and the ground on the path 332 or the path 333, as in the case of FIG. 1 .

[0201] Furthermore, in the case of the multilevel inverter 100B according to the third embodiment, the capacitor C4 and the ground are not limited to the case in Fig. 20 , and may be provided on the path 332, on the path 333, on the intermediate potential point M1, on the path 334, or on the negative wiring portion 5 between the DC terminal 32 and the fourth switching element 4. However, in order to efficiently release part of the noise to the ground, the case in Fig. 20 is more preferable.

[0202] In the case of the multilevel inverter 100D according to the fifth embodiment, the capacitor C5 and the ground may be arranged on the path 334, not limited to the case of FIG. 22, or may be arranged on the negative wiring portion 5 between the negative electrode N1 and the DC terminal 32.

[0203] In the multilevel inverter 100F according to the seventh embodiment (see FIG. 31 ), the multilevel inverter 100G according to the eighth embodiment (see FIG. 32 ), and the multilevel inverter 100H according to the ninth embodiment (see FIG. 33 ), the ground wiring G1, the ground wiring G2, and the ground wiring G3 are preferably provided at a position at a lower potential than the noise filter 8 from the viewpoint of dissipating part of the noise to the ground. For example, in the case of the multilevel inverter 100F according to the seventh embodiment, the ground wiring G1 is not limited to the case of FIG. 31 , and may be provided on the path 332, the path 333, the path 334, or the negative wiring portion 5 between the DC terminal 32 and the fourth switching element 4. However, in order to efficiently dissipate part of the noise to the ground, it is more preferable to provide the ground wiring G1 as in the case of FIG. 31 or on the path 332 or the path 333.

[0204] Furthermore, in the case of the multilevel inverter 100G according to the eighth embodiment, the ground wiring G2 is not limited to the case of FIG. 32 , and may be provided on the path 332, the intermediate potential point M1, the path 333, the path 334, or the negative wiring portion 5 between the DC terminal 32 and the fourth switching element 4. However, in order to efficiently release a portion of the noise to the ground, the case of FIG. 32 is more preferable. On the other hand, in the case of the multilevel inverter 100G according to the eighth embodiment, it is not preferable to provide the ground wiring G2 on the path 331. This is because providing the ground wiring G2 on the path 331 would cause a short circuit on the high-voltage side of the DC voltage.

[0205] In the case of the multilevel inverter 100H according to the ninth embodiment, the ground wiring G3 may be provided on the path 334, not limited to the case of FIG. 33, or may be provided on the negative wiring portion 5 between the negative electrode N1 and the DC terminal 32.

[0206] (Modifications) The above-described first to ninth embodiments and other embodiments are merely examples of various embodiments of the present disclosure. The above-described first to ninth embodiments and other embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0207] For example, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are a gate terminal, a drain terminal, and a source terminal, respectively. In each switching circuit 10, the MOSFETs constituting each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are, for example, normally-off n-channel MOSFETs. Note that although the MOSFETs are Si-based MOSFETs, they are not limited to Si-based MOSFETs and may be, for example, SiC-based MOSFETs.

[0208] Moreover, in the multilevel inverter 100E according to the sixth embodiment, the noise filter 8 may be provided in the same position as the noise filter 8 in any one of the second to fifth embodiments. Moreover, in the multilevel inverter 100E according to the sixth embodiment, the noise filter 8 may be provided in the same position as the third embodiment, and the capacitor C4 may be provided in the same position as the third embodiment. Moreover, in the multilevel inverter 100E according to the sixth embodiment, the noise filter 8 may be provided in the same position as the fifth embodiment, and the capacitor C5 may be provided in the same position as the fifth embodiment.

[0209] Each of the first bootstrap circuits 71 includes the Zener diode Z17, but may not include the Zener diode Z17. Each of the second bootstrap circuits 72 includes the Zener diode Z27, but may not include the Zener diode Z27.

[0210] Furthermore, the control unit 60 is not limited to being configured to perform voltage vector control, but may also be configured to perform PWM control.

[0211] Furthermore, the multilevel inverters 100 to 100H may be any multilevel inverter having three or more levels, and may be, for example, a five-level inverter.

[0212] (Aspects) The following aspects are disclosed in this specification.

[0213] A multilevel inverter (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a first aspect includes a positive wiring portion (4), a negative wiring portion (5), a DC power supply portion (3), a plurality of inverter circuits (1), a control device (6), and a noise filter (8). The DC power supply portion (3) has a first capacitor (C1) and a second capacitor (C2). In the DC power supply portion (3), the first capacitor (C1) and the second capacitor (C2) are connected in series between the positive wiring portion (4) and the negative wiring portion (5) in the order of the first capacitor (C1) and the second capacitor (C2) from the positive wiring portion (4) side. The plurality of inverter circuits (1) are connected between the positive wiring portion (4) and the negative wiring portion (5) and are connected to an intermediate potential point (M1) between the first capacitor (C1) and the second capacitor (C2). A control device (6) controls the plurality of inverter circuits (1). A noise filter (8) is provided on a path (33) between the positive wiring portion (4) and the negative wiring portion (5) in the DC power supply unit (3).

[0214] According to this aspect, it is possible to reduce noise.

[0215] In the multilevel inverter (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to the second aspect, in the first aspect, the noise filter (8) includes an inductor or a capacitor.

[0216] In the multilevel inverter (100; 100E; 100F) according to the third aspect, in the first or second aspect, the noise filter (8) is provided on the path (332) between the intermediate potential point (M1) and the first capacitor (C1).

[0217] The multilevel inverter (100; 100E; 100F) according to the fourth aspect is the third aspect, further comprising a noise removal capacitor (C3) connected between the intermediate potential point (M1) and ground.

[0218] According to this embodiment, it is possible to let a part of the noise escape to the ground through the capacitor (C3), thereby making it possible to further reduce the noise.

[0219] In the multilevel inverter (100A; 100B; 100G) according to the fifth aspect, in the first or second aspect, the noise filter (8) is provided on the path (331) between the first capacitor (C1) and the positive wiring portion (4).

[0220] The multilevel inverter (100B; 100G) according to the sixth aspect is the fifth aspect, further comprising a noise removal capacitor (C4) connected between the path between the noise filter (8) and the first capacitor (C1) and ground.

[0221] According to this embodiment, it is possible to let a part of the noise escape to the ground through the capacitor (C4), thereby making it possible to further reduce the noise.

[0222] In the multilevel inverter (100C; 100D; 100H) according to the seventh aspect, in the first or second aspect, the noise filter (8) is provided on the path (334) between the second capacitor (C2) and the negative wiring portion (5).

[0223] The multilevel inverter (100D; 100H) according to an eighth aspect is the seventh aspect, further comprising a noise removal capacitor (C5) connected between the negative wiring portion (5) and ground.

[0224] According to this embodiment, it is possible to let a part of the noise escape to the ground through the capacitor (C5), thereby making it possible to further reduce the noise.

[0225] In a multilevel inverter (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a ninth aspect, in the second aspect, the inductor includes a ferrite core, a bead core, or a toroidal core.

[0226] In a multilevel inverter (100; 100A; 100B; 100C; 100D; 100F; 100G; 100H) according to a tenth aspect, in any one of the first to ninth aspects, each of the plurality of inverter circuits (1) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4), a first diode (D1), a second diode (D2), a third diode (D3), and a fourth diode (D4), a first clamp diode (D5), and a second clamp diode (D6). The first diode (D1), the second diode (D2), the third diode (D3), and the fourth diode (D4) are connected in anti-parallel to the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4), respectively. In each of the multiple inverter circuits (1), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series between a positive wiring portion (4) and a negative wiring portion (5) in the order of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4). The cathode of a first clamp diode (D5) is connected to a first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and the anode of the first clamp diode (D5) is connected to an intermediate potential point (M1). The anode of a second clamp diode (D6) is connected to a second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and the cathode of the second clamp diode (D6) is connected to the intermediate potential point (M1). A third connection point (13) between the second switching element (Q2) and the third switching element (Q3) is connected to an output terminal (41) which is connected to an AC load (RA1).

[0227] In a multilevel inverter (100E) according to an eleventh aspect, in any one of the first to ninth aspects, each of the plurality of inverter circuits (1) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4), and a first diode (D1), a second diode (D2), a third diode (D3), and a fourth diode (D4). The first diode (D1), the second diode (D2), the third diode (D3), and the fourth diode (D4) are connected in anti-parallel to the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4), respectively. In each of the plurality of inverter circuits (1), the first switching element (Q1) and the second switching element (Q2) are connected in series from the positive wiring portion (4) to the negative wiring portion (5) in the order of the first switching element (Q1) and the second switching element (Q2). A series circuit of a third switching element (Q3) and a fourth switching element (Q4) is connected between an intermediate potential point (M1) and an output point, which is the connection point between the first switching element (Q1) and the second switching element (Q2).

[0228] In a multilevel inverter (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a twelfth aspect, in the tenth or eleventh aspect, the control device (6) has a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of bootstrap circuits (71), a power supply unit (9), and a control unit (60). The plurality of first gate drivers (61) drive first switching elements (Q1) of the plurality of inverter circuits (1), respectively. The plurality of second gate drivers (62) drive second switching elements (Q2) of the plurality of inverter circuits (1), respectively. The plurality of third gate drivers (63) drive third switching elements (Q3) of the plurality of inverter circuits (1), respectively. The plurality of fourth gate drivers (64) drive the fourth switching elements (Q4) of the plurality of inverter circuits (1). The plurality of bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61). Each of the plurality of bootstrap circuits (71) supplies a voltage to a corresponding one of the plurality of first gate drivers (61). The power supply unit (9) supplies a voltage to the plurality of bootstrap circuits (71). The control unit (60) controls the plurality of first gate drivers (61), the plurality of second gate drivers (62), the plurality of third gate drivers (63), and the plurality of fourth gate drivers (64). Each of the plurality of bootstrap circuits (71) includes a capacitor (C17) and a diode (D17) connected in series to the capacitor (C17).

[0229] According to this aspect, it is possible to achieve miniaturization.

[0230] In a multilevel inverter (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a thirteenth aspect, in the twelfth aspect, the control unit (60) ＊ ) is defined as a command voltage vector (V ＊A plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) are controlled within a predetermined control period (Ts) so as to match the voltages of the plurality of inverter circuits (1). Each of the group of voltage vectors is determined by a combination of a plurality of potential levels in the plurality of inverter circuits (1).

[0231] The multilevel inverter of the present disclosure can reduce noise, and is therefore industrially useful.

[0232] REFERENCE SIGNS LIST 1 Inverter circuit 3 DC power supply unit 33 Path 331 Path 332 Path 333 Path 334 Path 4 Positive wiring unit 5 Negative wiring unit 6 Control device 60 Control unit 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 8 Noise filter 9 Power supply unit 11 First connection point 12 Second connection point 13 Third connection point 71 Bootstrap circuit (first bootstrap circuit) 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H Multilevel inverter 113 Connection point (output point) C1 First capacitor C2 Second capacitor C3 Capacitor C4 Capacitor C5 Capacitor C17 Capacitor D1 First diode D2 Second diode D3 Third diode D4 Fourth diode D5 First clamp diode D6 Second clamp diode D17 Diode G1, G2, G3 Ground wiring Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element M1 Midpoint potential point Ts Control period V0 to V18 Voltage vector V ＊ Command voltage vector

Claims

1. A multilevel inverter comprising: a positive wiring section; a negative wiring section; a DC power supply section having a first capacitor and a second capacitor, the first capacitor and the second capacitor being connected in series between the positive wiring section and the negative wiring section, with the first capacitor and the second capacitor being arranged in series from the positive wiring section side to the negative wiring section; a plurality of inverter circuits connected between the positive wiring section and the negative wiring section and connected to an intermediate potential point between the first capacitor and the second capacitor; a control device for controlling the plurality of inverter circuits; and a noise filter provided on a path between the positive wiring section and the negative wiring section in the DC power supply section.

2. The multilevel inverter according to claim 1, wherein the noise filter includes an inductor or a capacitor.

3. The multilevel inverter according to claim 1 or 2, wherein the noise filter is provided on a path between the intermediate potential point and the first capacitor.

4. The multilevel inverter according to claim 3, further comprising a noise removing capacitor connected between the intermediate potential point and ground.

5. The multilevel inverter according to claim 1 or 2, wherein the noise filter is provided on a path between the first capacitor and the positive wiring portion.

6. The multilevel inverter according to claim 5, further comprising a noise removing capacitor connected between a connection point between said noise filter and said first capacitor and ground.

7. The multilevel inverter according to claim 1 or 2, wherein the noise filter is provided on a path between the second capacitor and the negative wiring section.

8. The multilevel inverter according to claim 7, further comprising a noise removing capacitor connected between the negative wiring section and ground.

9. The multilevel inverter of claim 2, wherein the inductor includes a ferrite core, a bead core, or a toroidal core.

10. Each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element; a first diode, a second diode, a third diode, and a fourth diode connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively; a first clamp diode; and a second clamp diode; and in each of the plurality of inverter circuits, the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series between the positive wiring portion and the negative wiring portion in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element; a cathode of the first clamp diode is connected to a first connection point between the first switching element and the second switching element, and an anode of the first clamp diode is connected to the intermediate potential point; an anode of the second clamp diode is connected to a second connection point between the third switching element and the fourth switching element, and a cathode of the second clamp diode is connected to the intermediate potential point; The multilevel inverter according to any one of claims 1 to 9, wherein a third connection point between the second switching element and the third switching element is connected to an output terminal connected to an AC load.

11. The multilevel inverter according to any one of claims 1 to 9, wherein each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively; and in each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive wiring section to the negative wiring section in the order of the first switching element and the second switching element, and a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and an output point, and the output point is a connection point between the first switching element and the second switching element.

12. The multilevel inverter according to claim 10 or 11, wherein the control device comprises: a plurality of first gate drivers driving the first switching elements of the respective inverter circuits; a plurality of second gate drivers driving the second switching elements of the respective inverter circuits; a plurality of third gate drivers driving the third switching elements of the respective inverter circuits; a plurality of fourth gate drivers driving the fourth switching elements of the respective inverter circuits; a plurality of bootstrap circuits each in one-to-one correspondence with the respective first gate drivers and supplying voltages to the corresponding first gate drivers; a power supply unit supplying voltages to the plurality of bootstrap circuits; and a control unit controlling the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers, each of the plurality of bootstrap circuits including a capacitor and a diode connected in series to the capacitor.

13. The multilevel inverter as described in claim 12, wherein the control unit controls the multiple first gate drivers, the multiple second gate drivers, the multiple third gate drivers and the multiple fourth gate drivers within a predetermined control period so as to match a composite vector of multiple voltage vectors corresponding to vertices of an equilateral triangle surrounding a command voltage vector, among a group of voltage vectors each determined by a combination of multiple potential levels in the multiple inverter circuits, with the command voltage vector.

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