Integrated circuit including vertical electrical connection connecting plurality of semiconductor dies, and electronic device including same

Abstract

A processing chip component according to one embodiment comprises: a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; and an interconnect layer disposed between the first die and the second die. The interconnect layer may comprise a first through silicon via (TSV) connecting the first SERDES circuit and the second SERDES circuit in order to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

Description

An integrated circuit comprising a vertical electrical connection connecting a plurality of semiconductor dies and an electronic device comprising the same

[0001] The present disclosure relates to an integrated circuit including a vertical electrical connection connecting a plurality of semiconductor dies and an electronic device including the same.

[0002] A system on a chip (SOC) is an electronic component that integrates circuits that perform various functions. As the number of functions supported by an electronic device containing an SOC increases, the complexity of the circuits integrated within the SOC can also increase.

[0003] The above information may be provided as background information to aid in understanding the present disclosure. None of the above is claimed to be prior art related to the present disclosure or can be used in making decisions related to prior art.

[0004] In one embodiment, a processing chip component may include a first die including a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first circuit and the second circuit. The processing chip component may include a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip component may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) connecting the first SERDES circuit and the second SERDES circuit to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

[0005] In one embodiment, a processing chip component may include a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit. The processing chip component may include a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip component may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the first circuit to the third circuit and configured to transmit a first type of signal from the first circuit to the third circuit. The interconnect layer may include a second TSV configured to connect the first SERDES circuit to the second SERDES circuit and configured to transmit a second type of signal based on serialization of the first SERDES circuit. The second type of signal transmitted through the second TSV may include a sequence of at least one bit provided by the first circuit and at least one bit provided by the second circuit.

[0006] In one embodiment, an electronic device may include a memory and a processor. The processor may include a first die including a plurality of circuits including a central processing unit (CPU) and a first serializer-deserializer (SERDES) circuit connected to each of the plurality of circuits. The processor may include a second die including a memory interface circuit for communicating with the memory and a second SERDES circuit. The processor may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the CPU and the memory interface circuit of the first die. The interconnect layer may include a second TSV configured to connect the first SERDES circuit and the second SERDES circuit. The CPU may be configured to transmit a data signal including data to be stored in the memory to the memory interface circuit through the first TSV. The CPU may be configured to transmit a control signal to the first SERDES circuit to control the memory interface circuit so that the data is transmitted to the memory.

[0007] According to an embodiment, a three-dimensional integrated circuit may include a substrate, a first integrated circuit layer disposed over the substrate and including a plurality of first circuit elements, a second integrated circuit layer disposed over the first integrated circuit layer and including a plurality of second circuit elements, and an interconnect layer disposed between the first integrated circuit layer and the second integrated circuit layer, the interconnect layer including a plurality of through silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first control signal pins and at least one first data signal pin. The plurality of first control signal pins may be connected to a first TSV of the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of second control signal terminals corresponding to the plurality of first control signal terminals and at least one second data signal terminal corresponding to at least one first data signal terminal. The first TSV may be connected to the plurality of second control signal terminals via a second SERDES circuit.

[0008] In one embodiment, an electronic device may include a display, an antenna, a printed circuit board, a first integrated circuit disposed on the printed circuit board, and a second integrated circuit disposed on the printed circuit board and electrically connected to the first integrated circuit. The second integrated circuit may include a first circuit layer including a plurality of first circuit elements, a second circuit layer disposed over the first circuit layer and including a plurality of second circuit elements, and a connection layer disposed between the first circuit layer and the second circuit layer, the connection layer including a plurality of through silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first control signal terminals and at least one first data signal terminal. The plurality of first control signal terminals may be connected to a first TSV among the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of second control signal terminals corresponding to the plurality of first control signal terminals and at least one second data signal terminal corresponding to the at least one first data signal terminal. The first TSV may be connected to the plurality of second control signal terminals via the second SERDES circuit.

[0009] In one embodiment, an integrated circuit may include a first integrated circuit layer including a plurality of first circuit elements corresponding to a first minimum circuit feature size. The integrated circuit may include a second integrated circuit layer disposed over the first integrated circuit layer and including a plurality of second circuit elements corresponding to a second minimum circuit feature size less than the first minimum circuit feature size. The integrated circuit may include a plurality of vias electrically connecting the first integrated circuit layer and the second integrated circuit layer. The first integrated circuit layer may include a first serializer-deserializer (SERDES) circuit connecting the plurality of first circuit elements to a first via, which is a portion of the plurality of vias. The second integrated circuit layer may include a second SERDES circuit connecting the first via to the plurality of second circuit elements.

[0010] In one embodiment, an application processor (AP) may include a first circuit layer including a first serializer-deserializer (SERDES) electronic component connected to each of a first electronic component, at least one second electronic component, and third electronic components including the first electronic component and the at least one second electronic component, a second circuit layer including a fourth electronic component and a second SERDES electronic component connected to the fourth electronic component, and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include TSVs including a first TSV connecting the first electronic component to the fourth electronic component and a second TSV connecting the first SERDES electronic component to the second SERDES electronic component. The first electronic component may transmit a first type of signal to the fourth electronic component through the first TSV in the interconnect layer. The first electronic component can transmit the second type signal to the first SERDES electronic component in order to transmit the second type signal to the fourth electronic component. The first SERDES electronic component can perform serialization of the second type signal together with at least one signal transmitted from the at least one second electronic component. The first SERDES electronic component can transmit a signal obtained based on the serialization to the second SERDES electronic component through the second TSV. The second SERDES electronic component can be configured to obtain the second type signal to be transmitted to the fourth electronic component based on demodulation and / or deserialization of the signal transmitted through the second TSV.

[0011] In one embodiment, an application processor (AP) may include a first circuit layer including a first electronic component, a plurality of second electronic components including the first electronic component, and a first serializer-deserializer (SERDES) electronic component connected to each of the plurality of second electronic components, a second circuit layer including a third electronic component and a second SERDES electronic component connected to the third electronic component, and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the first electronic component to the third electronic component and configured to transmit a first type of signal from the first electronic component to the third electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component to the second SERDES electronic component and configured to transmit a second type of signal based on serialization of the first SERDES electronic component. The second type of signal transmitted through the second TSV may include a sequence of bits of the plurality of second electronic components based on the serialization, including at least one bit provided by the first electronic component.

[0012] In one embodiment, an electronic device may include a memory and an application processor (AP). The AP may include a first circuit layer including a plurality of electronic components including a central processing unit (CPU) and a first serializer-deserializer (SERDES) electronic component connected to each of the plurality of electronic components, a second circuit layer including a memory interface electronic component and a second SERDES electronic component for communicating with the memory, and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the CPU and the memory interface electronic component of the first circuit layer. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component and the second SERDES electronic component. The CPU may be configured to transmit a data signal including data to be stored in the memory to the memory interface electronic component through the first TSV. The CPU may be configured to transmit a control signal to the memory interface electronic component so that the data is transmitted to the memory, with the first SERDES electronic component.

[0013] FIG. 1 illustrates an exemplary hardware configuration of an electronic device including an application processor (AP), according to one embodiment.

[0014] FIG. 2 illustrates an exemplary structure of an interconnect layer included in an AP according to one embodiment.

[0015] Figures 3a, 3b and 3c illustrate one embodiment of an AP comprising a plurality of circuit layers connected by interconnect layers.

[0016] FIG. 4 illustrates an exemplary structure of an interconnection layer included in an AP according to one embodiment.

[0017] Figure 5 illustrates an exemplary structure of an interconnection layer for supporting multiple wired communication protocols.

[0018] Figure 6 is an exemplary timing diagram for an electrical signal transmitted in an interconnect layer based on a BMC (bi-phase mark coding) scheme.

[0019] FIG. 7 is a block diagram of an electronic device within a network environment according to various embodiments.

[0020] Hereinafter, various embodiments of this document are described with reference to the attached drawings.

[0021] FIG. 1 illustrates an exemplary hardware configuration of an electronic device (101) including an application processor (AP) (110), according to one embodiment.

[0022] Referring to FIG. 1, the electronic device (101) may be one of various forms of electronic devices, such as a laptop PC (personal computer) (190), smartphones (191) having various form factors (e.g., a bar-type smartphone (191-1), a foldable-type smartphone (191-2), or a sliderable (or rollable) type smartphone (191-3)), a tablet PC (192), a head-mounted display (HMD) device (193), a watch (194), a cellular phone (not shown), and other similar computing devices (not shown). The electronic device (101) may be referred to as a mobile device, a user equipment (UE) (or user terminal), a multi-function device, a portable device, or a server. The form factor of the electronic device (101) is not limited to the exemplary form factors illustrated in FIG. 1. For example, the electronic device (101) may be included as an electronic control unit (ECU) in a vehicle (e.g., an electric vehicle (EV)). For example, the electronic device (101) may have a form factor that is wearable by a user, such as an earbud (or wireless earphone) and / or a ring, or may have a form factor that is implantable on a body part of a user.

[0023] The components, their relationships, and their functions illustrated in FIG. 1 are merely exemplary and do not limit the implementations described or claimed in this document. Referring to FIG. 1 , an electronic device (101) according to one embodiment may include components such as a processor (e.g., an application processor (AP), a communication processor (CP)) (110), a memory (e.g., a volatile memory (121) and / or a nonvolatile memory (122)), a display (123), a communication circuit (124), an image sensor (125), and / or a sensor (126). For example, the processor may be implemented as a three-dimensional integrated circuit (3D-IC) including a plurality of circuit layers.

[0024] Referring to FIG. 1, an embodiment is illustrated in which a processor (110), a volatile memory (121), a nonvolatile memory (122), and / or a communication circuit (124) are disposed over or on a printed circuit board (PCB) (105), but the embodiment is not limited thereto. On the PCB (105), the processor (110) may be electrically and / or operably coupled with the volatile memory (121), the nonvolatile memory (122), and / or the communication circuit (124). Hereinafter, operably coupled components may mean that a direct connection or an indirect connection is established between the components, either wired or wireless, such that a second component is controlled by a first component among the components.

[0025] The components included in the electronic device (101) are not limited to the embodiment of FIG. 1, and the electronic device (101) may include other components (e.g., a power management integrated circuit (PMIC), an audio processing circuit, an antenna, a rechargeable battery, or an input / output interface). For example, some components may be omitted from the electronic device (101). For example, some components may be integrated into a single component.

[0026] Referring to FIG. 1, a volatile memory (121) and / or a non-volatile memory (122) may be configured to store data and / or instructions based on an address space managed by the processor (110). A display (123) may display images and / or videos provided from the processor (110) on one surface (e.g., flat and / or curved) of a housing of the electronic device (101). A communication circuit (124) may be configured to support wired communication and / or wireless communication between the electronic device (101) including the processor (110) and an external electronic device. An image sensor (125) may be configured to provide an electrical signal representing external light to the processor (110) and / or a memory (e.g., the volatile memory (121) and / or the non-volatile memory (122)). The sensor (126) may be configured to provide an electrical signal based at least on an external environment to the processor (110) and / or memory (e.g., volatile memory (121) and / or non-volatile memory (122)). Each of the volatile memory (121), non-volatile memory (122), display (123), communication circuit (124), image sensor (125) and sensor (126) of FIG. 1 may correspond to the volatile memory (732), non-volatile memory (734), display module (760), communication module (790), camera module (780) and sensor module (776) illustrated in FIG. 7.

[0027] According to one embodiment, an electronic device (101) may include a processor (110) for processing data. The processor (110) may include circuit elements including passive components, transistors, diodes, or a combination thereof. Within the processor (110), logic circuits for processing data may be interconnected. The processor (110) may be referred to as an integrated circuit (IC) and / or a system on chip (SoC). Circuits included in the processor (110) may be classified into units, modules, and / or electronic components according to functions. For example, the processor (110) may include electronic components such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), a display controller, a memory controller, a storage controller, an application processor (AP), a communication processor (CP), and / or a sensor interface. Hereinafter, a unit, module and / or electronic component may mean a set of circuits included in the processor (110) and at least a portion of the processor (110) designed to perform a specific function. The processor (110) of FIG. 1 may correspond to the processor (120) of FIG. 7.

[0028] According to one embodiment, a processor (110) may have a three-dimensional integrated circuit (3D-IC) structure in which a plurality of dies are stacked. In terms of including one or more circuit elements, a die may be referred to as a circuit layer and / or an integrated circuit (IC) layer. The yield (e.g., the defect rate of the die) of a die may decrease (e.g., random fail) as the area of ​​the die decreases. A processor (110) designed to include a plurality of dies may be produced with an increased yield than a case designed to include a single die because the processor includes dies having a smaller area than the case for the single die. Hereinafter, a “layer” may be used as a term to distinguish dies and / or substrates stacked along a reference direction (the direction of the z-axis in one embodiment of FIG. 1) within the processor (110). For example, "layer" may be replaced with terms such as "substrate," "layer," "semiconductor die," and / or "die." The processor (110) may include a plurality of dies based on a silicon wafer. Embodiments are not limited thereto, and dies based on silicon carbide (SiC) wafers, gallium nitride (GaN) wafers, gallium arsenide (GaAs) wafers, and / or other suitable wafers may be included within the processor (110).

[0029] According to one embodiment, a processor (110) is illustrated with a first circuit layer (130) and a second circuit layer (150). The first circuit layer (130) may be disposed (or positioned) above the second circuit layer (150) within the processor (110). Referring to FIG. 1, an exemplary structure of a second circuit layer (150) included in the processor (110) and the first circuit layer (130) disposed over the second circuit layer (150) along the direction of the z-axis (e.g., vertical direction) is illustrated. The first circuit layer (130) and the second circuit layer (150) may be arranged parallel to the xy plane within the processor (110). Based on the first circuit layer (130) and / or the second circuit layer (150) arranged along the z-axis direction, the circuit elements may have distinct three-dimensional locations within the processor (110). In terms of including circuit elements having three-dimensional locations, the processor (110) may be referred to as a three-dimensional integrated circuit (3D-IC), 3D packaging, 3D stacked ICs (SICs), processing chip component, or monolithic 3D IC.

[0030] According to one embodiment, the processor (110) may include at least one interconnect layer (or connection layer) (140) disposed between the first circuit layer (130) and the second circuit layer (150). The interconnect layer may be referred to as an interposer layer (or interposer). The interconnect layer may be formed based on a material such as silicon, glass, and / or an organic compound.

[0031] In one embodiment, the processor (110) may further include other components not shown in FIG. 1, in addition to the first circuit layer (130), the second circuit layer (150), and the interconnect layer (140) exemplarily illustrated in FIG. 1. For example, the processor (110) may include a substrate, a redistribution layer (RDL), and / or at least one solder ball. The substrate and / or the RDL may be disposed, for example, below the second circuit layer (150) along the -z axis direction. The processor (110) may include a packaging structure enclosing the components described above.

[0032] In one embodiment, the interconnect layer (140) formed between the first circuit layer (130) and the second circuit layer (150) may include a component for supporting electrical connection between the first circuit layer (130) and the second circuit layer (150). The component may include a through silicon via (TSV). The TSV may be referred to as a through chip via and / or a through hole. The component is not limited to a TSV and may include other components (e.g., bonding wires) for electrical connection in the direction of the z-axis. The interconnect layer (140) may be formed in various shapes. For example, the interconnect layer (140) may be formed to have substantially the same width, height, thickness, area, shape, and / or size as the first circuit layer (130) and / or the second circuit layer (150), but is not limited thereto, and may be formed to have various widths, heights, thicknesses, areas, shapes, and / or sizes. According to one embodiment, the interconnect layer (140) may include at least one connecting member (e.g., a wire, a solder bump, a metal bump, or other conductive adhesive) based on a connection technology different from TSV. The first circuit layer (130) and the second circuit layer (150) may be electrically connected through the connecting member included in the interconnect layer (140).

[0033] Referring to FIG. 1, an example of an interconnect layer (140) including at least one TSV (e.g., a first TSV (141) and / or a second TSV (142)) is illustrated. A plurality of TSVs included in the interconnect layer (140) may be formed based on a via-first process that is formed before a front end of line (FEOL) process and / or a back end of line (BEOL) process of the first circuit layer (130) and / or the second circuit layer (150). Within the via-first process, the plurality of TSVs may be degraded or distorted by heat transferred to the interconnect layer (140) in the FEOL process and / or the BEOL process. The embodiment is not limited thereto, and the plurality of TSVs included in the interconnect layer (140) may be formed based on a via-last process that is formed after the FEOL process and / or the BEOL process. By the via-last process, multiple TSVs can be formed independently of the heat generated in the FEOL process and / or the BEOL process. While the multiple TSVs are formed by the via-last process (e.g., an etching process), circuit elements included in the first circuit layer (130) and / or the second circuit layer (140) may be damaged. For example, the yield of the processor (110) can be improved as the number of TSVs included in the interconnect layer (140) decreases.

[0034] According to one embodiment, the processor (110) may include a structure for reducing the number of TSVs included in the interconnect layer (140). For example, a TSV (141) may be formed in the interconnect layer (140) to transmit a combination (or bundle) of signals and / or information generated from each of the electronic components and / or circuits included in the first circuit layer (130). To generate the combination, the processor (110) may include a first serializer-deserializer (SERDES) circuit (131) connected to each of the electronic components (e.g., first circuit elements) included in the first circuit layer (130). The first SERDES circuit (131) may be electrically connected to one end of the TSV (141) adjacent to the first circuit layer (130).

[0035] In one embodiment, the processor (110) may include a second SERDES circuit (151) configured to receive a signal or combined information transmitted from a first SERDES through a TSV (141). The second SERDES circuit (151) may be electrically connected to another end of the TSV (141) adjacent to a second circuit layer (150). The second SERDES circuit (151) may be configured to obtain a signal and / or information to be transmitted from the signal or combination (i.e., the combined information) transmitted from the first SERDES through the TSV (141) to at least one of the circuits included in the second circuit layer (150). The second SERDES circuit (151) may be included in the second circuit layer (150). The second SERDES circuit (151) may be connected to each of the circuits included in the second circuit layer (150). Although an embodiment has been described in which a combination of signals and / or information generated in a first circuit layer (130) is transmitted to a second circuit layer (150) through a TSV (141), the embodiment is not limited thereto, and a combination of signals and / or information generated in each of the circuits of the second circuit layer (150) may be transmitted to the first circuit layer (130) through a TSV (141). That is, the first SERDES circuit (131), the second SERDES circuit (151), and the TSV (141) may enable bidirectional communication between a circuit in the second circuit layer (130) and a circuit in the second circuit layer (150). Exemplary structures of the first SERDES circuit (131) and the second SERDES circuit (151) connected to both ends of the TSV (141) are described with reference to FIGS. 2 to 5.

[0036] In a processor (110) including a TSV (141), a first SERDES circuit (131), and a second SERDES circuit (151) as described with reference to FIG. 1, the TSV (141) may be configured to transmit information between circuits disposed in different circuit layers (e.g., the first circuit layer (130) and / or the second circuit layer (150)). Since at least one circuit of the first circuit layer (130) is electrically connected to the TSV (141) through the first SERDES circuit (131) and at least one circuit of the second circuit layer (150) is electrically connected to the TSV (141) through the second SERDES circuit (151), a specific circuit of the first circuit layer (130) may be designed to communicate with another circuit disposed in the second circuit layer (150) without an additional TSV. For example, TSVs for connecting at least one circuit of the first circuit layer (130) and a circuit of the second circuit layer (150) may not be individually arranged for each circuit, but may be integrated into the TSV (141). In one embodiment, the interconnect layer (140) may further include a TSV (141) connecting the first SERDES circuit (131) and the second SERDES circuit (151), and another TSV dedicated to communication between circuits arranged in different circuit layers. In one embodiment of FIG. 1, the processor (110) may include a TSV (142) configured to electrically connect a circuit (132) of the first integrated circuit layer (130) and a circuit (152) of the second circuit layer (150). The circuit (132) can directly transmit a first type of signal (e.g., a signal including data) to the circuit (152) through the TSV (142). The circuit (132) can transmit the second type of signal (e.g., a signal for controlling the circuit (152)) to the first SERDES circuit (131) in order to transmit the second type of signal through the TSV (141).For example, depending on the type, data-rate and / or protocol of the signal, any one of the TSVs (141, 142) may be selected for transmission of the signal. Exemplary operations of the processor (110) and / or circuits within the processor (110) that communicate using the TSVs (141, 142) are described with reference to FIGS. 3A to 3C. An example of a communication protocol used by the first SERDES circuit (131) and the second SERDES circuit (151) for transmission of the signal in the TSV (141) is described with reference to FIG. 6.

[0037] As described above, according to one embodiment, the processor (110) included in the electronic device (101) may have a structure in which a plurality of signal paths (or signal pins) connecting between circuits are integrated into a signal path (e.g., TSV (141) forming a single signal path) less than the number of signal paths. By using an interface structure based on the TSV (141), the first SERDES circuit (131), and the second SERDES circuit (151), the processor (110) may support communication between a circuit (132) disposed in the first circuit layer (130) and a circuit (152) disposed in the second circuit layer (150). Since the processor (110) is designed and / or manufactured to have a relatively small number of TSVs based on the interface structure, the yield of the processor (110) may be improved.

[0038] For example, a processor (110) (or processing chip component) includes a first die (e.g., a first circuit layer (130)) including a first circuit, a second circuit, and a first SERDES circuit (131) connected to the first circuit and the second circuit; a second die (e.g., a second circuit layer (150)) including a third circuit, a fourth circuit, and a second SERDES circuit (151) connected to the third circuit and the fourth circuit; and an interconnect layer (140) disposed between the first die and the second die, wherein the interconnect layer (140) includes a first TSV (141) configured to be connected between the first SERDES circuit (131) and the second SERDES circuit (151). For example, the first TSV (141) may provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit. As described above, the first TSV (141) may provide a single signal passing through each of the first, second, third, and fourth signal paths.

[0039] The first SERDES circuit (131) may be configured to perform serialization of a signal transmitted from the first circuit together with a signal transmitted from the second circuit, and may be configured to transmit a signal obtained based on the serialization to the second SERDES circuit (151) through the first TSV (141). The second SERDES circuit (151) may be configured to obtain the signal to be transmitted to at least one of the third circuit and the fourth circuit based on deserialization of the signal transmitted through the first TSV (141). The second SERDES circuit (151) may also be configured to perform serialization of a signal transmitted from the second circuit together with a signal transmitted from the fourth circuit, and may be configured to transmit a signal obtained based on the serialization to the first SERDES circuit (131) through the first TSV (141). The first SERDES circuit (131) may also be configured to obtain the signal to be transmitted to at least one of the first circuit and the second circuit based on deserialization of the signal transmitted through the first TSV (141).

[0040] The first SERDES circuit (131) and the second SERDES circuit (151) may be configured to obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path, based on a position of each of the plurality of bits of a signal transmitted through the first TSV based on deserialization.

[0041] The interconnect layer (141) may further include a second TSV (142) connecting the first circuit to the third circuit. The second TSV (142) may provide a fifth signal path between the first circuit and the third circuit, and the fifth signal path does not include the first SERDES circuit (131) and does not include the second SERDES circuit (151).

[0042] For example, the first circuit may be configured to transmit a first type of signal to the third circuit through the second TSV (142) in the interconnect layer (140), and may be configured to transmit a second type of signal to the first SERDES circuit (131) to transmit the second type of signal to the third circuit through the first TSV. For example, the first circuit and the third circuit, which are directly (e.g., through the TSV (142)) and indirectly (e.g., through the first SERDES circuit (131), the TSV (141), and the second SERDES circuit (151)), may selectively utilize the direct or indirect connection based on the purpose, the data rate, and / or the content of the signal.

[0043] For example, the signal of the first type may include a data signal to be input to the third circuit, and the signal of the second type may include a control signal corresponding to the third circuit.

[0044] Additional features related to the first TSV (141) and the second TSV (142) included in the processor (110) of FIG. 1 are described below with respect to, for example, FIG. 2, FIG. 3a-3c, FIG. 4, and FIG. 5.

[0045] For example, the first SERDES circuit (131) may include a buffer for storing bits received from the first circuit and the second circuit, each of the bits corresponding to at least one of the first signal path, the second signal path, the third signal path, or the fourth signal path. The first SERDES circuit (131) may include a controller configured to perform serialization on the bits stored in the buffer to generate a sequence of bits to be included in a signal to be transmitted to the second die through the first TSV.

[0046] For example, it may include a buffer for storing bits received from the third signal and the fourth signal, each of the bits corresponding to at least one of the first signal path, the second signal path, the third signal path, or the fourth signal path. The second SERDES circuit (151) may include a controller configured to perform serialization on the bits stored in the buffer to generate a sequence of bits to be included in a signal to be transmitted to the first die through the first TSV (141).

[0047] The first SERDES circuit may be configured to store bits obtained from the first circuit and the second circuit within a specified time interval in the buffer; and may be configured to perform serialization of the bits stored in the buffer based on the expiration of the specified time interval.

[0048] The second SERDES circuit may be configured to store bits obtained from the third circuit and the fourth circuit within a specified time interval in the buffer, and may be configured to perform serialization of the bits stored in the buffer based on the expiration of the specified time interval.

[0049] Additional features associated with SERDES circuits (e.g., the buffer and the controller) that may be included in the processor (110) of FIG. 1 are described below with respect to, for example, FIGS. 2, 3a-3c, 4, and 5.

[0050] The circuitry included in the first die (e.g., the first circuit and the second circuit) and the second die (e.g., the third circuit and the fourth circuit) may include, for example, a central processing unit (CPU), a graphic processing unit (GPU), a serial communication interface / last level cache (SCI / LLC), a single interface (I / F), a high speed synchronous serial interface (HIS), a memory management (M / M), a neural processing unit (NPU), a low-power dynamic random access memory (LP-DDR), a physical interface (PHY), a network on chip (NOC), a display controller, an image signal processor (ISP), and / or a modem. However, these are merely examples, and the circuitry may include other suitable components.

[0051] For example, the first circuit may include a CPU circuit, and the second circuit may include a GPU circuit.

[0052] For example, the third circuit may include an ISP circuit, and the fourth circuit may include a display controller circuit. As another example, the third circuit may include a memory interface circuit for communicating with memory connected to a processing chip component, and the fourth circuit may include an NPU circuit.

[0053] For example, a first circuit may include a CPU circuit, a second circuit may include a GPU circuit, a third circuit may include an ISP circuit, and a fourth circuit may include a display controller circuit. The CPU circuit may include a first signal pin connected to a first SERDES circuit (131), and a second TSV (142) may be connected to a second signal pin of the CPU circuit. The ISP circuit may include a third signal pin electrically connected to the second TSV (142). The CPU circuit may be configured to transmit a control signal for requesting data from the ISP circuit to the first SERDES circuit (131) through the first signal pin, and receive data corresponding to the control signal from the ISP circuit through the second signal pin connected to the second TSV (142).

[0054] Additional features relating to signal pins that may be included in the processor (110) of FIG. 1 are described below with respect to, for example, FIGS. 2, 3A-3C, 4, and 5.

[0055] In an example where the first circuit includes a CPU, the second SERDES circuit (151) may be configured to receive, via the third circuit button, a signal to notify the first circuit of at least one of a state of the third circuit or an interruption (e.g., a software interrupt) associated with the third circuit.

[0056] For example, the first die may be configured to include circuit elements having a size smaller than a minimum size of circuit elements included in the second die. For example, the first die may include circuits produced by a process capable of implementing circuit elements based on a first minimum feature size (e.g., a 3 nm process and / or a 2 nm process), and the second die may include circuits produced by a process capable of implementing circuit elements based on a second minimum feature size greater than the first minimum feature size.

[0057] For example, the first SERDES circuit (131) may be configured to transmit a signal encoded based on a BMC (bi-phase mark coding) scheme and acquired based on serialization to the second SERDES circuit (151) through the first TSV (141). Additional features related to the BMC scheme that may be included in the processor (110) of FIG. 1 are described below, for example, with respect to FIG. 6.

[0058] For example, the power state of at least one of the first SERDES circuit (131) and the second SERDES circuit (151) may be controlled independently of the power state of the CPU included in the processing chip component. Additional features related to the states of the SERDES circuit that may be included in the processor (110) of FIG. 1 are described below, for example, with respect to FIGS. 3A to 3C.

[0059] For example, the interconnect layer (140) may include an auxiliary TSV configured to connect between the first SERDES circuit (131) and the second SERDES circuit (151), and configured to provide an auxiliary first signal path between the first circuit and the third circuit, an auxiliary second signal path between the first circuit and the fourth circuit, an auxiliary third signal path between the second circuit and the third circuit, and an auxiliary fourth signal path between the second circuit and the fourth circuit.

[0060] The first die may include a first switch circuit, and the second die may include a second switch circuit. The first switch circuit and the second switch circuit may be configured to control a connection between the first SERDES circuit (131) and the second SERDES circuit (151) by switching a connection between the first TSV and the auxiliary TSV.

[0061] Additional features related to the auxiliary TSV included in the processor (110) of FIG. 1 are described below, for example, with respect to FIG. 4.

[0062] For example, the interconnect layer may include a plurality of TSVs; the first SERDES circuit may include a first protocol circuit configured to support a first communication protocol, a second protocol circuit configured to support a second communication protocol, and a first multiplexer switch circuit configured to connect the plurality of TSVs to the first protocol circuit and the second protocol circuit; the second SERDES circuit may include a third protocol circuit configured to support the first communication protocol, a fourth protocol circuit configured to support the second communication protocol, and a second multiplexer switch circuit configured to connect the plurality of TSVs to the third protocol circuit and the fourth protocol circuit, wherein the first multiplexer switch circuit and the second multiplexer switch circuit may be configured to: select a communication protocol, and establish a connection between the first protocol circuit and the third protocol circuit through the plurality of TSVs when the first communication protocol is selected, and establish a connection between the second protocol circuit and the fourth protocol circuit through the plurality of TSVs when the second communication protocol is selected.

[0063] Additional features related to the protocol circuit that may be included in the processor (110) of FIG. 1 are described below, for example, with respect to FIG. 5.

[0064] Hereinafter, with reference to FIG. 2, an exemplary structure of an inter-circuit layer connection formed between circuit layers by a first SERDES circuit (131), a second SERDES circuit (151), and a TSV (141) is described.

[0065] FIG. 2 illustrates an exemplary structure of an interconnect layer (140) included in a processor (110), according to one embodiment. At least a portion of the processor (110) illustrated in FIG. 2 may correspond to at least a portion of the processor (110) illustrated in FIG. 1, and features described above with respect to the processor (110) of FIG. 1 may also be included in the processor (110) of FIG. 2, even if not illustrated or specifically described below.

[0066] Referring to FIG. 2, a second circuit layer (150), an interconnect layer (140), and a first circuit layer (130) are sequentially stacked along the z-axis direction within a processor (110). Within the interconnect layer (140), a TSV (141) may be formed to integrally transmit signals (e.g., signals based on general purpose input-output (GPIO)) transmitted between the first circuit layer (130) and the second circuit layer (150). In order to integrally transmit the signals through a single signal path such as the TSV (141), a first SERDES circuit (131) and a second SERDES circuit (151) may be disposed at both ends of the TSV (141). For example, when the first SERDES circuit (131) comprehensively transmits signals of circuits of the first circuit layer (130), the second SERDES circuit (151) can distribute the comprehensive signals to each of the circuits of the second circuit layer (150). Conversely, when the second SERDES circuit (151) comprehensively transmits signals of circuits of the second circuit layer (150), the first SERDES circuit (131) can distribute the comprehensive signals to each of the circuits of the first circuit layer (130).

[0067] According to one embodiment, a SERDES circuit (e.g., a first SERDES circuit (131) and / or a second SERDES circuit (151)) may include pins (or signal terminals) for electrically connecting with other circuits (e.g., circuits included in a circuit layer (e.g., a first integrated circuit layer (130) and / or a second integrated circuit layer (150)) on which the SERDES circuit is arranged). Referring to FIG. 2, a first SERDES circuit (131) including k pins (e.g., p11, p12, …, p1k) and a second SERDES circuit (151) including k pins (e.g., p21, p22, …, p2k) are exemplarily illustrated, but the number of pins extending from the SERDES circuit is not limited thereto. The k pins of the first SERDES circuit (131) may be electrically connected to different circuits arranged in the first circuit layer (130). Similarly, the k pins of the second SERDES circuit (151) may be electrically connected to different circuits arranged in the second circuit layer (150).

[0068] In one embodiment, a SERDES circuit (e.g., a first SERDES circuit (131) and / or a second SERDES circuit (151)) can receive an electrical signal comprising one or more bits from another circuit via at least one pin. For example, the one or more bits can represent a numeric value corresponding to a state of the other circuit. For example, the one or more bits can represent an interrupt generated by the other circuit (e.g., a software interrupt). The one or more bits representing an interrupt can represent a type of the interrupt and / or a numeric value uniquely assigned to the interrupt. For example, a circuit disposed in a particular circuit layer can transmit an electrical signal to a SERDES circuit connected to the circuit to notify a circuit disposed in another circuit layer of at least one of a state of the circuit and / or an interrupt associated with the circuit.

[0069] In one embodiment, the SERDES circuit may include buffers for storing signals independently received via different pins and / or bits included in the signals. Referring to FIG. 2, the first SERDES circuit (131) may include a buffer (212) for storing bits received via k pins. The second SERDES circuit (151) may include a buffer (222) for at least partially storing signals received via k pins. In each of the buffers (212, 222), bits indicating states of circuits included in each of the first circuit layer (130) and the second circuit layer (150) and / or interrupts generated in the circuits may be stored.

[0070] In one embodiment, the SERDES circuit may include a controller for performing serialization on bits stored in a buffer or for performing deserialization on bits included in a signal received through a TSV (141). Referring to FIG. 2, a controller (211) included in a first SERDES circuit (131) and a controller (221) included in a second SERDES circuit (151) are exemplarily illustrated. The controller (211) of the first SERDES circuit (131) may combine bits stored in a buffer (212) to obtain a plurality of bits to be included in a signal to be transmitted to the second circuit layer (150) and / or the second SERDES circuit (151) through the TSV (141). Similarly, the controller (221) of the second SERDES circuit (151) can combine bits stored in the buffer (222) to obtain a sequence of bits to be transmitted to the first circuit layer (130) and / or the first SERDES circuit (131) through the TSV (141).

[0071] In one embodiment, the first SERDES circuit (131) or the second SERDES circuit (151) may be implemented without a controller, including a PISO (parallel in serial out) function block, a SIPO (serial in parallel out) function block, or a clock circuit.

[0072] In one embodiment, the combining of bits performed by the controller (211) of the first SERDES circuit (131) and / or the controller (221) of the second SERDES circuit (151) may include serialization. Serialization may include obtaining a sequence of bits (e.g., a bitstream) to be sequentially transmitted down a single signal path (or lane), such as a TSV (141). For example, the controller (211) may generate or obtain the sequence of bits by concatenating bits stored in the buffer (212) and / or bits received via pins (p11 to p1k). The locations of each of the bits within the sequence may be determined based on the pin on which the bit was received. For example, Table 1 exemplarily shows bits received via four pins (p11 to p14).

[0073] pinp11p12p13p14bit1011

[0074] The controller (211) of the first SERDES circuit (131) that receives the bits illustrated in Table 1 can sequentially combine the bit (1) received through the pin (p11), the bit (0) received through the pin (p12), the bit (1) received through the pin (p13), and the bit (1) received through the pin (p14) to generate a sequence of bits (1011). Based on the above-described operation, the controller (211) can generate a sequence of k bits received from k pins. The controller (211) can transmit a signal representing the sequence through the TSV (141).

[0075] In one embodiment where the first SERDES circuit (131) is connected to k different circuits via k pins, the timings at which the k circuits transmit signals to the first SERDES circuit (131) may be different. In the exemplary case of receiving bits in Table 1, the timing of receiving bit (0) via pin (p12) and the timing of receiving bit (1) via pin (p11) may be the same or different. In one embodiment, the controller (211) may accumulate or store bits included in signals transmitted from different circuits during a specified time interval (e.g., about 5 milliseconds (ms)) in the buffer (212). For example, within the time interval distinguished based on the specified period, the controller (211) may receive at least one bit to be included in a signal to be transmitted to the TSV (141).

[0076] Based on or upon the expiration of the above time interval, the controller (211) can perform serialization on the bits stored in the buffer (212). If a particular circuit does not transmit any signal within the above time interval, the controller (211) can perform the serialization based on the bits that were transmitted from the particular circuit before the above time interval (e.g., stored in the buffer (212) before the above time interval).

[0077] In one embodiment, the first SERDES circuit (131) can transmit a signal to the second SERDES circuit (151) through the TSV (141) whenever a signal is generated at any one of the k pins (e.g., p11, p12, …, p1k). In one embodiment, the first SERDES circuit (131) can identify a pin or signal having a specified name or format among the k pins (e.g., p11, p12, …, p1k) and transmit the corresponding signal to the second SERDES circuit (151) regardless of the transmission cycle. In one embodiment, when a signal is generated at a pin having a specified name or format, the first SERDES circuit (131) can perform serialization on signals generated up to that point even if the transmission cycle has not yet been reached. The first SERDES circuit (131) can transmit a signal generated and / or obtained by the serialization to the second SERDES circuit (151).

[0078] With reference to Table 1, one embodiment of a first SERDES circuit (131) connected to k different circuits via k pins has been described, but the embodiment is not limited thereto. For example, at least two pins among the k pins may be configured to connect the first SERDES circuit (131) to one circuit. For example, a circuit connected to the first SERDES circuit (131) via two pins may transmit a signal including two bits. Using the signal, the circuit may indicate a current state of the circuit, selected from a maximum of four states.

[0079] According to one embodiment, the first SERDES circuit (131) can transmit a signal (e.g., a signal including a sequence of bits) obtained based on the operation (e.g., serialization) described above to the second SERDES circuit (151) through the TSV (141). The controller (221) of the second SERDES circuit (151) that receives the signal can perform deserialization (or reserialization) on the received signal to obtain at least one bit to be provided to at least one circuit of the second circuit layer (150). For example, the controller (221) can obtain or generate signals to be transmitted to the circuits of the second circuit layer (150) based on the deserialization.

[0080] For example, a controller (221) that receives a sequence of bits through a TSV (141) can allocate the plurality of bits to different pins based on the respective positions of the plurality of bits within the sequence. A second SERDES circuit (151) that receives a signal including a sequence of k bits through a TSV (141) can allocate bits located at different positions (digits) within the sequence to k pins (e.g., p21, p22, …, p2k). For example, a second SERDES circuit (151) that receives a sequence of bits (1011) through a TSV (141) can allocate bits located at different positions (digits) within the sequence to k pins (e.g., p21, p22, …, p2k). 3 Bit (1) of the position to pin (p21), 2 2 Bit (0) of the position to pin (p22), 2 1 Bit (1) of the position to pin (p23), 2 0 The bit (1) of the position can be output to the pin (p24). When the second SERDES circuit (151) is connected to the circuits of the second circuit layer (150) through different pins, different bits within the sequence can be transmitted to the circuits through the pins.

[0081] As described above, based on the serialization in the first SERDES circuit (131) and the deserialization in the second SERDES circuit (151), a bit input to a specific pin of the first SERDES circuit (131) can be output through a pin corresponding to the specific pin in the second SERDES circuit (151). For example, the pins of the first SERDES circuit (131) can be matched one on one with the pins of the second SERDES circuit (151). Based on the one-on-one relationship between the pins of the first SERDES circuit (131) and the pins of the second SERDES circuit (151), an exclusive connection between a specific circuit of the first circuit layer (130) and another circuit of the second circuit layer (150) can be established through the TSV (141). In one embodiment of FIG. 2, based on the first SERDES circuit (131), the second SERDES circuit (151), and the TSV (141), up to k exclusive connections can be established. In other words, since the k exclusive connections are integrated into one TSV (141), the processor (110) can be designed and manufactured with a relatively small number of TSVs. Since the processor (110) has a relatively small number of TSVs, the yield of the processor (110) can be improved.

[0082] Referring to FIG. 2, an embodiment of transmitting a signal from a first SERDES circuit (131) to a second SERDES circuit (151) has been described, but the embodiment is not limited thereto. For example, the controller (221) of the second SERDES circuit (151) may perform serialization on signals and / or bits stored in a buffer (222) within a specified time interval. Based on the serialization, bits received through different pins (p21, p22, ..., p2k) within the specified time interval may be integrated into one bitstream. The controller (221) may transmit a signal including the bitstream to the first circuit layer (130) and / or the first SERDES circuit (131) through a TSV (141). The first SERDES circuit (131) and / or the controller (211) that receives the signal through the TSV (141) can segment the bits included in the bitstream based on deserialization. The segmented bits based on their positions within the bitstream can be output through different pins (p11, p12, …, p1k) of the first SERDES circuit (131) by the controller (211). When the pins are connected to different circuits of the first circuit layer (130), the bits output through the pins (p11, p12, …, p1k) can be transmitted to the circuits.

[0083] As described above, based on the first SERDES circuit (131), the TSV (141), and the second SERDES circuit (151) included in the processor (110), signals of different circuits can be integrated and transmitted through the TSV (141). From the viewpoint of integrating signals, SERDES circuits such as the first SERDES circuit (131) and / or the second SERDES circuit (151) may be referred to as a signal combining circuit and / or a signal modulator. A signal transmitted through the TSV (141) may be split into one or more signals to be transmitted to different circuits by the SERDES circuit. From the viewpoint of signal splitting, SERDES circuits such as the first SERDES circuit (131) and / or the second SERDES circuit (151) may be referred to as a signal splitting circuit and / or a signal demodulator.

[0084] Below, an exemplary structure of a processor (110) including a first SERDES circuit (131), a TSV (141), and a second SERDES circuit (151) is described with reference to FIG. 2.

[0085] FIGS. 3A, 3B, and 3C illustrate one embodiment of a processor (110) that includes a plurality of circuit layers (e.g., a first circuit layer (130) and / or a second circuit layer (150)) connected by an interconnect layer (140). At least a portion of the processor (110) illustrated in FIGS. 3A through 3C may correspond to at least a portion of the processor (110) of FIGS. 1 and / or 2, and features described above with respect to the processor (110) of FIGS. 1 and / or 2 may be included in the processor (110) of FIGS. 3A through 3C, even if not depicted or specifically described below.

[0086] Referring to FIG. 3A, for convenience of explanation, circuits included in the processor (110) are illustrated in the form of blocks in each of the first circuit layer (130) and the second circuit layer (150). As examples of circuits included in the processor (110), a central processing unit (CPU) (310), a graphic processing unit (GPU) (312), a serial communication interface (SCI) / last level cache (LLC), a signal I / F (interface), a high speed synchronous serial interface (HSI), a memory management (M / M), a neural processing unit (NPU), a low power dynamic random access memory (LP-DDR) physical interface (PHY) (320), a network on chip (NOC), a display controller (322), an image signal processor (ISP) (324), and / or a MODEM are illustrated. The circuits included in the processor (110) are not limited to the embodiment of FIG. 3A, and the processor (110) may further include circuits not shown in FIG. 3A, or some of the circuits of FIG. 3A may be excluded from the processor (110).

[0087] Referring to FIG. 3A, an embodiment is illustrated in which a CPU (310) and / or a GPU (312) are disposed in a first circuit layer (130) and an NPU and / or a MODEM are disposed in a second circuit layer (150), but the embodiment is not limited thereto. For example, circuits depicted as different blocks in each of the first circuit layer (130) and the second circuit layer (150) may be disposed in different locations and / or dies than in the embodiment of FIG. 3A. For example, based on a heat dissipation structure within the processor (110), the locations of the circuits may be determined in either the first circuit layer (130) and / or the second circuit layer (150).

[0088] For example, the CPU (310) may include circuitry configured to process data based on at least one instruction input to the CPU (310). The GPU (312) may include circuitry configured to execute parallel operations for graphics (e.g., rendering). The NPU (or neural engine) may include circuitry configured to execute operations for an artificial intelligence model (e.g., convolution computation). The SCI / LLC may include circuitry configured to at least temporarily store data to be processed by the CPU (310), the GPU (312), and / or the NPU. The Signal I / F may include circuitry configured to control transmission of a signal within a circuit layer (e.g., the first circuit layer (130) and / or the second circuit layer (150)). The HSI may include circuitry configured to transmit signals at relatively high speed between circuits within a circuit layer (e.g., the first circuit layer (130) and / or the second circuit layer (150)). The M / M may include circuitry for converting between virtual addresses and physical addresses to access data stored in a memory (e.g., the volatile memory (121) and / or the non-volatile memory (122) of FIG. 1) coupled to the processor (110). The LP-DDR PHY (320) may include circuitry for transmitting and / or receiving data directly between the CPU (310) and the volatile memory (e.g., the volatile memory (121) of FIG. 1) coupled to the processor (110). The NOC may include circuitry configured to control the transmitting and receiving of signals between circuits within the processor (110).The display controller (322) may include circuitry for controlling a display electrically connected to the processor (110) using data (e.g., images and / or video based on rendering) provided from the CPU (310) and / or the GPU (312). An image signal processor (ISP) (324) may include circuitry for controlling a camera electrically connected to the processor (110) and / or receiving data (e.g., images, video and / or image frames acquired by the camera) from the camera. A MODEM may include circuitry configured to control a communication circuit (e.g., the communication circuit (124) of FIG. 1) connected to the processor (110).

[0089] The circuits described above may be arranged in either a first circuit layer (130) or a second circuit layer (150) produced based on different processes within the processor (110). For example, the minimum size of the first circuit elements included in the first circuit layer (130) may be smaller than the minimum size of the second circuit elements included in the second circuit layer (150). The first circuit layer (130) may be produced by a first process (e.g., a 3 nm process and / or a 2 nm process) capable of implementing circuit elements (e.g., transistors having a gate-all-around (GAA) structure) based on a minimum line width (line pitch) of 3 nm. The second circuit layer (150) may be produced by a second process that supports the production of circuit elements (e.g., transistors having a fin field-effect transistor (FinFET) structure) having a minimum line width greater than 3 nm. The processes corresponding to the first circuit layer (130) and the second circuit layer (150) are not limited to the first process and the second process described above.

[0090] In one embodiment, the circuits described as integrated in the processor (110) (e.g., CPU, ISP, MODEM, NPU, and / or GPU) may be implemented or produced as independent integrated circuits. Within the above embodiment, the integrated circuit including at least one of the CPU, ISP, MODEM, NPU, and / or GPU described above may be implemented as a 3D-IC including stacked circuit layers therein (e.g., semiconductor die layers) and serial interconnection lines (e.g., TSVs) connecting the stacked circuit layers.

[0091] In one embodiment, the performance (e.g., performance as measured by parameters such as instructions per cycle (IPC) and / or floating point operations per second (FLOPS)), power consumption, and / or yield of a circuit layer may be related to the process used to produce the circuit layer. Circuits included in the processor (110) may be placed in either the first integrated circuit layer (130) or the second integrated circuit layer (150) based on the required performance, power consumption, and / or yield. Referring to FIG. 3A, a processor (110) is illustrated by way of example, including a first circuit layer (130) including a CPU (310), a GPU (312), and an SCI / LLC, and a second circuit layer (150) including an NPU, an HIS, an LP-DDR PHY (320), a MODEM, an M / M, and a NOC, but the embodiment is not limited thereto.

[0092] Referring to FIG. 3A, a first circuit layer (130) of a processor (110) may include a first SERDES circuit (131) connected to each of a plurality of circuits (e.g., first circuit elements) of a first direct circuit layer (130), including a CPU (310). A second circuit layer (150) of the processor (110) may include a second SERDES circuit (151) connected to each of a plurality of circuits of the second circuit layer (150), including a memory interface circuit for communicating with a memory (e.g., a volatile memory (121) of FIG. 2), such as an LP-DDR PHY (320). The processor (110) may include an interconnect layer (140) disposed between the first circuit layer (130) and the second circuit layer (150).

[0093] In one embodiment, the interconnect layer (140) may include one or more signal paths for electrically and / or operatively connecting circuits of the first circuit layer (130) and circuits of the second circuit layer (150). The signal path may be established by a TSV. Referring to FIG. 3A, as an example of the signal path, a TSV (141) configured to connect a first SERDES circuit (131) and a second SERDES circuit (151) is illustrated. Through the TSV (141), a signal may be transmitted between the first SERDES circuit (131) and the second SERDES circuit (151) to indicate a state of another circuit and / or an interrupt. The signal may be transmitted at a relatively slow data rate (e.g., a data rate within a data rate range of 300 kbps to 5 Mbps, or a data rate below the data rate range). From the perspective of supporting relatively slow speeds, an interface established based on TSV (141) may be referred to as low-speed IO (low-speed input / output). In order to transmit a signal through a single TSV (141), the first SERDES circuit (131) and / or the second SERDES circuit (151) may transmit the signal based on a 1-wired protocol such as a BMC (bi-phase mark coding) method.

[0094] In one embodiment, a signal path usable by all circuits included in the first circuit layer (130) and the second circuit layer (150) may be established based on the first SERDES circuit (131) and the second SERDES circuit (151) connected to both ends of the TSV (141). The embodiment is not limited thereto, and the interconnect layer (140) of the processor (110) may include one or more signal paths dedicated to a pair of circuits disposed in each of the first circuit layer (130) and the second circuit layer (150).

[0095] Referring to FIG. 3A, a TSV (330) for electrical connection between a CPU (310) and a LP-DDR PHY (320) may be formed in the interconnect layer (140). For high-speed communication between the CPU (310) and the LP-DDR PHY (320), a plurality of TSVs including the TSV (330) may be formed. The high-speed communication may include peripheral component interconnect bus express (PCIe), universal serial bus (USB), mobile industry processor interface (MIPI), Marconi, universal flash storage (UFS), memory interface (MIF), inter-integrated circuit (I2C), and / or improved inter-integrated circuit (I3C). For the high-speed communication, a differential interface based on a plurality of TSVs (or signal paths) may be formed between circuits. For the above high-speed communication, any one of the plurality of TSVs can be used for transmitting a clock signal.

[0096] Referring to FIG. 3A, a signal path between a first circuit (e.g., CPU (310)) of a first circuit layer (130) and a second circuit (e.g., LP-DDR PHY (320)) of a second circuit layer (150) can be divided into a first signal path that directly connects the first circuit and the second circuit, and a second signal path that indirectly connects the first circuit and the second circuit based on a SERDES circuit. The TSV (330) can correspond to at least a part of the first signal path. The TSV (141), the first SERDES circuit (131), and / or the second SERDES circuit (151) can correspond to at least a part of the second signal path.

[0097] In one embodiment, the circuits directly and indirectly connected via the first signal path and the second signal path can selectively utilize any one of the signal paths based on the purpose, data rate, and / or content of the signal. For example, the first signal path including the TSV (330) can be utilized for transmitting a data signal (e.g., a signal including data to be transmitted to a volatile memory via the LP-DDR PHY (320). For example, the second signal path including the TSV (141) can be utilized for transmitting a control signal (e.g., a signal generated by the CPU (310) to control the state of the LP-DDR PHY (320).

[0098] Referring to FIG. 3B, an exemplary block diagram for explaining a first signal path and a second signal path formed by TSVs (141, 330) is illustrated. For transmission of a data signal based on the TSV (330), data signal terminals included in the CPU (310) and / or the LP-DDR PHY (320) may be directly connected through the TSV (330). For transmission of a control signal based on the TSV (141), one or more control signal terminals for transmission of a control signal to be transmitted to the LP-DDR PHY (320) among the terminals of the CPU (310) may be connected to one or more pins (P11, P12) of the first SERDES circuit (131). For example, the one or more control signal terminals may be connected to the TSV (141) through the first SERDES circuit (131). For example, a first control signal terminal for transmitting a signal related to an interrupt may be connected to a pin (P11) of the first SERDES circuit (131). For example, a second control signal terminal for transmitting a signal for controlling the state of the LP-DDR PHY (320), such as a reset, may be connected to a pin (P12) of the first SERDES circuit (131). The embodiment is not limited thereto.

[0099] In one embodiment of FIG. 3B, the CPU (310) can transmit a first type of signal for transmitting data to the LP-DDR PHY (320) through the TSV (330). For example, a data signal including data to be stored in a memory connected to the processor (110) can be transmitted from the CPU (310) to the LP-DDR PHY (320) through the TSV (330). The first type of signal can be transmitted at a speed within a first data-rate range within the TSV (330) that exclusively connects the CPU (310) and the LP-DDR PHY (320).

[0100] In one embodiment of FIG. 3B, the CPU (310) may transmit a second type of signal for controlling a controller of the LP-DDR PHY (320) to the first SERDES circuit (131) via one of the pins (P11, P12). For example, a control signal for controlling a state of the LP-DDR PHY (320) or for controlling the execution of a specific function (e.g., a function of transmitting data included in a first type of signal to a memory) and / or an operation (or computation) of the LP-DDR PHY (320) may be transmitted from the CPU (310) to the first SERDES circuit (131). For example, a control signal for transmitting data provided to the LP-DDR PHY (320) to a memory via a TSV (330) may be transmitted from the CPU (310) to the first SERDES circuit (131).

[0101] In one embodiment of FIG. 3B, the CPU (310) may include a plurality of sub-circuits. Each of the plurality of sub-circuits may correspond to different pins (P11, P12) and / or different TSVs (141, 330). For example, the plurality of sub-circuits of the CPU (310) may include a first sub-circuit connected to a first SERDES circuit (131) to transmit a second type of signal to the TSV (141) through the first SERDES circuit (131). The first sub-circuit of the CPU (310) may be connected to the first SERDES circuit (131) via at least one of the pins (P11, P12). The first sub-circuit of the CPU (310) may include a memory address register (MAR) and / or a control circuit within the CPU (310) to transmit a control signal corresponding to the LP-DDR PHY (320). The plurality of sub-circuits of the CPU (310) may include a second sub-circuit connected to the TSV (330) for transmitting a first type of signal. The second sub-circuit of the CPU (310) may include a memory buffer register (MBR) and / or a cache memory (e.g., L1, L2 and / or L3 cache memory) as a sub-circuit for transmitting a data signal to be input to the LP-DDR PHY (320).

[0102] In one embodiment, similar to the CPU (310) including sub-circuits configured to directly and / or indirectly connect to different TSVs (e.g., indirectly through the first SERDES circuit (131) and / or the second SERDES circuit (151), each circuit included in the processor (110) (e.g., the GPU (312), the SCI / LLC, the Signal I / F, the HSI, the M / M, the NPU, the LP-DDR PHY (320), the NOC, the display controller, the ISP (324), and / or the MODEM) may include a sub-circuit corresponding to at least one of the TSVs in the interconnect layer (140), such as the TSV (141). For example, the GPU (312) may include sub-circuits corresponding to each of a plurality of TSVs that are directly and / or indirectly connected to the GPU (312), including the TSV (141). The circuit within the processor (110) may include sub-circuits corresponding to each of the TSVs used by the circuit. The embodiment is not limited thereto, and the number of sub-circuits included in the circuit within the processor (110) may exceed or be smaller than the number of TSVs used by the circuit.

[0103] As described above with reference to FIG. 2, the first SERDES circuit (131) can modulate and / or serialize signals transmitted from circuits of the first circuit layer (130) including the CPU (310). For example, by serializing control signals transmitted from the circuits, the first SERDES circuit (131) can obtain a signal including a sequence of bits included in the control signals. The first SERDES circuit (131) can transmit the obtained signal through the TSV (141). In one embodiment where the circuits independently transmit control signals, the first SERDES circuit (131) can transmit the control signals transmitted at different timings to the second SERDES circuit (151) based on a designated cycle. Within the TSV (141), a signal generated based on serialization of the first SERDES circuit (131) or the second SERDES circuit (151) can be transmitted at a speed of a second data-rate range below the first data-rate range.

[0104] In one embodiment of FIG. 3B, a second SERDES circuit (151), which receives a signal based on serialization of a first SERDES circuit (131) through a TSV (141), may perform deserialization to divide a plurality of bits included in the signal. The second SERDES circuit (151) may assign the plurality of bits to pins of the second SERDES circuit (151) based on a relationship between pins of the first SERDES circuit (131) and pins of the second SERDES circuit (151). For example, control signal terminals of an LP-DDR PHY (320), which are targets of control signals transmitted to pins (P11, P12), may be connected to pins (P21, P22) corresponding to pins (P11, P12) of the first SERDES circuit (131), respectively. The LP-DDR PHY (320) can receive one or more bits transmitted from the CPU (310) to the pins (P11, P12) via the pins (P21, P22). The LP-DDR PHY (320) can perform an operation (e.g., an operation of transmitting data received via the TSV (330) to a volatile memory connected to the processor (110)) indicated by the one or more bits received via the pins (P21, P22).

[0105] As described above, a signal transmitted from the first SERDES circuit (131) through the TSV (141) may include one or more bits provided by circuits of the first circuit layer (130) including the CPU (310). For example, the signal may include a sequence of the one or more bits based on serialization.

[0106] Referring to FIG. 3B, an embodiment in which a data signal and / or a control signal is transmitted from a CPU (310) to an LP-DDR PHY (320) is described, but the embodiment is not limited thereto. For example, the LP-DDR PHY (320) may transmit data transmitted from a memory to the CPU (310) through a TSV (330). The LP-DDR PHY (320) may transmit a signal for notifying the status of the LP-DDR PHY (320) and / or an interrupt generated in the LP-DDR PHY (320) to the second SERDES circuit (151) through pins (P21, P22). The second SERDES circuit (151) can obtain or generate a signal to be transmitted to the first SERDES circuit (131) through the TSV (141) by merging (e.g., serializing) the signal with other signals transmitted from other circuits of the second circuit layer (150). The first SERDES circuit (131), which receives the signal generated by the second SERDES circuit (151) through the TSV (141), can obtain, based on deserialization, at least one bit to be transmitted to the CPU (310) through the pins (P11, P12) from among the bits included in the signal.

[0107] Referring to FIG. 3C, an exemplary block diagram is shown for explaining a plurality of signal paths formed by TSVs (141, 332, 334). A first circuit layer (130) (or first die) including circuits such as a CPU (310) and / or a GPU (312) may include a first SERDES circuit (131) connected to the CPU (310) and the GPU (312). A second circuit layer (150) (or second die) including circuits such as a display controller (322) and / or an ISP (324) may include a second SERDES circuit (151) connected to the display controller (322) and the ISP (324).

[0108] Referring to FIG. 3c, within the first circuit layer (130), the CPU (310) may be connected to the first SERDES circuit (131) via signal terminals (P11, P12), and the GPU (312) may be connected to the second SERDES circuit (131) via signal terminals (P13, P14). Within the second circuit layer (150), the display controller (322) may be connected to the second SERDES circuit (151) via signal terminals (P21, P22), and the ISP (324) may be connected to the second SERDES circuit (151) via signal terminals (P23, P24). Based on the serialization and / or deserialization (or modulation and / or demodulation) of the first SERDES circuit (131) and / or the second SERDES circuit (151), a plurality of signal paths may be integrated within the TSV (141). The plurality of signal paths may include a first signal path between the CPU (310) and the display controller (322), a second signal path between the CPU (310) and the ISP (324), a third signal path between the GPU (312) and the display controller (322), and a fourth signal path between the GPU (312) and the ISP (324). The first signal path may include signal terminals (P11, P21). The second signal path may include signal terminals (P12, P22). The third signal path may include signal terminals (P13, P23). The fourth signal path may include signal terminals (P14, P24).

[0109] Referring to FIG. 3c, the interconnect layer (140) may further include other TSVs (e.g., TSVs (332, 334)) for directly connecting the circuit of the first circuit layer (130) and the circuit of the second circuit layer (150), as well as TSVs (141) for providing the first to fourth signal paths. For example, the interconnect layer (140) may include a TSV (332) for connecting the CPU (310) and the display controller (322). The interconnect layer (140) may include a TSV (334) for connecting the GPU (312) and the ISP (324). The embodiment is not limited thereto, and TSVs connecting the CPU (310) and the ISP (324) and / or TSVs connecting the GPU (312) and the display controller (322) may be additionally formed within the interconnect layer (140).

[0110] In one embodiment, the plurality of sub-circuits included in the CPU (310) may include a first sub-circuit corresponding to the TSV (141) and / or the first SERDES circuit (131) (e.g., a first sub-circuit connected to at least one of the pins (P11, P12)) and / or a second sub-circuit connected to the TSV (332) to communicate with the display controller (322). The GPU (312) may include a third sub-circuit corresponding to the TSV (141) and / or the first SERDES circuit (131) (e.g., a third sub-circuit connected to at least one of the pins (P13, P14)) and / or a fourth sub-circuit connected to the TSV (334) to communicate with the ISP (324). The display controller (322) may include a fifth sub-circuit corresponding to the TSV (141) and / or the second SERDES circuit (151) (e.g., the fifth sub-circuit connected to the second SERDES circuit (151) via at least one of the pins (P21, P22)) and / or a sixth sub-circuit connected to the TSV (332) to communicate with the CPU (310). The ISP (324) may include a seventh sub-circuit corresponding to the TSV (141) and / or the second SERDES circuit (151) (e.g., the seventh sub-circuit connected to the second SERDES circuit (151) via at least one of the pins (P23, P24)) and / or an eighth sub-circuit connected to the TSV (334) to communicate with the GPU (312).

[0111] In one embodiment, the first to fourth signal paths may be used to transmit a control signal for controlling a function and / or operation of a circuit, a status signal for indicating a status of the circuit, and / or an interrupt signal for indicating an interrupt. The CPU (310) may transmit a first type of signal including the control signal, the status signal, and / or the interrupt signal to the display controller (322) and / or the ISP (324) via the TSV (141). For example, the CPU (310) may transmit a first signal of the first type related to the display controller (322) to the first SERDES circuit (131) via the signal terminal (P11). The CPU (310) may transmit a second signal of the first type related to the ISP (324) to the first SERDES circuit (131) via the signal terminal (P12). In the above example, the first SERDES circuit (131) can generate a third signal to be transmitted to the second SERDES circuit (151) through the TSV (141) based on the serialization of the first signal and the second signal. The first SERDES circuit (131) can transmit the third signal to the TSV (141).

[0112] In one embodiment where the third signal is transmitted through the TSV (141), the second SERDES circuit (151) can obtain the first signal and the second signal based on deserialization of the third signal, based on receiving the third signal through the TSV (141). The second SERDES circuit (151) can transmit the obtained first signal to the display controller (322) through the signal terminal (P21). The second SERDES circuit (151) can transmit the obtained second signal to the ISP (324) through the signal terminal (P22). Similarly, the GPU (312) can transmit the first type of signal to the display controller (322) using the signal terminal (P13) and can transmit the second type of signal to the ISP (324) using the signal terminal (P14).

[0113] In one embodiment, the TSVs (332, 334) that are different from the TSV (141) in which the first signal path to the third signal path are integrated may be used for transmitting data and / or information between circuits. For example, the CPU (310) may transmit information including an image and / or video to be displayed on a display to the display controller (322) via the TSV (332). In the example, the CPU (310) may transmit a first type of signal requesting the display controller (322) to output the information to the display using the TSV (141). The GPU (312) may receive information including an image and / or video (e.g., an image and / or video acquired by a camera) from the ISP (324) via the TSV (334). Within the above example, the GPU (312) may transmit a first type of signal requesting transmission of the information to the ISP (324) using the TSV (141).

[0114] Although an embodiment in which a circuit of the first circuit layer (130) transmits a signal to a circuit of the second circuit layer (150) has been described, the embodiment is not limited thereto. For example, the display controller (322) may transmit a first type of signal to the CPU (310) and / or the GPU (312) using each of the signal terminals (P21, P22) to notify the status of the display controller (322) and / or an interrupt generated in the display controller (322). Similarly, the ISP (324) may transmit a first type of signal to the CPU (310) and / or the GPU (312) to notify the status of the ISP (324) and / or an interrupt generated in the ISP (324) using the signal terminals (P23, P24). Signals received through signal terminals (P21, P22) may be modulated or serialized by a second SERDES circuit (151). The signals serialized by the second SERDES circuit (151) may be transmitted to a first SERDES circuit (131) through a TSV (141). The first SERDES circuit (131) may obtain or generate signals to be output to the CPU (310) and the GPU (312) through each of the signal terminals (P11, P12, P13, P14) based on deserialization of the signals received through the TSV (141).

[0115] Although one embodiment of a processor (110) including a CPU (310), a GPU (312), a display controller (322), and an ISP (324) is described, the embodiment is not limited thereto. For example, other circuits such as an LP-DDR PHY (320) and / or an NPU of the second circuit layer (150) may also be connected to the second SERDES circuit (151) to utilize a signal path based on TSV (141). For example, other circuits of the first circuit layer (130) different from the CPU (310) and / or GPU (312) may also be connected to the first SERDES circuit (131) to utilize a signal path based on TSV (141).

[0116] As described above with reference to FIGS. 3A to 3C, different circuits within the processor (110) including the CPU (310) and / or the LP-DDR PHY (320) may utilize an interface structure formed by the first SERDES circuit (131), the TSV (141), and the second SERDES circuit (151). Through the interface structure, states of the circuits of the first circuit layer (130) may be transmitted to circuits of the second circuit layer (150). Through the interface structure, states of the circuits of the second circuit layer (150) may be transmitted to circuits of the first circuit layer (130) and / or broadcast.

[0117] In one embodiment, to manage power consumption, the states of circuits within the processor (110) may be adaptively controlled. For example, the CPU (310) may adjust the states of the circuits, including the state of the CPU (310), based on the execution of instructions. For example, the power states of the circuits may include a sleep state (or low-voltage state, low-power state, disabled or deactivated state) that receives a power signal having a voltage below a specified voltage (e.g., a voltage within a range including 0 V). The states of the circuits may include a wake-up state (or enabled or activated state) that receives a power signal having a voltage above the specified voltage.

[0118] In one embodiment, to support transmission of signals between circuits independently of the state of the CPU (310) (e.g., the sleep state and / or wake-up state), the state of the first SERDES circuit (131) and / or the second SERDES circuit (151) may be switched or maintained independently of the state of the CPU (310). For example, the power state of at least one of the first SERDES circuit (131) and the second SERDES circuit (151) may be controlled independently of the power state of the CPU (310). For example, while the state of the CPU (310) corresponds to a low-power state, the state of the first SERDES circuit (131) and / or the second SERDES circuit (151) may be maintained in a wake-up state. Based on the wake-up state, the first SERDES circuit (131) and / or the second SERDES circuit (151) can perform transmission and / or reception of a signal based on the TSV (141). While the state of the CPU (310) corresponds to a low-power state, the first SERDES circuit (131) and the second SERDES circuit (151) can perform or control communication based on the TSV (141) independently of the CPU (310).

[0119] In one embodiment, communication based on TSV (141) may be controlled by a CPU (310) and / or a controller of SERDES circuits (e.g., controllers (211, 221)). While the state of CPU (310) corresponds to a wake-up state, CPU (310) may control communication in TSV (141). For example, by CPU (310) in wake-up state, a first timing for transmitting a signal from the first SERDES circuit (131) to the second SERDES circuit (151) and a second timing for transmitting a signal from the second SERDES circuit (151) to the first SERDES circuit (131) may be separated in a time domain. The embodiment is not limited thereto, and any one of controllers (211, 221) may act as a host for controlling the first timing and the second timing. For example, after the CPU (310) switches to a sleep state, any one of the controllers (211, 221) may operate as the host. In one embodiment, communication in the TSV (141) may be controlled by the CPU (310) and / or the controllers (211, 221) operating based on a link training & status state machine (LTSSM).

[0120] In one embodiment of periodically transmitting the states of the circuits through the TSV (141), the states of the first SERDES circuit (131) and the second SERDES circuit (151) may be periodically switched between a wake-up state and a sleep state. For example, the controllers (211, 221) may be periodically switched between the wake-up state and the sleep state based on a specified period (e.g., about 5 ms).

[0121] As described above, for example, to improve the yield of the processor (110), signal paths for specific purposes (e.g., signal paths for transmitting status and / or interrupts) may be integrated into a single TSV (141). For example, based on an interface structure based on the TSV (141), the first circuit (131), and the second circuit (151), the number of TSVs required to form the signal paths may be reduced. Since the number of TSVs is reduced, the difficulty and / or complexity of the process for forming the TSV may be reduced, and the yield of the processor (110) may be improved.

[0122] According to one embodiment, the processor (110) may be designed considering the yield of the TSV (141) for connecting the first SERDES circuit (131) and the second SERDES circuit (151). Hereinafter, with reference to FIG. 4, an exemplary structure of the interconnect layer (140) is described in relation to the yield of a single TSV (141) formed between the first SERDES circuit (131) and the second SERDES circuit (151).

[0123] FIG. 4 illustrates an exemplary structure of an interconnect layer (140) included in a processor (110), according to one embodiment. At least a portion of the processor (110) illustrated in FIG. 4 may correspond to at least a portion of the processor (110) of FIGS. 1, 2, and / or 3A-3C, and features described above with respect to the processor (110) of FIGS. 1, 2, and / or 3A-3C may be included in the processor (110) of FIG. 4, even if not illustrated or specifically described below.

[0124] Referring to FIG. 4, a second circuit layer (150), an interconnect layer (140), and a first circuit layer (130) are sequentially stacked along the z-axis direction within a processor (110). A TSV (141) based on a serial communication protocol such as a BMC method may be formed between the first SERDES circuit (131) and the second SERDES circuit (151). In one embodiment, the processor (110) may include an interface structure that is robust to failures of TSVs.

[0125] Referring to FIG. 4, the interconnect layer (140) may include at least two TSVs (141, 410) positioned between a first SERDES circuit (131) and a second SERDES circuit (151). The TSVs (141, 410) may be designed to have substantially the same characteristics (e.g., dimensions, material filling the TSV, and / or process). In one embodiment where the two TSVs (141, 410) are formed between the first SERDES circuit (131) and the second SERDES circuit (151), the first circuit layer (130) may include a first switching circuit (421) for connecting either of the TSVs (141, 410) to the first SERDES circuit (131). In the above embodiment, the second circuit layer (150) may include a second switching circuit (422) for connecting one of the TSVs (141, 410) to the second SERDES circuit (151). By the first switching circuit (421) and / or the second switching circuit (422), one of the TSVs (141, 410) may be electrically isolated from the first SERDES circuit (131) and the second SERDES circuit (151).

[0126] In one embodiment of FIG. 4, one end of the TSV (141) may be connected to the first SERDES circuit (131) through the first switching circuit (421), and the other end of the TSV (141) may be connected to the second SERDES circuit (151) through the second switching circuit (422). Since the TSV (141) is electrically connected to the first SERDES circuit (131) and the second SERDES circuit (151) by the first switching circuit (421) and the second switching circuit (422), the TSV (410) may be electrically isolated from the first SERDES circuit (131) and the second SERDES circuit (151). During the production process of the processor (110), a TSV (410) determined to be defective among the TSVs (141, 410) may be disconnected from the first SERDES circuit (131) and the second SERDES circuit (151).

[0127] In one embodiment of FIG. 4, a TSV (141) electrically connected to the first SERDES circuit (131) and the second SERDES circuit (151) may be referred to as a main TSV, a normal TSV, and / or a default TSV. In one embodiment of FIG. 4, a TSV (410) electrically disconnected from the first SERDES circuit (131) and the second SERDES circuit (151) may be referred to as a sub TSV, a redundant TSV, an auxiliary TSV, and / or an alternative (reserve or substitute) TSV. The embodiment is not limited thereto, and the TSV (410) may be formed within the interconnect layer (140) to establish an electrical connection based on a defect in the main TSV (e.g., the TSV (141)).

[0128] In one embodiment, the connection of the TSVs (141, 410) by the first switching circuit (421) and the second switching circuit (422) may be dynamically changed according to the characteristics of each of the TSVs (141, 410). For example, if the TSV (141) connected to the first SERDES circuit (131) and the second SERDES circuit (151) is damaged, the TSV (410) may be connected to the first SERDES circuit (131) and the second SERDES circuit (151) instead of the TSV (141). For example, based on the characteristics (e.g., type and / or speed) of the protocol used between the first SERDES circuit (131) and the second SERDES circuit (151) and / or the characteristics of the signal transmitted between the first SERDES circuit (131) and the second SERDES circuit (151), any one of the TSVs (141, 410) may be connected to the first SERDES circuit (131) and the second SERDES circuit (151). For example, when transmitting a signal based on the BMC method, the TSVs connected to the first SERDES circuit (131) and the second SERDES circuit (151) may be different from the TSVs connected to the first SERDES circuit (131) and the second SERDES circuit (151) when transmitting a signal based on a protocol (e.g., MIPI protocol) of a speed higher than the BMC method. Within the above example, any one of the TSVs (141, 410) may be selected based on different characteristics (e.g., interference characteristics and / or high frequency characteristics) of the TSVs (141, 410).

[0129] The connection between the TSVs (141, 410) and the SERDES circuit as exemplified above can be controlled by the first switching circuit (421) and the second switching circuit (422). The first switching circuit (421) and / or the second switching circuit (422) can include a controller for controlling the connection. The embodiment is not limited thereto, and the first switching circuit (421) and / or the second switching circuit (422) can be controlled by the controllers (211, 221) and / or the CPU (e.g., the CPU (310) of FIG. 3A).

[0130] In one embodiment including a plurality of TSVs (141, 410), the first SERDES circuit (131) and the second SERDES circuit (151) can transmit a single signal using all of the plurality of TSVs (141, 410). For example, a signal transmitted from the first SERDES circuit (131) can be propagated substantially simultaneously within the plurality of TSVs (141, 410). The second SERDES circuit (151) can compare or combine signals simultaneously received through the TSVs (141, 410) to eliminate an error generated in any one of the TSVs (141, 410).

[0131] In one embodiment including a plurality of TSVs (141, 410), the first SERDES circuit (131) and the second SERDES circuit (151) may use at least one first TSV (141) among the plurality of TSVs (141, 410) to transmit a signal from the first SERDES circuit to the second SERDES circuit, and may use the second TSV (410) to transmit a signal from the second SERDES circuit to the first SERDES circuit. According to one embodiment, transmission and reception of signals may be performed substantially simultaneously within the TSVs (141, 410).

[0132] As described above, according to one embodiment, the processor (110) may have an interface structure that is robust to the yield of TSV and / or errors occurring in TSV.

[0133] In one embodiment, the first SERDES circuit (131) and the second SERDES circuit (151) can support communication based on multiple protocols including the BMC method. Hereinafter, with reference to FIG. 5, an exemplary structure of a processor (110) including an interface structure supporting communication based on multiple protocols is described.

[0134] FIG. 5 illustrates an exemplary structure of an interconnect layer (140) for supporting multiple wired communication protocols. At least a portion of the processor (110) illustrated in FIG. 5 may correspond to at least a portion of the processor (110) of FIGS. 1, 2, 3A to 3C, and / or 4, and features described above with respect to the processor (110) of FIGS. 1, 2, 3A to 3C, and / or 4 may be included in the processor (110) of FIG. 5, even if not illustrated or specifically described below.

[0135] Referring to FIG. 5, at least a portion of a second circuit layer (150), an interconnect layer (140), and a first circuit layer (130) sequentially stacked along the z-axis direction within a processor (110) is illustrated. A first SERDES circuit (131) of the first circuit layer (130) may include pins (p11, p12, p13, p14, …, p1k) for connecting with circuits included in the first integrated circuit layer (130). A second SERDES circuit (151) of the second circuit layer (150) may include pins (p21, p22, p23, p24, …, p2k) for connecting with circuits included in the second circuit layer (150). In order to transmit bits obtained through the above-described pins, one or more TSVs may be formed between the first SERDES circuit (131) and the second SERDES circuit (151).

[0136] Referring to FIG. 5, in one embodiment including a plurality of TSVs (531, 532, 533, 534) formed in the interconnect layer (140), transmission of signals based on a plurality of protocols (e.g., serial communication protocols) may be supported between the first SERDES circuit (131) and the second SERDES circuit (151). For example, a high-speed communication protocol requiring a dedicated signal path for transmission of a clock signal (e.g., USB including PCIe, MIPI, and / or USB 3.2) may be supported by the plurality of TSVs (531, 532, 533, 534) and the first SERDES circuit (131) and the second SERDES circuit (151) connected to the plurality of TSVs (531, 532, 533, 534). Referring to FIG. 5, an interface structure based on four TSVs (531, 532, 533, 534) is exemplarily illustrated, but the embodiment is not limited thereto.

[0137] In one embodiment, the first SERDES circuit (131) may include circuitry for supporting different high-speed communication protocols. For example, the first SERDES circuit (131) may include a PCIe circuit (511) for transmitting and / or receiving a signal based on PCIe, a MIPI circuit (512) for transmitting and / or receiving a signal based on MIPI, and a USB circuit (513) for transmitting and / or receiving a signal based on USB. To support the high-speed communication protocols, the second SERDES circuit (132) may also include a PCIe circuit (521), a MIPI circuit (522), and a USB circuit (523). Although the first SERDES circuit (131) and / or the second SERDES circuit (151) are illustratively shown as including circuits for supporting three high-speed communication protocols (e.g., PCIe, MIPI, and / or USB), the embodiment is not limited thereto.

[0138] In one embodiment, the first SERDES circuit (131) may include a first multiplexer switching circuit (514) for selecting a protocol. Similarly, the second SERDES circuit (151) may also include a second multiplexer switching circuit (524) for selecting a protocol. During a first time interval for transmitting a USB-based signal, terminals of the USB circuit (513) and a plurality of TSVs (531, 532, 533, 534) may be connected within the first SERDES circuit (131) by the first multiplexer switching circuit (514). During the first time interval, terminals of the USB circuit (523) and a plurality of TSVs (531, 532, 533, 534) may be connected within the second SERDES circuit (151) by the second multiplexer switching circuit (524).

[0139] In one embodiment, during a second time interval for transmitting a signal based on PCIe, terminals of a PCIe circuit (511) and a plurality of TSVs (531, 532, 533, 534) may be connected by a first multiplexer switching circuit (514) within a first SERDES circuit (131). During the second time interval, terminals of a PCIe circuit (521) and a plurality of TSVs (531, 532, 533, 534) may be connected by a second multiplexer switching circuit (524) within a second SERDES circuit (151). During the second time interval, the plurality of TSVs (531, 532, 533, 534) may be matched to respective signal paths defined by PCIe.

[0140] Similarly, within a third time interval for transmitting a signal based on MIPI, electrical connections between MIPI circuits (512, 522) based on a plurality of TSVs (531, 532, 533, 534) can be established by the first multiplexer switching circuit (514) and the second multiplexer switching circuit (524). A protocol corresponding to a signal to be transmitted through the plurality of TSVs (531, 532, 533, 534) can be determined based on a speed (e.g., data rate) required for transmitting the signal, and a size of information and / or data included in the signal. The determination of the above protocol may be performed by a controller of the first SERDES circuit (131) and / or the second SERDES circuit (151) (e.g., controllers (211, 221) of FIG. 2) and / or another circuit within the processor (110) (e.g., CPU (310) of FIG. 3a).

[0141] As described above, according to one embodiment, the processor (110) may include an interface structure (e.g., an interface structure including a first SERDES circuit (131), a second SERDES circuit (151), and TSVs (e.g., TSVs (531, 532, 533, 534)) for supporting a plurality of communication protocols. Based on the interface structure, the processor (110) may select an appropriate interface protocol.

[0142] Below, with reference to FIG. 6, an exemplary operation of a processor (110) supporting single TSV communication based on the BMC method is described.

[0143] FIG. 6 is an exemplary timing diagram (600) for an electrical signal transmitted in an interconnect layer based on a BMC (bi-phase mark coding) scheme. The BMC scheme described with reference to FIG. 6 can be used for transmitting a signal in an interconnect layer (e.g., an interconnect layer (140) of FIGS. 1 to 5) within an interface structure (e.g., an interface structure including a first SERDES circuit (131), a second SERDES circuit (151), and a TSV (141)) included in a processor (110) of FIGS. 1 to 5.

[0144] In one embodiment, a first SERDES circuit of a first circuit layer (e.g., the first circuit layer (130) of FIGS. 1 to 5) may encode a signal obtained based on serialization based on a BMC scheme. The first SERDES circuit may transmit the encoded signal to a second SERDES circuit of a second circuit layer (e.g., the second circuit layer (150) of FIGS. 1 to 5) through a TSV.

[0145] In one embodiment, the BMC scheme may be used for communication (e.g., 1-wire power delivery (PD) communication) at the CC (Configuration Channel) terminal of a USB Type-C. The BMC scheme may be referred to as a differential Manchester encoding scheme. At the CC terminal, ID and / or power profile information may be transmitted or received based on the BMC scheme. Referring to FIG. 6, an exemplary timing diagram (600) related to electrical signals transmitted through TSVs (e.g., TSVs (141) of FIGS. 1 to 4) of an interconnect layer based on the BMC scheme is illustrated.

[0146] Referring to FIG. 6, within a timing diagram (600), graphs (610, 620, 630) are depicted along an equivalent time domain. Graph (610) depicts a clock signal associated with an electrical signal to be transmitted through the TSV. Graph (620) depicts a plurality of bits to be included in the electrical signal to be transmitted through the TSV. The plurality of bits may be serialized by a SERDES circuit. For example, the plurality of bits may be provided from different circuits connected to the SERDES circuit to indicate a status and / or an interrupt. Referring to graph (620) of FIG. 6, in one embodiment of transmitting from the most significant bit (MSB) in the sequence of serialized bits, the sequence of bits serialized by the SERDES circuit is 10011010010 (2) may include. Graph (630) may represent the final sequence of bits included in a signal transmitted to the TSV by the SERDES circuit.

[0147] According to one embodiment, a SERDES circuit can transmit both a clock signal and data (e.g., a sequence of bits) through a single signal path (e.g., TSV (141) of FIGS. 1 to 4) based on a BMC scheme. Based on the BMC scheme, bits to be included in the final sequence can be determined or changed based on bits represented by the graph (620) at each of a rising edge and a falling edge of the clock signal represented by the graph (610). Based on the BMC scheme, within a time interval (e.g., t1, t4, t5, t7, and / or t10) encoding a bit (1) within the sequence, the voltage level of the signal transmitted to the TSV can be changed. Within a visual guide (e.g., t2, t3, t6, t8, and / or t9) encoding a bit (0) within the sequence, the voltage level of the signal transmitted to the TSV can be maintained.

[0148] In one embodiment, a SERDES circuit that receives a signal of a voltage level such as graph (630) through a TSV can obtain a sequence of clocks and bits from the signal based on the characteristics of the BMC method. For example, within time intervals (t1, t4, t5, t7, and / or t10) in which the voltage level changes, the SERDES circuit can determine that a bit (1) is encoded. For example, within time intervals (t2, t3, t6, t8, and / or t9) in which the voltage level is maintained, the SERDES circuit can determine that a bit (0) is received. A SERDES circuit that identifies a sequence of bits represented by graph (620) from a signal based on graph (630) can obtain one bit (a bit) to be output to each of a plurality of pins of the SERDES circuit by dividing the bits based on deserialization.

[0149] Although an exemplary operation of a SERDES circuit for analyzing a signal transmitted through a single TSV based on the BMC scheme has been described, the embodiment is not limited thereto. As described above with reference to FIGS. 1 to 5, the SERDES circuit can transmit or analyze a signal based on a protocol having a data rate exceeding the data rate supported by the BMC scheme, such as I2C, I3C, USB (e.g., USB 3.2), PCIe, MIPI (D-PHY, C-PHY, M-PHY), DP (display port), LPDDR4~6, and / or UFS. To support high-speed protocols, multiple TSVs can be formed between SERDES circuits arranged in different circuit layers.

[0150] As described above, an electronic device including an AP having a structure in which a plurality of circuit layers are stacked is provided. Within the AP, an interconnection layer including signal paths (e.g., signal paths based on TSVs) between the plurality of circuit layers may be formed. In order to reduce the number of TSVs included in the interconnection layer, an integrated signal transmission interface based on SERDES circuits may be formed in each of the circuit layers disposed above and below the interconnection layer. Each of the SERDES circuits may perform serialization on bits of circuits included in a corresponding circuit layer (e.g., bits representing numerical values ​​for indicating states and / or interrupts of the circuits). A signal based on the serialization may be transmitted from a specific circuit layer to another circuit layer through at least one TSV of the interconnection layer. Each of the SERDES circuits may, in response to a signal received through the TSV, perform deserialization on bits included in the signal. Signals and / or bits obtained based on the above deserialization can be assigned to other circuits connected to the SERDES circuit that performed the deserialization.

[0151] Hereinafter, with reference to FIG. 7, an embodiment of the AP and / or electronic device described with reference to FIGS. 1 to 6 is described.

[0152] FIG. 7 is a block diagram of an electronic device (701) within a network environment (700) according to various embodiments. Referring to FIG. 7, in the network environment (700), the electronic device (701) may communicate with the electronic device (702) via a first network (798) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (704) or the server (708) via a second network (799) (e.g., a long-range wireless communication network). In one embodiment, the electronic device (701) may communicate with the electronic device (704) via the server (708). According to one embodiment, the electronic device (701) may include a processor (720), a memory (730), an input module (750), an audio output module (755), a display module (760), an audio module (770), a sensor module (776), an interface (777), a connection terminal (778), a haptic module (779), a camera module (780), a power management module (788), a battery (789), a communication module (790), a subscriber identification module (796), or an antenna module (797). In some embodiments, the electronic device (701) may omit at least one of these components (e.g., the connection terminal (778)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (776), the camera module (780), or the antenna module (797)) may be integrated into one component (e.g., the display module (760)).

[0153] The processor (720) may, for example, execute software (e.g., a program (740)) to control at least one other component (e.g., a hardware or software component) of the electronic device (701) connected to the processor (720) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (720) may store commands or data received from other components (e.g., a sensor module (776) or a communication module (790)) in a volatile memory (732), process the commands or data stored in the volatile memory (732), and store result data in a non-volatile memory (734). According to one embodiment, the processor (720) may include a main processor (721) (e.g., a central processing unit or an application processor) or an auxiliary processor (723) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (721). For example, when the electronic device (701) includes the main processor (721) and the auxiliary processor (723), the auxiliary processor (723) may be configured to use less power than the main processor (721) or to be specialized for a given function. The auxiliary processor (723) may be implemented separately from the main processor (721) or as a part thereof.

[0154] The auxiliary processor (723) may control at least a portion of functions or states associated with at least one component (e.g., a display module (760), a sensor module (776), or a communication module (790)) of the electronic device (701), for example, on behalf of the main processor (721) while the main processor (721) is in an inactive (e.g., sleep) state, or together with the main processor (721) while the main processor (721) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (723) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (780) or a communication module (790)). In one embodiment, the auxiliary processor (723) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (701) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (708)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0155] The memory (730) can store various data used by at least one component (e.g., the processor (720) or the sensor module (776)) of the electronic device (701). The data can include, for example, software (e.g., the program (740)) and input data or output data for commands related thereto. The memory (730) can include a volatile memory (732) or a non-volatile memory (734).

[0156] The program (740) may be stored as software in the memory (730) and may include, for example, an operating system (742), middleware (744), or an application (746).

[0157] The input module (750) can receive commands or data to be used in a component of the electronic device (701) (e.g., a processor (720)) from an external source (e.g., a user) of the electronic device (701). The input module (750) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0158] The audio output module (755) can output audio signals to the outside of the electronic device (701). The audio output module (755) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0159] The display module (760) can visually provide information to an external party (e.g., a user) of the electronic device (701). The display module (760) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (760) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0160] The audio module (770) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (770) can acquire sound through the input module (750), output sound through the sound output module (755), or an external electronic device (e.g., electronic device (702)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (701).

[0161] The sensor module (776) can detect the operating status (e.g., power or temperature) of the electronic device (701) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (776) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0162] The interface (777) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (701) with an external electronic device (e.g., the electronic device (702)). In one embodiment, the interface (777) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0163] The connection terminal (778) may include a connector through which the electronic device (701) may be physically connected to an external electronic device (e.g., the electronic device (702)). In one embodiment, the connection terminal (778) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0164] The haptic module (779) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (779) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0165] The camera module (780) can capture still images and videos. According to one embodiment, the camera module (780) may include one or more lenses, image sensors, image signal processors, or flashes.

[0166] The power management module (788) can manage the power supplied to the electronic device (701). According to one embodiment, the power management module (788) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0167] A battery (789) may power at least one component of the electronic device (701). In one embodiment, the battery (789) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0168] The communication module (790) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (701) and an external electronic device (e.g., electronic device (702), electronic device (704), or server (708)), and the performance of communication through the established communication channel. The communication module (790) may operate independently from the processor (720) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (790) may include a wireless communication module (792) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (794) (e.g., a local area network (LAN) communication module, or a power line communication module). Any of these communication modules may communicate with an external electronic device (704) via a first network (798) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (799) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (792) may use subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (796) to verify or authenticate the electronic device (701) within a communication network such as the first network (798) or the second network (799).

[0169] The wireless communication module (792) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency communications (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (792) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (792) may support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (792) may support various requirements specified in the electronic device (701), an external electronic device (e.g., the electronic device (704)), or a network system (e.g., the second network (799)). According to one embodiment, the wireless communication module (792) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0170] The antenna module (797) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (797) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (797) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (798) or the second network (799), may be selected from the plurality of antennas, for example, by the communication module (790). A signal or power may be transmitted or received between the communication module (790) and the external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (797).

[0171] According to various embodiments, the antenna module (797) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band.

[0172] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0173] According to one embodiment, commands or data may be transmitted or received between the electronic device (701) and an external electronic device (704) via a server (708) connected to a second network (799). Each of the external electronic devices (702 or 704) may be the same or a different type of device as the electronic device (701). According to one embodiment, all or part of the operations executed in the electronic device (701) may be executed in one or more of the external electronic devices (702, 704, or 708). For example, when the electronic device (701) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (701) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (701). The electronic device (701) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (701) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (704) may include an Internet of Things (IoT) device. The server (708) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (704) or the server (708) may be included in the second network (799).The electronic device (701) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0174] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0175] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0176] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0177] Various embodiments of the present document may be implemented as software (e.g., a program (740)) including one or more instructions stored in a storage medium (e.g., an internal memory (736) or an external memory (738)) readable by a machine (e.g., an electronic device (701)). For example, a processor (e.g., a processor (720)) of the machine (e.g., an electronic device (701)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0178] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as a computer program product. The computer program product may be traded between sellers and buyers as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or may be provided through an application store (e.g., Play Store). TM ) or directly between two user devices (e.g., smart phones), online distribution (e.g., downloading or uploading). In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0179] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0180] In one embodiment, a method may be required to integrate signal paths established within an AP. In one embodiment, a method may be required to increase the yield of an AP included in an electronic device. In one embodiment, a method may be required to reliably produce an AP including stacked circuit layers. As described above, according to one embodiment, a three-dimensional integrated circuit (3D-IC) (e.g., processor (110) of FIG. 1) may include a substrate, a first integrated circuit layer (e.g., second circuit layer (150) of FIG. 1) disposed over the substrate and including a plurality of first circuit elements, a second integrated circuit layer (e.g., first circuit layer (130) of FIG. 1) disposed over the first integrated circuit layer and including a plurality of second circuit elements, and an interconnect layer (e.g., interconnect layer (140) of FIG. 1) disposed between the first integrated circuit layer and the second integrated circuit layer and including a plurality of through silicon vias (TSVs) (e.g., TSVs (141, 142) of FIG. 1). The plurality of first circuit elements may include a plurality of first signal terminals (pins) corresponding to a first signal type and at least one second signal terminal corresponding to a second signal type. The plurality of first signal terminals may be connected to a first TSV (e.g., the TSV (141) of FIG. 1) among the plurality of TSVs through a first serializer-deserializer (SERDES) circuit (e.g., the second SERDES circuit (151) of FIG. 1). The plurality of second circuit elements may include a plurality of third signal terminals corresponding to the plurality of first signal terminals and at least one fourth signal terminal corresponding to the at least one second signal terminal. The first TSV may be connected to the plurality of third signal terminals through a second SERDES circuit (e.g., the first SERDES circuit (131) of FIG. 1).In one embodiment, signal paths established within the AP can be integrated. In one embodiment, the yield of the AP included in the electronic device can be increased. In one embodiment, the AP including stacked circuit layers can be reliably produced.

[0181] For example, the plurality of TSVs may include a substitute TSV (e.g., TSV (410) of FIG. 4) that connects between the first SERDES circuit and the second SERDES circuit and is configured to have the characteristics of the first TSV.

[0182] For example, the replacement TSV may be configured to operate based on a connection state based on the first TSV.

[0183] For example, the first signal type may correspond to a control signal, and the second signal type may correspond to a data signal.

[0184] For example, the first TSV and the replacement TSV may be connected to the first SERDES circuit through a first switching circuit (e.g., the second switching circuit (422) of FIG. 4). The first TSV and the replacement TSV may be configured to be connected to the second SERDES circuit through a second switching circuit (e.g., the first switching circuit (421) of FIG. 4).

[0185] For example, the at least one first data signal terminal and the at least one second data signal terminal may be configured to be directly connected through a second TSV among the plurality of TSVs.

[0186] For example, the plurality of first signal terminals may be configured to include a signal terminal related to an interrupt and a signal terminal related to a reset.

[0187] For example, a plurality of control signals corresponding to the plurality of first signal terminals may be generated at different timings. The first SERDES circuit may be configured to transmit the plurality of control signals to the second SERDES circuit based on a specified period.

[0188] For example, the plurality of first circuit elements may be configured to include a modem. The plurality of second circuit elements may be configured to include a central processing unit (CPU) (e.g., CPU (310) of FIGS. 3A to 3C).

[0189] For example, the minimum line width of the first integrated circuit layer may be greater than the minimum line width of the second integrated circuit layer.

[0190] For example, the first SERDES circuit and the second SERDES circuit may be configured to communicate using serial communication of 5 Mbps or less through the first TSV.

[0191] For example, the first SERDES circuit and the second SERDES circuit may be configured to communicate based on a serial communication protocol specified for each of the plurality of first signals among a plurality of serial communication protocols.

[0192] For example, the first TSV may be configured to be selected from among the plurality of TSVs based on the specified serial communication protocol.

[0193] For example, the first SERDES circuit may be configured to remain in a wake-up state while a low voltage power signal is supplied to the first circuit elements.

[0194] For example, the first SERDES circuit may include a controller (e.g., controller (211) of FIG. 2). The controller may be configured to control communication between the first SERDES circuit and the second SERDES circuit based on whether the first circuit elements receive the low voltage power signal.

[0195] According to one embodiment of the present invention, an electronic device (e.g., the electronic device (101) of FIG. 1) as described above may include a display (e.g., the display (123) of FIG. 1), an antenna, a printed circuit board (e.g., the PCB (105) of FIG. 1), a first integrated circuit disposed on the printed circuit board, and a second integrated circuit disposed on the printed circuit board and electrically connected to the first integrated circuit. The second integrated circuit may include a first circuit layer including a plurality of first circuit elements, a second circuit layer disposed over the first circuit layer and including a plurality of second circuit elements, and an interconnection layer disposed between the first circuit layer and the second circuit layer, the interconnection layer including a plurality of through silicon vias (TSVs). The plurality of first circuit elements may include a plurality of first signal terminals corresponding to a first signal type and at least one second signal terminal corresponding to a second signal type. The plurality of first signal terminals may be connected to a first TSV among the plurality of TSVs via a first serializer-deserializer (SERDES) circuit. The plurality of second circuit elements may include a plurality of third control signal terminals corresponding to the plurality of first signal terminals and at least one fourth signal terminal corresponding to the at least one second signal terminal. The first TSV may be connected to the plurality of third control signal terminals via the second SERDES circuit.

[0196] For example, the plurality of TSVs may include a second TSV that connects between the first SERDES circuit and the second SERDES circuit and transmits substantially the same signal as the first TSV.

[0197] For example, the at least one second signal terminal and the at least one fourth signal terminal may be directly connected through a third TSV among the plurality of TSVs.

[0198] According to one embodiment, as described above, an integrated circuit may include a first integrated circuit layer including a plurality of first circuit elements corresponding to a first minimum circuit feature size, a second integrated circuit layer disposed over the first integrated circuit layer and including a plurality of second circuit elements corresponding to a second minimum circuit feature size smaller than the first minimum circuit feature size, and a plurality of vias electrically connecting the first integrated circuit layer and the second integrated circuit layer. The first integrated circuit layer may include a first serializer-deserializer (SERDES) circuit connecting the plurality of first circuit elements to a first via, which is one of the plurality of vias. The second integrated circuit layer may include a second SERDES circuit connecting the first via to the plurality of second circuit elements.

[0199] For example, the plurality of first circuit elements may include a plurality of control signal terminals. A plurality of control signals corresponding to the plurality of control signal terminals may be configured to be transmitted through the first via based on a serial communication protocol.

[0200] For example, the integrated circuit may include a second via configured to transmit substantially the same signal as the first via. The second via may be configured to be positioned between the first SERDES circuit and the second SERDES circuit.

[0201] According to one embodiment, as described above, an application processor (AP) (e.g., processor (110) of FIGS. 1 to 5) includes a first circuit layer (e.g., first circuit layer (130) of FIG. 1) including a first electronic component (e.g., circuit (132) of FIG. 1), at least one second electronic component, and a first SERDES (serializer-deserializer) electronic component (e.g., first SERDES circuit (131) of FIG. 1) connected to each of third electronic components including the first electronic component and the at least one second electronic component, a second circuit layer (e.g., second circuit layer (150) of FIG. 1) including a fourth electronic component (e.g., second circuit (152) of FIG. 1) and a second SERDES electronic component (e.g., second SERDES circuit (151) of FIG. 1) connected to the fourth electronic component, and an interconnect disposed between the first circuit layer and the second circuit layer. A layer (e.g., an interconnect layer (140) of FIG. 1) may be included. The interconnect layer may include TSVs, including a first through silicon via (TSV) (e.g., TSV (142) of FIG. 1) connecting the first electronic component to the fourth electronic component and a second TSV (e.g., TSV (141) of FIG. 1) connecting the first SERDES electronic component to the second SERDES electronic component. The first electronic component may transmit a first type of signal to the fourth electronic component through the first TSV in the interconnect layer. The first electronic component may transmit a second type of signal to the first SERDES electronic component to transmit a second type of signal to the fourth electronic component. The first SERDES electronic component may serialize the second type of signal together with at least one signal transmitted from the at least one second electronic component.The first SERDES electronic component may transmit a signal obtained based on the serialization to the second SERDES electronic component through the second TSV. The second SERDES electronic component may be configured to obtain the second type of signal to be transmitted to the fourth electronic component based on deserialization of the signal transmitted through the second TSV.

[0202] For example, the first SERDES electronic component may include a buffer (e.g., buffer (212) of FIG. 2) configured to store one or more bits representing a state of the first electronic component, which are included in the signal of the second type.

[0203] For example, the first SERDES electronic component may be configured to perform serialization on the one or more bits and at least one bit included in the at least one signal transmitted from the at least one second electronic component, thereby generating a sequence of a plurality of bits. The first SERDES electronic component may be configured to transmit the signal including the sequence to the second SERDES electronic component through the second TSV.

[0204] For example, the first SERDES electronic component may be configured to store at least one bit obtained from the third electronic components within a specified time interval in the buffer. The first SERDES electronic component may be configured to perform serialization on the at least one bit stored in the buffer based on an expiration of the specified time interval.

[0205] For example, the second SERDES electronic component may be configured to generate a signal to be transmitted to the first SERDES electronic component through the second TSV based on the second type of signal transmitted from the fourth electronic component.

[0206] For example, the second SERDES electronic component may be connected to each of the fifth electronic components, including the fourth electronic component, included in the second circuit layer. The second SERDES electronic component may be configured to generate the signal to be transmitted to the first SERDES electronic component based on serialization of the second type of signals transmitted from the fifth electronic components.

[0207] For example, the second SERDES electronic component may be configured to receive the second type of signal from the fourth electronic component to notify the first electronic component, which is a central processing unit (CPU) (e.g., CPU (310) of FIGS. 3A to 3C), of at least one of a status of the fourth electronic component or an interrupt related to the fourth electronic component.

[0208] For example, the second SERDES electronic component may be configured to transmit the plurality of bits to each of the fifth electronic components on the second circuit layer including the fourth electronic component based on a digit of each of the plurality of bits in the signal transmitted through the second TSV based on the deserialization.

[0209] For example, the first circuit layer may be configured to include circuit elements having a size smaller than the minimum size of circuit elements included in the second circuit layer.

[0210] For example, the first SERDES electronic component may be configured to transmit the signal, obtained based on the serialization and encoded based on a bi-phase mark coding (BMC) scheme, to the second SERDES electronic component through the second TSV.

[0211] For example, the second TSV may be configured to transmit the signal within a first data-rate range that includes 300 kbps. The first TSV may be configured to transmit the signal of the first type within a second data-rate range that exceeds the first data-rate range.

[0212] For example, the interconnect layer may be configured to include a third TSV (e.g., TSV (410) of FIG. 4), a first switching electronic component (e.g., first switching circuit (421) of FIG. 4) configured to connect an end of the second TSV, among the second TSV or the third TSV, to the first SERDES electronic component, and a second switching electronic component (e.g., second switching circuit (422) of FIG. 4) configured to connect another end of the second TSV, among the second TSV or the third TSV, to the second SERDES electronic component.

[0213] For example, the first electronic component may be configured to transmit the first type of signal including data to the fourth electronic component through the first TSV. The first electronic component may be configured to transmit the second type of signal for controlling a controller included in the fourth electronic component to the first SERDES electronic component.

[0214] For example, the fourth electronic component may be configured to transmit the data to a volatile memory connected to the application processor based on the signal of the first type.

[0215] For example, the controller of the fourth electronic component may be configured to receive the second type of signal based on a general purpose input output (GPIO).

[0216] According to one embodiment, as described above, an application processor (AP) may include a first circuit layer including a first electronic component, a plurality of second electronic components including the first electronic component, and a first SERDES (serializer-deserializer) electronic component connected to each of the plurality of second electronic components, a second circuit layer including a third electronic component and a second SERDES electronic component connected to the third electronic component, and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the first electronic component to the third electronic component and to transmit a first type of signal from the first electronic component to the third electronic component. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component to the second SERDES electronic component and configured to transmit a second type of signal based on serialization of the first SERDES electronic component. The second type of signal transmitted through the second TSV may include a sequence of bits of the plurality of second electronic components based on the serialization, the sequence including at least one bit provided by the first electronic component.

[0217] For example, the first SERDES electronic component may include a buffer configured to store bits transmitted from each of the plurality of second electronic components. The first SERDES electronic component may be configured to obtain a plurality of bits to be included in the second type of signal to be transmitted to the second SERDES electronic component through the second TSV based on the serialization of the bits stored in the buffer during a specified time interval.

[0218] For example, the first SERDES electronic component may be configured to, in response to receiving the second type of signal from the second SERDES electronic component through the second TSV, perform deserialization on the received second type of signal to obtain at least one bit to be provided to each of the plurality of second electronic components.

[0219] For example, the first electronic component, which is a central processing unit (CPU), may be configured to transmit the first type of signal including data to the third electronic component through the first TSV. The first electronic component may be configured to transmit the second type of signal for controlling a controller of the third electronic component to the first SERDES electronic component.

[0220] According to one embodiment, as described above, an electronic device may include a memory and an application processor (AP). The AP may include a first circuit layer including a plurality of electronic components including a central processing unit (CPU) and a first serializer-deserializer (SERDES) electronic component connected to each of the plurality of electronic components, a second circuit layer including a memory interface electronic component and a second SERDES electronic component for communicating with the memory, and an interconnect layer disposed between the first circuit layer and the second circuit layer. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the CPU and the memory interface electronic component of the first circuit layer. The interconnect layer may include a second TSV configured to connect the first SERDES electronic component and the second SERDES electronic component. The CPU may be configured to transmit a data signal including data to be stored in the memory to the memory interface electronic component through the first TSV. The CPU may be configured to transmit a control signal to the first SERDES electronic component for controlling the memory interface electronic component so that the data is transmitted to the memory.

[0221] For example, the first SERDES electronic component may be configured to perform serialization on control signals obtained from the plurality of electronic components to obtain a signal including a sequence of bits included in the control signals. The first SERDES electronic component may be configured to transmit the signal including the sequence to the second SERDES electronic component through the second TSV.

[0222] For example, the first SERDES electronic component may be configured to transmit the signal including the sequence based on a bi-phase mark coding (BMC) scheme.

[0223] For example, the first SERDES electronic component may be configured to obtain at least one bit to be transmitted to the CPU based on deserialization of bits included in the received signal, based on receiving a signal transmitted from the second SERDES electronic component through the second TSV.

[0224] For example, the data signal may be configured to be transmitted within the first TSV at a first data rate that exceeds a second data rate supported by the second TSV.

[0225] For example, the plurality of electronic components may be configured to include circuit elements having a size smaller than a minimum size of circuit elements included in the memory interface electronic component of the second circuit layer.

[0226] According to one embodiment, a processing chip component as described above may include a first die including a first circuit, a second circuit, and a first serializer-deserializer (SERDES) circuit connected to the first circuit and the second circuit. The processing chip component may include a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip component may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) connecting the first SERDES circuit and the second SERDES circuit to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

[0227] For example, the interconnect layer may include a second TSV connecting the first circuit and the third circuit. The first circuit may be configured to transmit a first type signal to the third circuit through the second TSV in the interconnect layer. The first circuit may be configured to transmit the second type signal to the first SERDES circuit in order to transmit the second type signal to the third circuit. The first SERDES circuit may be configured to perform serialization of the second type signal and the signal transmitted from the second circuit. The first SERDES circuit may be configured to transmit a signal obtained based on the serialization to the second SERDES circuit through the first TSV. The second SERDES circuit may be configured to obtain the second type of signal to be transmitted to the third circuit based on deserialization of the signal transmitted through the first TSV.

[0228] For example, the signal of the first type may include a data signal to be input to the third circuit. The signal of the second type may include a control signal corresponding to the third circuit.

[0229] For example, the first SERDES circuit may include a buffer for storing bits received from the first circuit and the second circuit, the bits corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path. The first SERDES circuit may include a controller for performing serialization on the bits stored in the buffer to generate a sequence of the bits to be included in a signal to be transmitted to the second die through the first TSV.

[0230] For example, the first SERDES circuit may be configured to store the bits obtained from the first circuit and the second circuit in the buffer within a specified time interval. The first SERDES circuit may be configured to perform serialization on the bits stored in the buffer based on the expiration of the specified time interval.

[0231] For example, the first circuit may correspond to a central processing unit (CPU) circuit, and the second circuit may correspond to a graphic processing unit (GPU) circuit.

[0232] For example, the third circuit may correspond to an image signal processor (ISP) circuit. The fourth circuit may correspond to a display controller circuit.

[0233] For example, the interconnect layer may include a second TSV connected to a second signal terminal of the CPU circuit, which includes a first signal terminal connected to the first SERDES circuit. The ISP circuit may include a third signal terminal electrically connected to the second TSV.

[0234] For example, the CPU circuit may be configured to transmit a control signal for requesting data from the ISP circuit to the first SERDES circuit via the first signal terminal. The CPU circuit may be configured to receive the data corresponding to the control signal from the ISP circuit via the second signal terminal connected to the second TSV.

[0235] For example, the third circuit may correspond to a memory interface circuit for communicating with a memory connected to the processing chip component. The fourth circuit may correspond to a neural processing unit (NPU) circuit.

[0236] For example, the second SERDES circuit may be configured to generate a signal to be transmitted to the first SERDES circuit through the first TSV based on serialization of signals transmitted from the third circuit and the fourth circuit.

[0237] For example, the second SERDES circuit may be configured to receive a signal from the third circuit to notify the first circuit, which is a central processing unit (CPU) circuit, of at least one of a state of the third circuit or an interrupt associated with the third circuit.

[0238] For example, the second SERDES electronic component may be configured to obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path, based on a digit of each of the plurality of bits in the signal transmitted through the first TSV, based on deserialization.

[0239] For example, the first die may be configured to include circuit elements having a size smaller than the minimum size of circuit elements included in the second die.

[0240] For example, the first SERDES circuit may be configured to transmit the signal, obtained based on the serialization and encoded based on a bi-phase mark coding (BMC) scheme, to the second SERDES circuit through the first TSV.

[0241] For example, the first TSV may be configured to transmit a signal within a first data-rate range including 300 kbps. The interconnect layer may include a second TSV configured to transmit a signal within a second data-rate range exceeding the first data-rate range.

[0242] For example, the interconnect layer may include a redundant TSV. The interconnect layer may include a first switching circuit configured to connect an end of the first TSV, among the first TSV or the redundant TSV, to the first SERDES circuit. The interconnect layer may be configured to include a second switching circuit configured to connect another end of the first TSV, among the first TSV or the redundant TSV, to the second SERDES circuit.

[0243] For example, the first circuit may be configured to transmit a first type of signal including data to the third circuit through a second TSV included in the interconnect layer. The first circuit may be configured to transmit a second type of signal to the first SERDES circuit for controlling a controller included in the third circuit through the third signal path.

[0244] For example, the first SERDES circuit may be configured to transmit a signal based on a general purpose input output (GPIO) to the second SERDES circuit through the first TSV.

[0245] According to one embodiment, a processing chip component as described above may include a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit. The processing chip component may include a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit. The processing chip component may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the first circuit to the third circuit and configured to transmit a first type of signal from the first circuit to the third circuit. The interconnect layer may include a second TSV configured to connect the first SERDES circuit to the second SERDES circuit and configured to transmit a second type of signal based on serialization of the first SERDES circuit. The second type of signal transmitted through the second TSV may include a sequence of at least one bit provided by the first circuit and at least one bit provided by the second circuit.

[0246] According to one embodiment, an electronic device as described above may include a memory and a processor. The processor may include a first die including a plurality of circuits including a central processing unit (CPU) and a first serializer-deserializer (SERDES) circuit connected to each of the plurality of circuits. The processor may include a second die including a memory interface circuit for communicating with the memory and a second SERDES circuit. The processor may include an interconnect layer disposed between the first die and the second die. The interconnect layer may include a first through silicon via (TSV) configured to directly connect the CPU and the memory interface circuit of the first die. The interconnect layer may include a second TSV configured to connect the first SERDES circuit and the second SERDES circuit. The CPU may be configured to transmit a data signal including data to be stored in the memory to the memory interface circuit through the first TSV. The CPU may be configured to transmit a control signal to the first SERDES circuit for controlling the memory interface circuit so that the data is transmitted to the memory.

[0247] In a first example, a processing chip component is provided, comprising: a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; and an interconnect layer disposed between the first die and the second die, wherein the interconnect layer includes a first TSV configured to be connected between the first SERDES circuit and the second SERDES circuit and configured to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

[0248] In a second example, a processing chip component of the first example is provided, wherein the first SERDES circuit can be configured to perform serialization of a signal transmitted from the first circuit together with a signal transmitted from the second circuit, and transmit a signal obtained based on the serialization to the second SERDES circuit through the first TSV; and the second SERDES circuit can be configured to obtain the signal to be transmitted to at least one of the third circuit and the fourth circuit based on deserialization of the signal transmitted through the first TSV.

[0249] In a third example, the processing chip component of the first or second example is provided, wherein the interconnect layer further includes a second TSV connecting the first circuit to the third circuit, and the first circuit can be configured to transmit a first type of signal to the third circuit through the second TSV in the interconnect layer; and the first SERDES circuit can be configured to transmit a second type of signal to the third circuit through the first TSV.

[0250] In a fourth example, the processing chip component of the third example is provided, wherein the second TSV provides a fifth signal path between the first circuit and the third circuit, wherein the fifth signal path does not include the first SERDES circuit and does not include the second SERDES circuit.

[0251] In a fifth example, a processing chip component of the third or fourth example is provided, wherein the signal of the first signal includes a data signal to be input to the third signal, and the signal of the second type includes a control signal corresponding to the third circuit.

[0252] In a sixth example, a processing chip component of any one of the second to fourth examples is provided, wherein the first SERDES circuit includes a buffer for storing bits received from the first circuit and the second circuit, each of the bits corresponding to at least one of the first signal path, the second signal path, the third signal path, or the fourth signal path; and a controller configured to perform serialization on the bits stored in the buffer to generate a sequence of bits to be included in a signal to be transmitted to the second die through the first TSV.

[0253] In a seventh example, a processing chip component of the sixth example is provided, wherein the first SERDES circuit is configured to store bits obtained from the first circuit and the second circuit within a specified time interval in the buffer; and, based on the expiration of the specified time interval, perform serialization of the bits stored in the buffer.

[0254] In the eighth example, a processing chip component of any one of the first to seventh examples is provided, wherein the first circuit includes a CPU circuit and the second circuit includes a GPU circuit.

[0255] In a ninth example, the processing chip component of the eighth example is provided, wherein the third circuit includes an ISP circuit and the fourth circuit includes a display controller circuit.

[0256] In a tenth example, a processing chip component of the ninth example is provided, comprising a second TSV connected to a second signal pin of the CPU circuit, the CPU circuit comprising a first signal pin connected to the first SERDES circuit; and the ISP circuit comprising a third signal pin electrically connected to the second TSV.

[0257] In an eleventh example, a processing chip component of the tenth example is provided, wherein the CPU circuit is configured to transmit a control signal to the first SERDES circuit through the first signal pin to request data from the ISP circuit, and is configured to receive the data corresponding to the control signal from the ISP circuit through the second signal pin connected to the second TSV.

[0258] In a twelfth example, the processing chip component of the eleventh example is provided, wherein the third circuit includes a memory interface circuit for communicating with a memory connected to the processing chip component; and the fourth circuit includes an NPU circuit.

[0259] In a thirteenth example, a processing chip component of any one of examples 1 to 12 is provided, wherein the second SERDES circuit is configured to generate a signal to be transmitted to the first SERDES circuit through the first TSV based on serialization of signals transmitted from the third circuit and the fourth circuit.

[0260] In a fourteenth example, the processing chip component of the thirteenth example is provided, wherein the first circuit includes a CPU; and the second SERDES circuit is configured to receive, from the third circuit, a signal for notifying the first circuit of at least one of a state of the third circuit or an interruption associated with the third circuit.

[0261] In a fifteenth example, a processing chip component of any one of examples 1 to 14 is provided, wherein the second SERDES circuit is configured to obtain at least one bit corresponding to each of the first signal path, the second signal path, the third signal path, and the fourth signal path, based on a position of each of the plurality of bits of a signal transmitted through the first TSV based on deserialization.

[0262] In a sixteenth example, a processing chip component of any one of examples 1 to 15 is provided, wherein the first die is configured to include a circuit element having a size smaller than a minimum size of circuit elements included in the second die.

[0263] In a seventeenth example, a processing chip component of any one of examples 1 to 16 is provided, wherein the first die is produced by a process capable of implementing a circuit element based on a first minimum line width; and the second die is produced by a process capable of implementing a circuit element based on a second minimum line width, wherein the second minimum line width is larger than the first minimum line width.

[0264] In an eighteenth example, a processing chip component of any one of examples 1 to 17 is provided, wherein the first SERDES circuit is configured to transmit a signal encoded based on a BMC (bi-phase mark coding) scheme and acquired based on serialization to a second SERDES circuit through a first TSV.

[0265] In a nineteenth example, a processing chip component of any one of examples 1 to 18 is provided, wherein a power state of at least one of the first SERDES circuit and the second SERDES circuit is controlled independently of a power state of a CPU included in the processing chip component.

[0266] In a 20th example, a processing chip component of any one of examples 1 to 19 is provided, wherein the interconnect layer comprises an auxiliary TSV configured to connect between a first SERDES circuit and a second SERDES circuit, and configured to provide an auxiliary first signal path between the first circuit and the third circuit, an auxiliary second signal path between the first circuit and the fourth circuit, an auxiliary third signal path between the second circuit and the third circuit, and an auxiliary fourth signal path between the second circuit and the fourth circuit.

[0267] In a twenty-first example, a processing chip component of the twenty-first example is provided, wherein the first die includes a first switch circuit; the second die includes a second switch circuit; and the first switch circuit and the second switch circuit are configured to control a connection between the first SERDES circuit and the second SERDES circuit by switching a connection between the first TSV and the auxiliary TSV.

[0268] In a twenty-second example, a processing chip component of any one of examples 1 to 21 is provided, wherein the interconnect layer includes a plurality of TSVs; and the first SERDES circuit includes a first protocol circuit configured to support a first communication protocol, a second protocol circuit configured to support a second communication protocol, and a first multiplexer switch circuit configured to connect the plurality of TSVs to the first protocol circuit and the second protocol circuit. The second SERDES circuit may include a third protocol circuit configured to support the first communication protocol, a fourth protocol circuit configured to support the second communication protocol, and a second multiplexer switch circuit configured to connect the plurality of TSVs to the third protocol circuit and the fourth protocol circuit, wherein the first multiplexer switch circuit and the second multiplexer switch circuit may be configured to: select a communication protocol, and establish a connection between the first protocol circuit and the third protocol circuit through the plurality of TSVs when the first communication protocol is selected, and establish a connection between the second protocol circuit and the fourth protocol circuit through the plurality of TSVs when the second communication protocol is selected.

[0269] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

[0270] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0271] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. In this case, the medium may be one that continuously stores a computer-executable program or one that temporarily stores it for execution or download. In addition, the medium may be various recording means or storage means in the form of a single or multiple hardware combinations, and is not limited to a medium directly connected to a computer system, but may also be distributed over a network. Examples of the medium may include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and those configured to store program commands, including ROM, RAM, and flash memory. In addition, examples of other media may include recording media or storage media managed by app stores that distribute applications, sites that supply or distribute various software, servers, etc.

[0272] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0273] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In processing chip components, A first die including a first circuit, a second circuit, and a first SERDES (serializer-deserializer) circuit connected to the first circuit and the second circuit; A second die comprising a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; An interconnect layer disposed between the first die and the second die, The above interconnection layer is, A first signal path between the first circuit and the third circuit; A second signal path between the first circuit and the fourth circuit; A third signal path between the second circuit and the third circuit; A fourth signal path between the second circuit and the fourth circuit In order to provide, a first through silicon via (TSV) connecting between the first SERDES circuit and the second SERDES circuit, Processing chip components.

2. In claim 1, the interconnection layer is: Further comprising a second TSV connecting the first circuit and the third circuit, The first circuit above: Transmitting a first type signal to the third circuit through the second TSV within the interconnection layer; In order to transmit a second type signal to the third circuit, the first SERDES circuit is configured to transmit the second type signal, The above first SERDES circuit: Serialization of the signal of the second type and the signal transmitted from the second circuit is performed, It is configured to transmit a signal obtained based on the serialization to the second SERDES circuit through the first TSV, The second SERDES circuit is configured to obtain the second type of signal to be transmitted to the third circuit based on deserialization of the signal transmitted through the first TSV. Processing chip components.

3. In claim 2, the signal of the first type is, Contains a data signal to be input to the third circuit, The above second type of signal is, Containing a control signal corresponding to the third circuit, Processing chip components.

4. In claim 2, the first SERDES circuit comprises: A buffer for storing bits received from the first circuit and the second circuit, and corresponding to each of the first signal path, the second signal path, the third signal path and the fourth signal path; and A controller for performing serialization on the bits stored in the buffer to generate a sequence of the bits to be included in a signal to be transmitted to the second die through the first TSV. Processing chip components.

5. In claim 4, the first SERDES circuit, storing the bits obtained from the first circuit and the second circuit within a specified time interval in the buffer; configured to perform serialization on the bits stored in the buffer based on the expiration of the above specified time interval; Processing chip components.

6. In claim 1, The above first circuit corresponds to a CPU (central processing unit) circuit, The above second circuit corresponds to a GPU (graphic processing unit) circuit. Processing chip components.

7. In claim 6, The above third circuit corresponds to an ISP (image signal processor) circuit, The above fourth circuit corresponds to the display controller circuit, The above interconnection layer is, A second TSV connected to a second signal terminal of the CPU circuit, the second TSV including a first signal terminal connected to the first SERDES circuit, The above ISP circuit includes a third signal terminal electrically connected to the second TSV, The above CPU circuit, A control signal for requesting data from the ISP circuit is transmitted to the first SERDES circuit through the first signal terminal, configured to receive the data corresponding to the control signal from the ISP circuit through the second signal terminal connected to the second TSV; Processing chip components.

8. In claim 6, The above third circuit corresponds to a memory interface circuit for communicating with a memory connected to the processing chip component, The above fourth circuit corresponds to the NPU (neural processing unit) circuit. Processing chip components.

9. In any one of the aforementioned claims, the second SERDES circuit, Based on the serialization of signals transmitted from the third circuit and the fourth circuit, configured to generate a signal to be transmitted to the first SERDES circuit through the first TSV. Processing chip components.

10. In claim 9, the second SERDES circuit, configured to receive a signal from the third circuit to notify the first circuit, which is a central processing unit (CPU) circuit, of at least one of a state of the third circuit or an interrupt related to the third circuit. Processing chip components.

11. In any one of the aforementioned claims, the second SERDES electronic component comprises: Based on deserialization, at least one bit corresponding to each of the first signal path, the second signal path, the third signal path and the fourth signal path is obtained based on the digit of each of the plurality of bits in the signal transmitted through the first TSV. Processing chip components.

12. In any one of the claims set forth above, The above first die, configured to include circuit elements having a size smaller than the minimum size of the circuit elements included in the second die; Processing chip components.

13. In any one of the preceding claims, the first SERDES circuit comprises: configured to transmit the signal, which is obtained based on the above serialization and encoded based on the BMC (bi-phase mark coding) scheme, to the second SERDES circuit through the first TSV. Processing chip components.

14. In any one of the preceding claims, the interconnect layer comprises an auxiliary TSV configured to connect between the first SERDES circuit and the second SERDES circuit, the auxiliary TSV comprising: Auxiliary first signal path between the first circuit and the third circuit; A second auxiliary signal path between the first circuit and the fourth circuit; A third auxiliary signal path between the second circuit and the third circuit, and Auxiliary fourth signal path between the second circuit and the fourth circuit is configured to provide, The above first die includes a first switch circuit; The second die comprises a second switch circuit; and The first switch circuit and the second switch circuit are configured to control the connection between the first SERDES circuit and the second SERDES circuit by switching the connection between the first TSV and the auxiliary TSV. Processing chip components.

15. In any one of the preceding claims, the interconnect layer comprises a plurality of TSVs; The above first SERDES circuit: A first protocol circuit configured to support a first communication protocol; A second protocol circuit configured to support a second communication protocol, and A first multiplexer switch circuit configured to connect the plurality of TSVs with the first protocol circuit and the second protocol circuit; Including, The above second SERDES circuit: A third protocol circuit configured to support the first communication protocol; A fourth protocol circuit configured to support the second communication protocol, and A second multiplexer switch circuit configured to connect the plurality of TSVs to the third protocol circuit and the fourth protocol circuit; and The above first multiplexer switch circuit and the above second multiplexer switch circuit: Select a communication protocol, When the first communication protocol is selected, a connection is established between the first protocol circuit and the third protocol circuit through the plurality of TSVs, and When the second communication protocol is selected, a connection is established between the second protocol circuit and the fourth protocol circuit through the plurality of TSVs. Processing chip components.

Images