Signal transmission circuit and method, integrated circuit

Abstract

The present disclosure is about a signal transmission circuit and method, and an integrated circuit, wherein the signal transmission circuit includes: an input module for generating a first detection signal in response to a first control signal and a clock signal; a transmission chain, including a multi-stage transmission module connected in series, and the adjacent transmission modules in the transmission chain are connected through silicon vias, the transmission module at one end of the transmission chain is connected to the input module, and the multi-stage transmission modules transmit the first detection signal step by step in response to the clock signal; and a plurality of signal output terminals, wherein the first detection signal input terminal of each stage of the transmission module is correspondingly connected to a signal output terminal. The signal transmission circuit can improve the effective utilization rate of the chip in the integrated circuit with the silicon via detection circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular, to a signal transmission circuit and method, and an integrated circuit. Background Art

[0002] With the development and progress of technology, 3D integrated circuits are being used more and more widely. The chip layers in the 3D integrated circuits are connected through TSVs (Through-Silicon Vias). In order to ensure the performance of the 3D integrated circuits, it is usually necessary to test the connectivity of the TSVs.

[0003] When detecting the connectivity of TSVs in 3D integrated circuits, it is often necessary to provide detection signals to each chip layer. In the related art, multiple TSVs are set in the 3D integrated circuit, and detection signals are provided to each chip layer through the multiple TSVs. A large number of detection TSVs need to be set in the 3D integrated circuit, which reduces the effective utilization rate of the chip.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a signal transmission circuit and method, and an integrated circuit for providing signals for a through silicon via detection circuit, thereby overcoming to a certain extent the problem in the related art that the through silicon via detection circuit requires a large number of detection through silicon vias to transmit signals, thereby reducing the effective utilization rate of the chip.

[0006] According to a first aspect of the present disclosure, a signal transmission circuit is provided, the signal transmission circuit comprising:

[0007] An input module, configured to generate a first detection signal in response to a first control signal and a clock signal;

[0008] A transmission chain, comprising a plurality of transmission modules connected in series, wherein adjacent transmission modules in the transmission chain are connected via through silicon vias, the transmission module at one end of the transmission chain is connected to the input module, and the plurality of transmission modules transmit the first detection signal step by step in response to a clock signal;

[0009] A plurality of signal output terminals, wherein the first detection signal input terminal of each transmission module is correspondingly connected to a signal output terminal.

[0010] According to one embodiment of the present disclosure, the input module includes:

[0011] A first trigger, an input terminal of which is connected to a first control signal, and a clock terminal of which is connected to a clock signal;

[0012] The AND gate unit has a first input terminal connected to the first control signal and a second input terminal connected to the non-output terminal of the first trigger.

[0013] According to one embodiment of the present disclosure, the transmission module includes:

[0014] A second trigger, an input terminal of which is connected to the first detection signal, and a clock terminal of which is connected to the clock signal;

[0015] The third trigger has an input terminal connected to the output terminal of the second trigger, and a clock terminal connected to the clock signal.

[0016] According to one embodiment of the present disclosure, two adjacent levels of transfer modules in the transfer chain are connected through a through silicon via, wherein the output end of the third trigger of the first level of the transfer module is connected to the first end of the through silicon via, and the input end of the second trigger of the other level of the transfer module is connected to the second end of the through silicon via.

[0017] According to an embodiment of the present disclosure, the input module is arranged in the base chip layer of the integrated circuit, and a transmission module is arranged in each chip layer of the integrated circuit.

[0018] According to one embodiment of the present disclosure, the signal transmission circuit further includes:

[0019] The first detection TSV string includes a plurality of TSVs connected in series and is used to transmit the first control signal from the top chip layer to the base chip layer.

[0020] According to one embodiment of the present disclosure, the signal transmission circuit further includes:

[0021] A mode selection module, wherein a first input end is connected to the first detection signal, a second input end is connected to the second detection signal, a control end is connected to the first control signal, a first output end is connected to the input end of the transmission module, and is used to transmit the first detection signal to the input end of the transmission module under the control of the first control signal, a second output end is connected to the output end of the transmission module, and is used to transmit the second detection signal to the output end of the transmission module under the control of the first control signal, the first detection signal and the second detection signal are transmitted to adjacent chip layers through the same silicon through-via, and the second detection signal is respectively connected to the multiple signal output ends.

[0022] According to one embodiment of the present disclosure, the mode selection module includes:

[0023] A first switch unit, a first end of which is connected to the output end of the input module, a second end of which is connected to the input end of the transmission module, and a control end of which is connected to the first control signal;

[0024] The second switch unit has a first end connected to the second detection signal, a second end connected to the output end of the transmission module, and a control end connected to the first control signal.

[0025] According to an embodiment of the present disclosure, the first switch unit is an N-type metal oxide semiconductor field effect transistor, and the second switch unit is a P-type metal oxide semiconductor field effect transistor.

[0026] According to one embodiment of the present disclosure, the mode selection module includes:

[0027] A first inverter, an input terminal of which is connected to a first control signal;

[0028] A second inverter, an input end of which is connected to an output end of the first inverter;

[0029] A first switch unit, wherein a first end is connected to the first detection signal, a second end is connected to the input end of the transmission module, a first control end is connected to the output end of the first inverter, and a second control end is connected to the output end of the second inverter;

[0030] a second switch unit, wherein a first end is connected to the second detection signal, a second end is connected to the output end of the transmission module, a first control end is connected to the output end of the second inverter, and a second control end is connected to the output end of the first inverter;

[0031] Wherein, the first switch unit and the second switch unit are complementary metal oxide semiconductor transmission gates.

[0032] According to one embodiment of the present disclosure, the signal transmission circuit includes:

[0033] A multi-level mode selection module is provided in each chip layer of the integrated circuit.

[0034] According to one embodiment of the present disclosure, the signal transmission circuit further includes:

[0035] The second detection TSV string includes a plurality of TSVs connected in series and is used to provide a first control signal for the multi-stage mode selection modules.

[0036] According to a second aspect of the present disclosure, there is provided a signal transmission method, comprising:

[0037] The input module responds to the first control signal and the clock signal, and outputs the first detection signal to the input end of the first-stage transmission module in the transmission chain, where the first-stage transmission module is the transmission module in the transmission chain connected to the input module;

[0038] The multi-stage transmission modules respond to the clock signal in sequence and transmit the first detection signal in sequence along the transmission chain;

[0039] When the first detection signal is transmitted to the output end of any level of transmission module, the signal output end connected to the input end of the transmission module outputs the first detection signal.

[0040] According to an embodiment of the present disclosure, the input module responds to the first control signal and the clock signal, outputs the first detection signal to the input end of the first stage transmission module in the transmission chain, including:

[0041] The first trigger outputs a first trigger signal to the second input terminal of the AND gate unit in response to the first control signal and the clock signal;

[0042] The AND gate unit outputs a first detection signal to an input end of a first-stage transmission module in a transmission chain according to the first control signal and the first trigger signal.

[0043] According to an embodiment of the present disclosure, the multi-stage transmission module sequentially responds to the clock signal and sequentially transmits the first detection signal along the transmission chain, including:

[0044] The second trigger in the front-stage transmission module transmits the first detection signal to the third trigger in the transmission module according to the first detection signal and the clock signal;

[0045] The third trigger in the previous stage transfer module transmits the first detection signal to the second trigger in the next stage transfer module according to the first detection signal and the clock signal.

[0046] According to an embodiment of the present disclosure, the signal transmission method further includes:

[0047] The mode selection unit selects to output the first detection signal or the second detection signal according to the first control signal.

[0048] According to a third aspect of the present disclosure, there is provided an integrated circuit, comprising the above-mentioned signal transmission circuit.

[0049] The signal transmission circuit provided by the present disclosure has an input module that generates a first detection signal in response to a first control signal and a clock signal, transmits the first detection signal step by step through a multi-stage transmission module, and outputs the first detection signal to a multi-layer chip layer by layer through a plurality of signal output terminals that are respectively connected to the input terminals of the multi-stage transmission module. The detection signal is provided layer by layer for the through silicon via detection circuit, which is convenient for detecting the connectivity of the through silicon vias layer by layer, and the structure is simple, avoiding the problem of reduced chip effective area and low chip utilization caused by using a large number of through silicon vias to transmit detection signals in the related art.

[0050] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0052] Figure 1 A circuit diagram of a signal transmission circuit provided for an exemplary embodiment of the present disclosure;

[0053] Figure 2 A circuit diagram of an input module provided for an exemplary embodiment of the present disclosure;

[0054] Figure 3 A timing diagram of input signals and output signals of an input module provided for an exemplary embodiment of the present disclosure;

[0055] Figure 4 A circuit diagram of a transfer module provided for an exemplary embodiment of the present disclosure;

[0056] Figure 5 A timing diagram of input signals and output signals of a transfer module provided for an exemplary embodiment of the present disclosure;

[0057] Figure 6 A circuit diagram of another signal transmission circuit provided for an exemplary embodiment of the present disclosure;

[0058] Figure 7 A flowchart of a first signal transmission method provided for an exemplary embodiment of the present disclosure;

[0059] Figure 8 A flowchart of a second signal transmission method provided for an exemplary embodiment of the present disclosure;

[0060] Fig. 9 The present invention is a flowchart of a third signal transmission method provided by an exemplary embodiment of the present disclosure.

[0061] In the figure:

[0062] 100, input module; 101, first trigger; 102, AND gate unit; 200, transmission chain; 210, transmission module; 211, second trigger; 212, third trigger; 300, mode selection module; 310, first switch unit; 320, second switch unit; 311, first inverter; 321, second inverter;

[0063] TE, first control signal; TP, first detection signal; TF, second detection signal; CLK, clock signal; RST, reset signal; ST, signal output terminal; DTP, transmitted first detection signal. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0065] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, devices, steps, etc. may be adopted. In other cases, known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0066] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or parts of functional entities may be implemented in one or more software hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.

[0067] In the related art, TSVs in 3D integrated circuits are used to connect multiple chip layers. In order to ensure the connectivity of multiple chip layers, TSVs need to be tested. In TSV testing, in order to accurately locate the location of the faulty TSV, it is often necessary to test the TSV layer by layer. At this time, it is necessary to provide test signals layer by layer. The signal transmission circuit provided by the exemplary embodiment of the present disclosure can realize the function of providing test signals layer by layer.

[0068] like Figure 1 As shown, a signal transmission circuit provided by an exemplary embodiment of the present disclosure includes an input module 100, a transfer chain 200 and multiple signal output terminals ST; the input module 100 is used to generate a first detection signal TP in response to a first control signal TE and a clock signal; the transfer chain 200 includes a plurality of stages of transfer modules 210 connected in series, and adjacent transfer modules 210 in the transfer chain 200 are connected through silicon vias, the transfer module 210 at one end of the transfer chain 200 is connected to the input module 100, and the plurality of stages of transfer modules 210 transmit the first detection signal TP step by step in response to the clock signal; the first detection signal TP input terminal of each stage of the transfer module 210 is correspondingly connected to a signal output terminal ST, and the signal output terminal ST is used to provide a detection signal to the chip layer.

[0069] In the signal transmission circuit provided by the embodiment of the present disclosure, the input module 100 generates a first detection signal TP in response to the first control signal TE and the clock signal, transmits the first detection signal TP step by step through the multi-stage transmission module 210, and outputs the first detection signal TP to the multi-layer chip layer by layer through a plurality of signal output terminals ST respectively connected to the input terminals of the multi-stage transmission module 210. The detection signal is provided layer by layer for the through silicon via detection circuit, which is convenient for detecting the connectivity of the through silicon via layer by layer, and the structure is simple, avoiding the problem of reduced chip effective area and low chip utilization caused by using a large number of through silicon vias to transmit detection signals in the related art.

[0070] The signal transmission circuit provided by the embodiment of the present disclosure is described in detail below:

[0071] like Figure 2 As shown, the input module 100 includes a first trigger 101 and an AND gate unit 102, the input end of the first trigger 101 is connected to the first control signal TE, and the clock end is connected to the clock signal; the first input end of the AND gate unit 102 is connected to the first control signal TE, and the second input end is connected to the non-output end of the first trigger 101.

[0072] The first trigger 101 may be a D trigger, and the non-output terminal of the first trigger 101 is The first control signal TE, the clock signal, the first trigger signal and the first detection signal TP are as follows: Figure 3 As shown, the first control signal TE is input into the D terminal of the D flip-flop, and the clock signal is input into the clock terminal, then The first trigger signal is outputted from the terminal, and the first trigger signal and the first control signal TE are passed through the AND gate unit 102 to obtain the first detection signal TP.

[0073] like Figure 4 As shown, the transfer module 210 includes a second trigger 211 and a third trigger 212, the input end of the second trigger 211 is connected to the first detection signal TP, and the clock end is connected to the clock signal; the input end of the third trigger 212 is connected to the output end of the second trigger 211, and the clock end is connected to the clock signal.

[0074] The second trigger 211 and the third trigger 212 may be D triggers. Before the first detection signal TP is input into the second trigger 211, the second trigger 211 and the third trigger 212 are reset by the reset signal RST. The clock signal, the reset signal RST, the first detection signal TP input into the transfer module 210, and the first detection signal TP output from the transfer module 210 are as follows: Figure 5The first detection signal TP is input into the second flip-flop 211 to realize a shift of one clock cycle, and the first detection signal TP output by the second flip-flop 211 is shifted through the third flip-flop 212 to realize a shift of one clock cycle.

[0075] The two adjacent transfer modules 210 in the transfer chain 200 are connected via a through silicon via, wherein the output end of the third trigger 212 of the previous transfer module 210 is connected to the first end of the through silicon via, and the input end of the second trigger 211 of the next transfer module 210 is connected to the second end of the through silicon via. The two-stage transfer modules 210 are sorted according to the flow direction of the signal, and the transfer module 210 into which the first detection signal TP flows first is the previous transfer module 210.

[0076] It should be noted that at least one trigger can be set in the transmission module 210, for example, the transmission module 210 includes a second trigger 211, the input end of the second trigger 211 is connected to the first detection signal TP, and the output end is connected to the silicon through hole; or the transmission module 210 includes the second trigger 211 and the third trigger 212 as mentioned above; of course, the transmission module 210 can also include multiple triggers, and the multiple triggers are connected in series to transmit the first detection signal TP in sequence. The embodiment of the present disclosure does not make specific limitations on this.

[0077] The input module 100 is arranged in the base chip layer of the integrated circuit, and a transfer module 210 is arranged in each chip layer of the integrated circuit. For example, an integrated circuit includes N chip layers, and the input module 100 is located in the base chip layer. The base chip layer is recorded as the first layer, and so on. The multi-level transmission module can also be named according to this rule, that is, the transfer module 210 located in the bottom layer is the first-level transfer module, and the top layer is the N-th-level transfer module. A first-level transfer module 210 and a signal output terminal ST are arranged on each layer of the N-layer chip layer. The first detection signal TP output by the output module is transmitted layer by layer through the silicon via between the transmission module 210 and the transmission module 210, so as to provide the detection signal layer by layer for the silicon via detection circuit, wherein the detection signal is transmitted in sequence from one to N.

[0078] Of course, in practical applications, the input module 100 may also be disposed in the top chip layer. In this case, the first detection signal TP may be transmitted layer by layer from the top chip layer to the bottom chip layer. This embodiment of the present disclosure does not specifically limit this.

[0079] Since in actual applications, the first control signal TE generating device often cannot be directly arranged in the base chip layer, in order to transmit the first control signal TE to the input module 100 located in the base chip layer, the signal transmission circuit also includes a first detection silicon via string, the first detection through-hole includes a plurality of silicon vias connected in series, and is used to transmit the first control signal TE from the top chip layer to the base chip layer. The upper end of the first detection silicon via string is connected to the first control signal TE, and the lower end is connected to the input module 100.

[0080] Further, in order to satisfy the requirement that the through silicon via detection circuit can detect the entire through silicon via string at one time, the signal transmission circuit may further include a mode selection module 300, wherein the first input terminal of the mode selection module 300 is connected to the first detection signal TP, the second input terminal is connected to the second detection signal TF, the control terminal is connected to the first control signal TE, the first output terminal is connected to the input terminal of the transmission module 210, and is used to transmit the first detection signal TP to the input terminal of the transmission module 210 under the control of the first control signal TE, and the second output terminal is connected to the output terminal of the transmission module 210, and is used to transmit the second detection signal TF to the output terminal of the transmission module 210 under the control of the first control signal TE. The first detection signal TE and the second detection TP signal are transmitted to adjacent chip layers through the same through silicon via, and the second detection signal is connected to the multiple signal output terminals ST respectively.

[0081] It should be noted that, for the mode selection module 300 arranged on the base chip layer, the first detection signal TP is the first detection signal output by the input module; for the mode selection module 300 on the chip layer other than the base layer, the first detection signal and the second detection signal are the first detection signal TE and the second detection signal TP transmitted from the chip layer below the current chip layer through the silicon via.

[0082] The mode selection unit is used to realize a working mode in which the detection signal is transmitted layer by layer or the detection signal is transmitted in multiple layers at the same time, so that the application of the signal transmission circuit is more flexible and adaptable to more application scenarios.

[0083] like Figure 6 As shown, the mode selection module 300 includes a first switch unit 310 and a second switch unit 320; the first end of the first switch unit 310 is connected to the output end of the input module 100, the second end is connected to the input end of the transmission module 210, and the control end is connected to the first control signal TE; the first end of the second switch unit 320 is connected to the second detection signal TF, the second end is connected to the output end of the transmission module 210, and the control end is connected to the first control signal TE.

[0084] In a feasible implementation provided by the embodiment of the present disclosure, the first switch unit 310 is an NMOS (N-type metal oxide semiconductor field effect transistor), the first end is connected to the output end of the output module, the second end is connected to the input end of the transmission module 210, and the control end is connected to the first control signal TE; the second switch unit 320 is a PMOS (P-type metal oxide semiconductor field effect transistor), the first end is connected to the second detection signal TF, the second end is connected to one end of the silicon through hole, and the control end is connected to the first control signal TE. When the first control signal TE is a high-level signal, the first switch unit 310 is turned on, the second switch unit 320 is turned off, and the first output end of the mode selection module 300 outputs the first detection signal TP; when the first control signal TE is a low-level signal, the first switch unit 310 is turned off, the second switch unit 320 is turned on, and the second output end of the mode selection module 300 outputs the second detection signal TF.

[0085] In another feasible implementation provided by the embodiment of the present disclosure, the mode selection module includes: a first inverter 311, a second inverter 321, a first switch unit 310 and a second switch unit 320; the input end of the first inverter 311 is connected to the first control signal TE; the input end of the second inverter 321 is connected to the output end of the first inverter 311; the first end of the first switch unit 310 is connected to the first detection signal TP, the second end is connected to the input end of the transmission module, the first control end is connected to the output end of the first inverter 311, and the second control end is connected to the output end of the second inverter 321; the first end of the second switch unit 320 is connected to the second detection signal TF, the second end is connected to the output end of the transmission module 100, the first control end is connected to the output end of the second inverter 321, and the second control end is connected to the output end of the first inverter 311. Wherein, the first switch unit 310 and the second switch unit 320 are both CMOS transmission gates (complementary metal oxide semiconductor transmission gates).

[0086] Preferably, the signal transmission circuit includes a multi-stage mode selection module 300, each stage of the transfer module 210 is connected to a corresponding stage of the mode selection module 300, and the second output end of the previous stage of the mode selection module 300 in the adjacent mode selection modules 300 is connected to the second input end of the next stage of the mode selection module 300 through a silicon through hole. For example, the first input end of the mode selection module 300 located in the base chip layer is connected to the output end of the input module 100, the second input end is connected to the second detection signal TF, the first input end is connected to the input end of the transfer module 210 in the layer, and the second output end is connected to the output end of the transfer module 210 in the layer. The first input end and the second input end of the mode selection module 300 in the chip layer above the base chip layer are both connected to the lower silicon through hole, which is a silicon through hole connecting the chip layer below the current chip layer.

[0087] Furthermore, in order to provide the first control signal TE to the mode selection unit in each chip layer, the signal transmission circuit provided in the embodiment of the present disclosure also includes: a second detection silicon via string, including a plurality of silicon vias connected in series, for providing the first control signal TE to the multi-level mode selection module 300.

[0088] The present disclosure also provides a signal transmission method for use in the above-mentioned signal transmission circuit, such as Figure 7 The signal transmission method comprises the following steps:

[0089] Step S710, the input module 100 responds to the first control signal TE and the clock signal, and outputs the first detection signal TP to the input end of the first-stage transmission module 210 in the transmission chain 200, where the first-stage transmission module 210 is the transmission module 210 in the transmission chain 200 connected to the input module 100;

[0090] Step S720, the multi-stage transmission modules 210 sequentially respond to the clock signal and sequentially transmit the first detection signal TP along the transmission chain 200;

[0091] Step S730: When the first detection signal TP is transmitted to the output end of any level of the transmission module 210, the signal output end ST connected to the input end of the transmission module 210 outputs the first detection signal TP.

[0092] The signal transmission method provided by the embodiment of the present disclosure responds to the first control signal TE and the clock signal through the input module 100, outputs the first detection signal TP to the input end of the first-stage transmission module 210 in the transmission chain 200, and the multi-stage transmission modules 210 respond to the clock signal in turn, and sequentially transmit the first detection signal TP along the transmission chain 200; when the first detection signal TP is transmitted to the output end of any stage of the transmission module 210, the signal output end ST connected to the input end of the transmission module 210 outputs the first detection signal TP. The detection signal is transmitted layer by layer to the multi-layer chip layer, and the circuit structure used is simple, which can improve the effective utilization rate of the chip and reduce the cost.

[0093] like Figure 8 As shown, when the input module 100 includes a first trigger 101 and an AND gate unit 102, the input end of the first trigger 101 is connected to the first control signal TE, and the clock end is connected to the clock signal; the first input end of the AND gate unit 102 is connected to the first control signal TE, and the second input end is connected to the non-output end of the first trigger 101, step S710 includes:

[0094] Step S711, the first flip-flop 101 outputs a first trigger signal to the second input terminal of the AND gate unit 102 in response to the first control signal TE and the clock signal;

[0095] In step S712 , the AND gate unit 102 outputs a first detection signal TP to an input end of the first-stage transmission module 210 in the transmission chain 200 according to the first control signal TE and the first trigger signal.

[0096] like Fig. 9 As shown, the transfer module 210 includes a second trigger 211 and a third trigger 212, the input end of the second trigger 211 is connected to the first detection signal TP, and the clock end is connected to the clock signal; the input end of the third trigger 212 is connected to the output end of the second trigger 211, and the clock end is connected to the clock signal, and step S720 includes:

[0097] Step S721, the second trigger 211 in the previous stage transfer module 210 transmits the first detection signal TP to the third trigger 212 in the transfer module 210 according to the first detection signal TP and the clock signal;

[0098] In step S722 , the third flip-flop 212 in the previous stage transfer module 210 transmits the first detection signal TP to the second flip-flop 211 in the next stage transfer module 210 according to the first detection signal TP and the clock signal.

[0099] The previous stage transmission module 210 and the next stage transmission module 210 are two adjacent transmission modules 210 , and the transmission module 210 into which the detection signal first flows is the previous stage transmission module 210 .

[0100] Further, the signal transmission circuit also includes a mode selection module 300, a first input end of the mode selection module 300 is connected to the first detection signal, a second input end is connected to the second detection signal TF, a control end is connected to the first control signal TE, a first output end is connected to the input end of the transmission module 210, and is used to transmit the first detection signal TP to the input end of the transmission module 210 under the control of the first control signal TE, and a second output end is connected to the output end of the transmission module 210, and is used to transmit the second detection signal TF to the output end of the transmission module 210 under the control of the first control signal TE. At this time, the signal transmission method may also include:

[0101] In step S740 , the mode selection unit selects to output the first detection signal TP or the second detection signal TF according to the first control signal TE.

[0102] When the first control signal TE is at a high level, the first switch unit 310 is turned on, the second switch unit 320 is turned off, and the first output end of the mode selection module 300 outputs the first detection signal TP; when the first control signal TE is at a low level, the first switch unit 310 is turned off, the second switch unit 320 is turned on, and the second output end of the mode selection module 300 outputs the second detection signal TF.

[0103] The exemplary embodiment of the present disclosure also provides an integrated circuit, including the above-mentioned signal transmission circuit. Of course, in practical applications, the integrated circuit also includes other components such as through silicon via detection circuits, capacitors, resistors, etc., which are all prior art and will not be described in detail in the embodiment of the present disclosure.

[0104] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0105] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0106] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0107] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A signal transmission circuit, characterized in that: The signal transmission circuit comprises: An input module, configured to generate a first detection signal in response to a first control signal and a clock signal; A transmission chain, comprising a plurality of transmission modules connected in series, wherein adjacent transmission modules in the transmission chain are connected via through silicon vias, wherein the transmission module at the first end of the transmission chain is connected to the input module and receives the first detection signal, and wherein the plurality of transmission modules transmit the first detection signal stage by stage in response to a clock signal; A plurality of signal output terminals, wherein the input terminal of each level of the transmission module is correspondingly connected to a signal output terminal; A first detection through silicon via string, comprising a plurality of through silicon vias connected in series, for transmitting the first control signal from the top chip layer to the base chip layer, wherein the upper end of the first detection through silicon via string is used to receive the first control signal, and the lower end is connected to the input module; A mode selection module, wherein a first input end is connected to the first detection signal, a second input end is connected to the second detection signal, a control end is connected to the first control signal, a first output end is connected to the input end of the transmission module, and is used to transmit the first detection signal to the input end of the transmission module under the control of the first control signal, a second output end is connected to the output end of the transmission module, and is used to transmit the second detection signal to the output end of the transmission module under the control of the first control signal, the first detection signal and the second detection signal are transmitted to adjacent chip layers through the same through silicon via, and the second detection signal is respectively connected to the multiple signal output ends; The mode selection module comprises: A first switch unit, a first end of which is connected to the output end of the input module, a second end of which is connected to the input end of the transmission module, and a control end of which is connected to the first control signal; The second switch unit has a first end connected to the second detection signal, a second end connected to the output end of the transmission module, and a control end connected to the first control signal.

2. The signal transmission circuit according to claim 1, characterized in that: The input module comprises: A first trigger, an input terminal of which is connected to the first control signal, and a clock terminal of which is connected to a clock signal; An AND gate unit, wherein a first input terminal is connected to the first control signal, and a second input terminal is connected to the non-output terminal of the first trigger.

3. The signal transmission circuit according to claim 1, characterized in that: The transmission module comprises: A second trigger, an input terminal of which is connected to the first detection signal, and a clock terminal of which is connected to the clock signal; The third trigger has an input terminal connected to the output terminal of the second trigger, and a clock terminal connected to the clock signal.

4. The signal transmission circuit according to claim 3, characterized in that: Two adjacent transfer modules in the transfer chain are connected via a through silicon via, wherein the output end of the third trigger of the first transfer module is connected to the first end of the through silicon via, and the input end of the second trigger of the other transfer module is connected to the second end of the through silicon via.

5. The signal transmission circuit according to claim 1, characterized in that: The input module is arranged on the substrate chip layer of the integrated circuit, and the transmission module is arranged on each chip layer of the integrated circuit.

6. The signal transmission circuit according to claim 1, characterized in that: The first switch unit is an N-type metal oxide semiconductor field effect transistor, and the second switch unit is a P-type metal oxide semiconductor field effect transistor.

7. A signal transmission circuit, characterized in that: The signal transmission circuit comprises: An input module, configured to generate a first detection signal in response to a first control signal and a clock signal; A transmission chain, comprising a plurality of transmission modules connected in series, wherein adjacent transmission modules in the transmission chain are connected via through silicon vias, wherein the transmission module at the first end of the transmission chain is connected to the input module and receives the first detection signal, and wherein the plurality of transmission modules transmit the first detection signal stage by stage in response to a clock signal; A plurality of signal output terminals, wherein the input terminal of each level of the transmission module is correspondingly connected to a signal output terminal; A first detection through silicon via string, comprising a plurality of through silicon vias connected in series, for transmitting the first control signal from the top chip layer to the base chip layer, wherein the upper end of the first detection through silicon via string is used to receive the first control signal, and the lower end is connected to the input module; A mode selection module, wherein a first input end is connected to the first detection signal, a second input end is connected to the second detection signal, a control end is connected to the first control signal, a first output end is connected to the input end of the transmission module, and is used to transmit the first detection signal to the input end of the transmission module under the control of the first control signal, a second output end is connected to the output end of the transmission module, and is used to transmit the second detection signal to the output end of the transmission module under the control of the first control signal, the first detection signal and the second detection signal are transmitted to adjacent chip layers through the same through silicon via, and the second detection signal is respectively connected to the multiple signal output ends; The mode selection module comprises: A first inverter, an input terminal of which is connected to a first control signal; A second inverter, an input end of which is connected to an output end of the first inverter; A first switch unit, wherein a first end is connected to the first detection signal, a second end is connected to the input end of the transmission module, a first control end is connected to the output end of the first inverter, and a second control end is connected to the output end of the second inverter; a second switch unit, wherein a first end is connected to the second detection signal, a second end is connected to the output end of the transmission module, a first control end is connected to the output end of the second inverter, and a second control end is connected to the output end of the first inverter; Wherein, the first switch unit and the second switch unit are complementary metal oxide semiconductor transmission gates.

8. A signal transmission circuit, characterized in that: The signal transmission circuit comprises: An input module, configured to generate a first detection signal in response to a first control signal and a clock signal; A transmission chain, comprising a plurality of transmission modules connected in series, wherein adjacent transmission modules in the transmission chain are connected via through silicon vias, wherein the transmission module at the first end of the transmission chain is connected to the input module and receives the first detection signal, and wherein the plurality of transmission modules transmit the first detection signal stage by stage in response to a clock signal; A plurality of signal output terminals, wherein the input terminal of each level of the transmission module is correspondingly connected to a signal output terminal; A first detection through silicon via string, comprising a plurality of through silicon vias connected in series, for transmitting the first control signal from the top chip layer to the base chip layer, wherein the upper end of the first detection through silicon via string is used to receive the first control signal, and the lower end is connected to the input module; A multi-level mode selection module is provided in each chip layer of the integrated circuit.

9. The signal transmission circuit according to claim 8, characterized in that: The signal transmission circuit further includes: The second detection TSV string includes a plurality of TSVs connected in series and is used to provide a first control signal for the multi-stage mode selection modules.

10. A signal transmission method, used in the signal transmission circuit according to any one of claims 1 to 9, characterized in that: include: The input module responds to the first control signal and the clock signal, and outputs the first detection signal to the input end of the first-stage transmission module in the transmission chain, where the first-stage transmission module is the transmission module in the transmission chain connected to the input module; The multi-stage transmission module transmits the first detection signal sequentially along the transmission chain in response to the clock signal; When the first detection signal is transmitted to the output end of any level of transmission module, the signal output end connected to the input end of the transmission module outputs the first detection signal.

11. The signal transmission method according to claim 10, characterized in that: The input module responds to the first control signal and the clock signal, outputs the first detection signal to the input end of the first stage transmission module in the transmission chain, including: The first trigger outputs a first trigger signal to the second input terminal of the AND gate unit in response to the first control signal and the clock signal; The AND gate unit outputs a first detection signal to an input end of a first-stage transmission module in a transmission chain according to the first control signal and the first trigger signal.

12. The signal transmission method according to claim 10, characterized in that: The multi-stage transmission module sequentially responds to the clock signal and sequentially transmits the first detection signal along the transmission chain, including: The second trigger in the previous stage transmission module transmits the first detection signal to the third trigger in the transmission module according to the first detection signal and the clock signal; The third trigger in the previous stage transfer module transmits the first detection signal to the second trigger in the next stage transfer module according to the first detection signal and the clock signal.

13. The signal transmission method according to claim 10, characterized in that: The signal transmission method further includes: The mode selection unit selects to output the first detection signal or the second detection signal according to the first control signal.

14. An integrated circuit, characterized in that: The invention comprises the signal transmission circuit as described in any one of claims 1 to 9.

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