Memory device using semiconductor element

Abstract

In the present invention, a plurality of dynamic flash memory cells are arranged in a matrix on a substrate, first dynamic flash memory cells and second dynamic flash memory cells overlap each other in a vertical direction or a horizontal direction of the substrate and control a voltage applied to a selection gate line common to each thereof, a plate line, a bit line, and an independent first source line and a second source line, and perform data erase operation of the first and second dynamic flash memory cells, data write operation in either the first or second dynamic flash memory cells, data write-protect operation in the other, and data read operation in either the first or second dynamic flash memory cells.

Description

Memory device using semiconductor elements

[0001] The present invention relates to a memory device using semiconductor elements.

[0002] In recent years, with the development of LSI (Large Scale Integration) technology, there has been a demand for higher integration and higher performance of memory elements.

[0003] Advances are being made in increasing the density and performance of memory elements, including dynamic random access memories (DRAMs) using SGTs (surrounding gate transistors; see Patent Literature 1 and Non-Patent Literature 1) as selection transistors and connected to capacitors, phase change memories (PCMs) using variable resistance elements (see Non-Patent Literature 3), resistive random access memories (RRAMs) (see Non-Patent Literature 4), and magneto-resistive random access memories (MRAMs) that change resistance by changing the direction of magnetic spins using a current (see Non-Patent Literature 5).

[0004] There are also DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of a single MOS transistor without a capacitor. In a DRAM memory cell composed of a single MOS transistor, for example, a source-drain current of an N-channel MOS transistor generates holes and electrons in the channel by impact ionization, and some or all of the holes are retained in the channel to write logical data "1." Then, the holes are removed from the channel to write logical data "0." In a memory cell, a "1"-programmed memory cell and a "0"-programmed memory cell randomly exist for a common selected word line. When an on-voltage is applied to a selected word line, the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates significantly due to capacitive coupling between the gate electrode and the channel. The challenges for this memory cell are to improve the operating margin reduction caused by the floating body channel voltage fluctuation and the degradation of data retention characteristics caused by the removal of some of the holes, which are signal charges accumulated in the channel.

[0005] There is also a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 3 and 4 and Non-Patent Document 11). In these elements, the floating body channels of the two MOS transistors are separated by an N-type transistor, which serves as a source or drain. + The N layer is formed in contact with the insulating layer on the substrate side. +The floating body channels of the two MOS transistors are electrically isolated by the layer. The group of holes, which are the signal charge, is accumulated only in the floating body channel of one of the MOS transistors. The other MOS transistor acts as a switch for reading out the group of holes of the signal accumulated in the other MOS transistor. In this memory cell, the group of holes, which are the signal charge, is accumulated in the channel of one MOS transistor, so as with the memory cell consisting of one MOS transistor described above, there are issues to be addressed, such as improving the reduced operating margin or improving the reduced data retention characteristics caused by the removal of some of the group of holes, which are the signal charge accumulated in the channel.

[0006] Also, there is a dynamic flash memory (DFM) cell 111 shown in Fig. 3, which is composed of a MOS transistor and does not have a capacitor (see Patent Document 5 and Non-Patent Document 12). As shown in Fig. 3(a), a floating body semiconductor body 102 is provided on an SiO2 layer 101 of an SOI substrate. N-type semiconductor layers 102 connected to a source line SL are provided at both ends of the floating body semiconductor body 102. + layer 103 and the N connected to the bit line BL + layer 104. + a first gate insulating layer 109a connected to the layer 103 and covering the floating body semiconductor body 102; + There is a second gate insulating layer 109b that is connected to the layer 104 and the first gate insulating layer 109a via a slit insulating film 110 and covers the floating body semiconductor body 102. There is a first gate conductor layer 105a that covers the first gate insulating layer 109a and is connected to the plate line PL, and there is a second gate conductor layer 105b that covers the second gate insulating layer 109b and is connected to the word line WL. There is a slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of the DFM. Note that the source line SL is connected to the N + layer 104, and the bit line BL is connected to N + It may be configured to connect to layer 103 .

[0007] As shown in FIG. 3(a), for example, N + Zero voltage on layer 103, N + A positive voltage is applied to layer 104, causing the first N-channel MOS transistor region, consisting of floating body semiconductor body 102 covered with first gate conductor layer 105a, to operate in the saturation region, and the second N-channel MOS transistor region, consisting of floating body semiconductor body 102 covered with second gate conductor layer 105b, to operate in the linear region. As a result, no pinch-off point exists in the second N-channel MOS transistor region, and an inversion layer 107b is formed over the entire surface. This inversion layer 107b formed below second gate conductor layer 105b connected to word line WL essentially functions as the drain of the first N-channel MOS transistor region. As a result, the electric field is maximized in the boundary region of the semiconductor body between the first and second N-channel MOS transistor regions, causing impact ionization in this region. 3B, the memory write operation is performed by removing the electrons from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state becomes logical storage data "1."

[0008] As shown in FIG. 3(c), for example, a positive voltage is applied to the plate line PL, zero voltage is applied to the word line WL and bit line BL, and a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor matrix 102, thereby performing an erase operation. This state results in logical memory data "0." Then, by setting the voltage applied to the first gate conductor layer 105a connected to the plate line PL to a value higher than the threshold voltage for logical memory data "1" and lower than the threshold voltage for logical memory data "0," as shown in FIG. 3(d), no current flows even when the voltage on the word line WL is increased when reading logical memory data "0." This characteristic significantly expands the operating margin compared to a DRAM memory cell composed of a single MOS transistor without a capacitor. In this memory cell, the channels of the first and second N-channel MOS transistor regions, each having a gate formed by the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102. This significantly suppresses voltage fluctuations in the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL. This significantly improves the problems of the aforementioned memory cell, such as a reduction in operating margin and a reduction in data retention characteristics due to the removal of a portion of the hole group, which is the signal charge accumulated in the channel. Further improvements in the characteristics of this memory element will be required in the future.

[0009] Also known is a dynamic flash memory cell 8 having three gates and composed of MOS transistors without a capacitor, as shown in FIG. 4 (see Patent Document 6 and Non-Patent Document 13). A silicon semiconductor pillar (Si pillar) 2 is located on a substrate 1. The Si pillar 2 is then comprised of, from bottom to top, an N+ layer 3a, a P layer 7, and an N+ layer 3b. The P layer 7 between the N+ layers 3a and 3b forms a channel region 7a. Surrounding the Si pillar 2 are, from bottom to top, a first gate insulating layer 4a, a second gate insulating layer 4b, and a third gate insulating layer 4c. A first gate conductor layer 5a surrounds the first gate insulating layer 4a, a second gate conductor layer 5b surrounds the second gate insulating layer 4b, and a third gate conductor layer 5c surrounds the third gate insulating layer 4c. The first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6a, and the second gate conductor layer 5b and the third gate conductor layer 5c are separated by an insulating layer 6b. This forms a dynamic flash memory cell consisting of the N+ layers 3a and 3b, the P layer 7, the first gate insulating layer 4a, the second gate insulating layer 4b, the third gate insulating layer 4c, the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c. A feature of this structure is that the recombination of holes stored in the channel region 7a between the N+ layers 3a and 3b is significantly suppressed in the N+ layers 3a and 3b by utilizing the electrical shielding between the first gate conductor layer 5a and the third gate conductor layer 5c. As a result, the retention of data "1" is significantly improved. The dynamic flash memory cells can be arranged horizontally on the substrate 1, and multiple memory cells can be stacked vertically to increase the integration density (see Patent Document 8). Also, the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c can be divided (see, for example, Patent Document 9 and Non-Patent Document 18).

[0010] Also, a thyristor RAM memory with three gates and no capacitor has been announced (see Non-Patent Documents 14 and 15). This thyristor memory has the advantage that the equivalent memory cell size can be reduced by stacking multiple layers, but because it uses a thyristor as the read mechanism, there is a problem that the read current value fluctuates significantly, resulting in high power consumption.

[0011] Also, a 1T1C DRAM cell with a stackable capacitor has been announced (see Non-Patent Documents 16 and 17). However, the aspect ratio of the capacitor in a DRAM memory cell is as large as 50. Therefore, if the DRAM cell is placed horizontally, the area of ​​this capacitor is very large. Therefore, to obtain an economical memory cell area equivalent to that of a current vertically placed DRAM cell, for example, 200 layers must be stacked.

[0012] Another proposal is to stack DRAM memory cells each consisting of a single MOS transistor without a capacitor (see Patent Document 7). This structure presents a problem: when an on-voltage is applied to the selected word line, the floating body channel voltage of the selected memory cell connected to the selected word line fluctuates significantly due to capacitive coupling between the gate electrode and the channel. Furthermore, as shown in Fig. 1F of Patent Document 7, for example, a common floating body FB1 is controlled by two word lines WL0 and WL1, which causes a selectivity problem. As a workaround, a technique is shown in Fig. 1G in which alternate word lines are grounded as shield lines, but this method halves memory capacity and doubles costs.

[0013] JP-A-2-188966 JP-A-3-171768 US2008 / 0137394 A1US2003 / 0111681 A1 Patent No. 7057032 US2023 / 0186966 A1US2023 / 0106561 A1US2022 / 0367681 A1US2022 / 0367473 A1

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[0015] In dynamic flash memory cells, there is a demand for memory cells with smaller effective cell sizes.

[0016] In order to achieve the above object, a first invention of the present application provides a semiconductor memory device comprising: a plurality of semiconductor memory cells, including a first memory cell and a second memory cell, arranged in a matrix on a substrate; the first memory cell includes a first semiconductor body extending in a first direction parallel to the substrate; the second memory cell includes a second semiconductor body separated from the first semiconductor body in a vertical or horizontal direction, and overlapping with the first semiconductor body in a plan view when separated in the vertical direction, and overlapping with the first semiconductor body in a cross-sectional view when separated in the horizontal direction; a first impurity region and a second impurity region connected to both ends of the first semiconductor body, respectively; a third impurity region and a fourth impurity region connected to both ends of the second semiconductor body, respectively; a first gate insulating layer in contact with a side of the first semiconductor body facing the second semiconductor body; and a second gate insulating layer in contact with a side of the second semiconductor body facing the first semiconductor body, the gate insulating layer is provided with a first gate conductor layer and a second gate conductor layer that are in contact with the first and second gate insulating layers, are aligned in the first direction, and are separated from each other; a data write operation is performed by controlling voltages applied to the first to fourth impurity regions and the first to second gate conductor layers, so that some or all of the holes or electrons that are majority carriers generated by an impact ionization phenomenon caused by a current flowing in one of the first or second semiconductor body or a gate-induced drain leakage current remain in the first or second semiconductor body; and a data write inhibit operation is performed during the data write period, so that some or all of the holes or electrons that are majority carriers do not remain in the other of the first or second semiconductor body without causing an impact ionization phenomenon or causing a gate-induced drain leakage current to flow in the other of the first or second semiconductor body; a data erase operation for extracting the remaining hole group or electron group from one or both of the first and second impurity regions and one or both of the third and fourth impurity regions; and a data read operation for causing or not causing a current to flow in the first or second semiconductor body depending on the stored data in a data write state or a data erase state in one of the first or second semiconductor body.The present invention is characterized by carrying out the following.

[0017] A second invention of the present application is characterized in that, in the above-mentioned first invention, the first impurity region is connected to a first source line, the third impurity region is connected to a second source line, the second and fourth impurity regions are connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a first select gate line, and the other is connected to a plate line, and the data erase operation, the data write operation, and the data read operation are performed by controlling voltages applied to the first and second source lines, the bit line, the plate line, and the select gate line.

[0018] A third invention of the present application is characterized in that in the second invention, the same voltage is applied to the first or second source line and the bit line in the data write inhibit operation.

[0019] A fourth invention of the present application is characterized in that in the second invention, the same voltage is applied to the first or second source line and the bit line in the data read operation.

[0020] The fifth invention of the present application is characterized in that, in the second invention described above, the first and second semiconductor bodies overlap in a cross-sectional view of the substrate, and the plate line and the select gate line are arranged perpendicular to and parallel to the substrate in a planar view.

[0021] A sixth invention of the present application is characterized in that, in the second invention described above, the bit lines are orthogonal to the plate lines and the select gate lines in a vertical cross-sectional view relative to the substrate, and the first and second source lines are arranged perpendicularly to the plate lines and the select gate lines in a plan view.

[0022] The seventh invention of the present application is characterized in that, in the above-mentioned second invention, the first and second semiconductor bodies overlap in a planar view of the substrate, and the plate line and the select gate line are arranged perpendicular to and parallel to the substrate in a cross-sectional view.

[0023] The eighth invention of the present application is characterized in that, in the second invention described above, the bit lines are orthogonal to the plate lines and the select gate lines in a plan view relative to the substrate, and the first and second source lines are arranged perpendicular to and parallel to the plate lines and the select gate lines in a cross-sectional view.

[0024] A ninth invention of the present application is characterized in that, in the second invention described above, the first select gate line comprises a separated second select gate line and a third select gate line, one of the first gate conductor layer and the second gate conductor layer is divided into two, one of the divided gate conductor layers is connected to the second select gate line and the other is connected to the third select gate line, the undivided first gate conductor layer or the second gate conductor layer is connected to the plate line, and the two gate conductor layers connected to the second select gate line and the third select gate line are disposed on both sides of the gate conductor layer connected to the plate line.

[0025] A tenth aspect of the present invention is characterized in that, in the ninth aspect, the channel length of the gate conductor layer connected to the plate line is longer than the channel lengths of the gate conductor layers connected to the second select gate line and the third select gate line.

[0026] The eleventh invention of the present application is characterized in that, in the first invention described above, a plurality of semiconductor memory cells are arranged in a matrix on a substrate to form memory blocks, and a plurality of the memory blocks are selected during at least one of the data write operation, the data erase operation, and the data read operation.

[0027] FIG. 1 is a structural diagram of a memory cell according to the first embodiment. FIG. 2 is a structural diagram of a memory cell according to the first embodiment. FIG. 3 is a structural diagram of a memory cell according to the first embodiment. FIG. 4 is a structural diagram of a memory cell according to the first embodiment. FIG. 5 is a structural diagram of a memory cell according to the first embodiment. FIG. 6 is an equivalent circuit diagram of a memory cell according to the first embodiment. FIG. 7 is an operational waveform diagram of a memory cell according to the first embodiment. FIG. 8 is an operational waveform diagram of a memory cell according to the first embodiment. FIG. 9 is a diagram for explaining a conventional dynamic flash memory cell which does not have a capacitor and is composed of MOS transistors. FIG. 10 is a diagram for explaining a conventional dynamic flash memory cell which does not have a capacitor and is composed of MOS transistors and has three gates.

[0028] The structure and driving method of a memory device using semiconductor elements (hereinafter referred to as a dynamic flash memory) according to the present invention will be described below with reference to the drawings.

[0029] First Embodiment The structure, operation mechanism, and manufacturing method of a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference to FIGS. 1A to 1G. A structure in which a bit line 18 (BL) is disposed vertically relative to a substrate 10, and first and second select gate lines 11 (SG1) and 13 (SG2) and a plate line 12 (PL) are disposed horizontally will be described with reference to FIGS. 1G. A structure in which a bit line 18a (BL) is disposed horizontally relative to a substrate, and first and second select gate lines 11a (SG1) and 13a (SG2) and a plate line 12a (PL) are disposed vertically relative to a substrate will be described with reference to FIGS. 2A to 2C. An equivalent circuit diagram of a dynamic flash memory cell according to the first embodiment of the present invention, in which four layers are stacked on a substrate 10 in plan view or cross section, as well as data write operations, data write inhibit operations, and data read operations will be described.

[0030] FIG. 1A shows a bird's-eye view of a dynamic flash memory cell structure according to a first embodiment of the present invention. FIG. 1B(a) shows a plan view of the dynamic flash memory cell structure according to the first embodiment of the present invention, and FIG. 1B(b) and FIG. 1B(c) show cross-sectional views taken along lines X-X' and Y-Y' shown in FIG. 1B(a), respectively. A first semiconductor body 14 (an example of the "first semiconductor body" in the claims) of a P layer extends in a first direction (an example of the "first direction" in the claims) parallel to a substrate 10 (an example of the "substrate" in the claims). Patent Document 8 is a document relating to a structure in which dynamic flash memory cells are provided horizontally relative to the substrate 10. At both ends of the first semiconductor body 14, N + layer 15 (an example of the "first impurity region" in the claims), and N + A second semiconductor body 19 (an example of the "second semiconductor body" in the claims) of the P layer and a second semiconductor body 20 (an example of the "second semiconductor body" in the claims) of the N layer are provided on the upper side of the first semiconductor body 14. + layer 20 (an example of the "third impurity region" in the claims), and N + The first semiconductor body 14 and the second semiconductor body 19 have a first gate insulating film 23 (an example of the "first gate insulating film" in the claims) and a second gate insulating film 24 (an example of the "second gate insulating film" in the claims) formed around them.

[0031] The first gate conductor layer 11 (an example of the "first gate conductor layer" in the claims), the second gate conductor layer 12 (an example of the "second gate conductor layer" in the claims), and the third gate conductor layer 13 (an example of the "third gate conductor layer" in the claims) are separated from one another and contact the first side (an example of the "first side" in the claims) and the second side (an example of the "second side" in the claims) of the first gate insulating layer 23 and the second gate insulating layer 24, respectively. Although FIGS. 1A to 1C, 1F and 1G, and 2A and 2B show three gate conductor layers, i.e., the first to third gate conductor layers, two gate conductor layers may be used. As will be described later, either the first gate conductor layer 11 or the third gate conductor layer 13 may be omitted, as shown in FIGS. 1D and 1E, respectively.

[0032] The first impurity region 15 and the third impurity region 20 are connected to a first source line 17 (an example of a "first source line" in the claims) SL0 and a second source line 22 (an example of a "second source line" in the claims) SL1, respectively, and the second impurity region 16 and the fourth impurity region 21 are connected to a bit line 18 (an example of a "bit line" in the claims). The first gate conductor layer 11 is connected to a second select gate line SG1 (an example of a "second select gate line" in the claims), the second gate conductor layer 12 is connected to a plate line PL (an example of a "plate line" in the claims), and the third gate conductor layer 13 is connected to a third select gate line SG2 (an example of a "third select gate line" in the claims).

[0033] The five terminals of the first memory cell (an example of a "first memory cell" in the claims) are composed of a second select gate line SG1, a plate line PL, a third select gate line SG2, a first source line SL0, and a bit line BL, and the five terminals of the second memory cell (an example of a "second memory cell" in the claims) are composed of a second select gate line SG1, a plate line PL, a third select gate line SG2, a second source line SL1, and a bit line BL.

[0034] For example, when a first memory cell is selected, the first source line SL0 applies the ground voltage Vss, a positive voltage is applied to the bit line BL, and voltages applied to the plate line PL, the second select gate line SG1, and the third select gate line SG2 are controlled to perform a data write operation (an example of a "data write operation" in the claims) or a data read operation (an example of a "data read operation" in the claims) for the first memory cell. Meanwhile, the second source line SL1 applies the same voltage as the bit line BL. As a result, while the first memory cell is performing a data write operation, the second memory cell is in a data write inhibit operation (an example of a "data write inhibit operation" in the claims). Furthermore, while the first memory cell is performing a data read operation, the second memory cell does not perform a data read operation. In addition, the voltages applied to the first source line SL0, the second source line SL1, the bit line BL, the plate line PL, the second select gate line SG1, and the third select gate line SG2 are controlled to perform a data erase operation (an example of a "data erase operation" in the claims) on the first memory cell and the second memory cell.

[0035] 1B, the first to third gate conductor layers 11, 12, and 13 are common gate conductor layers for two dynamic flash memory cells having channels in the first semiconductor body 14 and the second semiconductor body 19. The first gate insulating film 23 may be provided at least between the first to third gate conductor layers 11, 12, and 13 and the first semiconductor body 14. Similarly, the second gate insulating film 24 may be provided at least between the first to third gate conductor layers 11, 12, and 13 and the second semiconductor body 19.

[0036] FIG. 1A shows a case where the channel length (length in the X-X' direction) of the plate line PL is the same as the lengths of the select gate lines SG1 and SG2. In contrast, as shown in FIG. 1C, the channel length (length in the X-X' direction) of the plate line PL may be longer than the select gate lines SG1 and SG2. This allows for better control of the plate line voltage relative to the floating body of the memory cell. Furthermore, depending on the channel length (gate length) of the plate line, a larger number of holes can be held in the floating body in the "1" write state.

[0037] FIG. 1D shows an example in which the second select gate line SG1 adjacent to the first source line SL0 and the second source line SL1 is eliminated. That is, the structure is composed of a third select gate line SG2, which is an undivided first select gate line (an example of the "first select gate line" in the claims), and a plate line PL. FIG. 1E shows an example in which the third select gate line SG2 adjacent to the bit lines BL0 and BL1 is eliminated. That is, the structure is composed of a second select gate line SG1, which is an undivided first select gate line, and a plate line PL. This allows for a smaller cell size of the dynamic flash memory cell. It also increases the cell current and enables higher speeds. While eliminating one select gate reduces data retention, it provides better control of the plate line voltage relative to the floating body of the memory cell. Furthermore, depending on the gate length of the plate line, more holes can be held in the floating body in the "1" write state. The choice of which structure to use depends on the application in which the dynamic flash memory cell is used.

[0038] 1F shows an example of stacking three dynamic flash memory cells. A third semiconductor body 28 is located above the second semiconductor body 19. Between the second semiconductor body 19 and the third semiconductor body 28, there are a first gate conductor layer 25 connected to a select gate line SG11, a second gate conductor layer 26 connected to a plate line PL1, and a third gate conductor layer 27 connected to a select gate line SG21. N +There are layers 29 and 30. + Layer 29 is connected to source line 31 (SL3), and N + The layer 30 is connected to a bit line 18 (BL). The first source line 17 (SL0), the second source line 22 (SL1), and the third source line 31 (SL2) are each selected by a decoder circuit (not shown).

[0039] 1G shows an example in which the second select gate line SG1, plate line PL, third select gate line SG2, and source line SL are arranged vertically relative to the substrate 10, and the bit line BL is arranged horizontally. In other words, this corresponds to the dynamic flash memory cell in which the dynamic flash memory cell shown in FIGS. 1A to 1F is rotated 90 degrees toward the depth of the drawing relative to the substrate 10. Either one can be selected depending on the application, but the main features of the dynamic flash memory cell in FIG. 1G are the same as those of the dynamic flash memory cell shown in FIGS. 1A to 1F.

[0040] 2A shows an equivalent circuit diagram of a dynamic flash memory cell according to the first embodiment of the present invention, in which four memory cells Cell0 to Cell3 are stacked on a substrate in a plan view or cross-sectional view. FIG. 2B shows waveforms of data write, data write inhibit, and data read operations for the four memory cells Cell0 to Cell3. At a first time T1, the bit line BL, the second select gate line SG11, the plate line PL1, the third select gate line SG21, and the second source line SL2 are respectively changed from ground voltage Vss to first voltage V1, second voltage V2, third voltage V3, fourth voltage V4, and first voltage V1, and the second source line SL1 is set to ground voltage Vss. This selects the second memory cell Cell1, and a data write or data read operation is performed in the second memory cell Cell1.

[0041] In addition, in the third memory cell Cell2, when the third source line SL2 is applied with the first voltage V1, which is the same voltage as the bit line BL, the third memory cell Cell2 is prohibited from being written while the second memory cell Cell1 is being written. Also, when the second memory cell Cell1 is being read, the third memory cell Cell2 is not read. In other words, multiple selection of the second memory cell Cell1 and the third memory cell Cell2 is prohibited.

[0042] 2C shows a bird's-eye view of the equivalent circuit diagram of FIG. 2B, with the bit line arrays increased in the depth direction to BLn. Here, for example, if n in BLn is 1023, the number of bit line arrays is 1024. A sense amplifier circuit (not shown) simultaneously writes data to these bit line arrays, and a sense amplifier circuit simultaneously reads data from these bit line arrays.

[0043] 1A to 1G and 2A to 2C are described using components having a rectangular vertical cross section, these vertical cross sections may be other shapes, such as trapezoidal, and the vertical cross sections of the components may be different. This also applies to other embodiments.

[0044] Also, N of the dynamic flash memory cells shown in FIGS. 1A and 1B + Dynamic flash memory operation is also possible in a structure in which the conductivity of the semiconductor bodies of layers 15, 16, 20, and 21 and the P layers 14 and 19 are reversed. In this case, in the N-type semiconductor body, the majority carriers are electrons. Therefore, electrons generated by impact ionization are stored in the floating body, setting the "1" state. Also, dynamic flash memory cells using a P-type semiconductor body and an N-type semiconductor body may be formed on the same substrate. This is the same for other embodiments.

[0045] Also, N of the dynamic flash memory cells shown in FIGS. 1A and 1B +A junctionless structure may be used in which the conductivity of the semiconductor bases of the layers 15, 16, 20, and 21 is the same as that of the P layers 14 and 19. This also applies to the other embodiments.

[0046] 1A to 1G and 2A to 2C may be arranged in a matrix on a substrate to form memory blocks, and multiple memory blocks may be selected during at least one of a data write operation, a data erase operation, and a data read operation. As a result, the number of memory cells selected from the multiple memory blocks increases, and data write, erase, and read times per cell can be increased.

[0047] This embodiment has the following features. (Features) In the dynamic flash memory cell according to the embodiment of the present invention, the two stacked memory cells share the second select gate line SG1, the plate line PL, and the third select gate line SG2. This reduces the aspect ratio of the stacked memory cells, allowing for a larger number of memory cells to be stacked, thereby reducing costs. This also applies to the memory cells shown in FIGS. 1C to 2C. Furthermore, by independently operating the first source line SL0 and the second source line SL1 of the two stacked memory cells Cell0 and Cell1, while one memory cell is performing a data write operation, the other memory cell is in a data write inhibit operation. Furthermore, while one memory cell is performing a data read operation, the other memory cell is not performing a data read operation.

[0048] (Other Embodiments) The gate conductor layer connected to the plate line may be a single layer or a combination of multiple conductor material layers. Similarly, the gate conductor layer connected to the second and third select gate lines may be a single layer or a combination of multiple conductor material layers. Furthermore, the outer side of the gate conductor layer may be connected to a wiring metal layer such as W. This also applies to other embodiments of the present invention.

[0049] Furthermore, the voltage applied to the plate line PL in the description of the embodiment may be a fixed voltage of, for example, 0 V, regardless of the operation mode. The voltage applied to the plate line PL may be a fixed voltage or a time-varying voltage, as long as the voltage satisfies the conditions for dynamic flash memory operation.

[0050] In addition, in FIG. 1, the first impurity region N + Layer 15 and / or second impurity region N + An N-type or P-type impurity region may be present between the layer 16 and the first semiconductor matrix P layer 14. This also applies to other embodiments of the present invention.

[0051] Furthermore, the present invention allows for various embodiments and modifications without departing from the broad spirit and scope of the present invention. Furthermore, each of the above-described embodiments is intended to illustrate one example of the present invention and does not limit the scope of the present invention. The above-described embodiments and modifications can be combined as desired. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, they will still fall within the scope of the technical concept of the present invention.

[0052] The memory device using semiconductor elements according to the present invention provides a high-density, high-performance dynamic flash memory.

[0053] 10, 1 Substrate 111, 8 Dynamic flash memory cell 101 SiO2 layer of SOI substrate SL Source line 103, 104, 3a, 3b N + Layer BL Bit line 102 Floating body semiconductor body 109a, 4a First gate insulating layer 110 Slit insulating film 109b, 4b Second gate insulating layer PL Plate line 105a First gate conductor layer WL Word line WL 105b Second gate conductor layer 110 Slit insulating layer 2 Silicon semiconductor pillar (Si pillar) 7 P layer 7a Channel region 4c Gate insulating layer 5a First gate conductor layer 5b Second gate conductor layer 4c Third gate insulating layer 5c Third gate conductor layer 6a Insulating layer 6a 14 First semiconductor body of P layer 19 Second semiconductor body of P layer 15 First impurity region N+ Layer 16 Second impurity region N + Layer 20: Third impurity region N + Layer 21 fourth impurity region N + Layer 23 First gate insulating film 24 Second gate insulating film 11 First gate conductor layer 12 Second gate conductor layer 13 Third gate conductor layer 17, SL0 First source line 22, SL1 Second source line SL2 Third source line SL3 Fourth source line 18, BL Bit lines SG1, SG10, SG11, SG12, SG13 Second select gate lines PL, PL0, PL1, PL2, PL3 Plate lines SG2, SG20, SG21, SG22, SG23 Third select gate lines

Claims

1. A plurality of semiconductor memory cells including a first memory cell and a second memory cell are arranged in a matrix on a substrate, the first memory cell includes a first semiconductor body extending in a first direction parallel to the substrate, and the second memory cell includes a second semiconductor body separated vertically or horizontally from the first semiconductor body, and overlapping with the first semiconductor body in a plan view when separated vertically and overlapping with the first semiconductor body in a cross-sectional view when separated horizontally, a first impurity region and a second impurity region respectively connected to both ends of the first semiconductor body, a third impurity region and a fourth impurity region respectively connected to both ends of the second semiconductor body, a first gate insulating layer in contact with a side of the first semiconductor body facing the second semiconductor body, and a second gate insulating layer in contact with a side of the second semiconductor body facing the first semiconductor body, the gate insulating layer is provided with a first gate conductor layer and a second gate conductor layer which are in contact with the first and second gate insulating layers, are aligned in the first direction, and are separated from each other; a data write operation is performed by controlling voltages applied to the first to fourth impurity regions and the first to second gate conductor layers, so that a part or all of a group of holes or a group of electrons which are majority carriers generated by an impact ionization phenomenon caused by a current flowing in one of the first or second semiconductor body or a gate induced drain leakage current remains in the first or second semiconductor body; and a data write inhibit operation is performed during the data write period, so that an impact ionization phenomenon does not occur in the other of the first or second semiconductor body, or a gate induced drain leakage current does not flow, and a part or all of the group of holes or the group of electrons which are majority carriers does not remain in the first or second semiconductor body; a data erase operation for extracting the remaining hole group or the remaining electron group from one or both of the first and second impurity regions and one or both of the third and fourth impurity regions, and a data read operation for causing or not causing a current to flow in the first or second semiconductor body depending on stored data in a data write state or a data erase state in one of the first or second semiconductor bodies.A memory device using a semiconductor element.

2. A memory device using a semiconductor element as described in claim 1, characterized in that the first impurity region is connected to a first source line, the third impurity region is connected to a second source line, the second and fourth impurity regions are connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a first select gate line and the other is connected to a plate line, and the data erase operation, the data write operation, and the data read operation are performed by controlling voltages applied to the first and second source lines, the bit line, the plate line, and the select gate line.

3. A memory device using a semiconductor element according to claim 2, wherein in the data write inhibit operation, the same voltage is applied to the first or second source line and the bit line.

4. The memory device using the semiconductor element according to claim 2, wherein the same voltage is applied to the first or second source line and the bit line in the data read operation.

5. A memory device using a semiconductor element as described in claim 2, characterized in that the first and second semiconductor bodies overlap in a cross-sectional view of the substrate, and the plate line and the select gate line are arranged perpendicularly and parallel to the substrate in a planar view.

6. A memory device using a semiconductor element as described in claim 2, characterized in that the bit line is perpendicular to the plate line and the select gate line in a vertical cross-sectional view relative to the substrate, and the first and second source lines are arranged perpendicularly in a plan view and parallel to the plate line and the select gate line.

7. A memory device using a semiconductor element as described in claim 2, characterized in that the first and second semiconductor bodies overlap when viewed in a plane of the substrate, and the plate line and the select gate line are arranged perpendicular to and parallel to the substrate when viewed in a cross section.

8. A memory device using a semiconductor element as described in claim 2, characterized in that the bit line is perpendicular to the plate line and the select gate line in a plan view of the substrate, and the first and second source lines are arranged perpendicularly and parallel to the plate line and the select gate line in a cross-sectional view.

9. A memory device using a semiconductor element as described in claim 2, characterized in that the first select gate line is composed of a separated second select gate line and a third select gate line, one of the first gate conductor layer and the second gate conductor layer is divided into two, one of the divided gate conductor layers is connected to the second select gate line and the other is connected to the third select gate line, and the first gate conductor layer or the second gate conductor layer which is not divided is connected to the plate line, and the two gate conductor layers connected to the second select gate line and the third select gate line are arranged on both sides of the gate conductor layer connected to the plate line.

10. A memory device using a semiconductor element as described in claim 9, characterized in that the channel length of the gate conductor layer connected to the plate line is longer than the channel length of the gate conductor layer connected to the second select gate line and the third select gate line.

11. A memory device using a semiconductor element as described in claim 1, characterized in that a plurality of semiconductor memory cells are arranged in a matrix on a substrate to form a memory block, and a plurality of said memory blocks are selected during at least one of the data write operation, the data erase operation, and the data read operation.

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