Display system with automatic bitplane adjustment

Abstract

Displaying an image as a sequence of bit planes can include storing the sequence of bit planes in a buffer. Utilization of the buffer may vary when the image for display is compressed. Images that have less compressibility may generate bit planes that utilize more of the buffer than images that have more compressibility. Some compressed images may not fit into the buffer when the buffer is made small to reduce its power consumed. For these compressed images, the disclosed display can determine which bit planes should be stored to balance a limited buffer size with a decreased quality of the displayed image.

Description

DISPLAY SYSTEM WITH AUTOMATIC BITPLANE ADJUSTMENTCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 587,795, filed on October 4, 2023, which is hereby incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to a display and more specifically to a display configured to display images based on bit planes.BACKGROUND

[0003] Color or grayscale images can be represented as a weighted series (i.e., sequence) of bit planes. To generate a sequence of bit planes, binary numbers are determined from each pixel’s grayscale level. Each binary number has a number of bits corresponding to the bit depth of the display. A bit plane can be generated for each bit of the binary number. A sequence of bit planes can be arranged from a most significant bit plane, which includes a most significant bit (MSB) of the binary number for each pixel, to a least significant bit plane, which includes a least significant bit (LSB) of the binary number for each pixel. Rendering images on a display using bit planes can help reduce the power and size of the display, making these displays useful for mobile and / or body-worn applications.SUMMARY

[0004] A display can adjust the number of bit planes used to render an image based on its compressed size. The adjustability allows for the efficient use of a buffer associated with the display, which can result in it being made smaller to reduce the power consumed by the display.

[0005] In some aspects, the techniques described herein relate to a display including: a preprocessor configured to: receive an image; remove a portion of pixels from the image to generate a compressed image; and determine a data length of the compressed image; and a bitplane generator that receives the compressed image and the data length of the compressed image, the bit-plane generator configured to: generate a sequence of bit planes representing thecompressed image, each bit plane having the data length of the compressed image; compare the data length to a threshold; designate a set of bit planes (i.e., at least one bit plane) as disabled when the data length is greater than the threshold; and disable the set of bit planes designated as disabled from being stored in a buffer so that a partial sequence of bit planes is stored in the buffer without overlapping.

[0006] In some aspects, the techniques described herein relate to a display including: a preprocessor configured to: receive an image including pixels; remove a portion of the pixels in the image to generate a compressed image; and determine a data length of the compressed image; a buffer configured to store a sequence of bit planes representing the compressed image, the buffer divided into segments, the segments having segment lengths that progressively increase from a first segment to a last segment of the buffer; and a bit-plane generator that receives the compressed image and the data length of the compressed image, the bit-plane generator configured to: generate bit planes of the sequence of bit planes, each bit plane of the sequence of bit planes having the data length of the compressed image; compare the data length to thresholds that progressively increase, each threshold being associated with a (different) data segment; and disable at least one bit plane from being stored in the buffer when the data length exceeds at least one of the thresholds so that a partial sequence of bit planes can be stored in the segments without overlap.

[0007] In some aspects, the techniques described herein relate to a method for displaying an image, the method including: receiving an image for display; generating a compressed image; determining a data length of the compressed image; generate a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; comparing the data length to a threshold corresponding to a segment length of a buffer; designating at least one bit plane of the sequence of bit planes as disabled when the data length exceeds the threshold; and not storing the at least one bit plane designating as disabled in the buffer so that a partial sequence of bit planes can be stored in the buffer without overlapping.

[0008] The foregoing illustrative summary, as well as other exemplary objectives and / or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a system block diagram of a display according to a possible implementation of the present disclosure.

[0010] FIG. 2 illustrates a sequence of bit planes for an image according to a possible implementation of the present disclosure.

[0011] FIG. 3 illustrates the contribution of each bit to a binary number representing a grayscale level according to a possible implementation of the present disclosure.

[0012] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure.

[0013] FIG. 5 is a system block diagram illustrating the compression and storage of bit planes in a buffer according to a possible implementation of the present disclosure.

[0014] FIG. 6 illustrates disabling bit planes in a buffer according to first possible implementation of the present disclosure.

[0015] FIG. 7 illustrates approximate bit planes to replace a set of bit planes disabled and not stored in the buffer according toa a possible implementation of the present disclosure.

[0016] FIG. 8 illustrates disabling bit planes in a buffer according to a second possible implementation of the present disclosure.

[0017] FIG. 9 illustrates a subsystem for comparing the data length to a plurality of thresholds according to a possible implementation of the present disclosure.

[0018] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.DETAILED DESCRIPTION

[0019] An image may be rendered using a sequence of bit planes. Each bit plane has a significance based on its corresponding bit in the binary gray scale level of the pixel. More significant bit planes carry more visual information than less significant bit planes. Accordingly, it may be possible to remove low significance bit planes and still render the image with reasonable quality. A buffer memory (e.g., buffer) can store the remaining bit planes so that they can be recalled to render the image on a pixel array by progressively displaying the recalled bit planes at different durations, corresponding to the bit plane’s significance.

[0020] For some applications (e.g., mobile devices), power consumption and physical size are strictly limited. In these applications, it may be desirable to use image compression so that the buffer memory size can be reduced. A technical problem with this approach is that the compression may differ for each image, which can make the buffer too large for highly compressed images, which is an inefficient use of power and size, and not large enough for images that are less compressed, which results in errors as bit planes overlap in the buffer.

[0021] The display of the present disclosure solves this technical problem by adjusting how a sequence of bit planes is stored in the buffer. The adjustment may include disabling at least one of the low significance bit planes from being stored in the buffer when the compressibility of the image is low. This adjustment may reduce the image quality somewhat but prevents data corruption in the buffer. A technical effect of the proposed solution is that a smaller buffer may be used so that the display consumes less power and has a smaller mechanical size. These features facilitate the use of the disclosed display in body-worn devices (e.g., augmented reality glasses, augmented reality goggles, smart watches, smart glasses, etc.).

[0022] FIG. l is a schematic block diagram of a display according to a possible implementation of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., pixel array 120). Each pixel 121 includes a micro-LED configured to generate light while conducting a drive current from a drive current module 140. Each pixel 121 further includes a memory cell (e.g., SRAM) for setting and maintaining the illumination state of a micro-LED as ON or OFF. The state of an SRAM cell of a pixel can be controlled (i.e., set / reset) by a signal (e.g., bit-line signal) transmitted over a column conductor (i.e., bit-line) coupled to the SRAM cell. The SRAM cell of the pixel is coupled to the bit-line based on a signal (e.g., word-line signal) transmitted over a row conductor (i.e., word-line) to the pixel. Accordingly, the display 100 further includes a word-line driver 112 configured to transmit a word-line signal to a word-line (i.e., row) of the pixel array 120. The word-line signal can activate a row so that each pixel in an active row is coupled to its respective bit-line.

[0023] As shown in FIG. 1, the display 100 further includes a bit-line driver 113 configured to transmit bit-line signals to the bit-lines of the pixels in an active row. The bit-line signals may change or maintain the state of the SRAMs in the active row according to an image for display. In a possible implementation, a bit-line signal is a differential signal. In this case, each bit-line may include a positive bit-line (BL+) configured to carry a positive bit-line signal and a negativebit-line configured to carry a negative bit-line signal (BL-). In this differential configuration, the positive bit-line and the negative bit-line may be referred to collectively as the bit-line.

[0024] The display 100 further includes a controller 400 configured to control the operation of the word-line driver 112 and the bit-line driver 113 to render an image on the pixel array 120. For example, the controller may transmit a word-line signal (i.e., ROW) to activate a row and then transmit the image data (i.e., DATA(COLUMN)) to the columns of the activated row.

[0025] The controller 400 may be configured to address and write to the SRAMs of the pixel array so that the micro-LEDs are illuminated to generate an image. Each image may be rendered on the pixel array 120 on a row-by-row basis until every row necessary for rendering the image has been activated. In a possible implementation, a rendering process includes transmitting a word-line signal to activate a row. After being activated, a bit-line signal for each pixel in the row controls the pixel ON / OFF according to the image data for each pixel in the active row. After the bit-line signals configure (i.e., write to) the pixels of the active row, the row may be deactivated, and another row may be activated until all rows of a frame have been activated. The SRAM cells for pixels in deactivated rows can hold the pixels of the deactivated rows ON (illuminated) or OFF (not illuminated) while the other rows of the frame are activated. After writing a frame to the SRAM cells of the pixel array 120, the SRAM cells can hold their values (e.g., 0, 1) until they are changed. As a result, updating the values in an SRAM display may only require a portion of the SRAM cells to change their state (i.e., flip) from a previous frame (i.e., bit plane).

[0026] The ON / OFF control of the pixels described above can be used to render a binary image in which each pixel is either ON (e.g., binary 1) or OFF (e.g., binary 0). A sequence of binary images (i.e., bit planes) may be displayed at a high rate to create a grayscale image perceived by an observer.

[0027] FIG. 2 illustrates a sequence of bit planes for an image according to a possible implementation of the present disclosure. In this example, an image 201 has four pixels. Each pixel defines a location and a grayscale level. The grayscale level for each pixel of the image 201 may be represented as a binary number. The binary numbers have a number of bits corresponding to the bit depth of the display. As shown, each pixel in the binary representation of the image 201 is a four bit binary number.

[0028] A bit plane sequence 220 can be generated to have a bit plane for each bit of the binary number. As shown, the bit plane sequence 220 includes four bit planes. A first bit plane is an image that represents the most significant bit (MSB) of each pixel (i.e., the most significant bit plane 221). A second bit plane 222 is less significant than the most significant bit plane 221. A third bit plane 223 is less significant than the second bit plane 222 but is more significant than the least significant bit plane 224, which represents the least significant bit (LSB) of each pixel. The bit plane sequence 220 may be divided in half to form a first group 231 including the more significant bit planes of the sequence and a second group 232 including the less significant bit planes. When there are an odd number of bit planes, a median significant bit plane may have a significance in the sequence that is between the first group 231 and the second group 232.

[0029] Displaying the gray scale image may include writing each bit plane to the pixel array (i.e., SRAM) in succession. When each bit plane is displayed at the same intensity, each bit plane may be weighted by the duration that it is displayed relative to the other bit planes. As shown, the weights (W) of the bit planes may double for each bit plane from the least significant bit plane 224 to the most significant bit plane 221.

[0030] The quality of an image may be determined by how well the sequence of bit planes represents the binary value of each pixel. The significance of the bit plane may correspond to how much its bit contributes to the binary value.

[0031] FIG. 3 illustrates the contribution of each bit to a binary number representing a grayscale level according to a possible implementation of the present disclosure. As shown, the binary number, 11111111, represents the grayscale level value of 255. The binary number includes eight bits (i.e., has a bit depth of 8) ranging from the most significant bit (b7) to the least significant bit (bO). The graph illustrates how each bit contributes to this grayscale level value. As shown, half of the grayscale level value is determined by the most significant bit. The bits may be considered as including two groups, with the bits bO, bl, b2, b3 having a lower significance than the bits b4, b5, b6, b7. As shown, bits b4, b5, b6, b7, may contribute 94% to the grayscale level value. Accordingly, these bits (i.e., this first !4 portion) may be referred to as the most significant bits of the binary number. As shown, bits bO, bl, b2, b3, may only contribute 6% to the grayscale level value. Accordingly, these bits (i.e., this second 14 portion) may be referred to as the least significant bits of the binary number. What this implies is that ignoring some of the least significant bits may still provide a reasonable approximation of thegrayscale level value of 255. For example, if bits bO and bl were ignored, the grayscale level value obtained from the remaining bits (i.e., b7, b6, b5, b4, b3, b2) would be 252, which in some cases may be a reasonable approximation of the grayscale level of 255. As each bit plane corresponds to a bit, a partial sequence of bit planes may be a reasonable approximation to a full sequence of bit planes.

[0032] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure. The controller may be implemented as a unitary device or may be part of a distributed computing system. The controller 400 includes digital processing, logic, and memory to perform the operations associated with controlling the pixels in a pixel array to render (i.e., display) an image. These operations may be performed by modules, which can include circuitry and / or software to perform one or more of the operations.

[0033] As shown in FIG. 4, the controller 400 includes a display preprocessor module (i.e., display preprocessor 410). The display preprocessor 410 may be configured to receive an image for display. The image may be a grayscale image or a color image. A color image for display can include three color channels, each represented by a gray scale image. Accordingly, the example of a grayscale image for display will be discussed in detail.

[0034] The display preprocessor 410 may be configured to generate a compressed image based on the received image. In a possible implementation, the display preprocessor 410 can detect compressible portions of pixels, which can be groups (e.g., segments, groups, rows, areas, lines, etc.) of pixels that have a grayscale level (i.e., intensity) that is zero (i.e., zero pixels). In other words, the display preprocessor 410 can process the image to detect portions of the image that contain no visual information. The display preprocessor 410 may be further configured to discard (i.e., remove) pixels in these compressible portions to generate a compressed image. The compressed image can still include zero pixels but these pixels are not removed because they are included in the visual information (i.e., are not compressible).

[0035] The compressed image may have a reduced size (i.e., data length) compared to the received image. Highly compressible images (e.g., text on a dark background) may have a very short data length (i.e. length) compared to the received image, while less compressible images (e.g., a picture, or frame of video) may have a data length that is almost as long as the received image. Bit planes generated from the compressed image can have the same data length as thecompressed image. This reduced length allows a buffer 450, which stores the bit planes to be made smaller, which can reduce its size and power consumption.

[0036] FIG. 5 is a system block diagram illustrating the compression and storage of bit planes in a buffer according to a possible implementation of the present disclosure. As shown, a portion of the pixels in the image 510 may be removed to generate a compressed image 520, which has a reduced size (i.e., data length). The compressed image 520 has a compressed data length (Lc) that is shorter than the (uncompressed) data length (L) of the image 510. A sequence of bit planes can be generated to represent the compressed image 520.

[0037] As shown in FIG. 5, each bit plane in the sequence of bit planes may be stored in a corresponding memory location (i.e., segment) of the buffer 450. A segment may be an address that can include a first location (e.g., start address), second location (e.g., end address), and a pointer designating the direction to write the data. Each bit plane may be written to the buffer according to a corresponding segment. For example, a first segment 530 (i.e., segment 1) may be configured to store a least significant bit plane of the sequence and a last segment 531 (i.e., segment N) may be configured to store the most significant bit plane. The sequential ordering of segments by significance is not required, however. For example, in a possible implementation, segments for storing less significant bit planes may be interleaved with segments for storing more significant bit planes.

[0038] As shown in FIG. 5, each segment may have a segment length 535. When the compressed data length (Lc) of the generated bit planes is less than the segment length 535 of the segments, then all N bit planes may be stored in the buffer without error. In other words, each bit plane is contained within its designated segment of the buffer. Were the image 510 less compressible, then the compressed length could exceed the segment length 535 resulting in more than one segment being written to the same location in the buffer (i.e., overwrite error), which can corrupt the bit planes.

[0039] Without the features of the disclosed display, a buffer would have to be made large enough to accommodate all possible compressed image sizes. For example, the buffer could be made large enough to store N uncompressed bit planes without a risk of overwrite errors. This approach, however, can be wasteful (e.g., large size, high power consumption) and can be an inefficient use of each segment. For example, it may be desirable to minimize an unused portion 536 of each segment.

[0040] Returning to FIG. 4, the display preprocessor 410 further includes a compression map module (i.e., zero mapper 420). The zero mapper 420 may be configured to generate a map that locates the compressible portions of the image. The map can designate the positions of zero pixels removed from the image so that they can be replaced to regenerate the image.

[0041] The display preprocessor 410 further includes a data length measurement module (i.e., data length counter 430). The data length counter is configured to determine a data length (Lc) of the compressed image, which can vary from image to image. For example, the data length counter 430 may count the pixels (e.g., non-zero pixels) of the compressed image to determine a data length.

[0042] The controller 400 further includes a bit-plane generator 440. The bit-plane generator 440 is configured to receive the compressed image and the data length. The bit-plane generator 440 is configured to generate a sequence of bit planes based on the compressed image and the data length. By default, the bit-plane generator 440 may be configured to generate a number (N) of bit planes, where N is the bit depth of the display.

[0043] In a possible implementation, the bit-plane generator 440 is further configured to compare the data length (Lc) to a threshold corresponding to a segment length of the buffer 450. For example, the bit-plane generator 440 may disable one or more of the bit planes when the data length of each bit plane is larger than a threshold (i.e., larger than a segment).

[0044] FIG. 6 illustrates disabling bit planes in a buffer according to a first possible implementation of the present disclosure. As shown, a sequence of bit planes 610 is generated. The sequence includes eight bit planes but any number could be created. The eight bit planes include the four most significant bit planes (MSB, MSB-1, MSB-1, MSB-3) and the four least significant bit planes (LSB, LSB+1, LSB+2, LSB+3). The bit planes are designated for storage in corresponding segments of a buffer 650. The buffer 650 is equally divided into a number (e.g., 8) of segments, equal to the number (e.g., 8) of bit planes.

[0045] As shown in FIG. 6, the buffer 650 is configured so that even segments store the most significant bit planes and odd segments store the least significant bit planes 620. A first segment 651 of a buffer 650 is configured to store a most significant bit plane 611 (MSB). A second segment 652 of the buffer 650 is configured to store the least significant bit plane 612 (LSB). A third segment 653 of the buffer 650 is configured to store the second most significant bit plane 613 (MSB-1). A fourth segment 654 of the buffer 650 is configured to store the second leastsignificant bit plane 614 (LSB+1). A fifth segment 655 of the buffer 650 is configured to store the third most significant bit plane 615 (MSB-2). A sixth segment 656 of the buffer 650 is configured to store the third least significant bit plane 616 (LSB+2). A seventh segment 657 of the buffer 650 is configured to store the fourth most significant bit plane 617 (MSB-3). An eighth segment 658 of the buffer 650 is configured to store the fourth least significant bit plane 618 (LSB+3).

[0046] As shown in FIG. 6, The bit plane generator may be configured to compare the data length (Lc) of each bit plane to a threshold length (LTH), which equals the length of each segment in the buffer. When the data length (Lc) of each bit plane is less than the threshold (LTH) then all bit planes may be stored in their respective segments. When the data length (Lc) of a bit plane (i.e., each bit plane) is greater than a threshold (LTH), the least significant bit planes 620 of the sequence of bit planes 610 may be designated are not stored in the buffer (i.e., disabled). Disabling the bit planes may include not generating bit planes designated as disabled or generating the disabled bit planes by not writing these bit planes to the buffer.

[0047] As shown, in FIG. 6, disabling the least significant bit planes 620, frees the second segment 652, the fourth segment 654, the sixth segment 656, and the eighth segment 658 so that the most significant bit plane 611, second most significant bit plane 613, third most significant bit plane 615, and fourth most significant bit plane 617 (i.e., a partial set of bit planes) can be written to the buffer without overlapping any other bitplane (i.e., without errors). In other words, the most significant bits of the sequence may be written to the buffer so that each bit plane occupies its corresponding odd segment and an adjacent even segment. The display can be configured to recall the partial set of bit planes stored in the buffer to render the image.

[0048] In a possible implementation, the data length (LC) can also be compared to a maximum length threshold (LMAX). For example, the maximum length in this first implementation, in which half of the bit planes can be disabled, is the length of two segments. When the data length exceeds the maximum length threshold, some other action may be taken. For example, only one of the bit planes (i.e., the most significant bit plane) may be written to the buffer.

[0049] Returning to FIG. 4, the controller 400 further includes a display post processor module (i.e., display post processor 460). The display post processor 460 is configured to receive the bit planes from the buffer 450 and the map from the zero mapper 420. The displaypost processor 460 may be configured to recall the bit planes from the buffer 450 and add back the portions (i.e., the zero pixels) removed by the display preprocessor 410 based on the map. The display post processor 460 may be further configured to address the rows and columns of the pixel array 120 (see FIG 1) to render the decompressed bit planes. The display post processor 460 may be further configured to generate approximate bit planes for any disabled bit planes.

[0050] FIG. 7 illustrates approximate bit planes to replace a set of bit planes disabled and not stored in the buffer according to a a possible implementation of the present disclosure. When the least significant bit planes 620 are not stored in the buffer (i.e., disabled) they may be replaced with approximate bit planes so that a grayscale value generated by the bit planes is approximated. As shown a grayscale value of 169 (i.e., 1010001 in binary) is illustrated.

[0051] In a first implementation 701, the disabled bit planes (i.e., the least significant bit planes 620) are disregarded and the remaining bit planes are weighted according to their bit position. In this case, an approximate grayscale value of 160 (i.e., IOIOXXXX) may be obtained.

[0052] In a second implementation 702, the disabled bit planes (i.e., the least significant bit planes 620) are replaced by approximate bit planes having pixels that are all zeros. In this case, an approximate grayscale value of 160 (i.e., 10100000) may be obtained.

[0053] In a third implementation 703, the disabled bit planes (i.e., the least significant bit planes 620) are replaced by approximate bit planes having pixels that are all ones. In this case, an approximate grayscale value of 175 (i.e., 10101111) may be obtained.

[0054] In a fourth implementation 704, the disabled bit planes (i.e., the least significant bit planes 620) are replaced by approximate bit planes having pixels that match one of the bit planes from the partial sequence of bit planes stored in the buffer. For example, the least significant bit planes 620 may all be made to match the next bit plane in the order of significance (i.e., MSB-3). The approximate bit planes in this case will have Is and 0s. In this case, an approximate grayscale value of 160 (i.e., 10100000) or 175 (i.e., 10101111) could be obtained, depending on its corresponding pixel value in the least significant bit plane of the partial set of bit planes (i.e., the MSB-3 bit plane).

[0055] FIG. 8 illustrates disabling bit planes in a buffer according to a second possible implementation of the present disclosure. This implementation includes multiple thresholds to increase the options of how to store bit planes in the buffer. As shown, a sequence of bit planes 810 is generated. The sequence includes four bit planes, but any number could be created. Thefour bit planes include the two most significant bit planes (MSB, MSB-1) and the two least significant bit planes (LSB+1, LSB). The bit planes are designated for storage in corresponding segments of a buffer 850. The buffer 650 is unequally divided into a number (e.g., 4) of segments, equal to the number (e.g., 4) of bit planes. The segments increase in length from a first segment 851 configured to store the least significant bit plane 811 to a fourth segment 854 configured to store the most significant bit plane 814.

[0056] As shown in FIG. 8, the segments are sized so that a segment doubles in length when combined with each segment having a significance below the segment. For example, a fourth segment length doubles when combined with a third length of the third segment 853, a second length of the second segment 852, and a first length of the first segment 851. Likewise, the third length of the third segment 853 doubles when combined with a second length of the second segment 852 and the first length of the first segment 851. Likewise, the second length of the second segment 852 doubles when combined with the first length of the first segment 851.

[0057] A plurality of thresholds, which correspond to the unequal segment lengths of the buffer, can be used to determine which of the bit planes to store in the buffer. The thresholds can increase by a factor of two. For example, a second threshold (LTHZ) is twice the length of a first threshold (LTHI). A third threshold (LTII is twice the length of the second threshold (LTH2). In this case, the third threshold is half the size (i.e. length) of the buffer 850. A maximum threshold (L AX), which is the length of the buffer 850, may also be used to determine when the length of a bit plane is too large to be stored.

[0058] The thresholds may be associated with a segment. For example, the maximum threshold (LMAX) may be associated with the fourth segment 854, which is configured to store the most significant bit plane 814 (MSB) of the sequence of bit planes 810. The third threshold (LITO) may be associated with the third segment 853, which is the second most significant bit plane 813 (MSB-1) of the sequence of bit planes 810. The second threshold (LTH2) may be associated with the second segment 852, which is the second least significant bit plane 812 (LSB+1) of the sequence of bit planes 810. The first threshold (LTHI) may be associated with the first segment 851, which is the least significant bit plane 811 (LSB) of the sequence of bit planes 810.

[0059] In other words, the segments progressively increase from a first segment 851 to the fourth segment 854 (i.e., a last segment) of the buffer 850. As shown in FIG. 8, the first segment851 corresponds to the least significant bit plane 81 1 of the sequence of bit planes 810 and has a first segment length that is the shortest of the segment lengths. The fourth segment 854 (i.e., last segment) of the buffer 850 corresponds to the most significant bit plane 814 of the sequence of bit planes 810 and has a least segment length that is the longest of the segment lengths. The thresholds correspond to each of the segments and progressively double from a first threshold (LTHI) corresponding to the first segment 851 to a maximum threshold (i.e. last threshold) corresponding to the fourth segment 854 (i.e., last segment).

[0060] The data length (Lc) of the bit planes (i.e., the length of the compressed image) can be compared to a plurality of thresholds to determine which bit planes are stored and in what segments they are stored. When the data length exceeds a particular threshold corresponding to a particular segment, the bit plane corresponding to the particular segment and all bit planes corresponding any shorter segments are disabled.

[0061] As shown in FIG. 8, the data length (Lc) of the bit planes is greater than the second threshold (LTH2) (and the first threshold (LTHI)). Accordingly, the second least significant bit plane 812 (LSB+1), corresponding to the second segment 852, and the least significant bit plane 811 (LSB), corresponding to the first segment 851 (i.e. the least significant bit planes 820), may be disabled from being stored in the buffer 850. As a result, the third segment 853 (and the fourth segment 854) is freed to store the second most significant bit plane 813, which overflows the second segment 852. The data length (Lc) does not exceed the third threshold or the maximum threshold so the storage of the most significant bit plane 814 in the fourth segment 854 proceeds without adjustment.

[0062] This approach has a few advantages. For example, more bit planes can be stored for longer data lengths because the bit planes are disabled incrementally as the data length of the compressed image increases. Further, the more significant bit planes, which carry most of the visual information, are allocated more memory, which makes them less likely to be disabled. Another advantage of this approach is that the implementation of comparing the data length to a sequence of thresholds, which double from one threshold to the next can be made very computationally efficient.

[0063] FIG. 9 illustrates a subsystem for comparing the data length to a plurality of thresholds according to a possible implementation of the present disclosure. As shown, the data length may be computed using a data length counter 430 to count the pixels (e.g., non-zeropixels) in the compressed image so that the data length is equivalent to a count (CNT). During the counting, the count may be compared to a first threshold (LTHI) with a digital comparator 910. The digital comparator may be configured to incrementally change thresholds as the count exceeds a threshold. When the count exceeds the first threshold, then the first threshold may be converted to the second threshold (i.e., doubled) by a bit shift. Next, when the count exceeds the second threshold (LTH2), then the second threshold may be converted to a third threshold (i.e., doubled) by the bit shift. This process may continue until the data length is completely counted. The bit shift reduces the memory and circuitry required for storing and comparing the thresholds, thereby further reducing the power and size of the display.

[0064] In the specification and / or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and / or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.

[0065] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0066] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and / or so forth.

[0067] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or subcombinations of the functions, components and / or features of the different implementations described.

[0068] It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0069] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, includevertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Claims

CLAIMS1. A display comprising: a preprocessor configured to: receive an image; remove a portion of pixels from the image to generate a compressed image; and determine a data length of the compressed image; and a bit-plane generator that receives the compressed image and the data length of the compressed image, the bit-plane generator configured to: generate a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; compare the data length to a threshold; designate a set of bit planes as disabled when the data length is greater than the threshold; and prevent the set of bit planes designated as disabled from being stored in a buffer so that a partial sequence of bit planes is stored in the buffer without overlapping.

2. The display according to claim 1, wherein: the set of bit planes that are disabled from being stored in the buffer are less significant in the sequence of bit planes than the partial sequence of bit planes stored in the buffer; and the display is configured to render the image based on the partial sequence of bit planes.

3. The display according to claim 1 or 2, wherein: the buffer is equally divided into a number of segments, the number of segments being equal to a number of bit planes in the sequence of bit planes, and each segment has a segment length that is equal to the threshold.

4. The display according to claim 3, wherein: odd segments of the buffer correspond to more significant bit planes; and even segments of the buffer correspond to less significant bit planes.

5. The display according to claim 4, wherein the bit-plane generator is further configured to: write the partial sequence of bit planes to the odd segments of the buffer so that each bit plane of the partial sequence of bit planes occupies an odd segment and an adjacent even segment of the buffer.

6. The display according to any one of the preceding claims, wherein the bit-plane generator is further configured to: enable all bit planes of the sequence of bit planes to be stored in the buffer when the data length is less than the threshold; and write the sequence of bit planes to the buffer so that each bit plane occupies a corresponding segment of the buffer.

7. The display according to any one of the preceding claims, wherein to disable the set of bit planes from being stored in the buffer, the bit-plane generator is configured to: not generate the set of bit planes designated as disabled.

8. The display according to any one of claims 1 to 6, wherein to disable the set of bit planes from being stored in the buffer, the bit-plane generator is configured to: generate the set of bit planes designated as disabled; and not write the set of bit planes designated as disabled to the buffer.

9. The display according to any one of the preceding claims, wherein: the portion of pixels removed from the image are zero pixels.

10. The display according to claim 9, wherein the preprocessor is further configured to: generate a map of the image, the map including locations of the zero pixels in the image; and transmit the map to a post processor configured to replace the zero pixels removed based on the map.

11. A display comprising: a preprocessor configured to: receive an image including pixels; remove a portion of the pixels in the image to generate a compressed image; and determine a data length of the compressed image; a buffer configured to store a sequence of bit planes representing the compressed image, the buffer divided into segments, the segments having segment lengths that progressively increase; and a bit-plane generator that receives the compressed image and the data length of the compressed image, the bit-plane generator configured to: generate bit planes of the sequence of bit planes, each bit plane of the sequence of bit planes having the data length of the compressed image; compare the data length to thresholds that progressively increase; and disable at least one bit plane from being stored in the buffer when the data length exceeds at least one of the thresholds so that a partial sequence of bit planes can be stored in the segments without overlap.

12. The display according to claim 11, wherein: the partial sequence of bit planes stored in the buffer includes bit planes that are more significant than the at least one bit plane being disabled; and the display is configured to display a rendered image based on the partial sequence of bit planes.

13. The display according to claim 11 or 12, further comprising a display post processor configured to: generate approximate bit planes for the at least one bit plane not stored in the buffer.

14. the display according to claim 13, wherein the approximate bit planes are bit planes having pixels that are all ones or all zeros.

15. The display according to claim 13, wherein the approximate bit planes are bit planes having pixels that match one bit plane in the partial sequence of bit planes.

16. The display according to any one of claims 11 to 15, wherein: a first segment of the buffer corresponds to a least significant bit plane of the sequence of bit planes and has a first segment length that is a shortest of the segment lengths; a last segment of the buffer corresponds to a most significant bit plane of the sequence of bit planes and has a last segment length that is a longest of the segment lengths; and the thresholds correspond to each of the segments and progressively double from a first threshold corresponding to the first segment to a maximum threshold corresponding to the last segment.

17. The display according to any one of claims 11 to 16, wherein: a particular bit plane corresponding to a particular segment is disabled when the data length exceeds a particular threshold corresponding to the particular segment; and any bit plane corresponding to a segment that is shorter than the particular segment is also disabled when the data length exceeds the particular threshold corresponding to the particular segment.

18. A method for displaying an image, the method comprising: receiving the image for display; generating a compressed image; determining a data length of the compressed image; generate a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; comparing the data length to a threshold corresponding to a segment length of a buffer; designating at least one bit plane of the sequence of bit planes as disabled when the data length exceeds the threshold; and not storing the at least one bit plane designating as disabled in the buffer so that a partial sequence of bit planes can be stored in the buffer without overlapping.

19. The method for displaying the image according to claim 18, wherein the at least one bit plane of the sequence of bit planes designated as disabled includes: bit planes of the sequence of bit planes that are least significant.

20. The method for displaying the image according to claim 18 or 19, further comprising: storing the partial sequence of bit planes in the buffer; recalling the partial sequence of bit planes from the buffer; generating approximate bit planes for the at least one bit plane not stored in the buffer; and displaying the image using the partial sequence of bit planes and the approximate bit planes.

Images