Radio frequency processing circuit, signal processing method, and radio frequency processing device

Abstract

Provided in the present embodiment are a radio frequency processing circuit, a signal processing method, and a radio frequency processing device, which are applied to the technical field of communications. The radio frequency processing circuit comprises a radio frequency channel, a plurality of power dividers and a channel detection channel, wherein combination ends of the plurality of power dividers are correspondingly coupled to a plurality of antenna array elements; first shunt ends of the plurality of power dividers are coupled to an input end of the radio frequency channel; second shunt ends of the plurality of power dividers are coupled to an input end of the channel detection channel; the plurality of power dividers are configured to acquire a plurality of corresponding radio frequency signals from the plurality of antenna array elements, and perform shunt processing on the plurality of radio frequency signals, so as to obtain a plurality of first radio frequency data signals and a plurality of radio frequency reference signals; the radio frequency channel is configured to input the plurality of first radio frequency data signals; the channel detection channel is configured to input the plurality of radio frequency reference signals; and the plurality of radio frequency reference signals are used for acquiring channel information of an antenna array element level. The present embodiment can shorten the beam polling time during full airspace coverage, and reduce the performance loss of a network system.

Description

Radio frequency processing circuit, signal processing method and radio frequency processing device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 27, 2023, with application number 202311416809.8 and application name “A radio frequency processing circuit, signal processing method and radio frequency processing device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a radio frequency processing circuit, a signal processing method, and a radio frequency processing device. Background Art

[0003] With the advancement of communication technology, the operating frequency of communication equipment has gradually increased, resulting in increased electromagnetic wave propagation loss in space. This requires higher equivalent isotropic radiated power (EIRP) on the macro base station side to compensate for path loss. Currently, the main method used to increase EIRP is to increase antenna gain using technologies related to the hybrid beamforming (HBF) architecture. However, increasing antenna gain through the HBF architecture requires a single RF channel to drive more antenna elements, resulting in a narrower beamwidth. With a narrower beamwidth, more beams are required to achieve full spatial coverage through time rotation, which in turn increases network system performance.

[0004] Therefore, how to reduce the beam rotation time when covering the entire airspace and reduce the performance loss of the network system has become a technical problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a radio frequency processing circuit, a signal processing method, and a radio frequency processing device to reduce the beam rotation time during full airspace coverage and reduce network system performance loss.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a radio frequency processing circuit is provided, which includes a radio frequency channel, multiple power splitters, and a channel detection channel. The combining ends of the multiple power splitters are coupled to the multiple antenna array elements; the first branching ends of the multiple power splitters are coupled to the input end of the radio frequency channel; and the second branching ends of the multiple power splitters are coupled to the input end of the channel detection channel. The multiple power splitters are used to: obtain corresponding multiple radio frequency signals from the multiple antenna array elements, branch the multiple radio frequency signals, and obtain multiple first radio frequency data signals and multiple radio frequency reference signals. The radio frequency channel is used to: input multiple first radio frequency data signals. The channel detection channel is used to: input multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element-level channel information.

[0009] In an embodiment of the present application, by mapping a radio frequency channel to multiple antenna array elements, the decoupling of the number of radio frequency channels and the number of antenna array elements is achieved, that is, the number of radio frequency channels required for the same antenna array element is reduced, and the convergence ratio between the radio frequency channel and the antenna array element is improved, so that more antenna array elements can be accommodated under the same physical aperture surface, thereby achieving the purpose of increasing antenna gain and enhancing coverage. However, under this implementation method, a single radio frequency channel drives more antenna array elements, which will cause the beam width to narrow. Under a narrower beam width, more beams are required for time rotation to achieve full airspace coverage, which in turn leads to increased network system performance loss. Therefore, a power splitter and a dedicated channel detection channel can be set in the radio frequency processing circuit. The power splitter obtains the corresponding radio frequency signal from the antenna array element and performs branch processing on the radio frequency signal to obtain the first radio frequency data signal and radio frequency reference signal at the antenna array element level. The dedicated channel detection channel inputs the RF reference signal at the antenna array element level. Since a single antenna array element has a large beam width, it can receive channel information in the entire airspace. Therefore, the antenna array element level channel information input by the channel detection channel can be used to obtain antenna array element level channel information or full airspace channel information after one or a few beam rotations, thereby reducing the beam rotation time during full airspace coverage, shortening the channel measurement cycle, reducing time overhead, reducing network system performance loss, delaying channel aging, and improving data transmission performance. Analysis shows that the RF processing circuit provided by the present application achieves the purpose of reducing the beam rotation time during full airspace coverage and reducing network system performance loss while increasing antenna gain.

[0010] In one possible implementation, the RF processing circuit further includes a gating circuit. The second branch terminals of the multiple power dividers are coupled to the branch terminal of the gating circuit. A common terminal of the gating circuit is coupled to the input terminal of a channel detection channel. In this embodiment, the channel detection channel and the gating circuit cooperate to dynamically acquire channel information at the level of different antenna array elements.

[0011] In a possible implementation, the gating circuit is a single-pole multi-throw switch.

[0012] In one possible implementation, the RF processing circuit further includes multiple low-noise amplifiers. The inputs of the multiple low-noise amplifiers are coupled to the multiple antenna elements, and the outputs of the multiple low-noise amplifiers are coupled to the combining ends of the multiple power splitters. By placing the power splitters at the outputs of the low-noise amplifiers to receive signals processed by the low-noise amplifiers, the impact of noise introduced by the antenna elements on the RF reference signal is reduced, thereby improving the quality of the signal received at the power splitters.

[0013] In one possible implementation, the RF processing circuit further includes a power amplifier. The channel detection channel is a predistortion feedback channel of the power amplifier corresponding to the power amplifier. This embodiment reduces RF circuit hardware consumption and hardware costs by sharing the channel detection channel with the predistortion feedback channel of the power amplifier.

[0014] In a second aspect, an embodiment of the present application further provides a signal processing method for use in a radio frequency processing circuit, the radio frequency processing circuit comprising a radio frequency channel, multiple power splitters, and a channel detection channel. The method comprises: multiple power splitters acquiring corresponding multiple radio frequency signals from multiple antenna array elements, performing branching processing on the multiple radio frequency signals, and obtaining multiple first radio frequency data signals and multiple radio frequency reference signals. The radio frequency channel inputs the multiple first radio frequency data signals. The channel detection channel inputs the multiple radio frequency reference signals, and the multiple radio frequency reference signals are used to obtain antenna array element-level channel information.

[0015] In one possible implementation, inputting multiple RF reference signals includes: inputting a control signal, wherein the control signal is used to instruct selection of one or more of the multiple RF reference signals, and inputting one or more of the multiple RF reference signals in response to the control signal.

[0016] In one possible implementation, the RF processing circuit further includes a power amplifier. The channel sounding channel is a predistortion feedback channel of the power amplifier corresponding to the power amplifier. The method further includes: in a first time slot, the RF channel transmits a second RF data signal via an antenna array element. Inputting one or more of the multiple RF reference signals, and further includes: in a second time slot, the channel sounding channel inputs one or more of the multiple RF reference signals. The first time slot and the second time slot are time slots apart.

[0017] In a third aspect, an embodiment of the present application further provides a radio frequency processing device, comprising a circuit board and any radio frequency processing circuit in the first aspect, wherein the radio frequency processing circuit is arranged on the circuit board.

[0018] In a fourth aspect, embodiments of the present application further provide a communications system comprising a baseband processing device and a radio frequency processing device as described in the third aspect. The baseband processing device is coupled to the radio frequency processing device. The radio frequency processing device is configured to output multiple radio frequency reference signals to the baseband processing device, where the multiple radio frequency reference signals are used to obtain antenna element-level channel information.

[0019] In a possible implementation, the baseband processing device is configured to obtain antenna array element-level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

[0020] In a possible implementation, the radio frequency processing device includes a controller; the controller is configured to obtain antenna array element-level channel information of the radio frequency processing circuit according to a radio frequency reference signal.

[0021] Regarding the technical principles and beneficial effects of the second, third and fourth aspects, please refer to the relevant description of the first aspect above, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a structural diagram of a communication system provided in an embodiment of the present application;

[0023] FIG2 is a structural diagram of a radio frequency processing device provided in an embodiment of the present application;

[0024] FIG3 is a structural diagram of an equivalent isotropically radiated power structure provided in an embodiment of the present application;

[0025] FIG4 is a comparison diagram of the number of antenna array elements and antenna gain provided in an embodiment of the present application;

[0026] FIG5 is a structural diagram 1 of a radio frequency processing circuit provided in an embodiment of the present application;

[0027] FIG6 is a structural diagram of an active antenna unit provided in an embodiment of the present application;

[0028] FIG7 is a second structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0029] FIG8 is a diagram showing a simulated relationship between the number of antenna elements and beam width provided in an embodiment of the present application;

[0030] FIG9 is a diagram showing the relationship between the number of antenna elements and beam width provided in an embodiment of the present application;

[0031] FIG10 is a diagram illustrating beam scanning to obtain full spatial channel information in a radio frequency processing circuit provided in an embodiment of the present application;

[0032] FIG11 is a third structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0033] FIG12 is a fourth structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0034] FIG13 is a fifth structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0035] FIG14 is a sixth structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0036] FIG15 is a seventh structural diagram of a radio frequency processing circuit provided in an embodiment of the present application;

[0037] FIG16 is a structural diagram 8 of a radio frequency processing circuit provided in an embodiment of the present application;

[0038] FIG17 is a structural diagram of another radio frequency processing device provided in an embodiment of the present application;

[0039] FIG18 is a flowchart of a signal processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0041] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0043] First, some basic concepts involved in this application are explained:

[0044] Equivalent isotropic radiated power (EIRP): Also known as effective isotropic radiated power, this represents the relative antenna gain of a transmitting antenna relative to the antenna gain of an isotropic radiating element, multiplied by the net power received by the antenna from the connected transmitter in a given direction. The power radiated in the central axis of the beam by satellite and earth station transmitting antennas is called the effective isotropic radiated power (EIRP) of the transmitting device. This is the product of the power supplied to the antenna by the radio transmitter and the absolute gain of the antenna in a given direction. It is an important indicator of the transmission capability of an earth station or repeater. An ideal isotropic antenna with the same unity gain in all directions is often used as a reference antenna for wireless communication systems. EIRP is defined as: EIRP = Pt * Gt, where Pt represents the net power received from the connected transmitter and Gt represents the antenna gain of the transmitting antenna. It represents the transmit power that can be obtained by the transmitter in the direction of maximum antenna gain, compared to an isotropic antenna.

[0045] Antenna gain is the ratio of the signal power density generated by an actual antenna to that of an ideal radiating element at the same point in space, under conditions of equal input power. It quantitatively describes the degree to which an antenna concentrates the input power. Gain is clearly closely related to the antenna pattern: the narrower the main lobe and the smaller the side lobes, the higher the gain. Antenna gain measures an antenna's ability to transmit and receive signals in a specific direction and is one of the most important parameters for selecting base station antennas. Generally speaking, increasing gain primarily relies on reducing the vertical beamwidth while maintaining omnidirectional radiation performance in the horizontal plane. Antenna gain is crucial to the operational quality of communication systems because it determines the signal level at the cell edge. Increasing gain can extend network coverage in a specific direction or increase the gain margin within a specific range. Any cellular system is a two-way process, so increasing antenna gain can also reduce the two-way system gain budget margin. Under the same conditions, higher gain increases the distance radio waves can travel.

[0046] Beam: This refers to the shape of the electromagnetic waves emitted by an antenna on the Earth's surface. It can also be understood as the main lobe of the antenna array's radiation pattern.

[0047] Beamwidth: This refers to the angular width on either side of the direction of maximum radiation when the power density relative to the direction of maximum radiation drops to half, also known as the 3dB beamwidth. The horizontal beamwidth at half power is called the horizontal beamwidth; the vertical beamwidth at half power is called the vertical beamwidth.

[0048] An embodiment of the present application provides a communications system 1000, as shown in Figure 1 , comprising a baseband processing device 100 and a radio frequency processing device 200. The baseband processing device 100 is coupled to the radio frequency processing device 200. The radio frequency processing device 200 is configured to output multiple radio frequency reference signals to the baseband processing device 100. The multiple radio frequency reference signals are used to obtain antenna element-level channel information. The antenna element-level channel information may include, but is not limited to, signal phase, amplitude, and delay information.

[0049] In some possible implementations, as shown in FIG. 2 , the RF processing device 200 includes a RF processing circuit 210 and a circuit board 220 , where the RF processing circuit 210 is disposed on the circuit board 220 .

[0050] For example, as 5G communications evolve towards 5.5G or 6G communications, the operating carrier frequency gradually evolves from below 6 GHz (sub-6 GHz) in 5G communications to higher frequencies above 6 GHz (up-6 GHz). As the operating frequency increases, the spatial propagation loss of electromagnetic waves increases, requiring a higher EIRP on the macro base station side to compensate for the path loss. Currently, there are two main technical paths to increasing EIRP: one is to increase the transmit power of the power amplifier 18 (PA), and the other is to increase the antenna gain. As shown in Figure 3, the PA transmit power and antenna gain together constitute the EIRP. However, since increasing the PA transmit power increases the power consumption of the RF processing circuit 210, there are significant constraints on increasing the PA transmit power. Therefore, in the evolution to higher frequencies up to 6 GHz, the EIRP is increased by increasing the antenna gain. Increasing antenna gain is mainly achieved by increasing the number of antenna elements. An antenna can include multiple antenna elements. As shown in Figure 4, since the wavelength of electromagnetic waves at up-6 GHz frequencies is shorter than that of electromagnetic waves at sub-6 GHz frequencies, the corresponding antenna element size can be reduced. Therefore, under the same physical aperture, more antenna elements can be accommodated and higher antenna gain can be achieved.

[0051] To increase EIRP, in some possible implementations, the RF processing circuit 210 can be a first RF processing circuit based on a digital beamforming (DBF) architecture. As shown in Figure 5, the first RF processing circuit 210A includes multiple first antenna elements 211A and first RF channels 212A, with each first RF channel 212A being mapped one-to-one with the first antenna elements 211A. The first RF channels 212A perform functions such as filtering and amplifying RF analog signals, while the first antenna elements 211A primarily transmit and receive analog signals.

[0052] The first RF processing circuit 210A can increase the EIRP by increasing the number of first antenna array elements 211A. However, as the number of first antenna array elements 211A increases, the number of first RF channels 212A corresponding to the back-end will also increase, which will greatly increase the device setup cost. As shown in Figure 5, the main advantage of the first RF processing circuit 210A is that the first RF channels 212A are mapped one-to-one with the first antenna array element 211A. Since the beam width of a single first antenna array element 211A is large, the controller in the baseband processing circuit or RF circuit can obtain full spatial channel information at one time without the need for multiple beam scans, thus optimizing the network performance. However, according to the mapping relationship between the first antenna array element 211A and the first RF channel 212A, it can be seen that the more first antenna array elements 211A there are, the more first RF channels 212A there are corresponding to them. As the number of first RF channels 212A increases, the hardware cost and power consumption in the first RF processing circuit 210A will increase. If the first RF processing circuit 210A is still used when the frequency evolves to up-6 GHz, as the operating frequency evolves to a higher frequency, the number of first antenna array elements 211A will increase sharply under the same physical caliber, and the hardware equipment such as the corresponding first RF channel 212A will also increase in the same proportion, which will lead to a sharp increase in the power consumption of the first RF processing circuit 210A and the hardware cost.

[0053] In one example, the first RF processing circuit 210A may also be configured to modulate the baseband signal to obtain an intermediate frequency signal, up-convert the intermediate frequency signal to obtain an RF signal; or directly modulate the baseband signal to an RF signal.

[0054] In one example, the first RF processing circuit 210A can be an active antenna unit (AAU) or a remote radio unit (RRU). As shown in Figure 6, the AAU includes a baseband, a digital intermediate frequency (DIF), a first RF channel 212A, and a first antenna array element 211A. The baseband portion primarily performs functions such as baseband signal encoding, modulation, layer mapping, and channel weighting; the digital IF portion primarily performs time-domain processing functions such as frequency conversion and filtering.

[0055] To address the issues with the first RF processing circuit 210A, in some possible implementations, the RF processing circuit 210 may be a second RF processing circuit based on a hybrid beamforming (HBF) architecture. As shown in FIG7 , the second RF processing circuit 210B includes multiple second antenna elements 211B, multiple second RF channels 212B, and one second RF channel 212B coupled to the multiple second antenna elements 211B. The second RF processing circuit 210B can be coupled to the multiple second antenna elements 211B via one second RF channel 212B. When the number of second antenna elements 211B remains constant, the number of required second RF channels 212B is reduced compared to the first RF processing circuit 210A. Therefore, the main advantage of the second RF processing circuit 210B is that the number of second RF channels 212B is decoupled from the number of second antenna elements 211B. That is, the same number of second antenna elements 211B requires fewer second RF channels 212B, thereby reducing the power consumption and hardware cost of the second RF processing circuit 210B. However, because a single second RF channel 212B drives more second antenna elements 211B, that is, a single channel maps more second antenna elements 211B, the beam of the second antenna element 211B of a single channel becomes narrower, as shown in Figure 8. Figure 8 shows the simulated relationship between the number of second antenna elements 211B coupled to a single second RF channel 212B, the angle (theta), and the antenna gain (ant-gain). In Figure 8, the lines with triangular blocks represent the coupling of a single second RF channel 212B to four second antenna elements 211B; the lines with circular blocks represent the coupling of a single second RF channel 212B to eight second antenna elements 211B; and the lines with square blocks represent the coupling of a single second RF channel 212B to 16 second antenna elements 211B. For example, as shown in (a) and (b) of FIG9 , the relationship between the number of second antenna array elements 211B and the beamwidth is shown. FIG9 (a) shows that one second RF channel 212B is mapped to eight second antenna array elements 211B, which is eight vertical units, with a gain of 13 dBi, a horizontal beamwidth of 100°, and a vertical beamwidth of 13°. FIG9 (b) shows that one second RF channel 212B is mapped to sixteen second antenna array elements 211B, which is sixteen vertical units, with a gain of 16 dBi, a horizontal beamwidth of 100°, and a vertical beamwidth of 6°.

[0056] In one example, to achieve full-area coverage, as shown in Figure 10, a phase shifter 213B can be provided between the second RF channel 212B and the second antenna element 211B. Its primary function is to configure different weights for phase shifter 213B and adjust the weight or phase value of phase shifter 213B to direct the beam in different directions, thereby controlling the beam scanning of the second antenna element 211B and enabling the beam to scan the entire airspace in a time-division manner. As can be seen, when the beamwidth of the second antenna element 211B becomes narrower, more beams are required for time round-robin to achieve full airspace coverage. This lengthens the channel measurement cycle, causes severe channel aging, degrades network performance, and correspondingly, significant data transmission performance loss, thereby increasing network system performance loss.

[0057] To reduce the beam rotation time during full airspace coverage and minimize network system performance loss, in some possible implementations, the RF processing circuit 210 may be a third RF processing circuit based on the HBF architecture. As shown in FIG11 , the third RF processing circuit 210C includes a third RF channel 212C, multiple power splitters 213C, and a channel detection channel 214C. The combining ends of the multiple power splitters 213C are coupled to the multiple third antenna elements 211C. The first branching ends of the multiple power splitters 213C are coupled to the input ends of the third RF channel 212C. The second branching ends of the multiple power splitters 213C are coupled to the input ends of the channel detection channel 214C. The multiple power splitters 213C are configured to obtain corresponding multiple RF signals from the multiple third antenna elements 211C, perform branching processing on the multiple RF signals, and obtain multiple first RF data signals and multiple RF reference signals. The third RF channel 212C is configured to input the multiple first RF data signals. The channel detection channel 214C is used to input multiple radio frequency reference signals, and the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

[0058] 12 , the third RF processing circuit 210C may include multiple channel detection channels 214C, and one channel detection channel 214C may correspond to multiple third antenna array elements 211C. The first RF data signal and the RF reference signal may be the same signal.

[0059] Illustratively, the third RF processing circuit 210C provided in this embodiment can be applied to, but not limited to, devices such as base stations, mobile communication terminals, and radars.

[0060] In an embodiment of the present application, by mapping a third RF channel 212C to multiple third antenna array elements 211C, the number of third RF channels 212C and the number of third antenna array elements 211C are decoupled, that is, the number of third RF channels 212C required for the same third antenna array element 211C is reduced, and the convergence ratio between the third RF channel 212C and the third antenna array element 211C is improved, thereby accommodating more third antenna array elements 211C under the same physical aperture, thereby increasing antenna gain and enhancing coverage. However, under this embodiment, a single third RF channel 212C drives more third antenna array elements 211C, which will cause the beam width to become narrower. With a narrower beam width, more beams are required for time round-robin to achieve full airspace coverage, which in turn leads to increased network system performance loss. Therefore, a power splitter 213C and a dedicated channel detection channel 214C can be provided in the third RF processing circuit 210C. The power splitter 213C obtains the corresponding RF signal from the third antenna element 211C and performs branching processing on the RF signal to obtain the first RF data signal and RF reference signal at the third antenna element 211C level. The dedicated channel detection channel 214C inputs the RF reference signal at the third antenna element 211C level. Because a single third antenna element 211C has a large beamwidth, it can receive channel information across the entire airspace. Thus, through the third antenna element 211C-level channel information input by the channel detection channel 214C, antenna element-level channel information or full airspace channel information can be obtained after one or a few beam rotations. This reduces the beam rotation time for full airspace coverage, shortens the channel measurement cycle, reduces time overhead, reduces network system performance loss, delays channel aging, and improves data transmission performance. Analysis shows that the third RF processing circuit 210C provided by the present application solution increases the antenna gain while reducing the beam rotation time during full airspace coverage, thereby reducing the performance loss of the network system.

[0061] In some possible implementations, as shown in FIG13 , the third RF processing circuit 210C further includes a gating circuit 215C; the second branch terminals of the plurality of power dividers 213C are coupled to the branch terminals of the gating circuit 215C; and the common terminal of the gating circuit 215C is coupled to the input terminal of the channel detection channel 214C.

[0062] Exemplarily, the gating circuit 215C selects the third antenna element 211C according to a preset rule. In this embodiment, the preset rule may be selecting the third antenna element 211C corresponding to a higher signal power according to the power strength of the signal received by the third antenna element 211C.

[0063] In some possible implementations, the gating circuit 215C may be a single-pole multi-throw switch.

[0064] In some possible implementations, the third RF processing circuit 210C further includes multiple low-noise amplifiers 216C; input ends of the multiple low-noise amplifiers 216C are correspondingly coupled to the multiple third antenna array elements 211C, and output ends of the multiple low-noise amplifiers 216C are coupled to the combining ends of the multiple power dividers 213C.

[0065] In one example, FIG14 shows a third RF processing circuit 210C for transmitting and receiving common phase shift. The circuit includes a single-pole double throw (SPDT) switch, a switch, or a circulator. The SPDT switch is used to switch operating time slots, such as a downlink operating time slot or an uplink operating time slot.

[0066] In one example, as shown in FIG15 , a third RF processing circuit 210C with independent phase shifting for transmission and reception is shown, which includes a SPDT, a switch, or a circulator.

[0067] In an embodiment of the present application, a power splitter is provided at the output end of a low-noise amplifier to receive a signal processed by the low-noise amplifier, thereby reducing the impact of noise introduced by the antenna array element end on the RF reference signal, thereby improving the quality of the signal received at the power splitter side.

[0068] In some possible implementations, as shown in FIG16 , the third RF processing circuit 210C further includes a power amplifier 217C; and the channel detection channel 214C is a power amplifier feedback channel 218C corresponding to the power amplifier 217C.

[0069] For example, as shown in FIG16 , when the RF signal is output from the third RF channel 212C, it needs to be amplified by the power amplifier 217C before it can be transmitted through the third antenna array element 211C. Ideally, the power amplifier 217C receives an input signal and outputs a higher power signal proportional to its input, thereby converting most of the DC power provided to the amplifier into signal output power. However, this is not an ideal situation, as the power amplifier 217C is made of power tubes. Power tubes are active devices that exhibit linear characteristics only within a certain operating range. When the power tube-based power amplifier 217C operates in the linear operating range, its output power is proportional to the input power by a certain amplification gain. When the power amplifier 217C operates at the saturation point of the linear operating range, it can achieve maximum operating efficiency. With the development of wireless communication technology, the modulation order of RF signals has become increasingly complex, resulting in RF signals with higher signal peak-to-average ratios. When the signal peak-to-average ratio increases, if power amplifier 217C operates at a higher power point in the linear operating region (even at the saturation power point in the linear operating range), the RF signal input to power amplifier 217C can easily enter the nonlinear operating range or even the saturation operating range of power amplifier 217C. This can cause significant nonlinear distortion in the RF signal output by power amplifier 217C, affecting communication. To avoid this nonlinear distortion, a certain amount of power back-off is typically performed, so that the saturation power point of power amplifier 217C in the linear operating range is backed off by a certain amount. However, the disadvantage of this power back-off is that it significantly reduces the operating efficiency of power amplifier 217C, causing most of the power provided by the power supply of power amplifier 217C to be lost as heat. Therefore, to reduce power loss, one improvement is to design a power combining architecture for power amplifier 217C, using a power amplifier circuit such as a Doherty architecture or other power combining architecture to improve the back-off amount and operating efficiency of power amplifier 217C. Another approach is to provide a predistortion amplifier circuit in the power amplifier 217C. The predistortion amplifier circuit pre-imposes nonlinear distortion characteristics opposite to those of the power amplifier 217C on the RF signal input to the power amplifier 217C, thereby compensating for the nonlinear distortion of the power amplifier 217C when operating in the power saturation range. The predistortion amplifier circuit can be a digital predistortion amplifier circuit or an analog predistortion amplifier circuit. In the process of using the predistortion amplifier circuit to compensate for nonlinear distortion, it is necessary to obtain the output RF signal from the output end of the power amplifier 217C in real time by branching. Feedback is provided based on the RF signal output by the power amplifier 217C, and the nonlinear distortion characteristics of the predistortion amplifier circuit are dynamically adjusted using the fed-back RF signal, thereby ensuring a good nonlinear compensation effect on the power amplifier 217C.During this feedback process, a corresponding pre-distortion feedback (FB) channel needs to be provided for the power amplifier 217C to enable sampling of the RF signal output by the power amplifier 217C. The power amplifier feedback channel 218C in this embodiment can be the pre-distortion feedback channel of the power amplifier 217C. The third RF processing circuit 210C is a HBF architecture that reuses FB channels, i.e., the original FB channel of the third RF processing circuit 210C is shared as the channel detection channel 214C, thereby enabling the channel detection channel 214C to be shared with the original FB channel of the third RF processing circuit 210C, thereby reducing hardware consumption. The FB channel is used for pre-distortion feedback of the HBF architecture power amplifier 217C. As shown in FIG16 , the branch end of the gating circuit 215C is coupled to the coupler, and the output of the power amplifier 217C is mainly fed back to the RF channel 12 for digital pre-distortion training. The branch end of the gating circuit 215C is coupled to the power divider 213C to provide a solution for this embodiment. Through an SPDT, since the pre-distortion of the power amplifier 217C in the coupling part of the branch end of the gating circuit 215C and the coupler mainly works in the downlink time slot, and the channel detection of this embodiment is used for the uplink time slot, the FB channel can be efficiently multiplexed through the single-pole double-throw switch, thereby reducing hardware investment and lowering hardware cost.

[0070] In some possible implementations, the baseband processing device 100 is configured to obtain antenna array element-level channel information of the RF processing circuit 210 according to the RF reference signal.

[0071] For example, the RF reference signal contains channel state information. In a communication system, the signal state information in the RF reference signal can be used to guide the transmission strategy of the transmitter. For example, when transmitting information, the transmitter can avoid propagation paths with poor channel conditions or select propagation paths with good channel conditions based on the acquired channel information, thereby improving the performance of the communication system.

[0072] In some possible implementations, as shown in FIG. 17 , the RF processing device 200 includes a controller 230 , and the controller 230 is configured to obtain antenna array element-level channel information of the RF processing circuit 210 according to the RF reference signal.

[0073] Based on the structures shown in Figures 11, 12, 13, 14, 15, and 16, a signal processing method including the following steps S100 to S300 as shown in Figure 18 can be implemented. This method can be applied to a radio frequency processing circuit, which includes a radio frequency channel, multiple power splitters, and a channel detection channel. The specific steps include:

[0074] S100: Multiple power splitters obtain corresponding multiple radio frequency signals from multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals.

[0075] For example, as shown in Figure 11, the RF processing circuit may include multiple RF channels. Each RF channel may be coupled to multiple power splitters, each of which may be coupled to one or more antenna elements. The circuit acquires corresponding RF signals from one or more antenna elements and performs branching processing on the RF signals to obtain a first RF data signal and a RF reference signal. The first RF data signal includes information transmitted by the channel; the RF reference signal includes channel attribute information and channel quality information, such as channel phase, amplitude, and delay.

[0076] In one example, the power splitter obtains the RF signal of the corresponding channel from the antenna array element and splits the RF signal into two to obtain a first RF data signal and a RF reference signal, which are used for RF channel input and channel detection channel input respectively.

[0077] S200: A radio frequency channel inputs a plurality of first radio frequency data signals.

[0078] S300: A channel sounding channel inputs multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element-level channel information.

[0079] In an embodiment of the present application, first, the effect of increasing the antenna gain is achieved by mapping a radio frequency channel to multiple antenna elements. Secondly, the power divider in the radio frequency processing circuit branches the multiple radio frequency signals obtained from multiple antenna elements to obtain multiple first radio frequency data signals and multiple radio frequency reference signals. Then, the radio frequency channel inputs multiple first radio frequency data signals for obtaining channel transmission information; the channel detection channel inputs multiple radio frequency reference signals for obtaining antenna element-level channel information. By setting different channels for obtaining different information in the channel, the purpose of enhancing the channel measurement capability is achieved. This avoids the related art where only one radio frequency channel is used, that is, for obtaining channel transmission information and for obtaining antenna element-level channel information, resulting in a lengthened channel measurement period, an increase in time overhead, an increase in network system performance loss, and accelerated channel aging.

[0080] In some possible implementations, step S300 may include the following sub-operations:

[0081] S310 . Input a control signal. The control signal is used to instruct selection of one or more of a plurality of RF reference signals.

[0082] Exemplarily, the control signal may be generated based on preset information included in the RF reference signal. The preset information may include energy information, signal quality information, etc. of the RF reference signal, which is not limited here.

[0083] S320: In response to the control signal, input one or more of the plurality of radio frequency reference signals.

[0084] Exemplarily, in response to the control signal, the channel sounding channel inputs one or more of the multiple RF reference signals to obtain antenna element-level channel information. In this embodiment, multiple of the multiple RF reference signals may be input at different times.

[0085] In some possible implementations, the RF processing circuit further includes a power amplifier; the channel detection channel is a power amplifier feedback channel corresponding to the power amplifier; the method further includes: in a first time slot, the RF channel transmits a second RF data signal through an antenna array element; inputs one or more of a plurality of RF reference signals, and further includes: in a second time slot, the channel detection channel inputs one or more of the plurality of RF reference signals; the first time slot and the second time slot are interval time slots.

[0086] For example, as shown in Figure 16, the power amplifier feedback channel can be used to provide feedback on power amplifier predistortion. The first time slot and the second time slot correspond to different operating states, for example, the first time slot can correspond to a downlink time slot operating state, and the second time slot can correspond to an uplink time slot operating state. The specific implementation process can be found in the description of the corresponding section above and will not be repeated here.

[0087] Exemplarily, the power amplifier feedback channel may be a power amplifier predistortion feedback channel.

[0088] In the embodiment of the present application, the power amplifier feedback channel is multiplexed as a channel detection channel to reduce the RF circuit hardware consumption and lower the hardware cost.

[0089] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0090] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0091] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0092] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0095] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0096] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0097] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0098] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A radio frequency processing circuit, characterized in that: It includes a radio frequency channel, a plurality of power dividers and a channel detection channel; the combining ends of the plurality of power dividers are coupled with a plurality of antenna array elements; the first branching ends of the plurality of power dividers are coupled with the input end of the radio frequency channel; The second branch ends of the plurality of power dividers are coupled to the input end of the channel detection channel; The multiple power dividers are used to: obtain corresponding multiple radio frequency signals from multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals; The radio frequency channel is used to: input the multiple first radio frequency data signals; The channel detection channel is used to: input the multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

2. The radio frequency processing circuit according to claim 1, characterized in that: The radio frequency processing circuit also includes a gating circuit; The second branch terminals of the plurality of power dividers are coupled to the branch terminal of the gating circuit; The common terminal of the gating circuit is coupled to the input terminal of the channel detection channel.

3. The radio frequency processing circuit according to claim 2, characterized in that: The gating circuit is a single-pole multi-throw switch.

4. The radio frequency processing circuit according to any one of claims 1 to 3, characterized in that: The radio frequency processing circuit also includes a plurality of low noise amplifiers; The input ends of the multiple low noise amplifiers are coupled to the multiple antenna array elements accordingly, and the output ends of the multiple low noise amplifiers are coupled to the combining ends of the multiple power dividers.

5. The radio frequency processing circuit according to any one of claims 1 to 4, characterized in that: The radio frequency processing circuit also includes a power amplifier; The channel detection channel is a power amplifier feedback channel corresponding to the power amplifier.

6. A signal processing method, characterized in that: Applied to a radio frequency processing circuit, the radio frequency processing circuit includes a radio frequency channel, a plurality of power dividers and a channel detection channel; the method includes: The multiple power dividers obtain the corresponding multiple radio frequency signals from the multiple antenna array elements, and perform branching processing on the multiple radio frequency signals to obtain multiple first radio frequency data signals and multiple radio frequency reference signals; The radio frequency channel inputs the plurality of first radio frequency data signals; The channel detection channel inputs the multiple radio frequency reference signals; the multiple radio frequency reference signals are used to obtain antenna array element level channel information.

7. The signal processing method according to claim 6, characterized in that: The inputting the multiple radio frequency reference signals comprises: input a control signal; the control signal is used to indicate the selection of one or more of the multiple radio frequency reference signals; In response to the control signal, one or more of the plurality of radio frequency reference signals are input.

8. The signal processing method according to claim 6 or 7, characterized in that: The radio frequency processing circuit also includes a power amplifier; the channel detection channel is a power amplifier feedback channel corresponding to the power amplifier; The method further includes: in the first time slot, the radio frequency channel transmits a second radio frequency data signal through the antenna array element; The inputting one or more of the multiple RF reference signals also includes: in the second time slot, the channel detection channel inputting one or more of the multiple RF reference signals; the first time slot and the second time slot are interval time slots.

9. A radio frequency processing device, characterized in that: It comprises a circuit board and the radio frequency processing circuit according to any one of claims 1 to 5, wherein the radio frequency processing circuit is arranged on the circuit board.

10. A communication system, characterized in that: include: A baseband processing device and a radio frequency processing device as claimed in claim 9; The baseband processing device is coupled to the radio frequency processing device; The radio frequency processing device is used to: output a plurality of radio frequency reference signals to the baseband processing device; the plurality of radio frequency reference signals are used to obtain antenna array element level channel information.

11. The communication system according to claim 10, characterized in that: The baseband processing device is used to obtain antenna array element level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

12. The communication system according to claim 10, characterized in that: The radio frequency processing device comprises a controller; the controller is used to obtain antenna array element level channel information of the radio frequency processing circuit according to the radio frequency reference signal.

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