Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a base substrate, an edge pixel group and a row driving circuit, wherein the base substrate comprises a display area and a peripheral area; the edge pixel group comprises a plurality of edge sub-pixels; the display area comprises an intermediate display area and an edge display area located on the side of the intermediate display area close to the peripheral area; each edge sub-pixel comprises an edge pixel driving circuit and an anode connected to the edge pixel driving circuit; the edge pixel group is located in the edge display area; and the row driving circuit is at least partially located in the edge display area and overlaps the anode of at least one edge sub-pixel in the edge pixel group. Thus, in the display panel, a row driving circuit can be at least partially arranged under a display area, instead of placing the entire row driving circuit in a peripheral area, so that the width of the peripheral area can be reduced, thereby reducing the bezel width of the display panel and realizing an ultra-narrow bezel.

Description

Display panel and display device Technical Field

[0001] Embodiments of the present application relate to a display panel and a display device. Background Art

[0002] With the continuous development of information technology, large-scale, high-resolution screens are increasingly being used in various scenarios, from command centers, monitoring centers, and network management centers to conferences and lectures. However, a single screen cannot meet these requirements.

[0003] Screen splicing technology combines multiple screens into a single display, dividing a complete image into multiple sub-images and displaying them separately on each screen. Therefore, screen splicing technology can achieve large-scale and high-resolution displays. Furthermore, screen splicing technology has broad market prospects because the screens used can not only be combined to form a large screen, but can also be used individually for display.

[0004] Active-matrix organic light-emitting diode (AMOLED) display technology, meanwhile, is becoming increasingly popular for various electronic products due to its advantages, including high contrast, wide viewing angles, fast response times, and thinness. By integrating AMOLED display technology with screen splicing, large-scale, high-resolution, high-contrast, wide viewing angles, fast response times, and thinness can be achieved.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a display panel and a display device. By at least partially disposing a row drive circuit in an edge display area and overlapping with the anode of at least one edge sub-pixel in an edge pixel group, the display panel can dispose the row drive circuit at least partially below the display area, without placing the entire row drive circuit in the peripheral area, thereby reducing the width of the peripheral area; and, by arranging multiple gate drive units and multiple light-emitting control units along a second direction, and allowing the multiple gate drive units and multiple light-emitting control units to share at least one of a clock signal line, a start line, a first power line, and a second power line, the display device can further reduce the width occupied by the row drive circuit and various drive lines, thereby further reducing the width of the peripheral area. In this way, the display panel has an extremely narrow frame.

[0007] At least one embodiment of the present disclosure provides a display device comprising a plurality of display panels spliced ​​together, wherein each display panel comprises: a base substrate comprising a display area and a peripheral area; an edge pixel group comprising a plurality of edge sub-pixels; and a row driving circuit comprising a plurality of gate driving units and a plurality of light emitting control units. The display area comprises a middle display area and an edge display area located on a side of the middle display area close to the peripheral area. Each edge sub-pixel comprises an edge pixel driving circuit and an anode connected to the edge pixel driving circuit. The edge pixel group is located in the edge display area. The row driving circuit is at least partially located in the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group. The plurality of edge pixel driving circuits of the plurality of edge sub-pixels in the edge pixel group are arranged along a first direction. The plurality of gate driving units and the plurality of light emitting control units are arranged along a second direction, the second direction being perpendicular to the first direction. The display panel further comprises a clock signal line, an enable line, a first power line, and a second power line, configured to drive the row driving circuit. The plurality of gate driving units and the plurality of light emitting control units share at least one of the clock signal line, the enable line, the first power line, and the second power line.

[0008] For example, in the display device provided in an embodiment of the present disclosure, each of the gate driving units includes an output transistor and an input transistor, the light-emitting control unit includes an output transistor and an input transistor, the second power line extends along the second direction and passes through the multiple gate driving units and the multiple light-emitting control units, the multiple gate driving units and the multiple light-emitting control units share the second power line, the output transistors of the gate driving units and the output transistors of the light-emitting control units are located on the first side of the second power line in the first direction, and the input transistors of the gate driving units and the input transistors of the light-emitting control units are located on the second side of the second power line in the first direction.

[0009] For example, in the display device provided in an embodiment of the present disclosure, the clock signal line, the start line and the first power line are located on a side of the input transistor of the gate driving unit and the input transistor of the light emitting control unit away from the second power line.

[0010] For example, in the display device provided by an embodiment of the present disclosure, the second power line is located within the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group.

[0011] For example, in the display device provided in an embodiment of the present disclosure, the clock signal line, the start line and the first power line are located within the edge display area and overlap with the anode of at least one edge sub-pixel in the edge pixel group.

[0012] For example, in the display device provided in an embodiment of the present disclosure, the output ends of two adjacent gate driving units in the second direction are connected to provide gate driving signals for the edge sub-pixels located in the same row in the same edge pixel group.

[0013] For example, in the display device provided in an embodiment of the present disclosure, two gate driving units are arranged between two adjacent light emitting control units.

[0014] For example, in a display device provided in an embodiment of the present disclosure, the row driving circuit further includes a virtual driving unit, which is not connected to the clock signal line, the start line and the first power line, and the virtual driving unit and the multiple gate driving units and the multiple light-emitting control units are arranged along the second direction.

[0015] For example, in the display device provided by an embodiment of the present disclosure, the virtual driving unit is inserted between the light emitting control units corresponding to a row of edge sub-pixels and the gate driving units corresponding to the next row of edge sub-pixels.

[0016] For example, in the display device provided in one embodiment of the present disclosure, the peripheral area, the edge display area and the middle display area are arranged along a first direction; in the edge pixel group, the size of the multiple edge pixel driving circuits of the multiple edge sub-pixels in the first direction is smaller than the size of the multiple anodes of the multiple edge sub-pixels in the first direction.

[0017] For example, in the display device provided in one embodiment of the present disclosure, all of the row driving circuits are located in the edge display area, and the orthographic projection of the edge of the row driving circuit away from the middle display area on the base substrate overlaps with the orthographic projection of the anode of the outermost edge sub-pixel in the edge pixel group on the base substrate.

[0018] For example, the display device provided by an embodiment of the present disclosure also includes: an intermediate pixel group, including multiple intermediate sub-pixels, the intermediate pixel group is located in the intermediate display area, and each intermediate sub-pixel includes an intermediate pixel driving circuit and an anode connected to the intermediate pixel driving circuit; the area occupied by the multiple intermediate pixel driving circuits of the multiple intermediate sub-pixels in the intermediate pixel group and the intervals between the multiple intermediate pixel driving circuits are larger than the area occupied by the multiple edge pixel driving circuits of the multiple edge sub-pixels in the edge pixel group and the intervals between the multiple edge pixel driving circuits.

[0019] For example, in a display device provided in an embodiment of the present disclosure, an area occupied by the intervals between the multiple intermediate pixel driving circuits of the multiple intermediate sub-pixels in the intermediate pixel group is greater than an area occupied by the intervals between the multiple edge pixel driving circuits of the multiple edge sub-pixels in the edge pixel group.

[0020] For example, in a display device provided in an embodiment of the present disclosure, the edge pixel group includes a first edge sub-pixel, a second edge sub-pixel, and a third edge sub-pixel, and the intermediate pixel group includes a first intermediate sub-pixel, a second intermediate sub-pixel, and a third intermediate sub-pixel. The first edge sub-pixel and the first intermediate sub-pixel are configured to emit light of a first color, the second edge sub-pixel and the second intermediate sub-pixel are configured to emit light of a second color, and the third edge sub-pixel and the third intermediate sub-pixel are configured to emit light of a third color.

[0021] For example, in a display device provided in one embodiment of the present disclosure, the anode of the first edge sub-pixel is the same size as the anode of the first middle sub-pixel, the anode of the second edge sub-pixel is the same size as the anode of the second middle sub-pixel, and the anode of the third edge sub-pixel is the same size as the anode of the third middle sub-pixel.

[0022] For example, in the display device provided by an embodiment of the present disclosure, the row driving circuit is located on a side of the edge pixel group away from the middle display area of ​​the plurality of edge pixel driving circuits.

[0023] For example, in a display device provided in an embodiment of the present disclosure, each edge sub-pixel further includes: an edge organic light-emitting layer located on a side of the anode away from the base substrate; and a cathode located on a side of the edge organic light-emitting layer away from the base substrate.

[0024] At least one embodiment of the present disclosure further provides a display panel, comprising: a base substrate comprising a display area and a peripheral area; an edge pixel group comprising a plurality of edge sub-pixels; and a row driving circuit comprising a plurality of gate driving units and a plurality of light emitting control units, wherein the display area comprises a middle display area and an edge display area located on a side of the middle display area close to the peripheral area, and each of the edge sub-pixels comprises an edge pixel driving circuit and an anode connected to the edge pixel driving circuit; the edge pixel group is located in the edge display area, the row driving circuit is at least partially located in the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group, the plurality of edge pixel driving circuits of the plurality of edge sub-pixels in the edge pixel group are arranged along a first direction, the plurality of gate driving units and the plurality of light emitting control units are arranged along a second direction, the second direction being perpendicular to the first direction, and the display panel further comprises a clock signal line, an enable line, a first power line, and a second power line, configured to drive the row driving circuit, the plurality of gate driving units and the plurality of light emitting control units sharing at least one of the clock signal line, the enable line, the first power line, and the second power line.

[0025] For example, in the display panel provided in an embodiment of the present disclosure, each of the gate driving units includes an output transistor and an input transistor, the light-emitting control unit includes an output transistor and an input transistor, the second power line extends along the second direction and passes through the multiple gate driving units and the multiple light-emitting control units, the multiple gate driving units and the multiple light-emitting control units share the second power line, the output transistors of the gate driving units and the output transistors of the light-emitting control units are located on the first side of the second power line in the first direction, and the input transistors of the gate driving units and the input transistors of the light-emitting control units are located on the second side of the second power line in the first direction.

[0026] For example, in the display panel provided by an embodiment of the present disclosure, the clock signal line, the start line and the first power line are located on a side of the input transistor of the gate driving unit and the input transistor of the light emitting control unit away from the second power line.

[0027] For example, in the display panel provided in an embodiment of the present disclosure, the second power line is located within the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group.

[0028] For example, in the display panel provided in an embodiment of the present disclosure, the clock signal line, the start line and the first power line are located within the edge display area and overlap with the anode of at least one edge sub-pixel in the edge pixel group. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not limitations to the present application.

[0030] FIG1 is a schematic diagram of a display panel provided in accordance with an embodiment of the present disclosure;

[0031] FIG2 is a partial schematic diagram of a row driving circuit provided in one embodiment of the present disclosure;

[0032] FIG3 is a schematic diagram of the overlap of a row driving circuit and an anode in a display panel provided by an embodiment of the present disclosure;

[0033] FIG4 is an equivalent circuit diagram of a gate driving unit in a display panel provided by an embodiment of the present disclosure;

[0034] 5A-5E are layout diagrams of a gate driving unit in a display panel according to an embodiment of the present disclosure;

[0035] FIG6 is an equivalent circuit diagram of a light emitting control unit in a display panel provided by an embodiment of the present disclosure;

[0036] 7A-7E are layout diagrams of a light emitting control unit in a display panel according to an embodiment of the present disclosure;

[0037] FIG8 is a schematic cross-sectional view of an edge sub-pixel in a display panel provided by an embodiment of the present disclosure;

[0038] FIG9 is a schematic diagram of another display panel provided in an embodiment of the present disclosure;

[0039] FIG10 is a schematic diagram of a row driving circuit in a display panel provided in an embodiment of the present disclosure;

[0040] FIG11 is a schematic diagram showing signal line connections in a row driving circuit of a display panel according to an embodiment of the present disclosure;

[0041] FIG12 is a schematic diagram of another display panel provided in an embodiment of the present disclosure; and

[0042] FIG13 is a schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0045] In screen splicing technology, in order to achieve excellent display effects, color-blur-free splicing and seamless splicing are very important technical points. To achieve seamless splicing, the screen used for splicing needs to have extremely narrow bezels.

[0046] In this regard, embodiments of the present disclosure provide a display panel and a display device. The display panel includes a substrate, an edge pixel group, and a row driver circuit; the substrate includes a display area and a peripheral area; the edge pixel group includes a plurality of edge sub-pixels; the row driver circuit includes a plurality of gate driver units and a plurality of light-emitting control units; the display area includes a middle display area and an edge display area located on a side of the middle display area close to the peripheral area; each edge sub-pixel includes an edge pixel driver circuit and an anode connected to the edge pixel driver circuit; the edge pixel group is located in the edge display area; the row driver circuit is at least partially located in the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group; the plurality of edge pixel driver circuits of the plurality of edge sub-pixels in the edge pixel group are arranged along a first direction, the plurality of gate driver units and the plurality of light-emitting control units are arranged along a second direction, the second direction being perpendicular to the first direction; the display panel also includes a clock signal line, an enable line, a first power line, and a second power line, configured to drive the row driver circuit; the plurality of gate driver units and the plurality of light-emitting control units share at least one of the clock signal line, the enable line, the first power line, and the second power line. Thus, by disposing the row driver circuit at least partially in the edge display area and overlapping the anode of at least one edge sub-pixel in the edge pixel group, the display panel can dispose the row driver circuit at least partially below the display area, rather than placing the entire row driver circuit in the peripheral area, thereby reducing the width of the peripheral area. Furthermore, by arranging multiple gate driver units and multiple light-emitting control units along the second direction and allowing the multiple gate driver units and multiple light-emitting control units to share at least one of the clock signal line, the enable line, the first power line, and the second power line, the display device can further reduce the width occupied by the row driver circuit and various driver lines, thereby further reducing the width of the peripheral area. In this way, the display panel has an extremely narrow bezel.

[0047] The present disclosure also provides a display device comprising a plurality of the aforementioned display panels spliced ​​together. This display device can combine multiple display panels into a large-scale, high-resolution display device by splicing them together. Furthermore, because the display panels have extremely narrow bezels, the display device can achieve seamless splicing, thereby providing excellent display effects.

[0048] Below, the display panel and the display device provided by the embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0049] FIG1 is a schematic diagram of a display panel provided in accordance with an embodiment of the present disclosure; FIG2 is a partial schematic diagram of a row driving circuit provided in accordance with an embodiment of the present disclosure. As shown in FIG1 , the display panel 100 includes a base substrate 110, an edge pixel group 120, and a row driving circuit 140; the base substrate 110 includes a display area 112 and a peripheral area 114; the edge pixel group 120 includes a plurality of edge sub-pixels 125; the row driving circuit 140 includes a plurality of gate driving units 141 and a plurality of light-emitting control units 142; the display area 112 includes a middle display area 112A and an edge display area 112B located near the peripheral area 114 in the middle display area 112A; each edge sub-pixel 125 includes an edge pixel driving circuit 1251 and an anode 1252 connected to the edge pixel driving circuit 1251. The edge pixel driving circuit 1251 can provide a driving current to the anode 1252 to drive the light-emitting layer on the anode 1252 to emit light for display.

[0050] As shown in FIG1 , the edge pixel group 120 is located in the edge display area 112B, and the row driving circuit 140 is at least partially located in the edge display area 112B and overlaps with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120; that is, the orthographic projection of the row driving circuit 140 on the base substrate 110 overlaps with the orthographic projection of the anode 1252 of at least one edge sub-pixel 124 in the edge pixel group 120 on the base substrate 110.

[0051] In conventional display panels, the row driver circuitry can be integrated into the peripheral area using Gate Driver on Array (GOA) technology. This allows the row driver circuitry to directly provide row driver signals, such as gate drive signals and light-emitting control signals, to the sub-pixel array, eliminating the need for additional gate driver chips and corresponding binding structures. This reduces costs and reduces bezel width. However, in this case, the row driver circuitry itself still occupies a certain width, making it impossible to achieve an extremely narrow bezel.

[0052] In the display panel provided by the embodiment of the present disclosure, by setting the row driving circuit at least partially in the edge display area and overlapping with the anode of at least one edge sub-pixel in the edge pixel group, the display panel can set the row driving circuit at least partially below the display area without placing the entire row driving circuit in the peripheral area, thereby reducing the width of the peripheral area.

[0053] Furthermore, as shown in FIG1 , the plurality of edge pixel driving circuits 1251 for the plurality of edge sub-pixels 125 in the edge pixel group 120 are arranged along a first direction, and the plurality of gate driving units 141 and the plurality of light-emitting control units 142 are arranged along a second direction, which intersects the first direction. As shown in FIG2 , the display panel 100 further includes a clock signal line 151, an enable line 152, a first power line 153, and a second power line 154, which are configured to drive the row driving circuit 140; the plurality of gate driving units 141 and the plurality of light-emitting control units 142 share at least one of the clock signal line 151, the enable line 152, the first power line 153, and the second power line 154.

[0054] In a typical display panel, the row driver circuit needs to provide gate drive signals and emission drive signals to the pixel driver circuit in the display area. The gate driver unit that provides the gate drive signal and the light control unit that provides the light control signal are arranged side by side, that is, arranged along a first direction, and therefore have a larger size in the first direction. In the display panel provided by the embodiments of the present disclosure, by arranging multiple gate driver units and multiple light control units along a second direction, the display panel can reduce the size of the row driver circuit in the first direction, thereby enabling the entire row driver circuit to be arranged in the edge display area. Furthermore, by sharing at least one of the clock signal line, the enable line, the first power line, and the second power line among the multiple gate driver units and the multiple light control units, the display device can further reduce the width occupied by the row driver circuit and various drive lines, thereby further reducing the width of the peripheral area. Thus, through the above-mentioned multiple designs, the display panel has an extremely narrow bezel. Furthermore, when the display panel provided by the embodiments of the present disclosure is used for a spliced ​​display, the spliced ​​display device can achieve seamless splicing and have an excellent display effect.

[0055] For example, the first direction and the second direction may be perpendicular to each other. Of course, the embodiments of the present disclosure include but are not limited to this.

[0056] In some examples, as shown in FIG. 2 , multiple gate driving units 141 and multiple light emitting control units 142 share a clock signal line 151 , a start line 152 , a first power line 153 , and a second power line 154 , thereby minimizing the number of signal lines.

[0057] In some examples, as shown in FIG2 , each gate driver unit 141 includes an output transistor GT5 and an input transistor GT1, and each emission control unit 142 includes an output transistor ET10 and an input transistor ET1. A second power line 154 extends along a second direction and passes through the plurality of gate driver units 141 and the plurality of emission control units 142. The plurality of gate driver units 141 and the plurality of emission control units 142 share the second power line 154. The output transistor GT5 of the gate driver unit 141 and the output transistor ET10 of the emission control unit 142 are located on a first side of the second power line 154 in the first direction, while the input transistor GT1 of the gate driver unit 142 and the input transistor ET1 of the emission control unit 142 are located on a second side of the second power line 154 in the first direction. In other words, the output transistor GT5 of the gate driver unit 141 and the output transistor ET10 of the emission control unit 142 are located on the same side of the second power line 154 in the first direction, while the input transistor GT1 of the gate driver unit 142 and the input transistor ET1 of the emission control unit 142 are located on the other side of the second power line 154 in the first direction. Therefore, the display panel can use the space occupied by the gate driving unit and the light-emitting control unit to set the second power line. On the one hand, it can make the layout of the second power line, the gate driving unit and the light-emitting control unit more compact and easier to connect. On the other hand, it can further reduce the width occupied by the row driving circuit and the second power line as a whole.

[0058] It should be noted that although FIG2 shows the specific circuit structure adopted by the gate drive unit and the light-emitting control unit, the specific circuit structure of the gate drive unit and the light-emitting control unit in the embodiment of the present disclosure includes but is not limited to this; on the other hand, since the output transistor generally needs to have a larger area (due to a larger channel width-to-length ratio), even if the gate drive unit and the light-emitting control unit adopt other types of specific circuit structures, the above design can still be adopted. In addition, in order to more clearly illustrate the positions of each transistor and capacitor, the reference numerals of the other transistors and capacitors in the gate drive unit 141 in FIG2 omit "G", and the reference numerals of the other transistors and capacitors in the light-emitting control unit 142 omit "E".

[0059] In some examples, as shown in FIG. 2 , the clock signal line 151 , the start line 152 , and the first power line 153 are located on a side of the input transistor GT1 of the gate driving unit 141 and the input transistor ET1 of the light emitting control unit 142 away from the second power line 154 .

[0060] Figure 3 is a schematic diagram illustrating the overlap of a row driver circuit and anodes in a display panel according to an embodiment of the present disclosure. As shown in Figure 3 , the second power line 154 is located within the edge display region 112B and overlaps with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120.

[0061] 3 , the clock signal line 151, the start line 152, and the first power line 153 are located within the edge display area 112B and overlap with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120. Thus, the display panel can further reduce the width of the peripheral area.

[0062] In some examples, as shown in FIG. 2 , the output ends of two adjacent gate driving units 141 in the second direction are connected to provide gate driving signals to edge sub-pixels 125 in the same row in the same edge pixel group 120 , thereby reducing fluctuations in the gate driving signals and stabilizing the input of the data voltage.

[0063] In some examples, as shown in Figures 1 and 2, two gate driving units 141 are provided between two adjacent light emitting control units 142. The two gate driving units 141 jointly provide gate driving signals to sub-pixels (including edge sub-pixels and middle sub-pixels) located in the same row, thereby reducing fluctuations in the gate driving signals and stabilizing the input of the data voltage.

[0064] In some examples, as shown in FIG1 , the peripheral area 114, the edge display area 112B, and the middle display area 112A are arranged along a first direction. In an edge pixel group 120, the size of the plurality of edge pixel driving circuits 1251 of the plurality of edge sub-pixels 125 in the first direction is smaller than the size of the plurality of anodes 1252 of the plurality of edge sub-pixels 125 in the first direction. By reducing the space occupied by the edge pixel driving circuits 1251, the display panel allows the row driving circuit 140 to overlap with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120, thereby reducing the border width.

[0065] In some examples, as shown in FIG1 , the entire row driver circuit 140 is located in the edge display area 112B, and the orthographic projection of the edge of the row driver circuit 140 away from the middle display area 112A on the base substrate 110 overlaps with the orthographic projection of the anode 1252 of the outermost edge sub-pixel 125 in the edge pixel group 120 on the base substrate 110. Thus, the width of the peripheral area of ​​the display panel can be minimized.

[0066] In some examples, as shown in FIG1 , the display panel 100 further includes an intermediate pixel group 130 including a plurality of intermediate sub-pixels 135. The intermediate pixel group 130 is located in the intermediate display area 112A, and each intermediate sub-pixel 135 includes an intermediate pixel driving circuit 1351 and an anode 1352 connected to the intermediate pixel driving circuit 1351. The area occupied by the plurality of intermediate pixel driving circuits 1351 and the spacing between the plurality of intermediate pixel driving circuits 1351 in the plurality of intermediate sub-pixels 135 in the intermediate pixel group 130 is greater than the area occupied by the plurality of edge pixel driving circuits 1251 and the spacing between the plurality of edge pixel driving circuits 1251 in the plurality of edge sub-pixels 125 in the edge pixel group 120. Thus, the display panel can reduce the border width by reducing the area occupied by the spacing between the edge pixel driving circuits, thereby allowing the row driving circuit 140 to overlap with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120.

[0067] It should be noted that the middle sub-pixels and edge sub-pixels here only differ in position and some structures; they are all sub-pixels used to display the same image; in some examples, the type, color, and size of light emitted by the middle sub-pixels and edge sub-pixels are the same.

[0068] In some examples, as shown in FIG1 , the area occupied by the spaces between the plurality of middle pixel driving circuits 1351 of the plurality of middle sub-pixels 135 in the middle pixel group 130 is larger than the area occupied by the spaces between the plurality of edge pixel driving circuits 1251 of the plurality of edge sub-pixels 125 in the edge pixel group 120. Thus, the display panel can reduce the area occupied by the spaces between the edge pixel driving circuits so that the row driving circuit 140 can overlap with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120, thereby reducing the border width.

[0069] In some examples, as shown in FIG1 , edge pixel group 120 includes a first edge sub-pixel 125A, a second edge sub-pixel 125B, and a third edge sub-pixel 125C. That is, edge sub-pixels 125 include first edge sub-pixel 125A, second edge sub-pixel 125B, and third edge sub-pixel 125C. Middle pixel group 130 includes a first middle sub-pixel 135A, second middle sub-pixel 135B, and third middle sub-pixel 135C. That is, middle sub-pixels 135 include first middle sub-pixel 135A, second middle sub-pixel 135B, and third middle sub-pixel 135C. First edge sub-pixel 125A and first middle sub-pixel 135A are configured to emit light of a first color, second edge sub-pixel 125B and second middle sub-pixel 135B are configured to emit light of a second color, and third edge sub-pixel 125C and third middle sub-pixel 135C are configured to emit light of a third color. Thus, the edge pixel group and middle pixel group of the display panel have the same composition.

[0070] For example, the first color is red, the second color is green, and the third color is blue. Of course, the embodiments of the present disclosure include but are not limited to this, and the first color, the second color, and the third color may also be other colors.

[0071] In some examples, as shown in FIG1 , the anode of the first edge sub-pixel 125A is the same size as the anode of the first middle sub-pixel 135A, the anode of the second edge sub-pixel 125B is the same size as the anode of the second middle sub-pixel 135B, and the anode of the third edge sub-pixel 125C is the same size as the anode of the third middle sub-pixel 135C. Thus, the display panel can improve display quality.

[0072] In some examples, as shown in FIG1 , the anode of third edge sub-pixel 125C is larger than the anode of first edge sub-pixel 125A and the anode of second edge sub-pixel 125B; and the anode of third middle sub-pixel 135C is larger than the anode of first middle sub-pixel 135A and the anode of second middle sub-pixel 135B. Thus, the display panel can balance the lifespans of sub-pixels of different colors.

[0073] 1 , the row driver circuit 140 is located on a side of the edge pixel group 120 away from the middle display area 112B, on the side of the edge pixel driver circuits 1251. However, embodiments of the present disclosure include but are not limited to this, and the row driver circuit may also be located between the edge pixel driver circuits in the edge pixel group.

[0074] FIG4 is an equivalent circuit diagram of a gate drive unit in a display panel provided by an embodiment of the present disclosure. As shown in FIG4 , the gate drive unit 141 includes an input transistor GT1, a first control transistor GT2, a second control transistor GT3, an output control transistor GT4, an output transistor GT5, a first noise reduction transistor GT7, a second noise reduction transistor GT6, a voltage regulator transistor GT8, a first capacitor GC1, and a second capacitor GC2. The gate of the input transistor GT1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, the second electrode of the input transistor GT1 is connected to the input terminal IN, and the first electrode of the input transistor GT1 is connected to the first node N1. For example, when the gate drive unit 141 is a first-stage gate drive unit, the input terminal IN is connected to the start line 152 to receive the start signal. When the gate drive unit 141 is a gate drive unit of other levels other than the first-stage gate drive unit, the input terminal IN is connected to the output terminal GOUT of its upper-level gate drive unit.

[0075] The gate of the first control transistor GT2 is connected to the first node N1, the second electrode of the first control transistor GT2 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, and the first electrode of the first control transistor GT2 is connected to the second node N2.

[0076] The gate of the second control transistor GT3 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, the second electrode of the second control transistor GT3 is connected to the second power line 154 to receive a low-level signal, and the first electrode of the second control transistor GT3 is connected to the second node N2.

[0077] The gate of the output control transistor GT4 is connected to the second node N2, the first electrode of the output control transistor GT4 is connected to the first power line 153 to receive a high-level signal, and the second electrode of the output control transistor GT4 is connected to the output terminal GOUT.

[0078] A first electrode of the first capacitor GC1 is connected to the second node N2 , and a second electrode of the first capacitor GC1 is connected to the first power line 153 .

[0079] The gate of the output transistor GT5 is connected to the third node N3, the first electrode of the output transistor GT5 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB), and the second electrode of the output transistor GT5 is connected to the output terminal GOUT.

[0080] A first electrode of the second capacitor GC2 is connected to the third node N3 , and a second electrode of the second capacitor GC2 is connected to the output terminal GOUT.

[0081] A gate of the first noise reduction transistor GT7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB) to receive the second clock signal, and a first electrode of the first noise reduction transistor GT7 is connected to the first node N1.

[0082] The gate of the second noise reduction transistor GT6 is connected to the second node N2, the first electrode of the second noise reduction transistor GT6 is connected to the first power line 153 to receive a high-level signal, and the second electrode of the second noise reduction transistor GT6 is connected to the second electrode of the first noise reduction transistor GT7.

[0083] The gate of the voltage stabilizing transistor GT8 is connected to the second power supply line 154 to receive a low-level signal, the first electrode of the voltage stabilizing transistor GT8 is connected to the first node N1, and the second electrode of the voltage stabilizing transistor GT8 is connected to the third node N3.

[0084] The transistors in the gate drive unit 141 shown in Figure 4 are all described using P-type transistors as an example, that is, each transistor is turned on (on level) when the gate is connected to a low level, and is turned off (off level) when the gate is connected to a high level. At this time, the first pole of the transistor can be a source, and the second pole of the transistor can be a drain. In other embodiments, the first pole and the second pole of the transistor can be interchangeable. Of course, the embodiments of the present disclosure include but are not limited to this. The various transistors in the gate drive unit 141 can also use N-type transistors or a mixture of P-type transistors and N-type transistors. It is only necessary to simultaneously connect the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiments of the present disclosure.

[0085] It should be noted that the clock signal line 151 includes the above-mentioned first clock signal line GCK and second clock signal line GCB. The transistors used in the gate drive unit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. Here, thin film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0086] The following is an exemplary introduction to a working process of the gate driving unit 141. The working process of the gate driving unit 141 includes four stages, namely a first stage t1, a second stage t2, a third stage t3 and a fourth stage t4.

[0087] During input phase t1, the first clock signal provided at the first clock signal terminal CK is a low-level signal, the second clock signal provided at the second clock signal terminal CB is a high-level signal, and the input terminal IN receives an enable signal from the enable line 152 or a enable signal from the output terminal of the previous-stage gate driver unit; for example, the enable signal is equal to the low-level signal VL provided by the second power line 154. Because the first clock signal is a low-level signal, the input transistor GT1 is turned on, and the input signal Vin at the input terminal IN is transmitted to the first node N1 via the input transistor GT1. Because the input transistor GT1 has a threshold loss when transmitting a low-level signal, the voltage at the first node N1 is Vin-Vth1, i.e., VL-Vth1, where Vth1 represents the threshold voltage of the input transistor GT1. Because the gate of the voltage stabilizing transistor GT8 receives a low-level signal provided by the second power line 154, the voltage stabilizing transistor GT8 is turned on. Consequently, the voltage VL-Vth1 is transmitted to the third node N3 via the voltage stabilizing transistor GT8. For example, the threshold voltage of the voltage stabilizing transistor GT8 is represented as Vth8. Similarly, because the voltage stabilizing transistor GT8 has a threshold loss when transmitting a low-level signal, the voltage at the third node N3 is VL-VthN1, where VthN1 is the smaller of Vth1 and Vth8. The voltage at the third node N3 can control the output transistor GT5 to conduct. The second clock signal is written to the output terminal GOUT via the output transistor GT5 as an output signal (i.e., a gate drive signal). In other words, during the input phase t1, the output signal is the high-level second clock signal, i.e., the high-level signal VH provided by the first power line 153.

[0088] During input phase t1, because the first clock signal is a low-level signal, the second control transistor GT3 is turned on. The low-level signal provided by the second power line 154 is transmitted to the second node N2 via the second control transistor GT3. Since the voltage at the first node N1 is VL-Vth1, the first control transistor GT2 is turned on, and the low-level first clock signal is transmitted to the second node N2 via the first control transistor GT2. For example, the threshold voltage of the first control transistor GT2 is represented by Vth2, and the threshold voltage of the second control transistor GT3 is represented by Vth3. When Vth3 < Vth2 + Vth1, the voltage at the second node N2 is VL-Vth3. At this time, the output control transistor GT4 and the second noise reduction transistor GT6 are both turned on. Because the second clock signal is a high-level signal, the first noise reduction transistor GT7 is turned off.

[0089] During output phase t2, the first clock signal provided at the first clock signal terminal CK is a high-level signal, the second clock signal provided at the second clock signal terminal CB is a low-level signal, and the input terminal IN receives the start signal on the start line 152 or the input signal Vin provided by the output terminal of the previous-stage gate driver unit, which is a high-level signal. The output transistor GT5 is turned on, and the second clock signal is written to the output terminal GOUT via the output transistor GT5 as the output signal. In the input stage t1, the voltage of one end of the second capacitor GC2 connected to the output terminal GOUT is the high-level signal VH provided by the first power line 153, and the voltage of one end of the second capacitor GC2 connected to the third node N3 is VL-VthN1. In the output stage t2, the voltage of one end of the second capacitor GC2 connected to the output terminal GOUT becomes the low-level signal provided by the second power line 154. Due to the bootstrap effect of the second capacitor GC2, the voltage of one end of the second capacitor GC2 connected to the third node N3 becomes 2VL-VthN1-VH, that is, the voltage of the third node N3 becomes 2VL-VthN1-VH. At this time, the voltage regulator transistor GT8 is turned off, the output transistor GT5 can be better opened, and the output signal is the low-level signal provided by the second power line 154.

[0090] During output phase t2, the first clock signal is high, turning off both the input transistor GT1 and the second control transistor GT3. The voltage at the first node N1 remains at VL-VthN1, and the first control transistor GT2 is turned on. The high-level first clock signal is transmitted to the second node N2 via the first control transistor GT2, resulting in a high-level voltage VH at the second node N2. Consequently, the output control transistor GT4 and the second noise reduction transistor GT6 are both turned off. Because the second clock signal is low, the first noise reduction transistor GT7 is turned on.

[0091] During buffering phase t3, the first clock signal provided at the first clock signal terminal CK and the second clock signal provided at the second clock signal terminal CB are both high-level signals. The input terminal IN, which receives the enable signal from the enable line 152 or the input signal Vin provided by the output terminal of the previous-stage gate driver unit, is also high-level. Output transistor GT5 is turned on, and the second clock signal is written to output terminal GOUT via output transistor GT5 as the output signal. At this point, the output signal is the high-level second clock signal, i.e., the high-level signal VH. Due to the bootstrap effect of second capacitor GC2, the voltage at third node N3 reaches VL - VthN1.

[0092] During buffering phase t3, the first clock signal is high, turning off both the input transistor GT1 and the second control transistor GT3. The voltage at the third node N3 reaches VL-VthN1. At this point, the voltage regulator transistor GT8 turns on, and the voltage at the first node N1 also reaches VL-VthN1. The first control transistor GT2 turns on, and the high-level first clock signal is transmitted to the second node N2 via the first control transistor GT2. That is, the voltage at the second node N2 reaches a high-level signal VH. Consequently, the second noise reduction transistor GT6 and the output control transistor GT4 are both turned off. Because the second clock signal is high, the first noise reduction transistor GT7 turns off.

[0093] In the first sub-phase t41 of the stable phase t4, the first clock signal provided at the first clock signal terminal CK is a low-level signal, the second clock signal provided at the second clock signal terminal CB is a high-level signal, and the input signal Vin provided by the output terminal of the previous-stage gate driver unit received at the input terminal IN is a high-level signal. For example, the input signal Vin at the input terminal IN is equal to the high-level signal VH provided by the first power line 153. Because the first clock signal is a low-level signal, the input transistor GT1 is turned on, and the input signal Vin at the input terminal IN is transmitted to the first node N1 via the input transistor GT1. Because the input transistor GT1 transmits a high-level signal without threshold loss, the voltage at the first node N1 is the input signal Vin at the input terminal IN (i.e., the high-level signal VH), and the first control transistor GT2 is turned off. Because the voltage regulator transistor GT8 is turned on, the voltage at the third node N3 is the same as the first node N1. In other words, the voltage at the third node N3 is VH, and the output transistor GT5 is turned off. Since the first clock signal is a low-level signal, the second control transistor GT3 is turned on, the voltage of the second node N2 is VL-Vth1, the second noise reduction transistor GT6 and the output control transistor GT4 are both turned on, and the high-level signal VH is transmitted to the output terminal GOUT via the output control transistor GT4, that is, the output signal is a high-level signal VH.

[0094] In the second sub-phase t42 of the stable phase t4, the first clock signal provided at the first clock signal terminal CK is a high-level signal, the second clock signal provided at the second clock signal terminal CB is a low-level signal, and the input signal Vin provided by the output terminal of the previous-stage gate driver unit received at the input terminal IN is a high-level signal. The voltages at the first node N1 and the third node N3 are the input signal Vin of the input terminal IN (i.e., the high-level signal VH provided by the first power line 153). The first control transistor GT2 and the output transistor GT5 are both turned off. The first clock signal is a high-level signal, so the input transistor GT1 and the second control transistor GT3 are both turned off. Due to the holding effect of the first capacitor GC1, the voltage at the second node N2 remains at VL-Vth3. The output control transistor GT4 and the second noise reduction transistor GT6 are both turned on, and the high-level signal VH is transmitted to the output terminal GOUT via the output control transistor GT4, resulting in the output signal being a high-level signal VH.

[0095] In the second sub-phase t42, since the second clock signal is a low-level signal, the first noise reduction transistor GT7 is turned on, so that the high-level signal VH is transmitted to the third node N3 and the first node N1 via the second noise reduction transistor GT6 and the first noise reduction transistor GT7, so that the voltage of the first node N1 and the voltage of the third node N3 are maintained at a high level.

[0096] In the third sub-phase t43 of the stable phase t4, the first clock signal provided at the first clock signal terminal CK and the second clock signal provided at the second clock signal terminal CB are both high-level signals. The input signal Vin, which is received at the input terminal IN and provided by the output terminal of the previous-stage gate driver unit, is also high-level. The voltages at the first node N1 and the third node N3 are both high-level signals VH, and the first control transistor GT2 and the output transistor GT5 are turned off. The first clock signal is high-level, so both the input transistor GT1 and the second control transistor GT3 are turned off. The voltage at the second node N2 remains at VL-Vth3, and the output control transistor GT4 and the second noise reduction transistor GT6 are both turned on. The high-level signal VH is transmitted to the output terminal GOUT via the output control transistor GT4, and the output signal is a high-level signal VH.

[0097] 5A-5E are layout diagrams of a gate driving unit in a display panel according to an embodiment of the present disclosure.

[0098] FIG5A shows a semiconductor layer 210, which includes an active layer GA1 of the input transistor GT1, an active layer GA2 of the first control transistor GT2, an active layer GA3 of the second control transistor GT3, an active layer GA4 of the output control transistor GT4, an active layer GA5 of the output transistor GT5, an active layer GA7 of the first noise reduction transistor GT7, an active layer GA6 of the second noise reduction transistor GT6, and an active layer GA8 of the voltage regulator transistor GT8. The active layer GA5 of the output transistor GT5 has a large channel width-to-length ratio, thereby reducing leakage current.

[0099] 5B shows a gate layer 220 , which includes a first connection line 221 , a second connection line 222 , a third connection line 223 , a fourth connection line 224 , a fifth connection line 225 , a first electrode block 226 , a second electrode block 227 , a first comb-tooth electrode 228 , and a second comb-tooth electrode 229 .

[0100] For example, as shown in Figure 5B, the first connecting line 221 overlaps with the active layer of the input transistor GT1 and the active layer of the second control transistor GT3 respectively. The part where the first connecting line 221 overlaps with the active layer of the input transistor GT1 can serve as the gate of the input transistor GT1, and the part where the first connecting line 221 overlaps with the active layer of the second control transistor GT3 can serve as the gate of the second control transistor GT3.

[0101] For example, as shown in FIG. 5B , the second connection line 222 overlaps the active layer GA2 of the first control transistor GT2 , and a portion where the second connection line 222 overlaps the active layer GA2 of the first control transistor GT2 may serve as the gate of the first control transistor GT2 .

[0102] For example, as shown in FIG. 5B , the third connection line 223 overlaps the active layer GA8 of the voltage stabilizing transistor GT8 , and the overlapping portion of the third connection line 223 and the active layer GA8 of the voltage stabilizing transistor GT8 may serve as the gate of the voltage stabilizing transistor GT8 .

[0103] For example, as shown in FIG. 5B , the fourth connection line 224 overlaps the active layer GA7 of the first noise reduction transistor GT7 , and the portion where the fourth connection line 224 overlaps the active layer GA7 of the first noise reduction transistor GT7 may serve as the gate of the first noise reduction transistor GT7 .

[0104] For example, as shown in FIG. 5B , the fifth connection line 225 overlaps the active layer GA6 of the second noise reduction transistor GT6 , and the portion where the fifth connection line 225 overlaps the active layer GA6 of the second noise reduction transistor GT6 may serve as the gate of the second noise reduction transistor GT6 .

[0105] For example, as shown in FIG5B , the first comb-teeth electrode 228 overlaps the active layer GA5 of the output transistor GT5 to serve as the gate of the output transistor GT5 , and the second comb-teeth electrode 229 overlaps the active layer GA4 of the control transistor GT4 to serve as the gate of the control transistor GT4 .

[0106] For example, as shown in FIG5B , the first electrode block 226 is connected to the active layer GA8 of the voltage stabilizing transistor GT8 and the gate of the output transistor GT5 to serve as the lower electrode plate of the second capacitor GC2 .

[0107] For example, as shown in FIG5B , the second electrode block 227 is connected to the gate of the output control transistor GT4 to serve as the lower electrode plate of the first capacitor GC1 .

[0108] Figure 5C shows a conductive layer 230, which includes a third electrode block 231 and a fourth electrode block 232. The third electrode block 231 overlaps with the first electrode block 226 to serve as the upper electrode plate of the second capacitor GC2, and the fourth electrode block 232 overlaps with the second electrode block 226 to serve as the upper electrode plate of the first capacitor GC1.

[0109] Figure 5C shows a conductive layer 230, which includes a third electrode block 231 and a fourth electrode block 232. The third electrode block 231 overlaps with the first electrode block 226 to serve as the upper electrode plate of the second capacitor GC2, and the fourth electrode block 232 overlaps with the second electrode block 226 to serve as the upper electrode plate of the first capacitor GC1.

[0110] FIG5D shows a plurality of via holes V used for connection between different layers of the gate driving unit, which will not be described in detail here.

[0111] 5E shows a first clock signal line GCK, a second clock signal line GCB, an enable line 152, a first power line 153 and a second power line 154; a first connection line 221 is connected to the first clock signal line GCK, and a fourth connection line 224 is connected to the second clock signal line GCB.

[0112] For example, as shown in Figure 5E, the output control transistor GT4, the output transistor GT5 and the voltage regulating transistor GT8 are located on one side of the second power line 154, and the input transistor GT1, the first control transistor GT2, the second control transistor GT3, the first noise reduction transistor GT7 and the second noise reduction transistor GT6 are located on the other side of the second power line 154.

[0113] For example, as shown in FIG. 5E , the second capacitor GC2 is located on one side of the second power line 154 , and the first capacitor GC1 is located on the other side of the second power line 154 .

[0114] It is worth noting that, unlike FIG. 4 and FIG. 5A to FIG. 5E , in order to more clearly illustrate the positions of the various transistors and capacitors, the reference numerals “G” of other transistors and capacitors in the gate driving unit 141 in FIG. 2 are omitted.

[0115] Figure 6 is an equivalent schematic diagram of an emission control unit in a display panel provided in one embodiment of the present disclosure. As shown in Figure 6, the emission control unit 142 includes: a first transistor ET1 (also known as an input transistor), a second transistor ET2, a third transistor ET3, a fourth transistor ET4, a fifth transistor ET5, a sixth transistor ET6, a seventh transistor ET7, an eighth transistor ET8, a ninth transistor ET9, a tenth transistor ET10 (also known as an output transistor), a first capacitor EC1, a second capacitor EC2, and a third capacitor EC3. The emission control unit adopts a 10T3C structure, and the embodiments of the present disclosure include but are not limited to this structure.

[0116] It should be noted that the above-mentioned light-emitting control unit is a light-emitting control shift register. When multiple light-emitting control shift registers are cascaded, the second electrode of the first transistor ET1 in the first-stage light-emitting control shift register can be connected to the input end, which is configured to be connected to the start line 152 to receive a trigger signal as an input signal, while the second electrodes of the first transistor ET1 in the light-emitting control shift register units at other stages are electrically connected to the output end of the previous stage light-emitting control shift register unit to receive the output signal output from the output end OUT of the previous stage light-emitting control shift register unit as an input signal, thereby realizing shifted output to provide, for example, row-by-row shifted light-emitting control signals to the pixels arranged in an array in the display area of ​​the display substrate.

[0117] As shown in FIG6 , the gate of the first transistor ET1 is connected to the first clock signal line GCK to receive the first clock signal, the first electrode of the first transistor ET1 is connected to the first node N1, and the second electrode of the first transistor ET1 is connected to the input terminal. For example, when the light-emitting control unit is a first-stage light-emitting control unit, the input terminal is connected to the enable line 152 to receive a trigger signal. When the light-emitting control unit is a light-emitting control unit of any other stage other than the first-stage light-emitting control unit, the input terminal is connected to the output terminal OUT of the light-emitting control unit of the previous stage.

[0118] As shown in FIG6 , the second transistor ET2 has its gate connected to the first node N1 , its first electrode connected to the second node N2 , and its second electrode connected to the first clock signal line GCK to receive the first clock signal.

[0119] As shown in Figure 6, the gate of the third transistor ET3 is connected to the first clock signal line GCK to receive the first clock signal, the first electrode of the third transistor ET3 is connected to the second node N2, and the second electrode of the third transistor ET3 is connected to the first power line 153 to receive a high level voltage.

[0120] As shown in FIG6 , a gate of the fourth transistor ET4 is connected to the second clock signal line GCB to receive the second clock signal, a first electrode of the fourth transistor ET4 is connected to the first node N1 , and a second electrode of the fourth transistor ET4 is connected to the second electrode of the fifth transistor ET5 .

[0121] As shown in FIG. 6 , a gate electrode of the fifth transistor ET5 is connected to the second node N2 , and a first electrode of the fifth transistor ET5 is connected to the second power line 154 to receive a low-level signal.

[0122] As shown in FIG6 , a first electrode of the sixth transistor ET6 is connected to the second clock signal line GCB to receive the second clock signal, and a second electrode of the sixth transistor ET6 is connected to the third node N3 .

[0123] As shown in FIG6 , a gate of the seventh transistor ET7 is connected to the second clock signal line GCB to receive the second clock signal, a first electrode of the seventh transistor ET7 is connected to the third node N3 , and a second electrode of the seventh transistor ET7 is connected to the fourth node N4 .

[0124] As shown in FIG6 , a gate of the eighth transistor ET8 is connected to the first node N1 , a first electrode of the eighth transistor ET8 is connected to the fourth node N4 , and a second electrode of the eighth transistor ET8 is connected to the second power line 154 to receive a low-level signal.

[0125] As shown in FIG6 , a gate of the ninth transistor ET9 is connected to the fourth node N4 , a first electrode of the ninth transistor ET9 is connected to the second power line 154 to receive a low-level signal, and a second electrode of the ninth transistor ET9 is connected to the output terminal.

[0126] As shown in FIG. 6 , a first electrode of the tenth transistor ET10 is connected to the first power line 153 to receive a high-level voltage, and a second electrode of the tenth transistor ET10 is connected to the output terminal.

[0127] As shown in Figure 6, the second electrode of the first capacitor EC1 is connected to the third node N3; the second electrode of the second capacitor EC2 is connected to the second clock signal line GCB to receive the second clock signal; the first electrode of the third capacitor EC3 is connected to the fourth node N4, and the second electrode of the third capacitor EC3 is connected to the second power line 154 to receive a low-level signal.

[0128] It should be noted that the transistors in the light-emitting control unit shown in Figure 6 are all described using p-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (on-level), and is turned off when the gate is connected to a high level (off-level). At this time, the first pole of the transistor can be a source, and the second pole of the transistor can be a drain. Of course, the embodiments of the present disclosure include but are not limited to this. Each transistor can also use an n-type transistor or a mixture of p-type transistors and n-type transistors. It is only necessary to simultaneously connect the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiment of the present disclosure. In addition, the working principle of the light-emitting control unit can refer to the relevant introduction in this field and will not be repeated here.

[0129] It should be noted that the transistors used in the light-emitting control unit can all be thin-film transistors or field-effect transistors or other switching devices with the same characteristics. Here, thin-film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiments of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0130] 7A to 7E are layout diagrams of a light emitting control unit in a display panel according to an embodiment of the present disclosure.

[0131] 7A shows a semiconductor layer 210, which includes an active layer EA1 of a first transistor ET1, an active layer EA2 of a second transistor ET2, an active layer EA3 of a third transistor ET3, an active layer EA4 of a fourth transistor ET4, an active layer EA5 of a fifth transistor ET5, an active layer EA6 of a sixth transistor ET6, an active layer EA7 of a seventh transistor ET7, an active layer EA9 of an eighth transistor ET8, an active layer EA9 of a ninth transistor ET9, and an active layer EA10 of a tenth transistor ET10. The active layer EA10 of the tenth transistor ET10 has a large channel width-to-length ratio, thereby reducing leakage current.

[0132] Figure 7B shows the gate layer 220, which includes a sixth connecting line 221E, a seventh connecting line 222E, an eighth connecting line 223E, a ninth connecting line 224E, a tenth connecting line 225E, an eleventh connecting line 226E, a twelfth connecting line 227E, a thirteenth connecting line 228E, a third comb-tooth electrode 229E, a fourth comb-tooth electrode 2210, a fifth electrode block 2211, a sixth electrode block 2212 and a seventh electrode block 2213.

[0133] For example, as shown in FIG. 7B , the sixth connection line 221E overlaps the active layer of the first transistor ET1 , and the portion where the sixth connection line 221E overlaps the active layer of the first transistor ET1 may serve as the gate of the first transistor ET1 .

[0134] For example, as shown in FIG. 7B , the seventh connection line 222E overlaps the active layer of the second transistor ET2 , and a portion where the seventh connection line 222E overlaps the active layer of the second transistor ET2 may serve as the gate of the second transistor ET2 .

[0135] For example, as shown in FIG. 7B , the eighth connection line 223E overlaps the active layer of the third transistor ET3 , and the overlapping portion of the eighth connection line 223E and the active layer of the third transistor ET3 may serve as the gate of the voltage stabilizing transistor GT8 .

[0136] For example, as shown in FIG. 7B , the ninth connection line 224E overlaps the active layer of the fourth transistor ET4 , and a portion where the ninth connection line 224E overlaps the active layer of the fourth transistor ET4 may serve as the gate of the fourth transistor ET4 .

[0137] For example, as shown in FIG. 7B , the tenth connection line 225E overlaps the active layer of the fifth transistor ET4 , and a portion where the tenth connection line 225E overlaps the active layer of the fifth transistor ET4 may serve as the gate of the fifth transistor ET4 .

[0138] For example, as shown in FIG. 7B , the eleventh connection line 226E overlaps the active layer of the sixth transistor ET6 , and the portion where the eleventh connection line 226E overlaps the active layer of the sixth transistor ET6 may serve as the gate of the sixth transistor ET6 .

[0139] For example, as shown in FIG. 7B , the twelfth connection line 227E overlaps the active layer of the seventh transistor ET7 , and a portion where the twelfth connection line 227E overlaps the active layer of the seventh transistor ET7 may serve as the gate of the seventh transistor ET7 .

[0140] For example, as shown in FIG. 7B , the thirteenth connection line 228E overlaps the active layer of the eighth transistor ET8 , and a portion where the thirteenth connection line 228E overlaps the active layer of the eighth transistor ET8 may serve as the gate of the eighth transistor ET8 .

[0141] For example, as shown in FIG. 7B , the third comb-teeth electrode 229E overlaps the active layer of the ninth transistor ET9 to serve as the gate of the ninth transistor ET9 , and the fourth comb-teeth electrode 2210 overlaps the active layer of the tenth transistor ET10 to serve as the gate of the tenth transistor ET10 .

[0142] For example, as shown in FIG7B , the fifth electrode block 2211 may serve as the lower electrode plate of the first capacitor EC1 , the sixth electrode block 2212 may serve as the lower electrode plate of the second capacitor EC2 , and the seventh electrode block 2213 may serve as the lower electrode plate of the third capacitor EC3 .

[0143] FIG7C shows a conductive layer 230 , which includes an upper electrode plate 233 of the first capacitor EC1 , an upper electrode plate 234 of the second capacitor EC2 , and an upper electrode plate 235 of the third capacitor EC3 .

[0144] FIG7D shows a plurality of via holes V used for connection between different layers of the gate driving unit, which will not be described in detail here.

[0145] 7E shows a first clock signal line GCK, a second clock signal line GCB, a start line 152, a first power line 153 and a second power line 154; a sixth connection line 221E is connected to the first clock signal line GCK, and a ninth connection line 224E and a twelfth connection line 227E are connected to the second clock signal line GCB.

[0146] For example, as shown in Figure 7E, the fourth transistor ET4, the ninth transistor ET9 and the tenth transistor ET10 are located on one side of the second power line 154, and the first transistor ET1, the second transistor ET2, the third transistor ET3, the fifth transistor ET5, the sixth transistor ET6, the seventh transistor ET7 and the eighth transistor ET8 are located on the other side of the second power line 154.

[0147] It is worth noting that, unlike FIG. 6 and FIG. 7A to FIG. 7E , in order to more clearly illustrate the positions of the various transistors and capacitors, the reference numerals “E” of the other transistors and capacitors in the light emitting control unit 142 in FIG. 2 are omitted.

[0148] Figure 8 is a schematic cross-sectional view of an edge sub-pixel in a display panel according to an embodiment of the present disclosure. As shown in Figure 8, each edge sub-pixel 125 further includes an edge organic light-emitting layer 1253 and a cathode 1254. The edge organic light-emitting layer 1253 is located on the side of the anode 1252 away from the base substrate 110, while the cathode 1254 is located on the side of the edge organic light-emitting layer 1253 away from the base substrate 110. In other words, the edge sub-pixels include organic light-emitting diodes, resulting in advantages such as high contrast, wide viewing angles, fast response speed, and a thin and lightweight design.

[0149] In some examples, each middle sub-pixel further includes a middle organic light-emitting layer and a cathode; the middle organic light-emitting layer is located on the side of the anode away from the base substrate; and the cathode is located on the side of the edge organic light-emitting layer away from the base substrate. The detailed structure of the middle sub-pixel can be seen in the edge sub-pixel in FIG8 .

[0150] In some examples, as shown in FIG8 , the anode 1252 can be connected to the output terminal of the corresponding edge pixel driving circuit 1251 through a via hole, so that the current output by the edge pixel driving circuit 1251 can be used to drive the edge organic light-emitting layer 1253 to emit light. It should be noted that the above-mentioned driving circuit 1251 can be the drain of the light-emitting control transistor.

[0151] In some examples, as shown in FIG. 8 , one of the anode 1252 and the cathode 1254 may include a reflective layer, and the other may include a semi-transmissive and semi-reflective layer, thereby improving light extraction efficiency.

[0152] In some examples, the edge pixel driving circuit 1251 may include multiple transistors and at least one storage capacitor. For example, the edge pixel driving circuit may adopt a 7T1C, 9T1C, 3T1C, etc. structure. It should be noted that the above "T" represents a transistor and "C" represents a capacitor.

[0153] In some examples, each edge sub-pixel may further include functional layers such as an electron injection layer, an electron transport layer, and a hole blocking layer located between the cathode and the edge organic light-emitting layer, and functional layers such as a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the edge organic light-emitting layer. Similarly, each middle sub-pixel may further include functional layers such as an electron injection layer, an electron transport layer, and a hole blocking layer located between the cathode and the middle organic light-emitting layer, and functional layers such as a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the middle organic light-emitting layer.

[0154] In some examples, the base substrate may be a rigid substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a flexible substrate such as a polyimide substrate.

[0155] FIG9 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. As shown in FIG9 , the display panel 100 includes a base substrate 110, an edge pixel group 120, and a row driver circuit 140. The base substrate 110 includes a display area 112 and a peripheral area 114. The edge pixel group 120 includes a plurality of edge sub-pixels 125. The display area 112 includes a central display area 112A and an edge display area 112B located near the peripheral area 114 within the central display area 112A. Each edge sub-pixel 125 includes an edge pixel driver circuit 1251 and an anode 1252 connected to the edge pixel driver circuit 1251. The edge pixel driver circuit 1251 can provide a driving current to the anode 1252 to drive the light-emitting layer on the anode 1252 to emit light for display.

[0156] As shown in FIG9 , the edge pixel group 120 is located in the edge display area 112B, and the row driving circuit 140 is at least partially located in the edge display area 112B and overlaps with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120; that is, the orthographic projection of the row driving circuit 140 on the base substrate 110 overlaps with the orthographic projection of the anode 1252 of at least one edge sub-pixel 124 in the edge pixel group 120 on the base substrate 110.

[0157] In conventional display panels, the row driver circuitry can be integrated into the peripheral area using Gate Driver on Array (GOA) technology. This allows the row driver circuitry to directly provide row driver signals, such as gate drive signals and light-emitting control signals, to the sub-pixel array, eliminating the need for additional gate driver chips and corresponding binding structures. This reduces costs and reduces bezel width. However, in this case, the row driver circuitry itself still occupies a certain width, making it impossible to achieve an extremely narrow bezel.

[0158] In the display panel provided by the embodiment of the present disclosure, by setting the row driving circuit at least partially in the edge display area and overlapping with the anode of at least one edge sub-pixel in the edge pixel group, the display panel can set the row driving circuit at least partially below the display area without placing the entire row driving circuit in the peripheral area, thereby reducing the width of the peripheral area.

[0159] In some examples, as shown in FIG9 , the row driver circuit 140 includes a plurality of gate driver units 141 and a plurality of light emission control units 142. The gate driver unit 141 can provide gate drive signals to the edge pixel driver circuit and the intermediate pixel driver circuit, and the light emission control unit 142 can provide light emission control signals to the edge pixel driver circuit and the intermediate pixel driver circuit. The plurality of edge pixel driver circuits 1251 of the plurality of edge sub-pixels 125 in the edge pixel group 120 are arranged along a first direction, and the plurality of gate driver units 141 and the plurality of light emission control units 142 are arranged along a second direction that intersects the first direction.

[0160] For example, the second direction may be perpendicular to the first direction, but the embodiments of the present disclosure include but are not limited to this.

[0161] Similarly, the display panel 100 also includes a clock signal line, a start line, a first power line and a second power line, which are configured to drive the row drive circuit; multiple gate drive units and multiple light-emitting control units share at least one of the clock signal line, the start line, the first power line and the second power line.

[0162] In a typical display panel, the row driver circuit needs to provide gate drive signals and emission drive signals to the pixel driver circuit in the display area. The gate driver unit that provides the gate drive signal and the light control unit that provides the light control signal are arranged side by side, that is, arranged along a first direction, and therefore have a larger size in the first direction. In the display panel provided by the embodiments of the present disclosure, by arranging multiple gate driver units and multiple light control units along a second direction, the display panel can reduce the size of the row driver circuit in the first direction, thereby enabling the entire row driver circuit to be arranged in the edge display area. Furthermore, by sharing at least one of the clock signal line, the enable line, the first power line, and the second power line among the multiple gate driver units and the multiple light control units, the display device can further reduce the width occupied by the row driver circuit and various drive lines, thereby further reducing the width of the peripheral area. Thus, through the above-mentioned multiple designs, the display panel has an extremely narrow bezel. Furthermore, when the display panel provided by the embodiments of the present disclosure is used for a spliced ​​display, the spliced ​​display device can achieve seamless splicing and have an excellent display effect.

[0163] In some examples, as shown in Figure 9, the row driving circuit 140 also includes a virtual driving unit 143, which is not connected to the clock signal line 151, the start line 152 and the first power line 153, and thus does not provide a row driving signal; the virtual driving unit 143 is arranged along the second direction with multiple gate driving units 141 and multiple light-emitting control units 142.

[0164] In some examples, as shown in FIG. 9 , the virtual driving unit 143 is inserted between the light emitting control units 142 corresponding to a row of edge sub-pixels 120 and the gate driving unit 141 corresponding to the next row of edge sub-pixels 120 .

[0165] In some examples, as shown in FIG9 , the entire row driver circuit 140 is located in the edge display area 112B, and the orthographic projection of the edge of the row driver circuit 140 away from the middle display area 112A on the base substrate 110 overlaps with the orthographic projection of the anode 1252 of the outermost edge sub-pixel 125 in the edge pixel group 120 on the base substrate 110. Thus, the width of the peripheral area of ​​the display panel can be minimized.

[0166] In some examples, as shown in FIG9 , the display panel 100 further includes an intermediate pixel group 130 including a plurality of intermediate sub-pixels 135. The intermediate pixel group 130 is located in the intermediate display area 112A, and each intermediate sub-pixel 135 includes an intermediate pixel driving circuit 1351 and an anode 1352 connected to the intermediate pixel driving circuit 1351. The area occupied by the plurality of intermediate pixel driving circuits 1351 and the spacing between the plurality of intermediate pixel driving circuits 1351 in the plurality of intermediate sub-pixels 135 in the intermediate pixel group 130 is greater than the area occupied by the plurality of edge pixel driving circuits 1251 and the spacing between the plurality of edge pixel driving circuits 1251 in the plurality of edge sub-pixels 125 in the edge pixel group 120. Thus, the display panel can reduce the border width by reducing the area occupied by the spacing between the edge pixel driving circuits, thereby allowing the row driving circuit 140 to overlap with the anode 1252 of at least one edge sub-pixel 125 in the edge pixel group 120.

[0167] It should be noted that the middle sub-pixels and edge sub-pixels here only differ in position and some structures; they are all sub-pixels used to display the same image; in some examples, the type, color, and size of light emitted by the middle sub-pixels and edge sub-pixels are the same.

[0168] Figure 10 is a schematic diagram of a row drive circuit in a display panel according to an embodiment of the present disclosure. As shown in Figure 10 , the output terminals of two adjacent gate drive units 141 in the second direction are connected to provide gate drive signals to edge sub-pixels in the same row within the same edge pixel group, thereby reducing fluctuations in the gate drive signals and stabilizing the input of data voltages.

[0169] Figure 11 is a schematic diagram of the signal line connections in a row driver circuit of a display panel provided by one embodiment of the present disclosure. As shown in Figure 11, multiple gate driver units 141 and multiple light-emitting control units 142 share at least one of the clock signal line 151, enable line 152, first power line 153, and second power line 154. This reduces the number of clock signal lines, enable lines, first power lines, and second power lines in the display panel, further reducing the bezel width.

[0170] In some examples, as shown in FIG11 , multiple gate drive units 141 and multiple light-emitting control units 142 share a clock signal line 151, an enable line 152, a first power line 153, and a second power line 154, thereby minimizing the number of signal lines. Of course, embodiments of the present disclosure include but are not limited to this, and multiple gate drive units 141 and multiple light-emitting control units 142 may share only a portion of the clock signal line 151, the enable line 152, the first power line 153, and the second power line 154.

[0171] FIG12 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. As shown in FIG12 , the display panel 100 includes a base substrate 110, an edge pixel group 120, and a row driver circuit 140. The base substrate 110 includes a display area 112 and a peripheral area 114. The edge pixel group 120 includes a plurality of edge sub-pixels 125. The display area 112 includes a central display area 112A and two edge display areas 112B located on either side of the central display area 112A. Each edge sub-pixel 125 includes an edge pixel driver circuit 1251 and an anode 1252 connected to the edge pixel driver circuit 1251. The edge pixel driver circuit 1251 can provide a driving current to the anode 1252 to drive the light-emitting layer on the anode 1252 to emit light for display.

[0172] As shown in FIG12 , edge sub-pixel groups 120 are respectively provided in two edge display regions 112B, and row driver circuits 140 are located in each of the two edge display regions 112B, thereby driving the sub-pixels in the display panel from both sides. Row driver circuit 140 overlaps with the anode 1252 of at least one edge sub-pixel 125 in an edge pixel group 120; that is, the orthographic projection of row driver circuit 140 on base substrate 110 overlaps with the orthographic projection of anode 1252 of at least one edge sub-pixel 124 in an edge pixel group 120 on base substrate 110.

[0173] In the display panel provided by the embodiments of the present disclosure, by disposing the row driver circuit at least partially in the edge display area and overlapping with the anode of at least one edge sub-pixel in the edge pixel group, the display panel can dispose the row driver circuit at least partially below the display area, rather than placing the entire row driver circuit in the peripheral area. This reduces the width of the peripheral area, thereby reducing the width of the display panel's border and achieving an extremely narrow border. Furthermore, when the display panel provided by the embodiments of the present disclosure is used for a spliced ​​display, the spliced ​​display device can achieve seamless splicing and excellent display effects.

[0174] It should be noted that the two row driving circuits 140 can drive the same row of sub-pixels simultaneously, or one of them can drive the odd-numbered rows of sub-pixels and the other can drive the even-numbered rows of sub-pixels.

[0175] In some examples, as shown in FIG12 , the row driver circuit 140 includes a plurality of gate driver units 141 and a plurality of light-emitting control units 142. The gate driver units 141 can provide gate driver signals to the edge pixel driver circuit and the middle pixel driver circuit, and the light-emitting control units 142 can provide light-emitting control signals to the edge pixel driver circuit and the middle pixel driver circuit. The plurality of gate driver units 141 and the plurality of light-emitting control units 142 are arranged along a second direction that intersects the first direction.

[0176] Similarly, the display panel 100 also includes a clock signal line, a start line, a first power line, and a second power line, which are configured to drive a row drive circuit; multiple gate drive units and multiple light-emitting control units share at least one of the clock signal line, the start line, the first power line, and the second power line. As a result, the display panel can reduce the size of the row drive circuit in the first direction, so that all the row drive circuits can be set in the edge display area. Moreover, by having multiple gate drive units and multiple light-emitting control units share at least one of the clock signal line, the start line, the first power line, and the second power line, the display device can further reduce the width occupied by the row drive circuit and various drive lines, thereby further reducing the width of the peripheral area. In this way, through the above-mentioned multiple designs, the display panel has an extremely narrow border. Furthermore, when the display panel provided by the embodiment of the present disclosure is used for splicing display, the spliced ​​display device can achieve seamless splicing and have an excellent display effect.

[0177] At least one embodiment of the present disclosure also provides a display device. Figure 13 is a schematic diagram of a display device provided by one embodiment of the present disclosure. As shown in Figure 13, the display device 500 includes a display panel 100. Thus, the display device can combine multiple display panels into a large-scale, high-resolution display device through splicing. Furthermore, because the display panels have extremely narrow bezels, the display device can achieve seamless splicing, thereby providing excellent display effects.

[0178] In some examples, as shown in FIG. 13 , the display device 500 includes a plurality of display panels 100 that are spliced ​​together.

[0179] There are a few points to note:

[0180] (1) The drawings of the embodiments of the present application only involve structures related to the embodiments of the present application, and other structures can refer to the general design.

[0181] (2) Unless there is a conflict, the features in the same embodiment and different embodiments of the present application may be combined with each other.

[0182] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display device comprising a plurality of mutually spliced display panels, wherein: Each of the display panels comprises: A base substrate, comprising a display area and a peripheral area; an edge pixel group, comprising a plurality of edge sub-pixels; and The row driving circuit includes a plurality of gate driving units and a plurality of light emitting control units. The display area includes a middle display area and an edge display area located on a side of the middle display area close to the peripheral area, and each edge sub-pixel includes an edge pixel driving circuit and an anode connected to the edge pixel driving circuit; The edge pixel group is located in the edge display area, the row driving circuit is at least partially located in the edge display area, and overlaps with the anode of at least one edge sub-pixel in the edge pixel group. The edge pixel driving circuits of the edge sub-pixels in the edge pixel group are arranged along a first direction, the gate driving units and the light emitting control units are arranged along a second direction, and the second direction intersects the first direction. The display panel also includes a clock signal line, a start line, a first power line and a second power line, which are configured to drive the row drive circuit, and the multiple gate drive units and the multiple light-emitting control units share at least one of the clock signal line, the start line, the first power line and the second power line.

2. The display device according to claim 1, wherein Each of the gate driving units includes an output transistor and an input transistor, and the light emitting control unit includes an output transistor and an input transistor. The second power line extends along the second direction and passes through the plurality of gate driving units and the plurality of light emitting control units. The plurality of gate driving units and the plurality of light emitting control units share the second power line. The output transistor of the gate driving unit and the output transistor of the light emitting control unit are located on a first side of the second power line in the first direction, and the input transistor of the gate driving unit and the input transistor of the light emitting control unit are located on a second side of the second power line in the first direction.

3. The display device according to claim 2, wherein: The clock signal line, the start line, and the first power line are located on a side of the input transistor of the gate driving unit and the input transistor of the light emitting control unit away from the second power line.

4. The display device according to claim 2, wherein The second power line is located in the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group.

5. The display device according to claim 2, wherein The clock signal line, the start line, and the first power line are located within the edge display area and overlap with the anode of at least one edge sub-pixel in the edge pixel group.

6. The display device according to any one of claims 1 to 5, wherein: The output ends of two adjacent gate driving units in the second direction are connected to provide gate driving signals to the edge sub-pixels located in the same row in the same edge pixel group.

7. The display device according to claim 6, wherein: Two gate driving units are arranged between two adjacent light emitting control units.

8. The display device according to any one of claims 1 to 5, wherein: The row driving circuit further includes a dummy driving unit, which is not connected to the clock signal line, the start line, and the first power line. The dummy driving unit, the plurality of gate driving units, and the plurality of light emitting control units are arranged along a second direction.

9. The display device according to claim 8, wherein The virtual driving unit is inserted between the light emitting control units corresponding to a row of edge sub-pixels and the gate driving unit corresponding to a next row of edge sub-pixels.

10. The display device according to any one of claims 1 to 9, wherein: The peripheral area, the edge display area and the middle display area are arranged along a first direction; in the edge pixel group, the size of the multiple edge pixel driving circuits of the multiple edge sub-pixels in the first direction is smaller than the size of the multiple anodes of the multiple edge sub-pixels in the first direction.

11. The display device according to any one of claims 1 to 9, wherein: The row driving circuit is entirely located in the edge display area, and the orthographic projection of the edge of the row driving circuit away from the middle display area on the base substrate overlaps with the orthographic projection of the anode of the outermost edge sub-pixel in the edge pixel group on the base substrate.

12. The display device according to any one of claims 1 to 9, further comprising: An intermediate pixel group, comprising a plurality of intermediate sub-pixels, The intermediate pixel group is located in the intermediate display area, and each intermediate sub-pixel includes an intermediate pixel driving circuit and an anode connected to the intermediate pixel driving circuit; The plurality of intermediate pixel driving circuits of the plurality of intermediate sub-pixels in the intermediate pixel group and An area occupied by intervals between the plurality of middle pixel driving circuits is larger than an area occupied by the plurality of edge pixel driving circuits of the plurality of edge sub-pixels in the edge pixel group and an area occupied by intervals between the plurality of edge pixel driving circuits.

13. The display device according to claim 12, wherein: An area occupied by intervals between the middle pixel driving circuits of the middle sub-pixels in the middle pixel group is larger than an area occupied by intervals between the edge pixel driving circuits of the edge sub-pixels in the edge pixel group.

14. The display device according to claim 12, wherein: The edge pixel group includes a first edge sub-pixel, a second edge sub-pixel, and a third edge sub-pixel, and the middle pixel group includes a first middle sub-pixel, a second middle sub-pixel, and a third middle sub-pixel. The first edge sub-pixel and the first middle sub-pixel are configured to emit light of a first color, the second edge sub-pixel and the second middle sub-pixel are configured to emit light of a second color, and the third edge sub-pixel and the third middle sub-pixel are configured to emit light of a third color.

15. The display device according to claim 14, wherein The anode of the first edge sub-pixel has the same size as the anode of the first middle sub-pixel, the anode of the second edge sub-pixel has the same size as the anode of the second middle sub-pixel, and the anode of the third edge sub-pixel has the same size as the anode of the third middle sub-pixel.

16. The display device according to any one of claims 1 to 15, wherein: The row driving circuit is located on a side of the edge pixel group where the plurality of edge pixel driving circuits are away from the middle display area.

17. The display device according to any one of claims 1 to 16, wherein: Each of the edge sub-pixels further includes: an edge organic light-emitting layer, located on a side of the anode away from the base substrate; and The cathode is located on a side of the edge organic light-emitting layer away from the base substrate.

18. A display panel comprising: A base substrate, comprising a display area and a peripheral area; an edge pixel group, comprising a plurality of edge sub-pixels; as well as The row driving circuit includes a plurality of gate driving units and a plurality of light emitting control units. The display area includes a middle display area and an edge display area located on a side of the middle display area close to the peripheral area, and each edge sub-pixel includes an edge pixel driving circuit and an anode connected to the edge pixel driving circuit; The edge pixel group is located in the edge display area, the row driving circuit is at least partially located in the edge display area, and overlaps with the anode of at least one edge sub-pixel in the edge pixel group. The edge pixel driving circuits of the edge sub-pixels in the edge pixel group are arranged along a first direction, the gate driving units and the light emitting control units are arranged along a second direction, and the second direction is perpendicular to the first direction. The display panel also includes a clock signal line, a start line, a first power line and a second power line, which are configured to drive the row drive circuit, and the multiple gate drive units and the multiple light-emitting control units share at least one of the clock signal line, the start line, the first power line and the second power line.

19. The display panel according to claim 18, wherein: Each of the gate driving units includes an output transistor and an input transistor, and the light emitting control unit includes an output transistor and an input transistor. The second power line extends along the second direction and passes through the plurality of gate driving units and the plurality of light emitting control units. The plurality of gate driving units and the plurality of light emitting control units share the second power line. The output transistor of the gate driving unit and the output transistor of the light emitting control unit are located on a first side of the second power line in the first direction, and the input transistor of the gate driving unit and the input transistor of the light emitting control unit are located on a second side of the second power line in the first direction.

20. The display panel according to claim 19, wherein The clock signal line, the start line, and the first power line are located on a side of the input transistor of the gate driving unit and the input transistor of the light emitting control unit away from the second power line.

21. The display panel according to claim 19, wherein The second power line is located in the edge display area and overlaps with the anode of at least one edge sub-pixel in the edge pixel group.

22. The display panel according to claim 19, wherein: The clock signal line, the start line, and the first power line are located within the edge display area and overlap with the anode of at least one edge sub-pixel in the edge pixel group.

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