Display panel and manufacturing method therefor, and display apparatus

Abstract

A display panel and a manufacturing method therefor, and a display apparatus. The display panel has a pixel region comprising a plurality of sub-pixel regions and a pixel spacing region located between adjacent sub-pixel regions, and comprises: a plurality of sub-pixels provided on a base substrate, each sub-pixel comprising a light-emitting device and a sub-pixel circuit configured to drive the light-emitting device to emit light, and each light-emitting device comprising a first electrode, a charge generation layer and a second electrode which are sequentially stacked; a pixel defining structure provided on the base substrate and having a plurality of sub-pixel openings to define light-emitting regions of the plurality of sub-pixels; and an isolation structure located in at least one of the pixel region and the pixel spacing region and comprising a portion having a first isolation height and a portion having a second isolation height, the second isolation height being greater than the first isolation height, and the charge generation layers of adjacent sub-pixels being disconnected from each other by at least one of the portion having the first isolation height and the portion having the second isolation height in the isolation structure.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display panel, a method for manufacturing the same, and a display device. Background Art

[0002] Compared with traditional liquid crystal display (LCD) panels, organic light-emitting diode (OLED) display panels have the advantages of self-luminescence, wide color gamut, high contrast, and light weight, making them widely used in fields such as mobile phones and tablets. They are also widely used in flexible wearables such as smart watches. Compared with traditional OLED devices, the luminous efficiency and lifespan of tandem OLED devices have been significantly improved, and they have great application prospects in multiple display fields such as automotive and laptop computers. Tandem OLED devices have high-mobility film layers such as charge generation layers. In OLED display panels, organic insulating materials are usually used to form pixel definition layers (PDLs) to define the light-emitting area and separate sub-pixels of different colors. However, traditional pixel definition layers may not be able to effectively separate different sub-pixels, and thus cannot effectively solve the problem of cross-color. On the other hand, traditional pixel definition layers may cause the cathodes of the light-emitting devices of multiple sub-pixels to be disconnected, which in turn leads to uneven brightness of the display panel and high power consumption, which cannot meet the higher requirements of products.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display panel having a pixel region including a plurality of sub-pixel regions and a pixel spacing region located between adjacent sub-pixel regions, and comprising: a base substrate; a plurality of sub-pixels, arranged on the base substrate and respectively located in the plurality of sub-pixel regions, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, each light-emitting device includes a first electrode, a charge generation layer, and a second electrode stacked in sequence, and the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel adjacent to each other and used to display different colors; a pixel defining structure, arranged on the base substrate and having a plurality of sub-pixel openings to define the light-emitting regions of the plurality of sub-pixels, wherein at least a portion of each light-emitting device is located in a corresponding sub-pixel opening; and an isolation structure, located in at least one of the pixel region and the pixel spacing region, and including a portion having a first isolation height and a portion having a second isolation height, the second isolation height being greater than the first isolation height, wherein the charge generation layers of adjacent sub-pixels in the plurality of sub-pixels are disconnected from each other by at least one of the portion having the first isolation height and the portion having the second isolation height in the isolation structure.

[0005] In the display panel provided according to at least one embodiment of the present disclosure, the light-emitting devices of the first sub-pixel, the second sub-pixel and the third sub-pixel further include a first light-emitting layer, a second light-emitting layer and a third light-emitting layer, respectively, located on the side of their respective charge generation layers close to the base substrate; the thickness of the second light-emitting layer and the thickness of the third light-emitting layer are greater than the thickness of the first light-emitting layer; and the charge generation layers of the first sub-pixel and the adjacent second sub-pixel or the third sub-pixel are disconnected from each other at least by a portion of the isolation structure having the first isolation height, and the charge generation layers of the second sub-pixel and the third sub-pixel are disconnected from each other by a portion of the isolation structure having the second isolation height.

[0006] In the display panel provided according to at least one embodiment of the present disclosure, the portion of the isolation structure having the first isolation height includes an isolation portion arranged in at least one of the first sub-pixel region where the first sub-pixel is located and the pixel spacing region between the first sub-pixel and the adjacent sub-pixel; the portion of the isolation structure having the second isolation height includes at least an isolation portion arranged in the pixel spacing region between the second sub-pixel and the third sub-pixel.

[0007] In the display panel provided according to at least one embodiment of the present disclosure, the portion of the isolation structure having the second isolation height also includes an isolation portion arranged in a pixel spacing area between the second sub-pixel and the first sub-pixel or in a pixel spacing area between the third sub-pixel and the first sub-pixel.

[0008] In the display panel provided according to at least one embodiment of the present disclosure, the isolation structure includes a plurality of pixel region isolation parts, which are respectively located in the plurality of sub-pixel regions, and at least the first pixel region isolation part located in the first sub-pixel region among the plurality of pixel region isolation parts has the first isolation height.

[0009] In the display panel provided according to at least one embodiment of the present disclosure, the multiple pixel region isolation portions include a second pixel region isolation portion and a third pixel region isolation portion, which are respectively located in the sub-pixel regions where the second sub-pixel and the third sub-pixel are located; and the second pixel region isolation portion and the third pixel region isolation portion have the first isolation height, or at least part of the second pixel region isolation portion and the third pixel region isolation portion has the second isolation height.

[0010] In the display panel provided according to at least one embodiment of the present disclosure, the isolation structure includes an inter-pixel isolation portion located between adjacent sub-pixels, and the inter-pixel isolation portion includes: a first inter-pixel isolation portion, located in the pixel spacing area between the first sub-pixel and the second sub-pixel or the first sub-pixel and the third sub-pixel; and a second inter-pixel isolation portion, located in the pixel spacing area between the second sub-pixel and the third sub-pixel.

[0011] In the display panel provided according to at least one embodiment of the present disclosure, the first inter-pixel isolation portion and the second inter-pixel isolation portion have the same second isolation height.

[0012] In the display panel provided according to at least one embodiment of the present disclosure, the first inter-pixel isolation portion has the first isolation height, and the second inter-pixel isolation portion has the second isolation height.

[0013] In the display panel provided according to at least one embodiment of the present disclosure, the first inter-pixel isolation portion and the second inter-pixel isolation portion are connected to or disconnected from each other, and the inter-pixel isolation portion includes an annular portion in a closed ring shape or an open ring shape, and the light-emitting area of ​​one or more sub-pixels among the multiple sub-pixels is surrounded by the annular portion in a direction parallel to the main surface of the base substrate.

[0014] In the display panel provided according to at least one embodiment of the present disclosure, at least one of the first inter-pixel isolation portion and the second inter-pixel isolation portion each includes a plurality of isolation sub-portions arranged side by side between adjacent sub-pixels along an arrangement direction of the adjacent sub-pixels.

[0015] In the display panel provided according to at least one embodiment of the present disclosure, the isolation structure includes: a first annular portion, which surrounds the light-emitting area of ​​a corresponding one of the multiple sub-pixels in a direction parallel to the main surface of the base substrate; and a second annular portion, which is located on a side of the first annular portion away from the sub-pixel and surrounds the first annular portion and the sub-pixel in a direction parallel to the main surface of the base substrate.

[0016] In the display panel provided according to at least one embodiment of the present disclosure, the multiple sub-pixels include a plurality of pixel units arranged in an array, and include: a first pixel column, including a plurality of the first sub-pixels arranged along a first direction; and a second pixel column, including a plurality of the second sub-pixels and a plurality of the third sub-pixels arranged alternately along the first direction, one or more of the first pixel columns and one or more of the second pixel columns are alternately arranged along a second direction intersecting with the first direction, wherein each first sub-pixel in the first pixel column and one second sub-pixel and one third sub-pixel in the second pixel column are adjacent to each other and form a pixel unit, wherein the light-emitting areas in the multiple sub-pixels are each surrounded by a corresponding isolation portion in the isolation structure in the sub-pixel arrangement direction.

[0017] In the display panel provided according to at least one embodiment of the present disclosure, the isolation structure includes at least one of a plurality of pixel area isolation parts and inter-pixel isolation parts; the plurality of pixel area isolation parts respectively surround the light-emitting areas of the plurality of sub-pixels in a direction parallel to the main surface of the base substrate; the inter-pixel isolation part includes: a first inter-pixel isolation part, extending along the first direction and located between the adjacent first pixel column and the second pixel column in the second direction; and a second inter-pixel isolation part, extending along the second direction and located between the adjacent second sub-pixel and third sub-pixel in the first direction.

[0018] In the display panel provided according to at least one embodiment of the present disclosure, the first inter-pixel isolation portion extends continuously along the first direction and is connected to a plurality of second inter-pixel isolation portions; or the first inter-pixel isolation portion and the second inter-pixel isolation portion are disconnected from each other, and the first inter-pixel isolation portion has a gap and includes a plurality of first pixel isolation portions disconnected from each other, each first pixel isolation portion being located between the corresponding first sub-pixel and the adjacent second sub-pixel and / or between the first sub-pixel and the adjacent third sub-pixel.

[0019] In the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the first sub-pixel on the first reference plane extending along the first direction has a first overlapping portion with the orthographic projection of the second sub-pixel on the first reference plane, and has a second overlapping portion with the orthographic projection of the third sub-pixel on the first reference plane; the orthographic projection of the gap of the first inter-pixel isolation portion on the first reference plane is offset from the first overlapping portion and the second overlapping portion, and the first overlapping portion and the second overlapping portion are respectively located within the orthographic projection of the corresponding first pixel isolation portion on the first reference plane.

[0020] In the display panel provided according to at least one embodiment of the present disclosure, the overlapping portion of the orthographic projections of adjacent second sub-pixels and third sub-pixels located in the same second pixel column on the second reference plane extending along the second direction is located within the orthographic projection of the second inter-pixel isolation portion on the second reference plane.

[0021] The display panel provided according to at least one embodiment of the present disclosure also includes a common electrode structure, and the second electrodes of the multiple sub-pixels share the common electrode structure, wherein the common electrode structure includes: a second electrode layer, arranged on a side of the charge generating layer away from the base substrate; and an auxiliary electrode layer, arranged on a side of the second electrode layer away from the base substrate and electrically connected to the second electrode layer, and the orthographic projection of the auxiliary electrode layer on the base substrate overlaps with the orthographic projection of the isolation structure on the base substrate.

[0022] According to at least one embodiment of the present disclosure, in the display panel provided, an orthographic projection of at least part of the isolation structure on the base substrate is located within an orthographic projection of the auxiliary electrode layer on the base substrate.

[0023] In the display panel provided according to at least one embodiment of the present disclosure, the second electrode layer includes a portion disconnected at the isolation structure, and the disconnected portion of the second electrode layer is electrically connected through the auxiliary electrode layer.

[0024] In the display panel provided according to at least one embodiment of the present disclosure, the auxiliary electrode layer includes at least one of a first auxiliary electrode layer and a second auxiliary electrode layer; the first auxiliary electrode layer extends in the pixel area and the pixel spacing area, and the orthographic projection of the second electrode layer on the base substrate is located within the orthographic projection of the first auxiliary electrode layer on the base substrate; and the orthographic projection of the second auxiliary electrode layer on the base substrate overlaps with the orthographic projection of at least part of the isolation structure on the base substrate, and is offset from the orthographic projection of at least part of the light-emitting areas of the multiple sub-pixels on the base substrate.

[0025] According to at least one embodiment of the present disclosure, a display panel is provided, which includes a light-emitting stacking layer, wherein the light-emitting stacking layer includes: a first light-emitting stacking portion, which includes at least the charge generation layer of the first sub-pixel; a second light-emitting stacking portion, which includes at least the charge generation layer of the second sub-pixel; a third light-emitting stacking portion, which includes at least the charge generation layer of the third sub-pixel; and a dummy stacking portion, which is located between adjacent light-emitting stacking portions in the first light-emitting stacking portion, the second light-emitting stacking portion and the third light-emitting stacking portion, wherein the first light-emitting stacking portion, the second light-emitting stacking portion and the third light-emitting stacking portion each include a first stacking sub-portion and a second stacking sub-portion; in each light-emitting stacking portion, the first stacking sub-portion is located in the light-emitting area defined by the sub-pixel opening of the pixel defining structure, and the second stacking sub-portion is located on the side of the portion of the pixel defining structure that defines the sub-pixel opening away from the base substrate.

[0026] In the display panel provided according to at least one embodiment of the present disclosure, the charge generation layers of the first stacking sub-section and the second stacking sub-section of the first light-emitting stacking section are disconnected from each other by the first pixel region isolation section of the isolation structure.

[0027] In the display panel provided according to at least one embodiment of the present disclosure, the step difference between the charge generation layers of the first stacking sub-section and the second stacking sub-section of the first light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the first isolation height.

[0028] In the display panel provided according to at least one embodiment of the present disclosure, the charge generation layers of the first stack sub-section and the second stack sub-section of the first light-emitting stack section are connected to each other.

[0029] In the display panel provided according to at least one embodiment of the present disclosure, the charge generation layers of the first stacking sub-unit and the second stacking sub-unit of the second light-emitting stacking unit are connected to each other or disconnected from each other; the charge generation layers of the first stacking sub-unit and the second stacking sub-unit of the third light-emitting stacking unit are connected to each other or disconnected from each other.

[0030] In the display panel provided according to at least one embodiment of the present disclosure, the dummy stacking portion includes: a first dummy stacking portion, located in a pixel spacing area between a first sub-pixel and a second sub-pixel adjacent to each other, and including a first dummy charge generating layer, the first dummy charge generating layer and the charge generating layers in the first light-emitting stacking portion and the second light-emitting stacking portion are disconnected from each other by the first inter-pixel isolation portion of the isolation structure.

[0031] In the display panel provided according to at least one embodiment of the present disclosure, the step difference between the first dummy charge generating layer and the charge generating layer in the second stacking sub-section of the first light-emitting stacking section or the second light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the first isolation height or the second isolation height.

[0032] In the display panel provided according to at least one embodiment of the present disclosure, the dummy stacking portion includes: a second dummy stacking portion, located in the pixel spacing area between the second sub-pixel and the third sub-pixel adjacent to each other, and including a second dummy charge generation layer, the second dummy charge generation layer and the charge generation layers in the second light-emitting stacking portion and the third light-emitting stacking portion are disconnected from each other by the second inter-pixel isolation portion of the isolation structure.

[0033] In the display panel provided according to at least one embodiment of the present disclosure, the step difference between the second dummy charge generation layer and the charge generation layer in the second stacking sub-section of the second light-emitting stacking section or the third light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the second isolation height.

[0034] In the display panel provided according to at least one embodiment of the present disclosure, at least one of the dummy stacked parts is connected to a dummy electrode, and the dummy electrode and the first electrode are provided in the same electrode layer and are electrically isolated from each other.

[0035] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure includes at least a first pixel defining layer and a second pixel defining layer, the second pixel defining layer is located on a side of the first pixel defining layer away from the base substrate, and includes an extension portion, the extension portion extends beyond the edge of the first pixel defining layer in a direction parallel to the main surface of the base substrate, and has an undercut structure between the extension portion and a material layer located on a side of the first pixel defining layer close to the base substrate, and the isolation structure includes at least the extension portion and the undercut structure.

[0036] The display panel provided according to at least one embodiment of the present disclosure further includes: a planarization structure, which is arranged on the base substrate, wherein the multiple first electrodes of the multiple sub-pixels are located on a side of the planarization structure away from the base substrate; the pixel defining structure is located on a side of the planarization structure and the multiple first electrodes away from the base substrate, and the multiple sub-pixel openings respectively expose portions of the multiple first electrodes, wherein the pixel defining structure also includes an isolation opening, which is located in a pixel spacing region between adjacent sub-pixels and exposes a portion of the surface of the planarization structure.

[0037] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure includes: a sub-pixel opening defining portion, which defines the sub-pixel opening and serves as a pixel area isolation portion of the isolation structure, the sub-pixel opening defining portion includes a first extension portion, and has a first undercut structure between the first extension portion and the first electrode; and an isolation opening defining portion, which defines the isolation opening and serves as an inter-pixel isolation portion of the isolation structure, the isolation opening defining portion includes a second extension portion, and has a second undercut structure between the second extension portion and the planarization structure.

[0038] In the display panel provided according to at least one embodiment of the present disclosure, the planarization structure has a recess, the recess is spatially connected to the isolation opening, and the sum of the depth of the isolation opening and the depth of the recess defines the second isolation height.

[0039] The display panel provided according to at least one embodiment of the present disclosure further includes a dummy electrode located between the planarization structure and the isolation opening defining portion, the dummy electrode having an electrode opening, the electrode opening being spatially connected to the isolation opening, and the sum of the depth of the isolation opening and the depth of the electrode opening defining the second isolation height.

[0040] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure further includes: a pixel defining main layer, located on the side of the first pixel defining layer close to the base substrate, defining the sub-pixel opening, and including a first main portion located between the first sub-pixel and the adjacent second sub-pixel or the third sub-pixel, and a second main portion located between the second sub-pixel and the third sub-pixel, wherein the first pixel defining layer and the second pixel defining layer include a first isolation portion and a second isolation portion respectively located on the first main portion and the second main portion, each isolation portion includes the extension portion of the second pixel defining layer, and has a bottom cut structure between the extension portion and the pixel defining main layer.

[0041] In the display panel provided according to at least one embodiment of the present disclosure, the first isolation portion has a first isolation opening, exposing a portion of the surface of the first main body portion, and the depth of the first isolation opening defines the first isolation height; and the second isolation portion has a second isolation opening, exposing a portion of the surface of the second main body portion, and the second main body portion has a main body recess, the main body recess is spatially connected to the second isolation opening, and the sum of the depth of the second isolation opening and the main body recess defines the second isolation height.

[0042] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure includes a plurality of pixel defining layers stacked in sequence in a direction perpendicular to the main surface of the base substrate, and the second pixel defining layer is one of the plurality of pixel defining layers farthest from the base substrate, and the pixel defining structure includes a sub-pixel opening defining portion and an isolation opening defining portion; in the sub-pixel opening defining portion, the side walls of the plurality of pixel defining layers are connected to each other and together constitute the side walls that define the sub-pixel opening; the isolation opening defining portion includes the extension portion and the undercut structure that constitute the isolation structure.

[0043] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure includes: a first pixel stacking portion, located between the first sub-pixel and the second sub-pixel, and having a first recess including one or more first isolation openings; and a second pixel stacking portion, located between the second sub-pixel and the third sub-pixel, and having a second recess including one or more second isolation openings; wherein the edge portion of each pixel stacking portion serves as a sub-pixel opening defining portion, defining a portion of the corresponding sub-pixel opening, and the portion defining the recess of each pixel stacking portion serves as an isolation opening defining portion, and includes one or more extensions of the pixel defining layer and one or more undercut structures.

[0044] In the display panel provided according to at least one embodiment of the present disclosure, the depth of the first recess is smaller than the depth of the second recess.

[0045] In the display panel provided according to at least one embodiment of the present disclosure, the pixel defining structure includes a plurality of first pixel defining layers and a plurality of second pixel defining layers alternately stacked in a direction perpendicular to the main surface of the base substrate, and includes a plurality of undercut structures, each undercut structure being located on a side of an extension portion of a corresponding second pixel defining layer close to the base substrate.

[0046] In the display panel provided according to at least one embodiment of the present disclosure, the first pixel defining layer and the second pixel defining layer include different materials.

[0047] In the display panel provided according to at least one embodiment of the present disclosure, at least one of the first pixel defining layer and the second pixel defining layer includes an inorganic material.

[0048] In the display panel provided according to at least one embodiment of the present disclosure, one of the first pixel defining layer and the second pixel defining layer includes aluminum oxide, and the other of the first pixel defining layer and the second pixel defining layer includes silicon nitride or silicon oxide; or one of the first pixel defining layer and the second pixel defining layer includes silicon oxide, and the other of the first pixel defining layer and the second pixel defining layer includes silicon carbonitride; or one of the first pixel defining layer and the second pixel defining layer includes titanium oxide, and the other of the first pixel defining layer and the second pixel defining layer includes niobium oxide.

[0049] In the display panel provided according to at least one embodiment of the present disclosure, the undercut structure has a width ranging from 0.05 μm to 5 μm in a direction parallel to the main surface of the base substrate.

[0050] In the display panel provided according to at least one embodiment of the present disclosure, the first isolation height ranges from 300 angstroms to 1250 angstroms, and the second isolation height ranges from 600 angstroms to 1650 angstroms.

[0051] An embodiment of the present disclosure provides a display device, comprising any one of the display panels described above.

[0052] At least one embodiment of the present disclosure provides a method for manufacturing a display panel, wherein the display panel has a pixel area including a plurality of sub-pixel areas and a pixel spacing area located between adjacent sub-pixel areas, the manufacturing method comprising: providing a base substrate; forming a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are respectively located in the plurality of sub-pixel areas, wherein each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, each light-emitting device includes a first electrode, a charge generation layer and a second electrode stacked in sequence, and the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel adjacent to each other and used to display different colors; forming a pixel defining structure, wherein the pixel defining structure has a plurality of sub-pixel openings to define the light-emitting areas of the plurality of sub-pixels, wherein at least a portion of each light-emitting device is located in a corresponding sub-pixel opening; and forming an isolation structure in at least one of the pixel area and the pixel spacing area, the isolation structure including a portion having a first isolation height and a portion having a second isolation height, the second isolation height being greater than the first isolation height, wherein the charge generation layers of adjacent sub-pixels in the plurality of sub-pixels are disconnected from each other by the isolation structure.

[0053] In the manufacturing method of the display panel provided according to at least one embodiment of the present disclosure, forming the pixel defining structure and the isolation structure includes: sequentially forming a first pixel defining layer and a second pixel defining layer on one side of the planarization structure on the base substrate; performing a first removal process to remove a portion of the second pixel defining layer and forming an opening in the second pixel defining layer, the opening being defined by an extension portion of the second pixel defining layer and exposing a portion of the surface of the first pixel defining layer; and performing a second removal process to remove the portion of the first pixel defining layer exposed by the opening and the portion covered by the extension portion of the second pixel defining layer, and forming an undercut structure on a side of the extension portion close to the base substrate, the isolation structure including the extension portion and the undercut structure.

[0054] In the method for manufacturing a display panel provided according to at least one embodiment of the present disclosure, after the second removal process, isolation openings exposing a portion of the surface of the planarization structure are formed in the first pixel defining layer and the second pixel defining layer.

[0055] The method for manufacturing a display panel provided according to at least one embodiment of the present disclosure further includes: performing a third removal process to remove a portion of the planarization structure exposed by the isolation opening and forming a recess in the planarization structure.

[0056] In the manufacturing method of the display panel provided according to at least one embodiment of the present disclosure, forming the pixel defining structure also includes: forming a pixel defining main layer before forming the first pixel defining layer, wherein after the second removal process, multiple openings in the first pixel defining layer and the second pixel defining layer expose part of the surface of the pixel defining main layer; and performing a third removal process to remove the portion of the pixel defining main layer exposed by some of the multiple openings to form a recess in a partial area of ​​the pixel defining main layer.

[0057] In the manufacturing method of the display panel provided according to at least one embodiment of the present disclosure, forming the pixel defining structure and the isolation structure includes: sequentially forming a plurality of pixel defining layers on the base substrate; performing a first removal process on a first pixel stacking portion of the plurality of pixel defining layers located in a first pixel spacing region to remove portions of at least two pixel defining layers among the plurality of pixel defining layers, and forming a first recess including one or more first isolation openings in the first spacing defining portion; and performing a second removal process on a second pixel stacking portion of the plurality of pixel defining layers located in a second pixel spacing region to remove portions of at least three pixel defining layers among the plurality of pixel defining layers, and forming a second recess including one or more second isolation openings in the second pixel stacking portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0059] Figure 1A shows a schematic plan view of multiple sub-pixels and isolation structures in a display panel according to some embodiments of the present disclosure; Figure 1B and Figure 1C show schematic cross-sectional views of the display panel according to some embodiments of the present disclosure, taken along line II' and line II-II' of Figure 1A, respectively.

[0060] 2A to 2G are schematic plan views of components such as a plurality of sub-pixels and an isolation structure in a display panel according to some embodiments of the present disclosure.

[0061] 3A and 3B illustrate schematic cross-sectional views of display panels according to some embodiments of the present disclosure.

[0062] 4A to 4G are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to some embodiments of the present disclosure.

[0063] FIG5 shows a schematic cross-sectional view of a display panel according to some other embodiments of the present disclosure.

[0064] 6A to 6D are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to other embodiments of the present disclosure.

[0065] FIG. 7 shows a schematic cross-sectional view of a display panel according to further embodiments of the present disclosure.

[0066] 8A to 8C are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to further embodiments of the present disclosure.

[0067] FIG9 is a schematic cross-sectional view illustrating a display panel according to further embodiments of the present disclosure.

[0068] 10A to 10E are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to further embodiments of the present disclosure.

[0069] FIG. 11 shows a schematic cross-sectional view of a display panel according to yet other embodiments of the present disclosure.

[0070] 12A to 12G are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to yet other embodiments of the present disclosure.

[0071] FIG13 illustrates a schematic cross-sectional view of an isolation structure in a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0072] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0074] In the display panels of various embodiments of the present disclosure, by providing isolation structures with various isolation heights to achieve separation between different sub-pixels, it is possible to effectively isolate high-mobility film layers, such as charge generation layers, between different sub-pixels, thereby avoiding electrical crosstalk between different sub-pixels and thereby improving the color gamut of the display panel. Furthermore, by providing isolation portions with smaller isolation heights in certain areas, the possibility of the second electrode layer (e.g., cathode) in the corresponding light-emitting device being disconnected by the isolation structure can be avoided or reduced while achieving pixel isolation. This can further avoid or reduce poor brightness uniformity and high power consumption of the light-emitting device caused by voltage drop due to the disconnection of the second electrode layer. In some embodiments, the second electrode layer can be further prevented from being disconnected by precisely controlling the isolation heights of the isolation portions of the isolation structure, or by designing the shape and other structures of the isolation structure and / or providing an auxiliary electrode layer, thereby improving the brightness uniformity and display quality of the display panel and reducing the power consumption of the light-emitting device.

[0075] Figure 1A shows a schematic plan view of multiple sub-pixels and an isolation structure in a display panel according to some embodiments of the present disclosure; Figure 1B and Figure 1C show schematic cross-sectional views of the display panel according to some embodiments of the present disclosure, taken along line II' and line II-II' of Figure 1A, respectively.

[0076] 1A , in some embodiments, the display panel may have a pixel region including a plurality of sub-pixel regions 10 and a pixel spacing region located between adjacent sub-pixel regions 10, and include a plurality of sub-pixels arranged on a base substrate and respectively located in the plurality of sub-pixel regions 10. Each sub-pixel may include a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light. In some embodiments, each light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode, and the light-emitting material layer may include a light-emitting layer and a charge generation layer, etc. The charge generation layer is, for example, arranged on a side of the light-emitting layer away from the base substrate. The first electrode and the second electrode may serve as the anode and cathode of the light-emitting device, respectively. In some embodiments, the display panel includes an isolation structure for disconnecting high-mobility film layers such as the charge generation layer of adjacent sub-pixels, thereby avoiding electrical crosstalk between adjacent sub-pixels.

[0077] In some embodiments, the isolation structure may be located in at least one of the pixel region and the pixel spacing region, and include a portion having a first isolation height and a portion having a second isolation height, the second isolation height being greater than the first isolation height, and the charge generation layers of adjacent sub-pixels in the plurality of sub-pixels are disconnected from each other by at least one of the portion having the first isolation height and the portion having the second isolation height in the isolation structure. In some embodiments, the thickness of the light-emitting layers of different sub-pixels is different, and the height of the charge generation layers is different. For example, at least a portion of the light-emitting layer is located on the side of the charge generation layer close to the substrate. To a certain extent, the greater the thickness of the light-emitting layer, the higher the position of the corresponding charge generation layer. The isolation height of the isolation structure can be set according to the height of the charge generation layer of the corresponding sub-pixel. Here, the height of the charge generation layer refers to the height of the charge generation layer from the surface of the light-emitting material layer closest to the substrate, or the distance between the charge generation layer and the main surface of the substrate.

[0078] In some embodiments, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel for displaying different colors. The portion of the isolation structure having a first isolation height may include an isolation portion disposed in at least one of a first sub-pixel region where the first sub-pixel is located and a pixel spacing region between the first sub-pixel and an adjacent sub-pixel. The portion of the isolation structure having a second isolation height may include at least an isolation portion disposed in the pixel spacing region between the second sub-pixel and the third sub-pixel, or may further include an isolation portion disposed in the pixel spacing region between the first sub-pixel and an adjacent second sub-pixel or third sub-pixel.

[0079] For example, the plurality of sub-pixels may include sub-pixels SP1, SP2, and SP3 located in sub-pixel regions 10a, 10b, and 10c, respectively. Sub-pixel regions 10a, 10b, and 10c may be referred to as the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, respectively; and sub-pixels SP1, SP2, and SP3 may be referred to as the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively. In some embodiments, the isolation structure IS may include a pixel region isolation portion 11 and an inter-pixel isolation portion 12 located in the pixel region and the inter-pixel region, respectively. The pixel region isolation portion 11 and the inter-pixel isolation portion 12 may each have the first isolation height and / or the second isolation height. In some embodiments, a pixel region isolation portion may be provided in each sub-pixel region; for example, the pixel region isolation portion 11 may include pixel region isolation portions 11a, 11b, and 11c respectively provided in the sub-pixel regions 10a, 10b, and 10c; the inter-pixel isolation portion 12 may include a portion provided between different adjacent sub-pixels, for example, may include an inter-pixel isolation portion 12a provided between sub-pixels SP1 and SP2 and / or between sub-pixels SP1 and SP3, and an inter-pixel isolation portion 12b provided between sub-pixels SP2 and sub-pixels SP3. In some embodiments, the plurality of pixel region isolation portions 11a-11c may have the same first isolation height, and the plurality of inter-pixel isolation portions 12a and 12b may have the same second isolation height; or a portion of the pixel region isolation portions (e.g., pixel region isolation portion 11a) may have the first isolation height, while another portion of the pixel region isolation portions (e.g., pixel region isolation portion 11b or 11c) may have the second isolation height; or a portion of the inter-pixel isolation portions (e.g., inter-pixel isolation portion 12a) may have the first isolation height, while another portion of the inter-pixel isolation portions (e.g., inter-pixel isolation portion 12b) may have the second isolation height. However, the present disclosure is not limited thereto.

[0080] 1B and 1C are schematic principle diagrams showing that the charge generation layers of adjacent sub-pixels in a plurality of sub-pixels are disconnected by an isolation structure.

[0081] Referring to Figures 1A to 1C , a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 are disposed above a base substrate 10. It should be understood that Figures 1B and 1C merely schematically illustrate the principle of disconnecting the charge generation layers of adjacent subpixels and do not specifically illustrate all components of the display panel. In some embodiments, the first subpixel SP1 includes a first light-emitting layer 13a and a charge generation layer 15a embedded within the first light-emitting layer 13a; the second subpixel SP2 includes a second light-emitting layer 13b and a charge generation layer 15b embedded within the second light-emitting layer 13b; and the third subpixel SP3 includes a third light-emitting layer 13c and a charge generation layer 15c embedded within the third light-emitting layer 13c. At least a portion of each light-emitting layer is located on the side of the charge generation layer closest to the base substrate. In some embodiments, the light-emitting layers of different subpixels may have different thicknesses; for example, the second and third light-emitting layers 13b and 13c may be thicker than the first light-emitting layer 13a. In some embodiments, the charge generation layer of the first sub-pixel SP1 and the adjacent second sub-pixel SP2 or third sub-pixel SP3 can be disconnected from each other by at least a portion having a first isolation height in the isolation structure, and the charge generation layers of the second sub-pixel SP2 and the third sub-pixel SP3 can be disconnected from each other by a portion having a second isolation height in the isolation structure.

[0082] For example, the plurality of pixel region isolation portions 11a, 11b, 11c may each have a first isolation height H1, and the inter-pixel isolation portions 12a, 12b may each have a second isolation height H2. In this article, the first isolation height represents a smaller isolation height, and is smaller than the second isolation height. The charge generation layers shown in Figures 1B and 1C schematically illustrate the conductive paths of each charge generation layer, and the cross symbol (×) indicates that the charge generation layer is disconnected at this location. For example, as shown in Figure 1B, for the first sub-pixel SP1 having a relatively small light-emitting layer thickness (i.e., the height of the charge generation layer is relatively low), the charge generation layer 15a may be disconnected at the pixel region isolation portion 11a having the first isolation height H1, and may also be disconnected at the inter-pixel isolation portion 12a having the second isolation height, so that the portion 15a1 of the charge generation layer 15a located in the light-emitting area can be disconnected from the charge generation layers of other adjacent sub-pixels. For the second and third sub-pixels SP2 and SP3, which have relatively thick luminescent layers (i.e., the charge generation layers are located at a relatively high height), the charge generation layers 15b and 15c may not be disconnected at the pixel region isolation portions 11b and 11c having the first isolation height H1. Instead, they can be disconnected at the inter-pixel isolation portions 12a and 12b having the second isolation height, respectively. This disconnects the charge generation layers in the luminescent regions of the second and third sub-pixels. In this way, the charge generation layers of adjacent sub-pixels are disconnected from each other, thereby preventing electrical crosstalk between adjacent sub-pixels.

[0083] It should be understood that the positions of the two isolation heights shown in Figures 1B and 1C are for illustrative purposes only and are not intended to limit the present disclosure. The two isolation heights of the isolation structure can be adjusted based on relevant product design and requirements, such as the sub-pixel arrangement and the evaporation area of ​​the light-emitting material in the pixel area, as long as the two isolation heights can achieve disconnection of high-mobility film layers such as the charge generation layer between adjacent sub-pixels.

[0084] In the disclosed embodiments, isolation structures with different isolation heights are provided for different sub-pixels. These different isolation heights correspond to the heights of the charge generation layers in different luminescent material layers, thereby achieving precise isolation between adjacent sub-pixels. Furthermore, by providing an isolation portion with a smaller isolation height for sub-pixels with thinner luminescent layers, the possibility of disconnection of the second electrode layer located above the luminescent material layer can be avoided or reduced.

[0085] Figures 2A to 2F illustrate schematic plan views of multiple sub-pixels and isolation structures in a display panel according to some embodiments of the present disclosure. The area surrounded by isolation structure 11 in Figures 2A to 2F represents the light-emitting region of each sub-pixel, and the dashed boxes in Figures 2A and 2B represent the vapor deposition region of the light-emitting material layer of each sub-pixel.

[0086] 2A to 2F , in some embodiments, the display panel includes a plurality of pixel units, and each pixel unit may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 adjacent to each other. The plurality of pixel units may be arranged in an array, for example, along a first direction D1 and a second direction D2 into an array including multiple rows and columns. For example, the plurality of subpixels may include a first pixel column 6 and a second pixel column 8. The first pixel column 6 includes a plurality of first subpixels SP1 arranged along a first direction (e.g., direction D1); the second pixel column 8 includes a plurality of second subpixels SP2 and a plurality of third subpixels SP3 arranged alternately along the first direction (e.g., direction D1). In some embodiments, one or more first pixel columns 6 and one or more second pixel columns 8 may be arranged alternately along a second direction (e.g., direction D2) that intersects the first direction. Each first subpixel SP1 in a first pixel column 6, together with one second subpixel SP2 and one third subpixel SP3 adjacent to it in an adjacent second pixel column 8, constitutes a pixel unit. That is, in the same pixel unit, the second sub-pixel SP2 and the third sub-pixel SP3 may be located on the same side of the first sub-pixel SP1 in direction D2 and in the same pixel column; the second sub-pixel SP3 and the third sub-pixel SP3 may each partially overlap with the first sub-pixel SP1 in direction D2, and the second sub-pixel SP2 and the third sub-pixel SP3 overlap each other in direction D1.

[0087] In some embodiments, the light-emitting regions of the plurality of sub-pixels are each surrounded by a corresponding isolation portion of the isolation structure in the sub-pixel arrangement direction. The isolation structure may include at least one of a plurality of pixel region isolation portions and an inter-pixel isolation portion. For example, the isolation structure may include at least a plurality of pixel region isolation portions 11a, 11b, and 11c.

[0088] In some embodiments, as shown in FIG2A , the charge generation layer in each sub-pixel region can be disconnected solely by a pixel region isolation portion, thereby isolating the charge generation layer of each sub-pixel from the charge generation layer of an adjacent sub-pixel. In some embodiments, there is no need to provide an inter-pixel isolation portion in the inter-pixel region between the sub-pixels, but the present disclosure is not limited thereto.

[0089] In some embodiments, a plurality of pixel region isolation portions surround the light-emitting regions of a plurality of sub-pixels in a direction parallel to the main surface of the substrate. One or more of the plurality of pixel region isolation portions may separate the charge generation layer located in the light-emitting region (i.e., the effective charge generation layer of the light-emitting device) of the corresponding sub-pixel region from the charge generation layer located outside the light-emitting region. For example, the pixel region isolation portion may be in the shape of a closed ring, but the present disclosure is not limited thereto.

[0090] Referring to Figure 2A , in this embodiment, the multiple pixel region isolation portions may have the same isolation height, and the effective charge generation layer of each sub-pixel may be isolated from the charge generation layers of other sub-pixels by the corresponding pixel region isolation portion. In other embodiments, the multiple pixel region isolation portions may have different isolation heights; for example, the pixel region isolation portion 11a corresponding to the first sub-pixel SP1 may have a smaller first isolation height, while the pixel region isolation portions 11b or 11c corresponding to the second sub-pixel SP2 and / or the third sub-pixel SP3 may have a larger second isolation height.

[0091] Referring to Figures 2B to 2F , in some embodiments, the isolation structure IS includes a pixel region isolation portion 11 and also includes an inter-pixel isolation portion 12. For example, the inter-pixel isolation portion 12 may include a first inter-pixel isolation portion 12a and a second inter-pixel isolation portion 12b. The first inter-pixel isolation portion 12a may extend along direction D1 and be located between adjacent first pixel column 6 and second pixel column 8 in direction D2. That is, the first inter-pixel isolation portion 12a is located in the inter-pixel region between sub-pixel SP1 and sub-pixels SP2 and / or SP3. The second inter-pixel isolation portion 12b may extend along direction D2 and be located in the inter-pixel region between adjacent sub-pixels SP2 and SP3 in direction D1. In some embodiments, the light-emitting material layer formation regions (e.g., vapor deposition regions) of adjacent sub-pixels SP1 in direction D1 may be spaced apart from each other, i.e., non-adjacent and non-overlapping. Therefore, an isolation structure may not be provided in the inter-pixel region between adjacent sub-pixels SP1, but the present disclosure is not limited thereto. In some other examples, an inter-pixel isolation portion may also be provided between adjacent sub-pixels SP1 in the direction D1.

[0092] In some embodiments, the first inter-pixel isolation portion 12a and the second inter-pixel isolation portion 12b may have the same or different isolation heights. For example, in some examples, the pixel region isolation portion 11 may have a first isolation height, and the first inter-pixel isolation portion 12a and the second inter-pixel isolation portion 12b may have the same second isolation height. In other examples, the pixel region isolation portion 11 may have a first isolation height, the first inter-pixel isolation portion 12a may have a first isolation height, and the second inter-pixel isolation portion 12b may have a second isolation height.

[0093] In some embodiments, the first inter-pixel isolation portion and the second inter-pixel isolation portion are connected to or disconnected from each other, and the inter-pixel isolation portion includes an annular portion in a closed ring shape or an open ring shape, and the light-emitting area of ​​one or more sub-pixels among the multiple sub-pixels is surrounded by the annular portion in a direction parallel to the main surface of the substrate.

[0094] In some embodiments, the isolation structure may include a first annular portion and a second annular portion, wherein the first annular portion surrounds the light-emitting area of ​​a corresponding one of the plurality of sub-pixels in a direction parallel to the main surface of the substrate; the second annular portion is located on a side of the first annular portion away from the sub-pixel and surrounds the first annular portion and the sub-pixel in a direction parallel to the main surface of the substrate. The first annular portion may be or include a pixel area isolation portion, and the second annular portion may be composed of a first inter-pixel isolation portion and a second inter-pixel isolation portion. The first annular portion and the second annular portion may each be a closed annular portion or an open annular portion (i.e., an annular portion with a gap).

[0095] In some embodiments, as shown in FIG2B , the first inter-pixel partition 12a and the second inter-pixel partition 12b may be connected to each other to form a closed ring-shaped annular portion, such that one or more sub-pixels among the plurality of sub-pixels are surrounded by the annular portion in a direction parallel to the main surface of the substrate. For example, the first inter-pixel partition 12a may extend continuously along direction D1, and multiple second inter-pixel partitions 12b located in the same pixel column may be connected to adjacent first inter-pixel partitions 12a to form an annular portion, such that corresponding sub-pixels SP2 and / or SP3 are surrounded by the annular portion.

[0096] In the example shown in FIG2B , the inter-pixel isolation portion extends continuously between multiple sub-pixels, and adjacent sub-pixels are completely separated by the inter-pixel isolation portion, thereby ensuring that the charge generation layers of adjacent sub-pixels can be effectively disconnected by the inter-pixel isolation portion. However, the present disclosure is not limited thereto.

[0097] With reference to FIG2C and FIG2D , in some examples, the first inter-pixel partition 12a may be disconnected from the second inter-pixel partition 12b. Each first inter-pixel partition 12a may include multiple disconnected first pixel partitions, each of which is located between a corresponding first sub-pixel and an adjacent second sub-pixel and / or between the first sub-pixel and an adjacent third sub-pixel. In other words, the first inter-pixel partition 12a may have one or more gaps 12o, and a gap may exist between the first inter-pixel partition 12a and the second inter-pixel partition 12b.

[0098] Continuing with reference to Figures 2C and 2D, in some embodiments, the orthographic projection of the first subpixel SP1 on the first reference plane extending along the first direction D1 has a first overlapping portion with the orthographic projection of the second subpixel SP2 on the first reference plane, and has a second overlapping portion with the orthographic projection of the third subpixel SP3 on the first reference plane. The orthographic projection of the notch 12o of the first inter-pixel spacer 12a on the first reference plane is offset from the first overlapping portion and the second overlapping portion, and the first overlapping portion and the second overlapping portion are respectively located within the orthographic projection of the corresponding first inter-pixel spacer on the first reference plane. In some embodiments, the overlapping portion of the orthographic projections of adjacent second subpixels SP2 and third subpixels SP3 in the same second pixel column 8 on the second reference plane extending along the second direction D2 is located within the orthographic projection of the second inter-pixel spacer 12b on the second reference plane.

[0099] In these embodiments, the inter-pixel isolation portion is disposed between overlapping portions of adjacent sub-pixels parallel to the main surface of the substrate, and the gap in the inter-pixel isolation portion is disposed in an area where adjacent sub-pixels do not overlap. This effectively disconnects the charge generation layers of adjacent sub-pixels while preventing or minimizing the possibility that the second electrode material (e.g., cathode) on the light-emitting material layer will also be disconnected by the isolation structure.

[0100] In the above example, a single inter-pixel isolation portion is provided between two adjacent sub-pixels to prevent electrical crosstalk between the adjacent sub-pixels, but the present disclosure is not limited thereto. In other examples, the inter-pixel isolation portion (e.g., at least one of the first inter-pixel isolation portion and the second inter-pixel isolation portion) between two adjacent sub-pixels may include multiple isolation sub-portions arranged side by side along the arrangement direction of the adjacent sub-pixels, thereby further ensuring that the charge generation layers of adjacent sub-pixels can be effectively disconnected by the isolation structure.

[0101] 2E and 2F , for example, the first inter-pixel partition 12a may include a partitioning sub-portion 12a1 and a partitioning sub-portion 12a2 spaced apart from each other. The partitioning sub-portions 12a1 and 12a2 may extend substantially parallel to each other along a direction D1 and be arranged along a direction D2 between the sub-pixel SP1 and the adjacent sub-pixel SP2 and / or between the sub-pixel SP1 and the adjacent sub-pixel SP3. The second inter-pixel partition 12b may include a partitioning sub-portion 12b1 and a partitioning sub-portion 12b2 spaced apart from each other. The partitioning sub-portions 12b1 and 12b2 may extend substantially parallel to each other along a direction D2 and be arranged along a direction D1 between the adjacent sub-pixels SP2 and SP3.

[0102] The cross-sectional structure of the display panel is described in detail below. It should be understood that the pixel arrangement and the planar layout of the isolation structure in the display panel of each embodiment may adopt any one of Figures 2A to 2F, and the present disclosure is not limited thereto.

[0103] FIG3A illustrates a schematic cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0104] Referring to FIG3A , in some embodiments, a display panel 500A includes a pixel region R1 and a pixel spacing region R2 located between adjacent sub-pixel regions. Pixel region R1 includes multiple sub-pixel regions, such as a first sub-pixel region R1a, a second sub-pixel region R1b, and a third sub-pixel region R1c. Pixel spacing region R2 includes a first pixel spacing region R2a located between sub-pixel region R1a and adjacent sub-pixel regions R1b and / or R1c, and a second pixel spacing region R2b located between adjacent sub-pixel regions R1b and R1c. In this context, a sub-pixel region includes a light-emitting region and a peripheral region adjacent to and surrounding the light-emitting region.

[0105] For example, a display panel 500a includes a plurality of sub-pixels and may include a base substrate 100, a pixel circuit layer CL, a planarization structure PL, a pixel defining structure PS, an isolation structure IS, and a light-emitting stack layer LE. The plurality of sub-pixels are disposed on the base substrate 100 and may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 for displaying different colors, located in sub-pixel region R1a, a second sub-pixel region R1b, and a third sub-pixel region R1c, respectively. In some embodiments, the display panel 500a may be an OLED display panel, such as a tandem OLED display panel. For example, each sub-pixel includes a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light. For example, each light-emitting device may include a first electrode E1, a light-emitting material layer including a light-emitting layer and a charge-generating layer, and a second electrode E2, stacked in sequence perpendicular to the base substrate. In some embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are blue, green, and red sub-pixels, respectively, but the present disclosure is not limited thereto.

[0106] In some embodiments, the pixel circuit layer CL is disposed on one side of the base substrate 100 and may include sub-pixel circuits for multiple sub-pixels. For example, each sub-pixel circuit may include one or more thin-film transistors T and capacitors. In some embodiments, a buffer layer 101 may be further disposed between the base substrate 100 and the pixel circuit layer CL. The planarization structure PL is disposed on the side of the pixel circuit layer CL away from the base substrate 100 and may include at least a planarization layer 111.

[0107] In some embodiments, the first electrodes E1 of multiple sub-pixels are arranged on a side of the planarization structure PL away from the base substrate 100, and are electrically connected to the corresponding sub-pixel circuits through vias located in the planarization structure PL, for example, connected to the source electrode or drain electrode of the corresponding thin film transistor.

[0108] The pixel-defining structure PS is disposed on a side of the planarization structure PL away from the base substrate 100 and has a plurality of sub-pixel openings to define the light-emitting areas of the plurality of sub-pixels, with at least a portion of each light-emitting device located within a corresponding sub-pixel opening. For example, the plurality of sub-pixel openings include sub-pixel openings PO1, PO2, and PO3, which are used to define the light-emitting areas of sub-pixels SP1, SP2, and SP3, respectively. The pixel-defining structure PS may cover edge portions of the first electrodes of the plurality of sub-pixels, and the plurality of sub-pixel openings may expose portions of the surfaces of the plurality of first electrodes E1, respectively. In some embodiments, the pixel-defining structure PS may further include one or more isolation openings located in the pixel spacing region between adjacent sub-pixels and exposing portions of the surface of the planarization structure PL. For example, the pixel-defining structure PS may include an isolation opening IO1 and an isolation opening IO2 located in the pixel spacing region R2a and the pixel spacing region R2b, respectively.

[0109] The light-emitting stacked layer LE is disposed on the side of the pixel-defining structure PS and the planarization structure PL that is away from the substrate, as well as within multiple openings of the pixel-defining structure PS, including sub-pixel openings and isolation openings. The light-emitting stacked layer LE includes light-emitting material layers for the light-emitting devices of the multiple sub-pixels and may also include a dummy light-emitting material layer.

[0110] For example, in the light-emitting stacked layer LE, the light-emitting material layer of the first sub-pixel SP1 includes a light-emitting layer 115a, a charge generation layer 116a, and a light-emitting layer 117a stacked in sequence in a direction perpendicular to the main surface of the substrate 100. The light-emitting material layer of the second sub-pixel SP2 includes a light-emitting layer 115b, a charge generation layer 116b, and a light-emitting layer 117b stacked in sequence in a direction perpendicular to the main surface of the substrate 100. The light-emitting material layer of the third sub-pixel SP3 includes a light-emitting layer 115c, a charge generation layer 116c, and a light-emitting layer 117c stacked in sequence in a direction perpendicular to the main surface of the substrate 100. The light-emitting layers 115a, 115b, and 115c may also be referred to as the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer, respectively.

[0111] In some embodiments, the light-emitting layers 115a, 115b, and 115c are respectively located on the side of the charge generation layers 116a, 116b, and 116c that is close to the substrate 100, and the light-emitting layers 117a, 117b, and 117c are respectively located on the side of the charge generation layers 116a, 116b, and 116c that is away from the substrate 100. It should be understood that the material types and number of material layers included in the light-emitting material layers located at the first electrode and the second electrode in the light-emitting device shown in the figure are only illustrative, and the present disclosure is not limited thereto. In other embodiments, the light-emitting material layer of each sub-pixel may further include other materials for light-emitting devices such as hole injection layers, hole transport layers, exciton blocking layers, electron transport layers, and electron injection layers; in some embodiments, the light-emitting layer located on the side of the charge generation layer that is away from the substrate may be omitted.

[0112] In some embodiments, the thickness of the light-emitting layers 115b and 115c may be greater than the thickness of the light-emitting layer 115a; the thickness of the light-emitting layers 115b and 115c may be the same as or different from each other; for example, the thickness of the light-emitting layer 115b may be greater than or less than the thickness of the light-emitting layer 115c.

[0113] Continuing with reference to FIG3A , in some embodiments, the isolation structure 11 includes a plurality of pixel region isolation portions 11 and inter-pixel isolation portions 12. The plurality of pixel region isolation portions 11 are respectively located in the plurality of sub-pixel regions R1, such as the first pixel region isolation portion 11a, the second pixel region isolation portion 11b, and the third pixel region isolation portion 11c, respectively located in the first sub-pixel region R1a, the second sub-pixel region R1b, and the third sub-pixel region R1c. Among the plurality of pixel region isolation portions 11, at least the first pixel region isolation portion 11a has a first isolation height H1. In some embodiments, the plurality of pixel region isolation portions 11 all have the same first isolation height H1, i.e., the second pixel region isolation portion 11b and the third pixel region isolation portion 11c may also have the first isolation height H1.

[0114] In some embodiments, the inter-pixel isolation portion 12 is located in the pixel spacing region R2 between adjacent sub-pixels. For example, it may include a first inter-pixel isolation portion 12a and a second inter-pixel isolation portion 12b located in the first pixel spacing region R2a and the second pixel spacing region R2b, respectively. In some embodiments, the first inter-pixel isolation portion 12a and the second inter-pixel isolation portion 12b have the same second isolation height H2, but the present disclosure is not limited thereto.

[0115] In some embodiments, a portion of the pixel-defining structure PS that defines an opening (e.g., a sub-pixel opening or an isolation opening) can be used as an isolation structure. In other words, the isolation structure IS can share the same insulating structure with the pixel-defining structure PS. For example, the portion of the pixel-defining structure PS that defines the opening includes an extension of the pixel-defining layer, the extension extending beyond the edge of the adjacent material layer in a direction parallel to the main surface of the substrate, and having an undercut structure on a side of the extension proximal to the substrate. The isolation structure includes at least the extension and the undercut structure. In the disclosed embodiments, a portion of the pixel-defining structure is used as an isolation structure, thereby allowing the pixel-defining structure and isolation structures with various isolation heights to be formed simultaneously without adding additional masks. This simplifies the process and saves costs, thereby resolving the issues of complex and high-cost isolation structures in traditional processes.

[0116] Referring to FIG. 3A , for example, the pixel defining structure PS may include a first pixel defining layer 112a and a second pixel defining layer 112b. The first pixel defining layer 112a is located on the side of the planarization structure PL away from the substrate 100 and, in some embodiments, may cover a portion of the first electrode E1. The second pixel defining layer 112b is located on the side of the first pixel defining layer 112a away from the substrate 100. The second pixel defining layer 112b may include an extension portion that extends beyond the edge of the first pixel defining layer 112a in a direction parallel to the major surface of the substrate 100, with an undercut structure between the extension portion and the material layer located on the side of the first pixel defining layer 112a closer to the substrate. In some embodiments, the orthographic projection of the first pixel defining layer 112a on the substrate is within the orthographic projection of the second pixel defining layer 112b on the substrate, and the orthographic projection area of ​​the second pixel defining layer 112b is larger than the orthographic projection area of ​​the first pixel defining layer 112a.

[0117] FIG. 4G shows a structure after a pixel defining structure is formed on a base substrate but before a light emitting stack layer is formed.

[0118] Referring to Figures 3A and 4G , for example, the pixel defining structure PS may include a sub-pixel opening defining portion P1 for defining a sub-pixel opening and an isolation opening defining portion P2 for defining an isolation opening. Multiple sub-pixel opening defining portions P1 may each serve as a pixel region isolation portion 11 of the isolation structure, and multiple isolation opening defining portions P2 may each serve as at least a portion of an inter-pixel isolation portion 12 of the isolation structure IS. For example, the sub-pixel opening defining portion P1 may include a first extension ex1 of the second pixel defining layer 112b, with a first undercut structure uc1 between the first extension ex1 and the first electrode E1 in a direction perpendicular to the main surface of the substrate. The isolation opening defining portion P2 may include a second extension ex2 of the second pixel defining layer 112b, with a second undercut structure uc2 between the second extension ex2 and the planarization structure PL in a direction perpendicular to the main surface of the substrate.

[0119] In some embodiments, each of the multiple sub-pixel openings and isolation openings in the pixel defining structure PS includes a first sub-opening in the first pixel defining layer 112a and a second sub-opening in the second pixel defining layer 112b, wherein the width of the first sub-opening is greater than the width of the second sub-opening; the first sub-opening in the first pixel defining layer includes at least a portion of an undercut structure located below an extension of the second pixel defining layer. For example, an orthographic projection of the second sub-opening on the main surface of the substrate is within the orthographic projection of the first sub-opening on the main surface of the substrate, and the orthographic projection area of ​​the second sub-opening is smaller than the orthographic projection area of ​​the first sub-opening.

[0120] In some embodiments, the planarization structure PL has one or more recesses rc, which may be spatially connected to the isolation opening IO1 or IO2 in the pixel defining structure PS. In some embodiments, the second undercut structure uc2 may also extend into the planarization structure PL; for example, the width of the recess rc may be approximately equal to the width of the first sub-opening in the corresponding isolation opening, and the recess rc and a portion of the first sub-opening are located between the extension ex2 of the second pixel defining layer 112b and the planarization structure PL in a direction perpendicular to the main surface of the substrate, and together constitute the second undercut structure uc2. However, the present disclosure is not limited to this. In other embodiments, the width of the recess rc may also be less than the width of the first sub-opening in the corresponding isolation opening, or may be approximately equal to the width of the second sub-opening. In this document, the width of an opening, recess, undercut structure, etc. refers to the width in a direction parallel to the main surface of the substrate.

[0121] In this embodiment, the pixel region isolation portion 11 includes an extension portion ex1 and an undercut structure uc1. A first isolation height H1 is defined by the sum of the thickness of the extension portion ex1 of the second pixel defining layer 112b and the depth of the undercut structure uc1. The undercut structure uc1 may be approximately equal to the thickness of the first pixel defining layer 112a. Therefore, the first isolation height H1 is approximately equal to the sum of the thicknesses of the pixel defining layers 112a and 112b. The inter-pixel isolation portion 12 includes an extension portion ex2 and an undercut structure uc1. A second isolation height H2 is defined by the sum of the thickness of the extension portion ex2 and the depth of the undercut structure uc (i.e., the sum of the depth of the isolation opening and the depth of the recess rc). The depth of the isolation opening may be approximately equal to the sum of the thicknesses of the pixel defining layers 112a and 112b in a direction perpendicular to the main surface of the base substrate. In other words, the second isolation height H2 may be approximately equal to the sum of the thicknesses of the pixel defining layers 112a and 112b and the depth of the recess rc in the planarization structure.

[0122] In some embodiments, as shown in FIG3A and FIG4G , the pixel-defining structure PS includes a plurality of pixel-defining stacked portions, each located between adjacent sub-pixels or to the sides of the sub-pixels and including two opposing sides (e.g., a first side and a second side) in a direction parallel to the main surface of the substrate. The pixel-defining stacked portion may include an extension portion and an undercut structure serving as an isolation structure on at least one of the two sides. For example, opposite sides of the pixel stacked portion located between adjacent sub-pixels may include a sub-pixel opening defining portion and an isolation opening defining portion, respectively, and each serving as at least part of the pixel region isolation portion and the inter-pixel isolation portion of the isolation structure.

[0123] 3A , in some embodiments, the light-emitting stack layer includes a first light-emitting stack portion, a second light-emitting stack portion, a third light-emitting stack portion, and a dummy stack portion; the first light-emitting stack portion, the second light-emitting stack portion, and the third light-emitting stack portion respectively include at least a light-emitting material layer including a charge generation layer for a first sub-pixel, a second sub-pixel, and a third sub-pixel. The dummy stack portion is located between adjacent light-emitting stack portions in the first to third light-emitting stack portions. The first light-emitting stack portion, the second light-emitting stack portion, and the third light-emitting stack portion each include a first stacking sub-portion and a second stacking sub-portion; in each light-emitting stack portion, the first stacking sub-portion is located in a light-emitting area defined by a sub-pixel opening of a pixel defining structure, and the second stacking sub-portion is located on a side of the portion of the pixel defining structure defining the sub-pixel opening away from the base substrate.

[0124] For example, the light-emitting stack layer LE includes light-emitting stack portions LS1, LS2, and LS3, and dummy stack portions DS1 and DS2. The light-emitting stack portions LS1, LS2, and LS3 may be referred to as a first light-emitting stack portion, a second light-emitting stack portion, and a third light-emitting stack portion, respectively; the dummy stack portions DS1 and DS2 may be referred to as a first dummy stack portion and a second dummy stack portion, respectively. The light-emitting stack portion LS1 may include a light-emitting layer 115a, a charge generation layer 116a, and a light-emitting layer 117a stacked in sequence perpendicular to the main surface of the substrate. The light-emitting stack portion LS2 may include a light-emitting layer 115b, a charge generation layer 116b, and a light-emitting layer 117b stacked in sequence perpendicular to the main surface of the substrate. The light-emitting stack portion LS3 may include a light-emitting layer 115c, a charge generation layer 116c, and a light-emitting layer 117c stacked in sequence perpendicular to the main surface of the substrate.

[0125] In some embodiments, the light-emitting stack portion LS1 includes a first stacking sub-portion located in the sub-pixel opening PO1 and a second stacking sub-portion located on a side of the pixel defining structure PS that defines the sub-pixel opening PO1, away from the base substrate. For example, the first stacking sub-portion may include a light-emitting layer 115a1, a charge generation layer 116a1, and a light-emitting layer 117a1; and the second stacking sub-portion may include a light-emitting layer 115a2, a charge generation layer 116a2, and a light-emitting layer 117a2. It should be understood that the corresponding material layers in the various stacking sub-portions of the same light-emitting stack portion are formed by the same formation process, and the portions of the various material layers located in different stacking sub-portions include the same material. For example, in the light-emitting stack portion LS1, the light-emitting layer 115a1, the charge generation layer 116a1, and the light-emitting layer 117a1 are formed by the same process and include the same material as the light-emitting layer 115a2, the charge generation layer 116a2, and the light-emitting layer 117a2, respectively.

[0126] In some embodiments, in the light-emitting stack portion LS1, the charge generation layer 116a1 of the first stack sub-portion and the charge generation layer 116a2 of the second stack sub-portion can be disconnected from each other by the first pixel region isolation portion 11a of the isolation structure IS. For example, the charge generation layer 116a1 and the charge generation layer 116a2 have a step difference in a direction perpendicular to the main surface of the base substrate, and the step difference can be defined by the first isolation height H1 of the first pixel region isolation portion 11a. For example, the step difference can be approximately equal to the first isolation height H1, but the present disclosure is not limited to this. In some embodiments, the light-emitting layer 115a1 and the light-emitting layer 115a2 can be connected or disconnected to each other, and the light-emitting layer 117a1 and the light-emitting layer 117a2 can be connected or disconnected to each other; in some examples, the light-emitting layer 117a1 can be connected to the light-emitting layer 115a1, but the present disclosure is not limited to this.

[0127] In some embodiments, the light-emitting stack portion LS2 includes a first stacking sub-portion located in the sub-pixel opening PO2 and a second stacking sub-portion located on the side of the pixel defining structure PS that defines the sub-pixel opening PO2, away from the base substrate; for example, in the light-emitting stack portion LS2, the first stacking sub-portion may include a light-emitting layer 115b1, a charge generating layer 116b1, and a light-emitting layer 117b1; the second stacking sub-portion may include a light-emitting layer 115b2, a charge generating layer 116b2, and a light-emitting layer 117b2.

[0128] In some embodiments, in the light-emitting stack portion LS2, the layers of the first stacking sub-portion and the second stacking sub-portion may be connected to each other, that is, the layers of the light-emitting stack portion LS2 may be continuous layers; for example, the light-emitting layer 115b1, the charge generation layer 116b1, and the light-emitting layer 117b1 of the first stacking sub-portion may be connected to the light-emitting layer 115b2, the charge generation layer 116b2, and the light-emitting layer 117b2 of the second stacking sub-portion, respectively. In other words, the charge generation layers of the first stacking sub-portion and the second stacking sub-portion in the light-emitting stack portion LS2 are not disconnected by the second pixel region isolation portion 12b. However, the present disclosure is not limited to this. In other embodiments, the charge generation layers of the first stacking sub-portion and the second stacking sub-portion of the light-emitting stack portion LS2 may also be disconnected from each other.

[0129] In some embodiments, the light-emitting stack portion LS3 includes a first stacking sub-portion located in the sub-pixel opening PO3 and a second stacking sub-portion located on the side of the pixel defining structure PS that defines the sub-pixel opening PO3, away from the base substrate; for example, in the light-emitting stack portion LS3, the first stacking sub-portion may include a light-emitting layer 115c1, a charge generation layer 116c1, and a light-emitting layer 117c1; the second stacking sub-portion may include a light-emitting layer 115c2, a charge generation layer 116c2, and a light-emitting layer 117c2.

[0130] In some embodiments, in the light-emitting stack portion LS3, the layers of the first stacking sub-portion and the second stacking sub-portion may be connected to each other, that is, the layers of the light-emitting stack portion LS3 may be continuous layers; for example, the light-emitting layer 115c1, the charge generation layer 116c1, and the light-emitting layer 117c1 of the first stacking sub-portion may be connected to the light-emitting layer 115c2, the charge generation layer 116c2, and the light-emitting layer 117c2 of the second stacking sub-portion, respectively. In other words, the charge generation layers of the first stacking sub-portion and the second stacking sub-portion in the light-emitting stack portion LS3 are not disconnected by the third pixel region isolation portion 12c. However, the present disclosure is not limited to this. In other embodiments, the charge generation layers of the first stacking sub-portion and the second stacking sub-portion of the light-emitting stack portion LS3 may also be disconnected from each other.

[0131] In some embodiments, the first dummy stacking portion is located in a pixel spacing region between a first sub-pixel and an adjacent second or third sub-pixel, and includes a first dummy charge generation layer, which is disconnected from the charge generation layers in the light-emitting stacking portions (e.g., the first light-emitting stacking portion, the second light-emitting stacking portion) of the first sub-pixel and the adjacent sub-pixel by a first inter-pixel isolation portion of the isolation structure.

[0132] For example, the dummy stack portion DS1 may include a dummy light-emitting layer 5b3, a dummy charge generation layer 6b3, and a dummy light-emitting layer 7b3 stacked in sequence perpendicular to the main surface of the base substrate. The dummy stack portion DS1 may be located within the isolation opening 101 of the pixel defining structure PS and the recess of the planarization structure PL, and may contact a portion of the surface of the planarization structure PL. The dummy charge generation layer 6b3 may be disconnected from the charge generation layers in the light-emitting stack portions LS1 and LS2 by the first inter-pixel isolation portion 12a of the isolation structure IS. For example, the dummy charge generation layer 6b3 may have a step difference with the charge generation layer of the light-emitting stack portion LS1 or the light-emitting stack portion LS2 in a direction perpendicular to the main surface of the base substrate, and the step difference may be defined by the isolation height of the first inter-pixel isolation portion 12a (e.g., the second isolation height H2). For example, in this example, the step difference between the dummy charge generation layer 6b3 and the charge generation layer 116b2 in the light-emitting stack portion LS2 may be substantially equal to the second isolation height H2, but the present disclosure is not limited to this.

[0133] In some embodiments, the dummy light-emitting layer 5b3, the dummy charge generation layer 6b3 and the dummy light-emitting layer 7b3 of the dummy stack portion DS1 may respectively have the same materials as the light-emitting layer 115b, the charge generation layer 116b and the light-emitting layer 117b of the light-emitting stack portion LS2, but the present disclosure is not limited thereto.

[0134] Continuing with reference to Figure 3A, in some embodiments, the second dummy stacking portion is located in the pixel spacing area between the second sub-pixel and the third sub-pixel adjacent to each other, and includes a second dummy charge generation layer, and the second dummy charge generation layer and the charge generation layers in the second light-emitting stacking portion and the third light-emitting stacking portion can be disconnected from each other by the second inter-pixel isolation portion of the isolation structure.

[0135] For example, the dummy stack portion DS2 may include a dummy light-emitting layer 5c3, a dummy charge generation layer 6c3, and a dummy light-emitting layer 7c3 stacked in sequence in a direction perpendicular to the main surface of the base substrate. The dummy stack portion DS2 may be located within the isolation opening 102 of the pixel defining structure PS and the recess of the planarization structure PL, and may contact a portion of the surface of the planarization structure PL. The dummy charge generation layer 6c3 may be disconnected from the charge generation layers in the light-emitting stack portions LS2 and LS3 by the second inter-pixel isolation portion 12b of the isolation structure IS. For example, the dummy charge generation layer 6b3 and the charge generation layers of the second stacking sub-section of the light-emitting stack portion LS2 or the light-emitting stack portion LS3 may have a step difference in a direction perpendicular to the main surface of the base substrate, and the step difference may be defined by the isolation height of the second inter-pixel isolation portion 12b (e.g., a second isolation height H2). For example, in this example, the step difference between the dummy charge generation layer 6c3 and the charge generation layer 116c2 in the light-emitting stack portion LS3 may be substantially equal to the second isolation height H2, but the present disclosure is not limited to this.

[0136] In some embodiments, the dummy light-emitting layer 5c3, dummy charge generation layer 6c3, and dummy light-emitting layer 7c3 of the dummy stack portion DS2 may be made of the same material as the light-emitting layer 115c, charge generation layer 116c, and light-emitting layer 117c of the light-emitting stack portion LS3, respectively, but the present disclosure is not limited thereto. In other embodiments, the dummy light-emitting layer and dummy charge generation layer of the dummy stack portion DS2 may also be made of the same material as the corresponding light-emitting layer and charge generation layer of the light-emitting stack portion LS2, respectively, and the step difference between the dummy charge generation layer and the charge generation layer 116b2 in the light-emitting stack portion LS2 may be substantially equal to the second isolation height.

[0137] Continuing with FIG3A , in some embodiments, the light-emitting stacked layer LE may further include a dummy stacking portion DS3. The dummy stacking portion DS3 may be located on a side of the portion of the pixel defining structure PS defining the isolation opening IO1, away from the base substrate, and may include a dummy light-emitting layer 5b4, a dummy charge generation layer 6b4, and a dummy light-emitting layer 7b4 stacked in sequence perpendicular to the main surface of the base substrate. The dummy charge generation layer 6b4 may be disconnected from the dummy charge generation layer 6b3. In some embodiments, the dummy light-emitting layer 5b4, the dummy light-emitting layer 5b3, and the light-emitting layer 115b may be made of the same material; the dummy charge generation layer 6b4, the dummy charge generation layer 6b3, and the charge generation layer 116b may be made of the same material; and the dummy light-emitting layer 7b4, the dummy light-emitting layer 7b3, and the light-emitting layer 117b may be made of the same material, but the present disclosure is not limited thereto. In some embodiments, the step difference between the dummy charge generation layer 6b4 and the dummy charge generation layer 6b3 in the direction perpendicular to the main surface of the substrate can be defined by the second isolation height of the first inter-pixel isolation portion 12a, for example, approximately equal to the second isolation height H2 of the first inter-pixel isolation portion 12a.

[0138] In some embodiments, the dummy stack portion DS3 may be adjacent to a portion of the second stack sub-portion of the light-emitting stack portion LS1, and the charge generation layers of the two may be connected or disconnected. In this example, since the charge generation layers of the first and second stack sub-portions of the light-emitting stack portion LS1 are disconnected from each other, even though the dummy charge generation layer 6b4 of the dummy stack portion DS3 is connected to the charge generation layer 116a2 of the second stack sub-portion, the dummy charge generation layer 6b4 is disconnected from the charge generation layer 116a1 of the first stack sub-portion. Furthermore, since the dummy charge generation layer 6b4, the dummy charge generation layer 6b3, and the charge generation layer 116b2 of the light-emitting stack portion LS2 are disconnected from each other by the inter-pixel isolation portion 12a having the second isolation height, the charge generation layer 116a1 in the light-emitting device of the first sub-pixel SP1 is effectively disconnected from the charge generation layer 116b in the light-emitting device of the second sub-pixel SP2.

[0139] In some embodiments, the display panel 500a further includes a common electrode structure CE, and the second electrodes of multiple sub-pixels share the common electrode structure CE. For example, the common electrode structure CE may include a second electrode layer E2 and an auxiliary electrode layer AE. The second electrode layer E2 is disposed on a side of the light-emitting stack layer LE that is away from the base substrate 100; the auxiliary electrode layer AE is disposed on a side of the second electrode layer E2 that is away from the base substrate 100 and is electrically connected to the second electrode layer E2. In some embodiments, the orthographic projection of the auxiliary electrode layer AE on the base substrate overlaps with the orthographic projection of the isolation structure IS on the base substrate 100. The orthographic projection of the isolation structure IS on the base substrate 100 may be within the orthographic projection of the auxiliary electrode layer AE on the base substrate 100. It should be understood that FIG3A schematically illustrates the common electrode structure CE above the light-emitting stack layer LE, and does not specifically illustrate the morphology of the common electrode structure. In some embodiments, each layer in the common electrode structure CE may have a similar morphology to the underlying structure.

[0140] FIG3B is a schematic cross-sectional view of a display panel 500 a according to some embodiments of the present disclosure, schematically illustrating the appearance of a common electrode structure CE.

[0141] 3A and 3B , in some embodiments, the second electrode layer E2 may include portions disconnected at the isolation structure IS (e.g., the inter-pixel isolation portion 12), and these disconnected portions of the second electrode layer E2 may be electrically connected via the auxiliary electrode layer AE. For example, the second electrode layer E2 may be conformal to the underlying structure (i.e., the light-emitting stack layer LE) and may include a plurality of first electrode portions E21 and one or more second electrode portions E22; the plurality of first electrode portions E21 are respectively located on the light-emitting stack portions of the plurality of sub-pixels, and the second electrode portion E22 is located on the dummy stack portion in the sub-pixel spacing region. In some embodiments, the first electrode portion E21 and the second electrode portion E22 may be disconnected by the inter-pixel isolation portion 12.

[0142] It should be noted that in FIG3A , in order to clearly illustrate the case where the charge generation layer is disconnected, a gap is shown between the light-emitting stacking portion / dummy stacking portion where the charge generation is disconnected, but it should be understood that the adjacent stacking portions in the light-emitting stacking layer will be connected and in contact with each other, or will overlap with each other in a direction perpendicular to the main surface of the substrate, except that the charge generation layers of these stacking portions are disconnected from each other. FIG3B illustrates a case where adjacent stacking portions are connected to each other. As shown in FIG3B , in some embodiments, the dummy stacking portion may be connected to the adjacent light-emitting stacking portion; at each isolation portion, the sidewall of the extension portion of the second pixel defining layer and the surface thereof on the side away from the substrate may be covered by the light-emitting stacking layer; the undercut structure may be surrounded and wrapped by the pixel defining layer, the light-emitting stacking layer, and the material layer located below the pixel defining layer (e.g., the first electrode or the planarization structure), and an air gap may be formed. That is, at least a portion of the undercut structure will not be filled by the light-emitting stacking layer. It should be understood that the air gap may include air or any other type of gas, and the present disclosure is not limited thereto.

[0143] As shown in Figure 3B, in some examples, the second electrode layer E2 may be continuous at the pixel area isolation portion 11 and may be disconnected at the inter-pixel isolation portion 12; for example, a plurality of first electrode portions E21 corresponding to a plurality of sub-pixels SP1, SP2, and SP3 are each disconnected from an adjacent second electrode portion E22, thereby disconnecting adjacent first electrode portions E21 from each other.

[0144] In some embodiments, disconnected portions of the second electrode layer E2 may be electrically connected via the auxiliary electrode layer AE. For example, the auxiliary electrode layer AE may include at least one of a first auxiliary electrode layer AE1 and a second auxiliary electrode layer AE2. The first auxiliary electrode layer AE1 may extend within the pixel region and the inter-pixel region, for example, continuously, or disconnected at an isolation structure. The first auxiliary electrode layer AE1 may contact and be electrically connected to the second electrode layer E2. The orthographic projection of the first auxiliary electrode layer AE1 on the base substrate may overlap or coincide with the orthographic projection of the second electrode layer E2 on the base substrate. In some embodiments, the orthographic projection of the second electrode layer E2 on the base substrate may be within the orthographic projection of the first auxiliary electrode layer AE1 on the base substrate, but the present disclosure is not limited thereto.

[0145] In some embodiments, the first auxiliary electrode layer AE1 may also be disconnected at the isolation structure; for example, the first auxiliary electrode layer AE1 may include a first auxiliary electrode portion AE11 and a second auxiliary electrode portion AE12; the first auxiliary electrode portion AE11 is located on (e.g., directly above) the light-emitting stack portions of the plurality of sub-pixels, and the second auxiliary electrode portion AE12 is located on the dummy stack portion in the isolation opening. In some embodiments, the first auxiliary electrode portion AE11 and the second auxiliary electrode portion AE12 may be disconnected by the inter-pixel isolation portion 12 of the isolation structure IS, but the present disclosure is not limited thereto. In other embodiments, the first auxiliary electrode portion AE11 and the second auxiliary electrode portion AE12 may not be disconnected by the isolation structure, but may be continuous with each other.

[0146] As shown in Figure 3B, in some embodiments, the second auxiliary electrode portion AE12 covers the second electrode portion E22, and contacts and is electrically connected to the adjacent first electrode portion E21, and the first electrode portion E21 contacts and is electrically connected to the first auxiliary electrode portion AE11; therefore, the multiple first electrode portions E21 and the second electrode portions E22 of the second electrode layer E2 that are disconnected by the isolation structure can be electrically connected through the second auxiliary electrode portion AE12; the first auxiliary electrode portion AE11 and the second auxiliary electrode portion AE12 that are disconnected by the isolation structure can be electrically connected through the first electrode portion E21 of the second electrode layer E2.

[0147] Continuing with reference to FIG3B , when the auxiliary electrode layer AE includes both a first auxiliary electrode layer AE1 and a second auxiliary electrode layer AE2, the second auxiliary electrode layer AE2 may be disposed on a side of the first auxiliary electrode layer AE1 away from the base substrate 100. In some embodiments, the orthographic projection of the second auxiliary electrode layer AE2 on the base substrate may overlap with the orthographic projection of at least part or all of the isolation structure IS on the base substrate 100, and may be offset from the orthographic projection of at least part of the light-emitting regions (i.e., sub-pixel openings) of the plurality of sub-pixels on the base substrate. FIG2G illustrates a schematic plan view of the second auxiliary electrode layer AE2, the plurality of sub-pixels, and the isolation structure. Referring to FIG3B and FIG2G , in some embodiments, the orthographic projection of at least part or all of the isolation structure IS on the base substrate is located within the orthographic projection of the second auxiliary electrode layer AE2 on the base substrate.

[0148] For example, an electrode selection layer 119 is provided on portions of the second electrode layer E21 and the first auxiliary electrode portion AE11 located in the light-emitting region. The electrode selection layer 119 is a material used for selective deposition of electrode material during the electrode formation process, making it difficult for auxiliary electrode material to form in the region having the electrode selection layer 119. The common electrode structure may be a cathode of the light-emitting device, and the electrode selection layer 119 may be a cathode patterning material (CPM). That is, it is difficult for cathode material to form in the region where the cathode selection layer is located.

[0149] For example, the electrode selection layer 119 is provided at a position corresponding to the light-emitting area of ​​the plurality of sub-pixels; the orthographic projection of the electrode selection layer 119 on the base substrate may overlap with the orthographic projection of the plurality of sub-pixel openings on the base substrate. For example, the orthographic projection of the plurality of sub-pixel openings on the base substrate may be located within the orthographic projection of the electrode selection layer 119 on the base substrate. The second auxiliary electrode layer AE2 is formed in an area outside the electrode selection layer 119 and may cover the second auxiliary electrode portion AE12 and a portion of the first auxiliary electrode portion AE11 adjacent thereto. In a case where the first auxiliary electrode portion AE11 and the second auxiliary electrode portion AE12 of the first auxiliary electrode layer AE1 are disconnected by an isolation structure, the first auxiliary electrode portion AE11 and the second auxiliary electrode portion AE12 may be electrically connected to each other through the second auxiliary electrode layer AE12, and the first electrode portion E21 and the second electrode portion E22 of the second electrode layer E2, which are disconnected from each other, may also be electrically connected through the first auxiliary electrode layer AE1 and the second auxiliary electrode layer AE2.

[0150] In some embodiments, providing a second auxiliary electrode layer AE2 can further ensure that the disconnected portions of the second electrode layer E2 are electrically connected to each other via the auxiliary electrode layer. Furthermore, the second auxiliary electrode layer AE2 is provided in an area outside the cathode selection layer 119 corresponding to the light-emitting area to avoid reducing light transmittance. In some embodiments, only the second auxiliary electrode layer AE2 can be provided, while the first auxiliary electrode layer AE1 can be omitted. That is, the auxiliary electrode layer AE can be provided at least in the area corresponding to the isolation structure, and the orthographic projection of at least the portion of the second electrode layer E2 disconnected by the isolation structure IS on the base substrate 100 is within the orthographic projection of the auxiliary electrode layer AE on the base substrate 100. In some embodiments, because the second electrode layer E2 is easily disconnected at an isolation portion having a higher second isolation height, the second auxiliary electrode layer AE2 can be provided opposite the isolation portion having the second isolation height, so that the disconnected portions of the second electrode layer E2 can be electrically connected via the auxiliary electrode layer.

[0151] It should be understood that the morphology of the second electrode layer E2 shown in Figure 3B and its disconnection at the isolation portion, as well as the morphology of each layer in the common electrode structure, and the setting of the auxiliary electrode layer AE can be set according to the disconnection of the second electrode layer E2 in actual applications to ensure that the disconnected portion of the second electrode layer E2 can be connected through the auxiliary electrode layer AE.

[0152] In the embodiments of the present disclosure, the provision of an auxiliary electrode layer further prevents disconnection of the second electrodes (e.g., cathodes) of the light-emitting devices of multiple sub-pixels, thereby avoiding the increase in resistance caused by the disconnection of the second electrodes and the resulting poor brightness uniformity and high device power consumption. In other words, the embodiments of the present disclosure, through the provision of the isolation structure and / or the auxiliary electrode layer, ensure that the second electrodes of the light-emitting devices of multiple sub-pixels are connected to each other and can form a continuous structure, thereby improving the brightness uniformity of the display panel and reducing device power consumption.

[0153] Referring to FIG. 3A , in some embodiments, the display panel 500a may further include an encapsulation layer 120. The encapsulation layer 120 is disposed on a side of the common electrode structure CE away from the base substrate to protect the light-emitting devices of the multiple sub-pixels. For example, the encapsulation layer 120 can prevent external water and oxygen molecules from corroding the light-emitting devices of the display panel, thereby extending the service life of the light-emitting devices and the display panel.

[0154] 4A to 4G are schematic cross-sectional views illustrating intermediate structures in various steps of a method for manufacturing a display panel according to some embodiments of the present disclosure.

[0155] Referring to FIG4A , in some embodiments, a base substrate 100 is provided, and a buffer layer 101 is formed on the base substrate 100 ; a pixel circuit layer CL is formed on a side of the buffer layer 101 away from the base substrate 100 . The pixel circuit layer CL may include sub-pixel circuits for multiple sub-pixels and may include multiple thin-film transistors and capacitors. For example, the pixel circuit layer CL may include an active material layer 103, a dielectric layer 105, a conductive layer 106, a dielectric layer 107, a conductive layer 108, a dielectric layer 109, and a conductive layer 110 stacked in sequence. The multiple thin-film transistors in the multiple sub-pixel circuits may each include an active layer AL, a first gate G1, a second gate G2, a source electrode S, and a drain electrode D. The active layer AL, the first gate G1, and the second gate G2 of the multiple thin-film transistors may be disposed on the active material layer 103, the conductive layer 106, and the conductive layer 108, respectively. The source electrode S and the drain electrode D of the multiple thin-film transistors may be disposed on the conductive layer 110. Dielectric layer 105 is disposed between conductive layer 106 and active material layer 103 and can serve as a gate dielectric layer for multiple thin film transistors. Dielectric layer 107 is located between conductive layer 106 and conductive layer 108 and can serve as an inter-gate dielectric layer for multiple thin film transistors. Dielectric layer 109 can be disposed between conductive layer 108 and conductive layer 110, with source electrode S and drain electrode D extending through dielectric layers 109, 107, and 105, respectively, and connected to the corresponding active layer AL. For example, dielectric layers 109, 107, and 105 may have vias therein, and source electrode S and drain electrode D may be connected to active layer AL through the vias. In some embodiments, electrode plates of capacitors of multiple sub-pixel circuits may be disposed in two or more of active material layer AL, conductive layer 106, conductive layer 108, and conductive layer 110.

[0156] It should be noted that the figure schematically shows only one thin film transistor in each sub-pixel circuit, but it should be understood that each sub-pixel circuit can adopt any appropriate circuit structure according to product design and requirements, for example, it can be a 2T1C, 3T1C, 6T1C, 7T1C, 8T1C, 10T1C, 6T2C, 7T2C, 8T2C, 10T2C pixel circuit. In addition, each thin film transistor in the sub-pixel circuit can be an amorphous silicon thin film transistor, a low temperature polysilicon (LTPS) thin film transistor, or an oxide thin film transistor. The pixel circuit structure of each sub-pixel and the type of each thin film transistor can be set and adjusted according to product design and requirements, and the present disclosure is not limited thereto.

[0157] Continuing with FIG. 4A , after forming the pixel circuit layer CL, a planarization structure PL may be formed on a side of the pixel circuit layer CL remote from the base substrate 100. For example, forming the planarization structure PL includes forming a planarization layer 111 on a side of the dielectric layer 109 remote from the base substrate 100. The planarization layer 111 covers the sidewalls of the conductive layer 110 and its surface remote from the base substrate. The planarization structure PL has a flat surface on the side remote from the base substrate 100, allowing subsequent light-emitting devices to be formed on the flat surface, thereby improving the uniformity of light emitted by the light-emitting devices.

[0158] In some embodiments, a patterning process is performed on the planarization structure PL to form a plurality of via holes in the planarization structure PL. Each via hole extends through the planarization structure PL and exposes a corresponding component of the sub-pixel circuit, for example, the source electrode S or the drain electrode D of the thin film transistor. The patterning process may include photolithography and etching processes.

[0159] Referring to FIG4B , a first electrode layer is formed on the planarization structure PL. The first electrode layer may include a plurality of first electrodes E1 for each sub-pixel. Each first electrode E1 is formed on a side of the planarization structure PL away from the base substrate 100 and connected to the source electrode S or drain electrode D of a corresponding thin-film transistor via a via. The plurality of first electrodes E1 may be formed using a deposition process such as sputtering and a patterning process. For example, after forming a plurality of vias in the planarization structure PL, a first electrode material layer may be formed on the planarization structure PL using a deposition process such as sputtering. The first electrode material layer extends continuously along the side of the planarization structure PL away from the base substrate and fills the plurality of vias to electrically connect to the corresponding components of the sub-pixel circuit. The first electrode material layer may be a single layer or a multilayer structure, for example, a multilayer structure including an ITO / Ag / ITO stack. In some examples, the thicknesses of the ITO / Ag / ITO layers may be 80 angstroms, 1000 angstroms, or 120 angstroms, respectively, but the present disclosure is not limited thereto. Next, a patterning process may be performed on the first electrode material layer to form a plurality of first electrodes E1 ; the patterning process may include photolithography and etching processes.

[0160] Next, a pixel defining structure PS and an isolation structure IS are formed on a side of the planarization structure PL and the first electrode E1 that is away from the substrate 100. For example, forming the pixel defining structure PS and the isolation structure IS may include: sequentially forming a first pixel defining layer and a second pixel defining layer on one side of the planarization structure; performing a first removal process to remove a portion of the second pixel defining layer and forming an opening in the second pixel defining layer, the opening being defined by an extension of the second pixel defining layer and exposing a portion of the surface of the first pixel defining layer; and performing a second removal process to remove the portion of the first pixel defining layer exposed by the opening and the portion covered by the extension of the second pixel defining layer, and forming an undercut structure on a side of the extension that is closer to the substrate, the isolation structure including the extension and the undercut structure. In some embodiments, after the second removal process, an isolation opening is formed in the pixel defining layer that exposes a portion of the surface of the planarization structure. The manufacturing method may further include performing a third removal process to remove the portion of the planarization structure exposed by the isolation opening and form a recess in the planarization structure.

[0161] Referring to FIG. 4C , for example, a first pixel defining layer 112a is formed on the side of the planarization structure PL and the first electrode E1 that is away from the substrate 100, and a second pixel defining layer 112b is formed on the side of the first pixel defining layer 112a that is away from the substrate 100. The first pixel defining layer 112a and the second pixel defining layer 112b can comprise different materials and have a high etch selectivity in a subsequent etching process. For example, at least one of the first pixel defining layer 112a and the second pixel defining layer 112b can comprise an inorganic material, such as an inorganic insulating material. In some embodiments, each pixel defining layer can be selected from inorganic materials such as SiO, SiN, SiON, and SiCN; metal oxides such as Al2O3, NbO, Nb2O5, IGZO, and TiO; and organic adhesives.

[0162] For example, one of the first pixel defining layer 112a and the second pixel defining layer 112b includes a first inorganic insulating material, and the other includes a second inorganic insulating material or an organic insulating material. For example, in some examples, one of the first pixel defining layer 112a and the second pixel defining layer 112b includes aluminum oxide (Al2O3), and the other includes silicon nitride (SiN) or silicon oxide (SiO); or one of the first pixel defining layer 112a and the second pixel defining layer 112b includes silicon oxide, and the other includes silicon carbonitride (SiCN); or one of the first pixel defining layer 112a and the second pixel defining layer 112b includes titanium oxide (TiO), and the other includes niobium oxide (Nb2O5).

[0163] Referring to FIG4D , a mask layer 113 is formed on a side of the first pixel defining layer 112a and the second pixel defining layer 112b away from the base substrate 100 to cover portions of the pixel defining layers. The mask layer 113 may include a patterned photoresist layer and have a first mask opening 113a and a second mask opening 113b. The first mask opening 113a and the second mask opening 113b may be used to form sub-pixel openings and isolation openings in the pixel defining layers, respectively. For example, the plurality of first mask openings 113a may expose portions of the pixel defining layer directly above the plurality of first electrodes E1; the second mask opening 113b may expose portions of the pixel defining layer located between adjacent first electrodes.

[0164] Referring to Figures 4D and 4E, a first removal process is performed to remove portions of the second pixel defining layer 112b and form openings in the second pixel defining layer 112b. The first removal process may include using the mask layer 113 as an etching mask to perform an etching process on the second pixel defining layer 112b to remove portions of the second pixel defining layer 112b exposed by the multiple mask openings of the mask layer 113, and to form multiple openings b01 and b02 in the second pixel defining layer 112b. The positions of the openings b01 and b02 correspond to the positions of the first mask opening 113a and the second mask opening 113b, respectively, and each exposes a portion of the surface of the first pixel defining layer 112a away from the substrate. The portions of the second pixel defining layer 112b that define the openings b01 and b02 are extensions thereof.

[0165] Referring to FIG. 4F , in some embodiments, a second removal process is performed to remove portions of the first pixel defining layer 112a. For example, the second removal process may include etching the first pixel defining layer 112a using the mask layer 113 and the patterned second pixel defining layer 112b as etching masks. The etching process removes portions of the first pixel defining layer 112a exposed by the plurality of mask openings and the plurality of openings b01 and b02 of the second pixel defining layer, and removes portions of the first pixel defining layer 112a covered by the extensions of the second pixel defining layer 112b. This forms a plurality of openings a01 and a02 in the first pixel defining layer 112a, each of which includes an undercut structure located beneath the extensions of the second pixel defining layer. Each opening a01 is spatially connected to a corresponding opening b01 and together constitutes a sub-pixel opening of the pixel defining structure, and may be referred to as a first sub-opening and a second sub-opening of the sub-pixel opening, respectively. Each opening a02 is spatially connected to a corresponding opening b02 and together constitutes an isolation opening of the pixel defining structure, and may be referred to as a first sub-opening and a second sub-opening of the isolation opening, respectively.

[0166] In some embodiments, after removing these portions of the second pixel defining layer 112a, each sub-pixel opening exposes a portion of the surface of the first electrode E1, and each isolation opening exposes a portion of the surface of the planarization structure PL. In some embodiments, a third removal process may be further performed to remove the portions of the planarization structure PL exposed by the isolation openings, thereby forming recesses rc in the planarization structure PL. The recesses rc are spatially connected to the corresponding isolation openings, and each recess rc may have substantially the same width as the corresponding opening a02 in the first pixel defining layer 112a, or may also have substantially the same width as the opening b02.

[0167] In some embodiments, the first, second, and third removal processes may be etching processes using one or more etching gases or etchants, and in the etching process for the first pixel defining layer and the planarization structure, the etching process has a high etching selectivity between the first pixel defining layer / planarization structure and the second pixel defining layer; that is, the etching rate for the first pixel defining layer and the planarization structure may be greater than the etching rate for the second pixel defining layer, so that during the etching process, the first pixel defining layer and the planarization structure may be retracted relative to the edge of the second pixel defining layer to form an undercut structure. However, the present disclosure is not limited to this.

[0168] 4F and 4G , the mask layer 113 is removed, thereby completing the fabrication of the pixel defining structure PS, wherein portions of the pixel defining structure PS defining the openings serve as isolation structures IS.

[0169] Referring to Figure 4G and Figures 3A and 3B, after forming the pixel-defining structure PS and the isolation structure IS, a light-emitting stack layer can be formed on the side of the pixel-defining structure PS away from the base substrate using multiple deposition processes, such as evaporation. For example, a first evaporation process, a second evaporation process, and a third evaporation process can be used to form the light-emitting stack portion LS1, the light-emitting stack portion LS2, and the light-emitting stack portion LS3, respectively. The deposition area of ​​each evaporation process covers at least the corresponding sub-pixel area and may also cover the adjacent sub-pixel spacing area. A dummy stack portion can be formed in the same evaporation process as one of the adjacent light-emitting stack portions. For example, the second evaporation process can also form dummy stack portions DS1 and DS3, and the third evaporation process can also form dummy stack portion DS2. In other words, the layers of dummy stack portions DS1, DS3, and the light-emitting stack portion LS2 can be formed from the same material; and the layers of dummy stack portion DS2 and the light-emitting stack portion LS3 can also be formed from the same material.

[0170] 3A and 3B , a common electrode structure CE is formed on one side of the light-emitting stack layer LE. For example, forming the common electrode structure CE may include: forming a second electrode layer E2 on the side of the light-emitting stack layer LE remote from the substrate 100; forming a first auxiliary electrode layer AE1 on the side of the second electrode layer E2 remote from the substrate 100; forming an electrode selection layer 119 on the side of the first auxiliary electrode layer AE1 remote from the substrate 100. The electrode selection layer 119 may be formed in a region corresponding to the light-emitting region of each sub-pixel; then, forming a second auxiliary electrode layer AE2 on the side of the first auxiliary electrode layer AE1 remote from the substrate 100. Because the electrode selection layer 119 is provided in the regions corresponding to the light-emitting regions of each sub-pixel, the electrode material of the second auxiliary electrode layer is not formed in these regions. Instead, it is formed in regions of the first auxiliary electrode layer AE1 not provided with the electrode selection layer 119. Subsequently, an encapsulation process may be performed to form an encapsulation layer 120 on the side of the common electrode structure CE remote from the substrate to protect the light-emitting devices of the multiple sub-pixels.

[0171] FIG5 shows a schematic cross-sectional view of a display panel 500b according to other embodiments of the present disclosure. FIG6D shows a schematic cross-sectional view of a portion of the display panel 500b, including a pixel defining structure. The display panel 500b is similar to the display panel 500a, with the difference that: in the display panel 500b, the inter-pixel isolation portions of the isolation structure located in different pixel spacing regions may have different isolation heights; and the planarization structure PL may be a multi-layer structure. The following will specifically describe the features of the display panel 500b that are different from the display panel 500a. The features of the display panel 500b that are similar to the aforementioned embodiments can be referred to the above description of the display panel 500a and will not be repeated below.

[0172] Referring to FIG. 5 , in some embodiments, the planarization structure PL may be a multilayer structure and, for example, may include a planarization layer 111a, a buffer layer 111b, and a passivation layer 111c. The materials of the planarization layer 111a, the buffer layer 111b, and the passivation layer 111c may be different from one another. The buffer layer 111b and the passivation layer 111c may be made of a material having a high etch selectivity in an etching process. For example, the passivation layer 111c may be made of one of SiO, SiN, SiON, and Al2O3. In one example, the passivation layer 111c includes Al2O3, and the buffer layer 111b includes SiO, but the present disclosure is not limited thereto.

[0173] The pixel defining structure PS may include a first pixel defining layer 112a and a second pixel defining layer 112b and may have a plurality of sub-pixel openings PO1, PO2, PO3 and isolation openings IO1, IO2. The structure of each opening of the pixel defining structure PS is similar to that of the previous embodiment and will not be repeated here.

[0174] In some embodiments, the pixel defining structure PS has a sub-pixel opening defining portion P1 that defines the sub-pixel opening and an isolation opening defining portion P2 that defines the isolation opening; each sub-pixel opening defining portion includes a first extension portion ex1 of the second pixel defining layer 112b, and has a first undercut structure uc1 between the first extension portion ex1 and the first electrode E1, and the first undercut structure uc1 is defined by the surfaces of the first extension portion ex1 and the first electrode E1 relative to each other and the side walls of the first pixel defining layer 112a.

[0175] In some embodiments, the plurality of isolation opening defining portions P2 include isolation opening defining portions P2a and P2b. Isolation opening defining portions P2a and P2b respectively define isolation opening IO1 located between adjacent sub-pixels P1 and P2, and isolation opening IO2 located between adjacent sub-pixels P2 and P3. Isolation opening defining portion P2a has an extension ex3 and an undercut structure uc3 between the extension ex3 and the passivation layer 111c of the planarization structure PL. Isolation opening defining portion P2b has an extension ex2 and an undercut structure uc3 between the extension ex2 and the passivation layer 111c of the planarization structure PL.

[0176] In some embodiments, the planarization structure PL may have a recess at a location corresponding to a portion of the isolation opening, while not having a recess at a location corresponding to another portion of the isolation opening. The recess may be formed in the passivation layer. For example, the planarization structure PL may have a recess rc, which may be located in the passivation layer 111c and spatially connected to the isolation opening 102. In some embodiments, the width of the recess rc may be less than the width of the first sub-opening in the isolation opening 102 (i.e., the corresponding opening width in the first pixel defining layer 112a) and may be approximately equal to the width of the second sub-opening in the isolation opening 102 (i.e., the corresponding opening width in the second pixel defining layer 112b). For example, the orthographic projection of the recess rc on the substrate overlaps with the orthographic projection of the isolation opening 102 on the substrate and may be located within the orthographic projection of the isolation opening 102 on the substrate. For example, the orthographic projection of the recess rc on the substrate may substantially coincide with the orthographic projection of the second sub-opening of the isolation opening 102 on the substrate, and the orthographic projections of the recess rc and the second sub-opening on the substrate may be located within the orthographic projection of the first sub-opening on the substrate.

[0177] In some embodiments, the recess rc can be referred to as a passivation opening of the passivation layer 111c, and the portion of the passivation layer 111c defining the passivation opening protrudes from the portion of the first pixel-defining layer 112a defining the isolation opening in a direction parallel to the main surface of the substrate, and can also be referred to as a passivation extension. That is, the undercut structure uc2 can be located between the extension ex2 of the second pixel-defining layer 112b and the passivation extension of the passivation layer 111c in a direction perpendicular to the main surface of the substrate, and can be defined by the opposing surfaces of the extension ex2 and the passivation extension, as well as the sidewalls of the first pixel-defining layer 112a. In some embodiments, the isolation opening 102 and the recess rc (i.e., the passivation opening) expose a portion of the surface of the buffer layer 111b on the side away from the substrate.

[0178] In some embodiments, the planarization structure PL may not have a recess at the position corresponding to the isolation opening IO1, that is, the isolation opening IO1 may expose a portion of the surface of the passivation layer 111c away from the substrate, and the buffer layer 111b is covered by the passivation layer 111c and will not be exposed by the isolation opening IO1.

[0179] Continuing with reference to Figures 5 and 6D, in some embodiments, the isolation structure IS may include portions of the pixel defining structure PS and portions of the planarization structure PL; for example, the isolation structure IS may include multiple pixel region isolation portions 11 and multiple inter-pixel isolation portions 12. Each of the multiple pixel region isolation portions 11 may include an extension ex1 of the second pixel defining layer 112b and an undercut structure uc1 located between the extension ex1 and the first electrode E1. In some embodiments, the multiple pixel region isolation portions 11 may have the same first isolation height H1, which may be defined by the sum of the thickness of the extension of the second pixel defining layer 112b and the height of the undercut structure uc1; the height of the undercut structure uc1 may be approximately equal to the thickness of the first pixel defining layer 112a. In other words, the first isolation height H1 may be approximately equal to the sum of the thicknesses of the second pixel defining layer 112b and the first pixel defining layer 112a.

[0180] In some embodiments, the plurality of inter-pixel isolation portions 12 may include a first inter-pixel isolation portion 12a and a second inter-pixel isolation portion opening 12b. For example, the first inter-pixel isolation portion 12a may include an extension portion ex3 of the second pixel defining layer 112b and an undercut structure uc3 between the extension portion ex3 and the passivation layer 111c. The second inter-pixel isolation portion 12b may include an extension portion ex2 of the second pixel defining layer 112b, an undercut structure uc2 between the extension portion ex2 and the planarization structure, and a recessed portion of the planarization structure PL (e.g., a passivation extension portion of the passivation layer 111c). In some embodiments, the first inter-pixel isolation portion 12a may be located between adjacent first and second sub-pixels or between adjacent first and third sub-pixels. The second inter-pixel isolation portion 12b may be located between adjacent second and third sub-pixels.

[0181] The first inter-pixel isolation portion 12a and the second inter-pixel isolation portion 12b may have different isolation heights. In this embodiment, the first inter-pixel isolation portion 12a may have a first isolation height H1, which is defined by the depth of the isolation opening 101, i.e., the sum of the thickness of the extension of the second pixel defining layer 112b and the height of the undercut structure uc3. The height of the undercut structure uc3 may be approximately equal to the thickness of the first pixel defining layer 112a. For example, the first isolation height H1 may be approximately equal to the sum of the thicknesses of the first and second pixel defining layers 112a, 112b. The second inter-pixel isolation portion 12b may have a second isolation height H2, which is defined by the sum of the depth of the isolation opening 102 and the depth of the recess rc. The depth of the isolation opening 102 is approximately equal to the sum of the thicknesses of the second pixel defining layer 112b and the first pixel defining layer 112a. The depth of the recess rc may be approximately equal to the thickness of the passivation layer 111c. For example, the second isolation height H2 may be substantially equal to the sum of the thicknesses of the first pixel defining layer 112a, the second pixel defining layer 112b, and the passivation layer 111c. However, the present disclosure is not limited thereto. In other embodiments, the depth of the recess in the planarization structure may be greater than the thickness of the passivation layer, and a multi-layered planarization structure may be used to facilitate control of the recess depth.

[0182] Referring to FIG. 5 , in some embodiments, the light-emitting stack layer LE includes light-emitting stack sections LS1, LS2, and LS3, and dummy stack sections DS1 and DS2. In this embodiment, the positions of the light-emitting stack sections LS2, LS3, and dummy stack section DS2, as well as the material layers and other related features, are similar to those of the display panel 500a and are not further described here. The charge generation layers in the light-emitting stack sections LS2 and LS3 and the dummy charge generation layer 6c3 in the dummy stack section DS2 are disconnected from each other by an inter-pixel isolation portion 12b.

[0183] Similar to the aforementioned embodiment, in the light-emitting stack portion LS1, the charge generation layer 116a1 of the first stack sub-portion and the charge generation layer 116a2 of the second stack sub-portion located in the sub-pixel opening PO1 are disconnected from each other by the pixel region isolation portion 11a. In some embodiments, the dummy stack portion DS1 is located in the isolation opening IO1 of the pixel defining structure PS and includes a dummy light-emitting layer 5a3, a dummy charge generation layer 6a3, and a dummy light-emitting layer 7a3 stacked in sequence in a direction perpendicular to the main surface of the base substrate.

[0184] The dummy charge layer 6a3 in the dummy stack portion DS1 and the charge generation layers 116a2 and 116b2 in the light-emitting stack portions LS1 and LS2 can be disconnected from each other by an inter-pixel isolation portion 12a having a first isolation height H1. In some embodiments, the dummy light-emitting layer 5a3, the dummy charge generation layer 6a3, and the dummy light-emitting layer 7a3 in the dummy stack portion DS1 are made of the same material as the light-emitting layer 115a, the charge generation layer 116a, and the light-emitting layer 117a of the light-emitting stack layer LS1, respectively. Furthermore, each material layer in the dummy stack portion DS1 can be formed in the same formation process (e.g., an evaporation process) as the corresponding material layers in the light-emitting stack layer LS1.

[0185] In this example, the second stacking sub-portion of the light-emitting stacking portion LS1 may extend continuously from the sub-pixel opening defining portion defining the sub-pixel opening PO1 of the pixel defining structure LS to the isolation opening defining portion defining the isolation opening IO1, and other dummy stacking portions adjacent to the second stacking sub-portion and including different materials may not be provided on the side of the pixel defining structure away from the base substrate, for example, a third dummy stacking portion DS3 similar to that in the display panel 500a may not be provided.

[0186] Continuing with reference to Figure 5, in some embodiments, the step difference between the dummy charge generation layer 6a3 of the dummy stack portion DS1 and the charge generation layer 116a2 of the second stack sub-portion of the light-emitting stack portion LS1 in a direction perpendicular to the main surface of the substrate may be defined by the isolation height (e.g., the first isolation height H1) of the inter-pixel isolation portion 12a; for example, the step difference between the dummy charge generation layer 6a3 and the charge generation layer 116a2 may be approximately equal to the first isolation height H1, but the present disclosure is not limited to this.

[0187] In this embodiment, because the various material layers of the dummy stack portion DS1 and the various material layers of the light-emitting stack portion LS1 are made of the same material, the thicknesses of the dummy light-emitting layer and the light-emitting layer in the light-emitting stack portion are both relatively small. Therefore, the inter-pixel isolation portion 12a can have a relatively small first isolation height H1 to disconnect the charge generation layers of the first sub-pixel and the adjacent sub-pixel. Furthermore, the use of a small isolation height reduces the likelihood of disconnection between the second electrodes located on the light-emitting stack portion LS1 and the dummy stack portion DS1, thereby avoiding or reducing poor brightness uniformity and high power consumption of the light-emitting device module caused by voltage drop due to disconnection of the second electrodes.

[0188] The common electrode structure CE and the encapsulation layer 120 are disposed on a side of the light-emitting stack LE that is away from the base substrate. Similar to the display panel 500a, the common electrode structure CE includes a second electrode layer E2 and an auxiliary electrode layer CE. In some examples, the second electrode layer E2 may be disconnected at one or more isolation portions of the isolation structure (e.g., the second inter-pixel isolation portion 12b), and the disconnected portions of the second electrode layer E2 may be electrically connected via the auxiliary electrode layer. The features and specific morphology of the common electrode structure CE are similar to those described for the display panel 500a in the above embodiment and are not further described here.

[0189] Figures 6A to 6D illustrate schematic cross-sectional views of intermediate structures of various steps in a method for manufacturing a display panel 500b according to some embodiments of the present disclosure. The following details the differences between the manufacturing method and the aforementioned embodiments. Similar steps and / or processes to those of the aforementioned embodiments can be found in the aforementioned description and will not be further elaborated upon.

[0190] 6A , in some embodiments, after forming a pixel circuit layer CL on a base substrate 100, a planarization structure PL is formed on a side of the pixel circuit layer CL away from the base substrate; in some embodiments, forming the planarization structure PL may include sequentially forming a planarization layer 111a, a buffer layer 111b, and a passivation layer 111c on the pixel circuit layer CL through a deposition process; thereafter, a plurality of vias are formed in the planarization structure PL, each via extending through the passivation layer 111c, the buffer layer 111b, and the planarization layer 111a to expose corresponding components in the sub-pixel circuit, such as a source electrode or a drain electrode of a thin film transistor.

[0191] A plurality of first electrodes E1 are formed on the planarization structure PL; each first electrode E1 is formed on a side of the passivation layer 111 c in the planarization structure PL away from the base substrate, and is connected to a corresponding sub-pixel circuit through a via hole.

[0192] Referring to Figures 6A to 6D , a pixel-defining structure PS is formed on the side of the planarization structure PL and the first electrode E1 facing away from the substrate. For example, forming the pixel-defining structure PS may include forming a first pixel-defining layer 112a on the passivation layer 111c to cover the sidewalls of the first electrode E1 and its surface facing away from the substrate; forming a second pixel-defining layer 112b on the side of the first pixel-defining layer 112a facing away from the substrate; and patterning the second pixel-defining layer 112b and the first pixel-defining layer 112a to form a plurality of sub-pixel openings and isolation openings in the pixel-defining structure. For example, the patterning may include forming a mask layer 113 including a plurality of first mask openings 113a and a second mask opening 113b on the side of the second pixel-defining layer 112b facing away from the substrate; and then etching the pixel-defining structure using the mask layer 113 as an etch mask to remove portions of the second pixel-defining layer 112b and the first pixel-defining layer 112a.

[0193] 6A and 6B , in some embodiments, a first removal process is performed to remove portions of the second pixel defining layer 112b exposed by the mask layer 113, and a plurality of openings b01 and b02 are formed in the second pixel defining layer 112b, wherein the plurality of openings b01 and b02 respectively expose portions of the surface of the first pixel defining layer 112b; and a second removal process is performed to remove portions of the first pixel defining layer 112a exposed by the plurality of openings b01 and b02 and portions covered by extensions of the second pixel defining layer 112b, and a plurality of openings a01 and a02 are formed in the first pixel defining layer 112a, wherein the openings a01 and a02 each include an undercut structure located below the corresponding extensions of the second pixel defining layer 112b.

[0194] 6B and 6C , in some embodiments, after forming a plurality of sub-pixel openings and isolation openings in the pixel defining structure PS, a third removal process may be further performed to remove portions of the planarization structure PL exposed by the partial isolation openings and form a recess rc in the planarization structure PL. For example, the third removal process may include removing portions of the passivation layer 111c exposed by the partial isolation openings by etching, and forming a passivation opening in the passivation layer 111c, wherein the passivation opening constitutes the recess rc of the planarization structure PL. In some embodiments, during the third removal process, portions of the passivation layer 111c exposed by another partial isolation opening are covered by a mask layer and are not removed. For example, the third removal process may remove portions of the passivation layer 111c exposed by the isolation opening 102, while the isolation opening 101 may be covered by the mask layer. As a result, the portions of the passivation layer 111c exposed by the isolation opening 101 are covered by the mask layer and are not removed during the third removal process.

[0195] For example, before performing the third removal process, a mask layer 114 may be formed on a side of the pixel defining structure PS away from the base substrate. The mask layer 114 covers the pixel defining structure PS and fills the isolation opening 101 to cover the passivation layer 111c exposed by the isolation opening 101. Forming the mask layer 114 may include filling a mask material into the mask opening 113b of the mask layer 113 corresponding to the isolation opening 101. In this example, the mask layer 114 still has mask openings that expose the light-emitting areas of each sub-pixel. Alternatively, the mask layer 113 may be removed first and then the mask layer 114 may be formed. In these examples, the mask layer 114 may only have mask openings corresponding to the isolation opening 102, and may not have mask openings at positions corresponding to the pixel openings and other isolation openings.

[0196] In some embodiments, the second removal process may include an isotropic etching process, and the etching process has a high etching selectivity for the first pixel defining layer 112b and the second pixel defining layer 112a, and may also have a high etching selectivity for the first pixel defining layer 112b and the passivation layer 111c; the third removal process may include anisotropic etching, and the buffer layer 111b and / or the first electrode E1 may serve as an etching stop layer for the etching process.

[0197] Referring to Figures 6C, 6D, and 5, mask layer 114 is removed, and components such as a light-emitting stack layer, a common electrode structure, and an encapsulation layer can then be formed on the side of the pixel defining structure PS away from the base substrate, thereby forming display panel 500b. The subsequent processes are similar to those of the aforementioned embodiment, with the difference that when forming the light-emitting stack layer, the evaporation area of ​​the first evaporation process used to form the light-emitting stack portion LS1 can also cover a portion of the first pixel spacing region R2a, allowing the first evaporation process to simultaneously form the light-emitting stack portion LS1 and the dummy stack portion DS1. In other words, the various material layers in the light-emitting stack portion LS1 and the dummy stack portion DS1 can be formed using the same material through the same evaporation process.

[0198] Figure 7 shows a schematic cross-sectional view of a display panel 500c according to further embodiments of the present disclosure. Figure 8C shows a schematic cross-sectional view of portions of the display panel 500c, including a pixel definition structure. Display panel 500c is similar to display panel 500b in the aforementioned embodiment, except that it further includes dummy electrodes. The differences between display panel 500c and the aforementioned embodiments will be described in detail below. For other features of display panel 500c similar to those in the aforementioned embodiments, reference can be made to the above description and will not be repeated here.

[0199] In some embodiments, the dummy electrode may be arranged in the same electrode layer as the first electrode and electrically isolated from each other; at least one of the dummy stack portions may be connected to the dummy electrode; for example, the dummy electrode may be located between the planarization structure and the isolation opening defining portion of the pixel defining structure in a direction perpendicular to the main surface of the substrate, and the dummy electrode may have an electrode opening, which is spatially connected to the corresponding isolation opening of the pixel defining structure; for example, a partial inter-pixel isolation portion of the isolation structure may include an extension of the isolation opening defining portion, a dummy electrode, and a bottom cut structure located between the extension and the dummy electrode, and the inter-pixel isolation portion has a second isolation height defined by the sum of the depth of the isolation opening and the depth of the electrode opening.

[0200] For example, referring to FIG7 , in some embodiments, the display panel 500b further includes a dummy electrode DE. The dummy electrode DE may be disposed on a side of the planarization structure PL away from the base substrate and may be disposed in the same layer as the first electrodes E1 of the plurality of sub-pixels. In this context, disposing the plurality of components in the same layer may include forming the components using the same material layer through the same patterning process. In other words, the dummy electrode DE may be formed from the same material layer through the same patterning process as the plurality of first electrodes E1.

[0201] Referring to Figures 7 and 8C, in some embodiments, at least a portion of the dummy electrode DE is located between the planarization structure PL and the isolation opening defining portion P2b of the pixel defining structure PS. For example, the isolation opening defining portion P2b has an extension ex2, and an undercut structure uc2 is formed between the extension ex2 and the dummy electrode DE. The orthographic projection of the dummy electrode De on the primary surface of the base substrate may overlap with the orthographic projection of the extension ex2 of the second pixel defining layer on the base substrate. The dummy electrode DE has an electrode opening EO, which is spatially connected to the isolation opening IO2. The width of the electrode opening EO may be the same as or different from the width of the isolation opening IO2. For example, the width of the electrode opening EO may be approximately equal to the width of the second sub-opening of the isolation opening IO2 and smaller than the width of the first sub-opening, but the present disclosure is not limited to this. In other embodiments, the electrode opening EO may be smaller or larger than the width of the second sub-opening and may be smaller than or approximately equal to the width of the first sub-opening. In some embodiments, a portion of the dummy electrode De extends beyond the edge of the first pixel defining layer in a direction parallel to the primary surface of the base substrate, and this portion may be referred to as an electrode extension.

[0202] In some embodiments, the inter-pixel isolation portion 12b of the isolation structure IS may include an extension portion ex2 of the second pixel defining layer, an undercut structure uc2, and an electrode extension portion of the dummy electrode DE. Furthermore, a second isolation height H2 of the inter-pixel isolation portion 12b may be defined by the sum of the depth of the isolation opening IO2 and the depth of the electrode opening EO. For example, the depth of the isolation opening IO2 may be approximately equal to the sum of the thicknesses of the first pixel defining layer 112a and the second pixel defining layer 112b, and the depth of the electrode opening EO may be approximately equal to the thickness of the dummy electrode DE. In some examples, the second isolation height H2 may be approximately equal to the sum of the thicknesses of the first pixel defining layer 112a, the second pixel defining layer 112b, and the dummy electrode DE.

[0203] In some embodiments, the electrode opening EO exposes a portion of the surface of the planarization structure PL, and the planarization structure PL may not include a recess, but the present disclosure is not limited thereto. In alternative embodiments, the planarization structure PL may include a recess, and the recess may be spatially connected to the electrode opening and the isolation opening, such that the isolation height of the inter-pixel isolation portion is defined by the sum of the depths of the isolation opening, the electrode opening, and the recess. It should be understood that the isolation height can be set and adjusted based on product design and requirements.

[0204] In some embodiments, the planarization structure PL may include a single-layer structure or a multi-layer structure; for example, the planarization structure PL may include a planarization layer 111a and a buffer layer 111b, but the present disclosure is not limited to this. The planarization structure PL may also include other material layers, such as the passivation layer shown in Figure 5, or may also include fewer material layers, for example, the buffer layer 111b may be omitted and only the planarization layer 111a may be included.

[0205] In some embodiments, the dummy electrode DE can be connected to a low voltage signal, for example, a low voltage terminal such as ground, zero potential, or power supply voltage VSS. The dummy electrode DE can be connected to a dummy electrode signal line, and the dummy electrode signal line can be provided in at least one of the conductive layer 110, the conductive layer 108, the conductive layer 106, and the active material layer 103. For example, the dummy electrode DE can be electrically connected to the dummy electrode signal line del located in the conductive layer 110 through a via in the planarization structure PL, and the dummy electrode signal line is configured to apply a low voltage signal to the dummy electrode DE. However, the present disclosure is not limited thereto. In an alternative embodiment, the dummy electrode DE can also be electrically floating, that is, not connected to any other conductive member and / or voltage source.

[0206] 7 and 8C , in some embodiments, the structures and isolation heights of the plurality of pixel region isolation portions 11 and inter-pixel isolation portions 12 a in the isolation structure IS are similar to those of the display panel 500 b and are not further described herein.

[0207] In some embodiments, in the light-emitting stack portion LE, the dummy stack portion DS2 is located within the isolation opening 102 and the electrode opening DE, and the dummy charge generation layer 6c3 in the dummy stack portion DS2 can be disconnected from the charge generation layers 116b2 and 116c2 in the light-emitting stack portions LS2 and LS3 by the inter-pixel isolation portion 12b. In some embodiments, the dummy stack layer DS2 can be connected to the dummy electrode DE, and the dummy electrode DE maintains a low voltage state, thereby facilitating the discharge of excess charge generated in the dummy stack layer and / or the light-emitting device (e.g., the charge generation layer, the hole injection layer, etc.), thereby preventing charge accumulation from damaging the device.

[0208] 8A to 8C are schematic cross-sectional views illustrating intermediate structures of various steps in a method for manufacturing a display panel 500 c according to some embodiments of the present disclosure.

[0209] Referring to FIG. 8A , in some embodiments, a pixel circuit layer CL is formed on one side of a base substrate 100. Forming the pixel circuit layer CL may further include forming a dummy electrode signal line in one or more of the active layer AL, the conductive layer 106, the conductive layer 108, and the conductive layer 110. That is, the dummy electrode signal line may be disposed in the same layer as at least one of the active layer AL, the first gate electrode G1, the second gate electrode G2, and the source electrode S / drain electrode D. For example, forming the conductive layer 110 may also include forming a dummy electrode signal line del. For example, the source electrode S, the drain electrode D, and the dummy electrode signal line del may be formed from the same material through the same patterning process.

[0210] A planarization structure PL is formed on the side of the pixel circuit layer CL away from the base substrate 100. The planarization structure PL may include, for example, a planarization layer 111a and a buffer layer 111b, but the present disclosure is not limited thereto. Next, a patterning process is performed on the planarization structure PL to form a plurality of vias in the planarization structure PL. The plurality of vias may include one or more vias (or referred to as first vias) that expose relevant components of the sub-pixel circuit (e.g., the source electrode or the drain electrode of the thin film transistor) and one or more vias (or referred to as second vias) that expose the dummy electrode signal line del. It should be understood that when the dummy electrode signal line is provided in the active layer AL, the conductive layer 106, and the conductive layer 108, the second via is also formed in the corresponding dielectric layer on the side of the planarization structure PL close to the base substrate to expose the dummy electrode signal line.

[0211] Subsequently, a plurality of first electrodes E1 and dummy electrodes DE are formed on the planarized structure PL. The plurality of first electrodes E1 are formed on a side of the planarized structure PL away from the base substrate and are filled into a plurality of first vias to electrically connect to corresponding sub-pixel circuits. The dummy electrode DE is formed on a side of the planarized structure PL away from the base substrate and is filled into a plurality of second vias to electrically connect to the dummy electrode signal line del. In some embodiments, the plurality of first electrodes E1 and the dummy electrode DE can be formed by forming a first electrode material layer on the planarized structure PL and then patterning the first electrode material layer. In some embodiments, the patterning process further forms an electrode opening EO in the dummy electrode DE. For example, the dummy electrode DE can be a continuous ring-shaped electrode, with the electrode opening located within the ring-shaped electrode; or the dummy electrode DE can include a plurality of dummy sub-electrodes separated from each other, with the electrode opening EO located between adjacent dummy sub-electrodes.

[0212] 8A and 8B , a pixel defining structure PS is formed on a side of the planarization structure PL away from the base substrate, and a portion of the pixel defining structure PS and the dummy electrode DE together constitute an isolation structure IS. The method for forming the pixel defining structure PS is similar to that of the aforementioned embodiment, and for example includes the following processes: forming a first pixel defining layer 112a on the side of the planarization structure PL away from the base substrate to cover the side walls of the first electrode E1 and the dummy electrode DE and their surfaces away from the base substrate; forming a second pixel defining layer 112b on the side of the first pixel defining layer 112a away from the base substrate; forming a mask layer 113 on the side of the second pixel defining layer 112b away from the base substrate, the mask layer 113 may, for example, include a first mask opening 113a and a second mask opening 113b, wherein part of the second mask opening 113b may be located at a position corresponding to the electrode opening EO of the dummy electrode DE; thereafter, the second pixel defining layer 112b and the first pixel defining layer 112a are etched using the mask layer 113 as an etching mask, and the first electrode E1, the dummy electrode DE and the planarization structure PL may serve as etching stop layers for the etching process. The etching process forms a plurality of sub-pixel openings PO1, PO2, PO3 and isolation openings IO1, IO2 in the pixel defining structure PS, and the etching process removes the pixel defining material located in the electrode opening EO, so that the formed isolation opening IO2 and the electrode opening EO are spatially connected and part of the surface of the planarization structure is exposed.

[0213] 8B , 8C and 7 , the mask layer 113 is then removed, and components such as a light emitting stacked layer LE, a common electrode structure CE and an encapsulation layer 112 are formed on the pixel defining structure PS, thereby forming a display panel 500 c .

[0214] FIG9 shows a schematic cross-sectional view of a display panel 500 d according to some other embodiments of the present disclosure.

[0215] In some embodiments, the pixel-defining structure may include a pixel-defining body layer, a first pixel-defining layer, and a second pixel-defining layer. The pixel-defining body layer may be disposed on a side of the first pixel-defining layer proximal to the substrate and define a plurality of sub-pixel openings. For example, the pixel-defining body layer may include a first body portion positioned between a first sub-pixel and an adjacent second or third sub-pixel, and a second body portion positioned between the second sub-pixel and the third sub-pixel. The first and second pixel-defining layers may include first and second isolation portions positioned on the first and second body portions, respectively. Each isolation portion may include an extension of the first pixel-defining layer and an undercut structure positioned between the extension and the pixel-defining body layer.

[0216] For example, referring to FIG. 9 , in display panel 500d , the pixel-defining structure PS may include a pixel-defining body layer 112z, a first pixel-defining layer 112a, and a second pixel-defining layer 112b. The pixel-defining structure PS defines multiple sub-pixel openings, with portions of the pixel-defining structure PS serving as isolation structures IS. In some embodiments, the multiple sub-pixel openings PO1, PO2, and PO3 may be primarily defined by the pixel-defining body layer 112z, with the first and second pixel-defining layers 112a and 112b also serving as portions of the sub-pixel openings. In some embodiments, the pixel-defining body layer may include multiple body portions, each located between adjacent sub-pixels. The first and second pixel-defining layers may be formed on the body portions of the pixel-defining layers and include multiple isolation portions. In each isolation portion, the second pixel-defining layer has an extension extending parallel to the major surface of the substrate beyond the edge of the first pixel-defining layer, with an undercut structure between the extension and the pixel-defining body layer. The undercut structure may be located within the first pixel-defining layer or may extend further into the pixel-defining body layer.

[0217] For example, the pixel-defining body layer 112z may include a first body portion 112z1 located between the first sub-pixel SP1 and the second sub-pixel SP2, and a second body portion 112z2 located between the second sub-pixel SP2 and the third sub-pixel SP3. A portion of the pixel-defining structure PS serves as an isolation structure, and the isolation structure may include a first isolation portion IS1 and a second isolation portion IS2 located on the first body portion 112z1 and the second body portion 112z2, respectively.

[0218] In some embodiments, the first isolation portion IS1 may include portions of the first pixel defining layer 112a and the second pixel defining layer 112b located above the first main portion 112z1. For example, in the first isolation portion IS1, the second pixel defining layer 112b may include an extension ex1 that protrudes from an edge of the first pixel defining layer 112a in a direction parallel to the main surface of the substrate, and an undercut structure uc1 may be provided between the extension ex1 of the second pixel defining layer 112b and the first main portion 112z1 of the pixel defining main layer.

[0219] In some embodiments, an edge portion of the first isolation portion IS1 is adjacent to the corresponding sub-pixel opening, and an undercut structure uc1 in the edge portion is spatially connected to the corresponding sub-pixel opening. The edge portion can also serve to partially define the sub-pixel opening. In some embodiments, the first isolation portion IS1 may include a single isolation portion, or may include multiple isolation sub-portions, with an isolation opening between adjacent isolation sub-portions. For example, the first isolation portion IS1 may include an isolation sub-portion IS11 and an isolation sub-portion IS12, with an isolation opening IO1 between the isolation sub-portions IS11 and IS12. In each isolation sub-portion, the second pixel-defining layer includes an extension with an undercut structure between the extension and the pixel-defining main layer. Similar to the previous embodiment, the isolation opening IO1 includes a first sub-opening in the first pixel-defining layer 112a and a second sub-opening in the second pixel-defining layer 112b, with the first sub-opening including a portion of the undercut structure uc1 in the isolation sub-portions IS11 and IS12. The isolation opening IO1 may expose a portion of the surface of the pixel-defining main layer 112z1. In some embodiments, the plurality of isolation sub-portions of the first isolation portion IS1 may be arranged along an arrangement direction of corresponding adjacent sub-pixels.

[0220] In some embodiments, in the first main portion 112z1, the surface of the pixel-defining main layer 112z1 in contact with the first pixel-defining layer 112a and the surface of the pixel-defining main layer 112z1 exposed by the isolation opening IO1 may be substantially flush in a direction parallel to the main surface of the substrate. The first isolation portion IS1 may serve as a pixel region isolation portion and / or an inter-pixel isolation portion of the isolation structure and have a first isolation height H1. The first isolation height H1 may be defined by the sum of the thickness of the extension portion ex1 of the second pixel-defining layer 112b and the depth of the undercut structure uc1 (i.e., the depth of the isolation opening IO1). In this example, the depth of the undercut structure uc1 may be substantially equal to the thickness of the first pixel-defining layer 112a. That is, the first isolation height H1 may be substantially equal to the sum of the thicknesses of the second pixel-defining layer 112b and the first pixel-defining layer 112a.

[0221] In some embodiments, the second isolation portion IS2 may include portions of the first pixel defining layer 112a and the second pixel defining layer 112b located above the second main body portion 112z2. For example, the second main body portion 112z2 may have a recess rc (or may be referred to as a main body recess) and may include a main body sub-portion z21 and a protrusion z22. The protrusion z22 protrudes from the surface of the main body sub-portion z21, which is away from the substrate, toward the main surface of the first pixel defining layer in a direction perpendicular to the main surface of the substrate. In other words, the main body sub-portion z21 is recessed relative to the protrusion z22 toward the substrate in a direction perpendicular to the main surface of the substrate, and the recess rc is defined by the surface of the main body sub-portion z21, which is away from the substrate, and the sidewalls of the protrusion z22. In some embodiments, the protrusion z22 of the second main body portion 112z2 and the second isolation portion IS2 of the first and second pixel defining layers located above the protrusion together constitute the pixel region isolation portion and / or inter-pixel isolation portion of the isolation structure.

[0222] For example, in the second isolation portion IS2, the second pixel defining layer 112b has an extension portion ex2 extending beyond the first pixel defining layer 112a in a direction parallel to the main surface of the substrate. An undercut structure uc2 is provided between the extension portion ex2 of the second pixel defining layer 112b and the second main portion 112z2. In some embodiments, the sidewalls of the protrusion z22 of the second main portion 112z2 may be substantially aligned with the corresponding sidewalls of the first pixel defining layer 112a in a direction perpendicular to the main surface of the substrate. That is, the protrusion z22 is also recessed relative to the second pixel defining layer 112b in a direction parallel to the main surface of the substrate, such that the undercut structure uc2 extends into the second main portion 112z2. However, the present disclosure is not limited to this. In other embodiments, the sidewalls of the protrusion z22 may not be aligned with the sidewalls of the first pixel defining layer, and may be aligned or non-aligned with the sidewalls of the second pixel defining layer. The undercut structure uc2 is at least located in the first pixel defining layer and may further extend into the pixel defining body layer. In some examples, the depth of the undercut structure uc2 may be substantially equal to the sum of the thicknesses of the first pixel defining layer and the protrusion z22 .

[0223] In some embodiments, an edge portion of the second isolation portion IS2 is adjacent to the corresponding sub-pixel opening, and an undercut structure uc2 in the edge portion is spatially connected to the corresponding sub-pixel opening. The edge portion may also serve to partially define the sub-pixel opening. In some embodiments, the second isolation portion IS2 may include a single isolation portion, or may include multiple isolation sub-portions, with an isolation opening between adjacent isolation sub-portions. For example, the second isolation portion IS2 may include isolation sub-portions IS21 and IS22, with an isolation opening IO2 between the isolation sub-portions IS21 and IS22. In each isolation sub-portion, the second pixel-defining layer includes an extension with an undercut structure between the extension and the pixel-defining body layer. Similar to the previous embodiment, the isolation opening IO2 includes a first sub-opening in the first sub-pixel-defining layer 112a and a second sub-opening in the second sub-pixel-defining layer 112b. The recess rc in the second body portion 112z2 of the pixel-defining body layer is spatially connected to the isolation opening IO2. For example, the undercut structure uc2 may include portions of the first sub-opening and recess rc. The isolation opening IO2 may expose a portion of the surface of the pixel-defining body layer 112z1. In some embodiments, the plurality of isolation sub-portions of the second isolation portion IS2 may be arranged along an arrangement direction of corresponding adjacent sub-pixels (eg, the second sub-pixel and the third sub-pixel).

[0224] In some embodiments, in the second main body portion 112z2, the surface of the second main body portion 112z2 in contact with the first pixel defining layer 112a (e.g., the first surface) is higher than the surface of the second main body portion 112z2 exposed by the isolation opening IO2 (e.g., the second surface); that is, in a direction perpendicular to the main surface of the substrate substrate, the distance between the first surface and the main surface of the substrate substrate is greater than the distance between the second surface and the main surface of the substrate substrate.

[0225] The second isolation portion IS2 of the first and second pixel defining layers and the protrusion z2 of the pixel defining body layer together constitute the pixel region isolation portion and / or inter-pixel isolation portion of the isolation structure, and may have a second isolation height H2. This second isolation height H2 may be defined by the sum of the depth of the isolation opening IO2 and the depth of the body recess rc, for example, approximately equal to the sum of the thickness of the extension ex2 and the depth of the undercut structure uc2. The depth of the isolation opening IO2 is approximately equal to the sum of the thicknesses of the first and second pixel defining layers, and the depth of the recess rc is approximately equal to the thickness of the protrusion z22 of the second body portion 112z2. In other words, the second isolation height H2 may be approximately equal to the sum of the thicknesses of the second pixel defining layer 112b, the first pixel defining layer 112a, and the protrusion z22.

[0226] In some embodiments, the first pixel region isolation portion corresponding to the first sub-pixel SP1 may include a portion of the first isolation portion IS1 (e.g., its isolation sub-portion IS11) near the sub-pixel opening PO1; the second pixel region isolation portion corresponding to the second sub-pixel SP2 may include a portion of the first isolation portion IS1 (e.g., its isolation sub-portion IS12) near the sub-pixel opening PO2 and a portion of the second isolation portion IS2 (e.g., its isolation sub-portion IS21) near the sub-pixel opening PO2; the third pixel region isolation portion corresponding to the third sub-pixel SP3 may include a portion of the second isolation portion IS2 (e.g., its isolation sub-portion IS22) near the sub-pixel opening SP3. The first inter-pixel isolation portion between the first sub-pixel and the adjacent sub-pixel (e.g., the second sub-pixel) may include portions of the isolation sub-portions IS11 and IS12 of the first isolation portion IS1 defining the isolation opening IO1; the second inter-pixel isolation portion between the second and third sub-pixels may include portions of the isolation sub-portions IS21 and IS22 of the second isolation portion IS2 defining the isolation opening IO2 and the protrusion z22 of the pixel-defining body layer.

[0227] That is, in this embodiment, the first pixel region isolation portion and the first inter-pixel isolation portion have a first isolation height H1; part of the second pixel region isolation portion has a first isolation height H1, and another part of the second pixel region isolation portion has a second isolation height H2; the third pixel region isolation portion and the second inter-pixel isolation portion have a second isolation height H2.

[0228] In this embodiment, the sub-pixel opening defining portion of the pixel defining structure PS may include the pixel defining body layer and portions of the first and second pixel defining layers, and the isolation opening defining portion includes portions of the first and second pixel defining layers.

[0229] Continuing with reference to FIG9 , the light-emitting stack layer LE is disposed on a side of the pixel-defining structure PS away from the base substrate and includes light-emitting stack portions LS1, LS2, and LS3 of multiple sub-pixels, multiple stack portions AS1, AS2, AS3, and AS4 located on a side of the isolation structure IS away from the base substrate, and dummy stack portions DS1 and DS2 located in the isolation opening. In some embodiments, the stack portion located on the isolation structure is adjacent to the light-emitting stack portion of an adjacent sub-pixel and may be adjacent to or disconnected from the light-emitting stack portion and may also be referred to as a stacked sub-portion of the light-emitting stack portion. The dummy charge generation layer of the dummy stack portion located in the isolation opening is disconnected from the charge generation layer of the stack portion located on the adjacent isolation portion, and is further disconnected from the charge generation layer of the light-emitting stack portion of the sub-pixel.

[0230] In some embodiments, the angle α between the sidewall of the pixel-defining body layer 112z defining the sub-pixel opening and a reference plane parallel to the main surface of the substrate (e.g., the surface of the first electrode E1 away from the substrate) can be in the range of 10° to 45° or 10° to 65°, thereby helping to prevent leakage current from the light-emitting region. In some embodiments, the light-emitting stack portion of each sub-pixel can include a first stack sub-portion located in the sub-pixel opening and a second stack sub-portion located on the pixel-defining body layer, and the charge generation layers of the first stack sub-portion and the second stack sub-portion can be connected to each other.

[0231] For example, the light-emitting stack portion LS1 may include a light-emitting layer 115a, a charge-generating layer 116a, and a light-emitting layer 117a stacked in sequence in a direction perpendicular to the main surface of the base substrate, and may include a first stacking sub-portion located in the sub-pixel opening PO1 and a second stacking sub-portion located on the pixel-defining body layer 112z. The various material layers of the light-emitting stack portion LS1 may extend continuously over the first electrode E1 and the pixel-defining body layer 112z; that is, the layers in the first and second stacking sub-portions may be connected to each other.

[0232] For example, the light-emitting stack portion LS2 may include a light-emitting layer 115b, a charge generation layer 116b, and a light-emitting layer 117b stacked in sequence in a direction perpendicular to the main surface of the base substrate; the light-emitting stack portion LS2 may include a first stacking sub-portion located in the sub-pixel opening PO2, and may also include a second stacking sub-portion located on the pixel-defining main layer 112z. It should be understood that although only the first stacking sub-portion of the light-emitting stack portion LS2 is shown in the figure, it may also include a second stacking sub-portion connected to the first stacking sub-portion. For example, the various material layers of the light-emitting stack portion LS2 may extend continuously on the first electrode E1 and the pixel-defining main layer 112z; that is, the layers in the first stacking sub-portion and the second stacking sub-portion may be connected to each other.

[0233] For example, the light-emitting stacking layer LS3 may include a light-emitting layer 115c, a charge generating layer 116c and a light-emitting layer 117c stacked in sequence in a direction perpendicular to the main surface of the base substrate, and may include a first stacking sub-portion located in the sub-pixel opening PO3 and a second stacking sub-portion located on the pixel defining main layer 112z, and the layers in the first stacking sub-portion and the second stacking sub-portion may be connected to each other.

[0234] In some embodiments, stack portion AS1 and stack portion AS2 are located on isolation sub-portion IS11 and isolation sub-portion IS12 of first isolation portion IS1, respectively. Stack portion AS1 may include a light-emitting layer 5a4, a charge generation layer 6a4, and a light-emitting layer 7a4 stacked in sequence, while stack portion AS2 may include a light-emitting layer 5a5, a charge generation layer 6a5, and a light-emitting layer 7a5 stacked in sequence. In some embodiments, stack portion AS1 may also be considered a second stack sub-portion of light-emitting stack portion LS1. A dummy stack portion DS1 is located within isolation opening IO1 and between stack portions AS1 and AS2. Dummy stack portion DS1 may include a dummy light-emitting layer 5a3, a dummy charge generation layer 6a3, and a dummy light-emitting layer 7a3 stacked in sequence.

[0235] In some embodiments, the charge generation layer 6a4 of stack portion AS1 and the charge generation layer 116a of light-emitting stack portion LS1 may be disconnected from each other by a first pixel region isolation portion (i.e., a portion of the first isolation sub-portion IS11 of the first isolation portion IS1); the charge generation layer 6a5 of stack portion AS2 and the charge generation layer 116b of light-emitting stack portion LS2 may be disconnected from each other by a second pixel region isolation portion (i.e., a portion of the second isolation sub-portion IS12 of the first isolation portion IS1); and the charge generation layer 6a4 of stack portion AS1, the charge generation layer 6a5 of stack portion AS2, and the dummy charge generation layer 6a3 of dummy stack portion DS1 may be disconnected from each other by a first inter-pixel isolation portion (i.e., a portion of the first isolation sub-portion IS11 and the second isolation sub-portion IS12 of the first isolation portion IS1 that define the isolation opening IO1). In some embodiments, stack portions AS1 and AS2 may also be referred to as dummy stack portions.

[0236] In some embodiments, the light-emitting layers 5a4 / 5a5, charge generation layers 6a4 / 6a5, and light-emitting layers 7a4 / 7a5 in stacking sections AS1 / AS2, and the dummy light-emitting layers 5a3, dummy charge generation layers 6a3, and dummy light-emitting layers 7a3 in dummy stacking section DS1 may be made of the same material as the light-emitting layer 115a, charge generation layer 116a, and light-emitting layer 117a in light-emitting stacking section LS1, and may be formed in the same evaporation process, but the present disclosure is not limited thereto. In other embodiments, the material layers of stacking section AS1 may be made of the same material as the material layers in light-emitting stacking layer LS1 and may be formed in the same evaporation process; the material layers of stacking section AS2 may be made of the same material as the material layers in light-emitting stacking layer LS2 and may be formed in the same evaporation process; and the material layers of dummy stacking section DS1 may be made of the same material as the material layers in light-emitting stacking layer LS1 or LS2 and may be formed in the same evaporation process.

[0237] In some embodiments, stack portion AS3 and stack portion AS4 are located on isolation sub-portion IS21 and isolation sub-portion IS22 of second isolation portion IS2, respectively. Stack portion AS3 may include a light-emitting layer 5b1, a charge generation layer 6b1, and a light-emitting layer 7b1 stacked in sequence, while stack portion AS4 may include a light-emitting layer 5c1, a charge generation layer 6c1, and a light-emitting layer 7c1 stacked in sequence. A dummy stack portion DS2 is located within isolation opening IO2 and between stack portions AS3 and AS4. Dummy stack portion DS2 may include a dummy light-emitting layer 5b2, a dummy charge generation layer 6b2, and a dummy light-emitting layer 7b2 stacked in sequence. In some embodiments, stack portion AS3 may be considered a second stacked sub-portion of light-emitting stack portion LS2, and stack portion AS4 may be considered a second stacked sub-portion of light-emitting stack portion LS3.

[0238] In some embodiments, the charge generation layer 6b1 of stack portion AS3 and the charge generation layer 116b of light-emitting stack portion LS2 may be disconnected from each other by a second pixel region isolation portion (i.e., the portion of the isolation sub-portion IS21 and the protrusion z22); the charge generation layer 6c1 of stack portion AS4 and the charge generation layer 116c of light-emitting stack portion LS3 may be disconnected from each other by a third pixel region isolation portion (i.e., the portion of the isolation sub-portion IS22 and the protrusion z22); and the charge generation layer 6b1 of stack portion AS3, the charge generation layer 6c1 of stack portion AS4, and the dummy charge generation layer 6b2 of dummy stack portion DS2 may be disconnected from each other by a second inter-pixel isolation portion (i.e., the portion of the isolation sub-portions IS11 and IS12 and the protrusion z22 near the isolation opening IO2). In some embodiments, stack portions AS3 and AS4 may also be referred to as dummy stack portions.

[0239] In some embodiments, the light-emitting layer 5b1, the charge generation layer 6b1, the light-emitting layer 7b1 in the stacking portion AS3 and the dummy light-emitting layer 5b2, the dummy charge generation layer 6b2, and the dummy light-emitting layer 7b2 in the dummy stacking portion DS2 may respectively have the same materials as the light-emitting layer 115b, the charge generation layer 116b, and the light-emitting layer 117b in the light-emitting stacking portion LS2, and may be formed in the same evaporation process; the light-emitting layer 5c1, the charge generation layer 6c1, and the light-emitting layer 7c1 in the stacking portion AS4 may respectively have the same materials as the light-emitting layer 115c, the charge generation layer 116c, and the light-emitting layer 117c in the light-emitting stacking portion LS3, and may be formed in the same evaporation process; however, the present disclosure is not limited to this. In other embodiments, each material layer in stack portions AS3, AS4, and the dummy stack portion DS2 may be made of the same material as each material layer in the light-emitting stack portion LS2, or may be made of the same material as each material layer in the light-emitting stack layer LS3; or, each material layer in stack portion AS3 may be made of the same material as each material layer in the light-emitting stack portion LS2, while each material layer in stack portion AS4 and the dummy stack portion DS2 may be made of the same material as each material layer in the light-emitting stack portion LS3. In other words, stack portion AS3, stack portion AS4, and dummy stack portion DS2 may each be formed by the same evaporation process as one of the light-emitting stack portions of two adjacent sub-pixels and may be made of the same material.

[0240] Similar to the aforementioned embodiment, the display panel 500d may further include a common electrode structure CE and an encapsulation layer 120 , and the relevant features of the common electrode structure CE and the encapsulation layer 120 are similar to those of the aforementioned embodiment and are not described again herein.

[0241] 10A to 10C are schematic cross-sectional views illustrating intermediate structures of various steps in a method for manufacturing a display panel 500 d according to some embodiments of the present disclosure.

[0242] Referring to FIG. 10A , in some embodiments, after forming a pixel circuit layer CL, a planarization structure PL, and a first electrode E1 on a base substrate 100, a pixel-defining body layer 112z is formed on a side of the planarization structure PL and the first electrode E1 away from the base substrate. For example, the pixel-defining body layer 112z can comprise an organic insulating material, such as a resin material. The pixel-defining body layer 112z is patterned to form a plurality of sub-pixel openings defining a plurality of light-emitting regions, each of which exposes a portion of the surface of a corresponding first electrode E1. The edge portion of the first electrode E1 may be covered by the pixel-defining body layer 112z, but this is not a limitation of the present disclosure. In some embodiments, when patterning the sub-pixel openings, the angle α between the sidewalls of the pixel-defining body layer 112z defining the sub-pixel openings and a horizontal plane can be controlled within a suitable range to ensure that leakage current is not generated in the light-emitting stack layer subsequently formed in the light-emitting region.

[0243] Referring to Figure 10B , a first pixel-defining layer 112a and a second pixel-defining layer 112b are sequentially formed on the side of the pixel-defining body layer 112z and the first electrode E1 away from the base substrate 100. The first and second pixel-defining layers 112a, 112b comprise different materials, and the material selection for the pixel-defining layers is similar to that described in the previous embodiment and will not be repeated here. In this step, the first and second pixel-defining layers 112a, 112b extend along the surface of the pixel-defining body portion 112z and fill the plurality of sub-pixel openings.

[0244] Referring to FIG10C , a mask layer 113 is formed on a side of the second pixel-defining layer 112b away from the base substrate. In some embodiments, the mask layer 113 may cover a portion of the area between adjacent sub-pixels and expose the areas where the multiple sub-pixel openings are located. For example, the mask layer 113 may include a first mask opening 113a and a second mask opening 113b; the first mask opening 113a exposes the pixel-defining layer located within the sub-pixel openings; and the second mask opening 113b exposes a portion of the pixel-defining layer located on the main portion of the pixel-defining main layer.

[0245] 10C and 10D , the second pixel defining layer 112 b and the first pixel defining layer 112 a are etched using the mask layer 113 as an etching mask to remove portions of the second pixel defining layer and the first pixel defining layer exposed by the plurality of mask openings, and to form a plurality of openings in the second pixel defining layer and the first pixel defining layer. The plurality of openings expose portions of the surface of the pixel defining body layer, and thereby re-expose the plurality of sub-pixel openings. The etching process is similar to that described in the aforementioned embodiment; for example, portions of the second pixel defining layer and the first pixel defining layer located in each sub-pixel opening are removed by the etching process, thereby exposing the surface of the first electrode E1 and the sidewalls of the pixel defining body layer that define the sub-pixel openings; and portions of the second pixel defining layer and the first pixel defining layer located on the body portion of the pixel defining body layer are removed to form isolation openings IO1 and IO2. Similar to the previous embodiment, the first pixel defining layer 112a and the second pixel defining layer 112b are formed from different materials, and the etching process has a high etch selectivity for the first pixel defining layer 112a and the second pixel defining layer 112b. Undercut structures uc1 and uc2' may be formed on the sides of the first pixel defining layer 112a, between the second pixel defining layer 112b and the underlying material layer (e.g., the main portions 112z1 and 112z2 of the pixel defining body layer). In some embodiments, during this step, the undercut structures uc1 and uc2' may have the same height, for example, both may be substantially equal to the thickness of the first pixel defining layer 112a.

[0246] 10D and 10E , in some embodiments, the main body portion of the pixel-defining body layer 112z may be further subjected to a removal process to remove portions of the pixel-defining body layer exposed by the partial openings of the first and second pixel-defining layers, thereby forming a recess in a portion of the pixel-defining body layer. For example, a portion of the second main body portion of the pixel-defining body layer may be removed by an etching process to form a recess rc in the second main body portion 112z. In some embodiments, the recess rc extends below the extension portion of the second pixel-defining layer, thereby causing the undercut structure uc2' to further extend into the second main body portion and form an undercut structure uc2, such that the height of the undercut structure uc2 is greater than the height of the undercut structure uc1. In alternative embodiments, the recess rc may not extend below the extension portion of the pixel-defining layer, and the protrusion of the formed second main body portion 112z2 may also extend beyond the edge of the first pixel-defining layer in a direction parallel to the main surface of the substrate, and the undercut structure uc2 may be located between the extension portion of the second pixel-defining layer 112b and the protrusion of the second main body portion.

[0247] In some embodiments, during the etching process, the first main portion 112z1 of the pixel defining body layer 112z may not be removed. For example, during the etching process on the pixel defining body layer 112z, a mask may be used to cover areas of the pixel defining body layer where recesses are not required, while the mask exposes areas where recesses are required. For example, the mask may include a new mask formed by filling a portion of the mask openings of the mask layer 113 with a mask material, or may be a mask formed after the mask layer 113 is removed.

[0248] Referring to Figures 10E and 9 , a light-emitting stack layer LE and a common electrode structure CE are then formed on the side of the pixel-defining structure away from the base substrate. For example, forming the light-emitting stack layer LE may include performing multiple evaporation processes, such as a first evaporation process, a second evaporation process, and a third evaporation process. The evaporation regions of the first evaporation process, the second evaporation process, and the third evaporation process may at least include the corresponding sub-pixel regions, or may also include the spacing regions between adjacent sub-pixels; for example, the first evaporation process, the second evaporation process, and the third evaporation process may at least form light-emitting stack portions LS1, LS2, and LS3, respectively. In some embodiments, the first evaporation process further forms stack portions AS1, AS2, and a dummy stack portion DS1; the second evaporation process may further form a stack portion AS3 and a dummy stack portion DS2; and the third evaporation process may further form a stack portion AS4. However, the present disclosure is not limited thereto.

[0249] Fig. 11 is a schematic cross-sectional view of a display panel 500e according to some other embodiments of the present disclosure. Fig. 12B is a schematic cross-sectional view of a portion of the display panel 500e, including a pixel defining structure.

[0250] In some embodiments, the pixel defining structure PS of the display panel may include a plurality of pixel defining layers stacked in sequence in a direction perpendicular to the main surface of the substrate, and the second pixel defining layer is the one farthest from the substrate among the plurality of pixel defining layers, and the first pixel defining layer is the one adjacent to the second pixel defining layer among the plurality of pixel defining layers; in some embodiments, the pixel defining structure includes a sub-pixel opening defining portion and an isolation opening defining portion; in the sub-pixel opening defining portion, the side walls of the plurality of pixel defining layers are connected to each other and together constitute the side walls that define the sub-pixel opening; the isolation opening defining portion includes an extension portion and a bottom cut structure that constitute an isolation structure.

[0251] For example, referring to Figure 11, the pixel definition structure PS may include a plurality of pixel definition layers a1, a2, a3, 112a, and 112b stacked in sequence in a direction perpendicular to the main surface of the base substrate; in some embodiments, the pixel definition layers 112a and 112b may be respectively referred to as the first pixel definition layer and the second pixel definition layer, and one or more of the pixel definition layers a1, a2, and a3 located on the side of the pixel definition layer 112a close to the base substrate 100 may be collectively referred to as the pixel definition main layer.

[0252] In some embodiments, the plurality of pixel defining layers a1, a2, a3, 112a, and 112b may each comprise an inorganic material, such as SiO, SiN, SiON, SiCN, Al2O3, NbO, TiO, or the like. In some embodiments, adjacent pixel defining layers within the plurality of pixel defining layers may comprise different materials. In some embodiments, the overall thickness of the pixel defining structure PS (i.e., the sum of the thicknesses of the plurality of pixel defining layers) may be set within a range of 0.1 μm to 3 μm, but the present disclosure is not limited thereto.

[0253] In some embodiments, the pixel-defining structure PS has a plurality of sub-pixel openings PO1, PO2, and PO3, each extending through a plurality of pixel-defining layers and exposing a portion of the surface of a corresponding first electrode E1. In some embodiments, the sidewalls of the plurality of pixel-defining layers defining the same sub-pixel opening are connected to each other and collectively constitute the sidewalls of the pixel-defining structure defining the sub-pixel opening. For example, the sidewalls may be inclined, and the angle α between the sidewalls and a reference plane parallel to the main surface of the substrate may be an acute angle, such as ranging from approximately 10° to approximately 40° or 45°, or less than 20°. This angle may also be referred to as the inclination angle of the sub-pixel opening sidewall. In some embodiments, the angles of the sidewalls defining the same sub-pixel opening of the plurality of pixel-defining layers may be substantially the same or different.

[0254] In some embodiments, the cross-sectional shape of the sub-pixel opening may be an inverted trapezoid or a similar shape; for example, the width of the sub-pixel opening may gradually decrease as it approaches the substrate and the first electrode, and gradually increase as it moves away from the substrate and the first electrode. Each sub-pixel opening includes multiple sub-openings located in multiple pixel defining layers, and the width of the sub-openings of the pixel defining layers closer to the first electrode in the multiple pixel defining layers is smaller, while the width of the pixel defining layers farther away from the first electrode is larger. For example, in the same sub-pixel opening, the sub-openings in the pixel defining layers a1, a2, a3, 112a, and 112b gradually increase in size. In some embodiments, the undercut structure may not be present on the side of the pixel defining structure close to the sub-pixel opening.

[0255] In some embodiments, the pixel defining structure PS may include a plurality of pixel defining stacking portions located between different adjacent sub-pixels, the edge portion of each pixel defining stacking portion being used to define the corresponding sub-pixel opening and may be referred to as a sub-pixel opening defining portion; the pixel defining stacking portion may have a recess, which may include one or more isolation openings; the portion of the pixel defining stacking portion that defines the isolation opening may include one or more extensions of the pixel defining layer and one or more undercut structures, and serve as an inter-pixel isolation portion of the isolation structure.

[0256] In some embodiments, the sub-pixel opening defining portion has a first side and a second side opposite to each other in a direction parallel to the main surface of the substrate, the first side being used to define the sub-pixel opening, and the second side being used to define the recess, and including an extension portion and an undercut structure. In other words, the second side of the sub-pixel opening defining portion may also be referred to as an isolation portion. In some embodiments, the pixel defining stacking portion includes an isolation portion disposed in the recess, the isolation portion including an extension portion of one or more pixel defining layers and one or more undercut structures. The isolation portion in the recess is spaced apart from adjacent sub-pixel opening defining portions and has an isolation opening between the two. The isolation portion in each recess may be a single isolation portion, or may include multiple isolation sub-portions, with isolation openings between adjacent isolation sub-portions. In some embodiments, the recess depths in different pixel defining stacking portions may be different; the recess depths are used to define the isolation height of the isolation portion between pixels; by setting different recess depths, isolation portions with different isolation heights can be formed. In some embodiments, the recess is formed in at least two layers of pixel defining layers.

[0257] Referring to Figures 11 and 12B , for example, the pixel-defining structure PS may include a pixel-defining stack portion PS1 located between the first subpixel SP1 and the second subpixel SP2, and a pixel-defining stack portion PS2 located between the second subpixel SP2 and the third subpixel SP3. The pixel-defining stack portion PS1 may include subpixel opening defining portions OS1a and OS1b, and may have a recess RC1. The first and second sides of the subpixel opening defining portion OS1a, respectively, define portions of the subpixel opening PO1 and the recess RC1; the first and second sides of the subpixel opening defining portion OS1b, respectively, define portions of the subpixel opening PO2 and the recess RC1. In some embodiments, the second side of each of the subpixel opening defining portions OS1a and OS1b may include one or more extensions of the pixel defining layer extending beyond the edge of an adjacent pixel defining layer in a direction parallel to the main surface of the base substrate. These extensions may also have undercuts on the side of the extensions that is closer to the base substrate. These undercuts are formed by lateral contraction of the adjacent pixel defining layer in a direction parallel to the main surface of the base substrate. For example, on the second side of the sub-pixel opening defining portions OS1a and OS1b, the pixel defining layer 112b has an extension portion ex1, which extends beyond the edge of the pixel defining layer 112a in a direction parallel to the main surface of the base substrate, thereby forming a bottom cut structure uc1 on the side of the pixel defining layer 112a away from the sub-pixel opening, for example, between the extension portion ex1 and the pixel defining layer a3 below.

[0258] In some embodiments, an isolation portion IS1 is provided in the recess RC1. The isolation portion IS1 is spaced apart from the sub-pixel opening defining portions OS1a and OS1b, and an isolation opening IO1 is provided between the isolation portion IS1 and the sub-pixel opening defining portion OS1a, and between the isolation portion IS1 and the sub-pixel opening defining portion OS1b. In other words, the recess RC1 may include a plurality of isolation openings IO1. The plurality of isolation openings IO1 may be separated from each other (i.e., not connected to each other), but may also be connected to each other. For example, the isolation opening IO1 may extend through the pixel defining layers 112b and 112a and expose a portion of the surface of the pixel defining layer a3 on the side away from the base substrate.

[0259] In some embodiments, the isolation portion IS1 includes an extension portion ex1 extending from the pixel defining layer 112b in a direction parallel to the main surface of the substrate beyond the opposite edge of the pixel defining layer 112b, and includes an undercut structure uc1 on the side of the pixel defining layer 112a between the pixel defining layer 112b and the pixel defining layer a3. The isolation portion IS1 has a first side and a second side opposing each other in a direction parallel to the main surface of the substrate. The first and second sides of the isolation portion IS1 face the second side of the sub-pixel opening defining portion OS1a and the sub-pixel opening defining portion OS1b, respectively, and together with the sub-pixel opening defining portions OS1a and OS1b, define the isolation opening IO1. In other words, the second sides of the sub-pixel opening defining portions OS1a and OS1b, as well as the isolation portion IS1, all serve as isolation opening defining portions. Similar to the previous embodiment, each isolation opening IO1 includes multiple sub-openings in the pixel defining layer, for example, a first sub-opening in the pixel defining layer 112a and a second sub-opening in the pixel defining layer 112b. The first sub-opening is wider than the second sub-opening and includes the undercut structure.

[0260] In some embodiments, the isolation portion IS1 may be a single isolation portion, or may include multiple isolation sub-portions, each of which has the structure of the isolation portion IS1 shown in FIG12B , and has an isolation opening IO1 between adjacent isolation sub-portions. In some embodiments, the height of each isolation portion is determined by the thickness of the extension portion of the corresponding pixel defining layer and the height of the undercut structure.

[0261] In this embodiment, the isolation portion on the second side of the sub-pixel opening defining portions OS1a and OS1b, and the isolation portion IS1 located in the recess RC1, collectively constitute an inter-pixel isolation portion between the first sub-pixel SP1 and the second sub-pixel SP2. The inter-pixel isolation portion has an isolation height defined by the sum of the thickness of the extension portion ex1 of the pixel defining layer 112b and the height of the undercut structure uc1.

[0262] In some embodiments, because multiple pixel defining layers are formed on the first electrode and may have a conformal morphology with the underlying material layer (e.g., some regions may have a stepped shape), the multiple pixel defining layers may have portions extending in a direction parallel to the main surface of the substrate (e.g., horizontally) and may also have portions extending in a direction intersecting (e.g., perpendicular) to the main surface of the substrate (e.g., vertically). For each of the isolation portions on the second side of the sub-pixel opening defining portions OS1a and OS1b, and the isolation portion IS1 located in the recess RC1, its extension portion ex1 may include a horizontally extending portion and / or a vertically extending portion of the pixel defining layer 112b. Therefore, the extension portions or undercut structures located in different regions of the same pixel defining layer may have different thicknesses / heights. For example, in the example shown in FIG12B , the extension ex1 included in the isolation portion on the second side of the sub-pixel opening defining portions OS1a and OS1b comprises a portion of the pixel defining layer 112b extending in a direction intersecting the main surface of the substrate, while the extension ex1 of the isolation portion IS1 comprises a portion of the pixel defining layer 112b extending in a direction parallel to the main surface of the substrate. Furthermore, the thickness of the extension ex1 of the isolation portion IS1 may be less than the thickness of the extension ex1 of the sub-pixel opening defining portions OS1a and OS1b, thereby making the isolation height of the isolation portion IS1 less than the isolation height of the isolation portion on the second side of the sub-pixel opening defining portions. In some embodiments, the isolation height of the isolation portion IS1 is approximately equal to the sum of the thicknesses of the pixel defining layers 112b and 112b, while the isolation height on the second side of the sub-pixel opening defining portions OS1a and OS1b is greater than the sum of the thicknesses of the pixel defining layers 112a and 112b. In other words, in this example, the isolation height of the inter-pixel isolation portion between the first and second sub-pixels may be greater than or equal to the sum of the thicknesses of the pixel defining layers 112b and 112a. In this document, the thickness of a material layer refers to its thickness in a direction perpendicular to its extension. The thickness of the pixel defining layer is defined herein as the portion of the pixel defining layer extending parallel to the major surface of the substrate (i.e., the horizontally extending portion), and the thickness refers to the thickness of the horizontally extending portion in a direction perpendicular to the major surface of the substrate.

[0263] In other embodiments, the isolation portion IS1 may not be provided in the recess RC1 of the pixel defining portion PS1, that is, the recess RC1 is a single isolation opening defined by the second sides of the sub-pixel opening defining portions OS1a and OS1b, and the inter-pixel isolation portion located between the first sub-pixel and the second sub-pixel may only include the isolation portion formed by the second sides of the sub-pixel defining portions OS1a and OS1b.

[0264] Continuing with FIG. 12B , pixel-defining stack portion PS2 may include sub-pixel opening-defining portions OS2a and OS2b and have a recess RC2. The structure of pixel-defining stack portion PS2 is similar to that of pixel-defining stack portion PS1, except that the depth of recess RC2 differs. In some embodiments, recess RC2 may be formed in two or more pixel-defining layers, for example, in pixel-defining layers 112b, 112a, and a3.

[0265] For example, the first and second sides of sub-pixel opening defining portion OS2a respectively define a portion of sub-pixel opening PO2 and a portion of recess RC2; the first and second sides of sub-pixel opening defining portion OS2b respectively define a portion of sub-pixel opening PO3 and a portion of recess RC2. In some embodiments, the second side of each sub-pixel opening defining portion OS2a or OS2b includes one or more extensions of the pixel defining layer extending beyond the edge of an adjacent pixel defining layer in a direction parallel to the main surface of the substrate. These extensions have undercut structures on the side of the extensions proximal to the substrate. These undercut structures are formed by lateral indentation of the adjacent pixel defining layer in a direction parallel to the main surface of the substrate. For example, on the second sides of sub-pixel opening defining portions OS2a or OS2b, pixel defining layers 112B and a3 have extensions ex2. These extensions ex2 extend beyond the edge of pixel defining layer 112a in a direction parallel to the main surface of the substrate, thereby forming an undercut structure uc2 on the side of pixel defining layer 112a away from the sub-pixel opening, for example, between the extensions ex1 and the underlying pixel defining layer a3. That is, the second sides of the sub-pixel opening defining portions OS2a and OS2b also serve as isolation portions.

[0266] In some embodiments, an isolation portion IS2 is provided in the recess RC2. The isolation portion IS2 is spaced apart from the sub-pixel opening defining portions OS2a and OS2b, and an isolation opening IO2 is provided between the isolation portion IS2 and the sub-pixel opening defining portion OS2a, and between the isolation portion IS2 and the sub-pixel opening defining portion OS2b. In other words, the recess RC2 may include a plurality of isolation openings IO2. The plurality of isolation openings IO2 may be separated from each other (i.e., not connected to each other), but may also be connected to each other. The isolation opening IO2 extends through the pixel defining layers 112b, 112a, and a3 and may expose a portion of the surface of the pixel defining layer a2 on the side away from the base substrate.

[0267] In some embodiments, isolation portion IS2 includes an extension portion ex2 extending from pixel defining layers 112b and a3 in a direction parallel to the main surface of the substrate beyond the opposing edges of pixel defining layer 112a. Furthermore, an undercut structure uc2 is formed on the side of pixel defining layer 112a between pixel defining layer 112b and the extension portion ex2 of pixel defining layer a3. Isolation portion IS2 has a first side and a second side opposing each other in a direction parallel to the main surface of the substrate. The first and second sides of isolation portion IS2 face the second side of sub-pixel opening defining portion OS2a and the second side of sub-pixel opening defining portion OS2b, respectively, and together with sub-pixel opening defining portions OS2a and OS2b, define isolation opening 102. In other words, the second sides of sub-pixel opening defining portions OS2a and OS2b, as well as isolation portion IS2, function as the isolation opening defining portion.

[0268] In some embodiments, the isolation portion IS2 may be a single isolation portion, or may include multiple isolation sub-portions, each of which has the structure of the isolation portion IS2 shown in FIG12B , and has an isolation opening IO2 between adjacent isolation sub-portions. In some embodiments, the height of each isolation portion is determined by the thickness of the extension portion of the corresponding pixel defining layer and the depth of the undercut structure.

[0269] In this embodiment, the isolation portion on the second side of the sub-pixel opening defining portions OS2a and OS2b, and the isolation portion IS2 located in the recess RC2, collectively constitute the inter-pixel isolation portion between the second sub-pixel SP2 and the third sub-pixel SP3. This inter-pixel isolation portion has an isolation height defined by the sum of the thickness of the extension portion ex2 of the pixel defining layers 112b and a3 and the depth of the undercut structure uc2. These isolation heights are defined in a manner similar to the isolation heights discussed above for the isolation heights between the first and second sub-pixels. For example, the isolation height of the inter-pixel isolation portion between the second sub-pixel SP2 and the third sub-pixel SP3 can be greater than or equal to the sum of the thicknesses of the pixel defining layers 112b / 112a / a3, and can be greater than the isolation height of the inter-pixel isolation portion between the first sub-pixel and the adjacent sub-pixel.

[0270] It should be understood that in other embodiments, the isolation portion IS2 may not be provided in the recess RC2 of the pixel defining portion PS2, that is, the recess RC2 is a single isolation opening defined by the second side of the sub-pixel opening defining portions OS2a and OS2b, and the inter-pixel isolation portion located between the second sub-pixel and the third sub-pixel may only include the isolation portion formed by the second side of the sub-pixel defining portions OS2a and OS2b.

[0271] It should be understood that the number of pixel defining layers and the depths of the isolation openings in the pixel defining structures shown in Figures 11 and 12B are for illustrative purposes only and are not intended to limit the present disclosure. In other embodiments, the pixel defining structure may include more or fewer layers of pixel defining layers, and recesses of varying depths may be formed between adjacent sub-pixels to form isolation portions with varying isolation heights. Each isolation portion may include one or more extensions of the pixel defining layer and one or more undercut structures. In some embodiments, recesses of varying depths may be formed by etching away varying numbers of pixel defining layers.

[0272] With reference to FIG11 , in some embodiments, the light-emitting stack layer LE may include light-emitting stack portions LS1, LS2, and LS3 located in a plurality of sub-pixel openings, and stack portions AS1, AS2, AS12, AS3, AS4, and AS34 located in the recess of the pixel stack portion. In this embodiment, the isolation structure may not include a pixel region isolation portion, and in the light-emitting stack portions LS1, LS2, and LS3 of the plurality of sub-pixels, the material layers in the first stack sub-portion located in the sub-pixel opening and the second stack sub-portion located on the side of the sub-pixel opening defining portion away from the base substrate of each light-emitting stack portion are connected to each other, i.e., they are continuous layers and are not disconnected. That is, the charge generation layers of the first stack sub-portion and the second stack sub-portion of each light-emitting stack portion are connected to each other. In this embodiment, the material layers included in each light-emitting stack portion are similar to those in the aforementioned embodiment and are not further described here.

[0273] In some embodiments, the charge generation layers of adjacent light-emitting stacking sections in a plurality of light-emitting stacking sections may be disconnected from each other by an inter-pixel isolation section located between adjacent sub-pixels, and the inter-pixel isolation sections between different adjacent sub-pixels may have different isolation heights. For example, the charge generation layers of light-emitting stacking sections LS1 and LS2 may be disconnected from each other by a first inter-pixel isolation section (i.e., an isolation section defining isolation opening IO1) located between the first and second sub-pixels; the first inter-pixel isolation section has a first isolation height; the charge generation layers of light-emitting stacking sections LS2 and LS3 may be disconnected from each other by a second inter-pixel isolation section (i.e., an isolation section defining isolation opening IO2) located between the second and third sub-pixels; the second inter-pixel isolation section has a second isolation height, and the second isolation height is greater than the first height.

[0274] In some embodiments, stack portion AS1 and stack portion AS2 are each located within isolation opening IO1, and stack portion AS12 is located on a side of isolation portion IS1 away from the base substrate. In some embodiments, the charge generation layer and light-emitting layer, and other material layers, in stack portions AS1, AS2, and AS12 may each comprise the same material as the material layers in light-emitting stack portion LS1, and the charge generation layers of light-emitting stack portion LS1, stack portions AS1, AS2, and AS12, as well as adjacent stack portions within light-emitting stack portion LS2, are disconnected from each other by a first inter-pixel isolation portion, but the present disclosure is not limited to this. In other embodiments, the material layers in stack portion AS2 or stack portions AS2 and AS12 may each comprise the same material as the corresponding material layers in light-emitting stack portion LS2, and the charge generation layers in stack portions AS2, AS12, and light-emitting stack portion LS2 may or may not be disconnected from each other; at least the material layers in stack portion AS1 comprise the same material as the material layers in light-emitting stack portion LS1, and the charge generation layers of stack portion AS1 and light-emitting stack portion LS1 are disconnected from each other. In some embodiments, the charge generation layers between at least one set of adjacent light-emitting stacks LS1 and LS2 and one or more stacks AS1, AS12, and AS2 therebetween are disconnected from each other, thereby ensuring that the charge generation layers of light-emitting stacks LS1 and LS2 are disconnected from each other. In some embodiments, one or more of stacks AS1, AS12, and AS2 are dummy stacks.

[0275] In some embodiments, stacking portion AS3 and stacking portion AS4 are respectively located in isolation opening IO2, and stacking portion AS34 is located on the side of isolation portion IS2 away from the base substrate. In some embodiments, the charge generation layer and light-emitting layer in stacking portions AS3, AS4, and AS34 are made of the same material as the material layers in light-emitting stacking portion LS2 or LS3. In some embodiments, in light-emitting stacking portions LS2 and LS3, and one or more stacking portions AS3, AS34, and AS4 therebetween, the charge generation layers between at least one group of adjacent stacking portions are disconnected from each other, thereby ensuring that the charge generation layers of light-emitting stacking portions LS2 and LS3 are disconnected from each other. One or more of stacking portions AS3, AS34, and AS4 may be dummy stacking portions. For example, the charge generation layers of light-emitting stacking portion LS2 and stacking portions AS3, AS34, and AS4, as well as adjacent stacking portions in light-emitting stacking portion LS3, are all disconnected from each other, and stacking portions AS3, AS34, and AS4 may all be dummy stacking portions.

[0276] 11 , a common electrode structure CE and an encapsulation layer 120 are provided on a side of the light emitting stacked layer LE away from the base substrate, and the relevant features of these layers are similar to those of the aforementioned embodiment and are not described again herein.

[0277] In this embodiment, the pixel defining structure is formed by stacking a plurality of pixel defining layers, which is conducive to controlling the inclination angle of the side wall of the sub-pixel opening within a smaller angle range, thereby ensuring that the second electrode layer above the light-emitting area is continuous and improving the light extraction efficiency of the light-emitting device. For example, the multiple arrows in FIG11 schematically illustrate the light emitted from the light-emitting device. As shown in FIG11 , the multiple stacked layers of the pixel defining structure have a converging effect on the light on the light-emitting surface of the light-emitting device, thereby improving the light extraction efficiency of the light-emitting device. In addition, an etching process is performed on part of the pixel defining layers of the multiple pixel defining layers to form an isolation opening including an undercut structure, thereby forming an isolation structure to achieve the disconnection of the charge generation layers of adjacent sub-pixels; the multiple stacked layer arrangement can be conducive to controlling the isolation height, and can improve the process stability of the isolation structure, and can easily form an isolation portion including multiple undercut structures, thereby ensuring the disconnection of the charge generation layers of adjacent sub-pixels.

[0278] 12A to 12C are schematic cross-sectional views illustrating intermediate structures of various steps in a method for manufacturing a display panel 500 e according to some embodiments of the present disclosure.

[0279] Referring to FIG. 12A , in some embodiments, after forming a pixel circuit layer CL, a planarization structure PL, and a first electrode E1 on a display panel 100, a plurality of pixel definition layers a1, a2, a3, 112a, and 112b are sequentially formed on the side of the planarization structure PL and the first electrode E1 away from the base substrate. Subsequently, a mask layer 80 is formed on the side of the plurality of pixel definition layers away from the base substrate. The mask layer 80 may have a plurality of mask openings 80a, each of which is used to define a sub-pixel opening. For example, the plurality of mask openings 80a may expose portions of the plurality of pixel definition layers located above the first electrode E1.

[0280] 12A and 12B , in some embodiments, a mask layer 80 is used as an etching mask to perform an etching process on the plurality of pixel definition layers to form a plurality of sub-pixel openings PO1, PO2, and PO3 in the plurality of pixel definition layers. The etching process can be anisotropic, and by adjusting the material combination and etching process of each pixel definition layer, the formed sub-pixel openings can have inclined sidewalls, and the inclination angle of the sidewalls can be controlled within a relatively small angle range to ensure that the second electrode layer subsequently formed above the light-emitting area is not broken, thereby improving the light extraction efficiency of the light-emitting device.

[0281] After forming the sub-pixel openings, an etching process can be performed on the pixel-defining stack portions of the multiple pixel-defining layers located between adjacent sub-pixel openings to form recesses (i.e., isolation openings) in the pixel-defining stack portions, with the portion defining the recesses having an undercut structure, thereby forming isolation portions. In some embodiments, recesses of varying depths can be formed in different pixel-defining stack portions through multiple etching processes, thereby forming isolation portions with varying isolation heights. The depth of the recesses can be controlled by controlling the number of pixel-defining layer layers removed during the etching process.

[0282] For example, referring to Figures 12B and 12C, the mask layer 80 is removed and a mask layer 81 is formed on the pixel defining structure. The mask layer 81 may have one or more mask openings 81a to expose a portion of the surface of the pixel defining stack portion PS1 located between the sub-pixel openings PO1 and PO2. Then, as shown in Figures 12C and 12D, the mask layer 81 is used as an etching mask to perform an etching process on at least two pixel defining layers (for example, pixel defining layers 112b and 112a) among the multiple pixel defining layers to remove portions of these pixel defining layers and form a recess including one or more isolation openings IO1 in the pixel defining stack portion PS1. During the etching process, the portion of the pixel defining structure that defines the sub-pixel openings and other pixel defining stack portions may be covered by the mask layer 81.

[0283] 12D and 12E , the mask layer 81 is removed and a mask layer 82 is formed on the pixel defining structure PS. The mask layer 82 may have one or more mask openings 82a to expose a portion of the surface of the pixel defining stack portion PS2 located between the sub-pixel openings PO2 and PO3. As shown in FIG12E and 12F , the mask layer 82 is then used as an etching mask to perform an etching process on the plurality of pixel defining layers (e.g., pixel defining layers 112b, 112a, a3) to remove portions of these pixel defining layers and form a recess including one or more isolation openings IO2 in the pixel defining stack portion PS2. During the etching process, the portion of the pixel defining structure that defines the sub-pixel openings and other pixel defining stack portions may be covered by the mask layer 82.

[0284] In some embodiments, to form isolation portions of different isolation heights, the number of pixel defining layer layers removed by the etching process for the pixel defining stack portion PS1 (e.g., a first etching process) and the etching process for the pixel defining stack portion PS2 (e.g., a second etching process) is different; for example, the number of pixel defining layer layers removed by the second etching process (e.g., at least three layers) is greater than the number of pixel defining layer layers removed by the first etching process (e.g., at least two layers). In some embodiments, forming a stack of multiple pixel defining layers can facilitate controlling the number and thickness of etched material layers in the relevant etching process, thereby facilitating precise control of the isolation height of the isolation structure. In some embodiments, the number of pixel defining layer layers removed by the etching process can be less than or equal to the total number of pixel defining layer layers in the pixel defining structure, and the present disclosure does not limit the number of layers removed, as long as isolation portions of different isolation heights can be formed in each pixel defining stack portion. In some embodiments, the etching process may not remove the planarization structure, but the present disclosure is not limited to this. In some other embodiments, the etching process for one or more pixel defining stacks may further remove a portion of the planarization structure after forming the isolation openings through all pixel defining layers to form recesses in the planarization structure.

[0285] Referring to Figures 12F and 12G , mask layer 82 is removed, resulting in a pixel-defining structure PS having multiple sub-pixel openings and isolation openings. Subsequent processes may then be performed on pixel-defining structure PS to form a light-emitting stacked layer LE, a common electrode structure CE, and an encapsulation layer 120, thereby forming display panel 500e as shown in Figure 11 .

[0286] In the above embodiments, the pixel defining structure and / or a portion of an adjacent material layer (e.g., a material layer in a planarization structure) located on a side of the pixel defining structure close to the substrate is used as an isolation structure. The individual layers used to form the isolation structure may be referred to as isolation layers. The isolation structure comprises a plurality of stacked isolation layers (e.g., at least two isolation layers), and a first portion of the isolation layer (e.g., one or more layers) in the plurality of stacked layers extends beyond the edge of a second portion of the isolation layer (one or more layers) in a direction parallel to the main surface of the substrate, i.e., the second portion of the isolation layer is laterally indented relative to the first portion of the isolation layer in a direction parallel to the main surface of the substrate, thereby forming one or more undercut structures. In the display panels 500a to 500e of the above embodiments, the isolation portions of the isolation structure shown each include only one undercut structure, but this is for illustrative purposes only and the present disclosure is not limited thereto. In each embodiment, each isolation portion of the isolation structure may also have multiple undercut structures, and different isolation portions may have different numbers of undercut structures. The present disclosure does not limit the number of undercut structures included in each isolation portion.

[0287] Figure 13 shows a schematic cross-sectional view of an isolation structure having multiple undercut structures in a display panel according to other embodiments of the present disclosure. It should be understood that for the sake of simplicity, Figure 13 only schematically shows multiple isolation layers of the isolation structure, without specifically showing other components in the display panel.

[0288] Referring to FIG. 13 , in some embodiments, an isolation structure IS is formed on a bottom structure 200 , which may be a planarization structure, an electrode layer, or the like on a base substrate. The isolation structure IS may include multiple isolation layers stacked in a direction perpendicular to the main surface of the base substrate. The multiple isolation layers may include two or more inorganic insulating materials and / or organic insulating materials, and the number of stacked layers may be greater than or equal to two or greater than or equal to three. For example, the isolation structure IS may be a stacked structure of three layers, four layers, or six layers, such as a four-layer SiO / SiN / SiO / SiN stack, a six-layer SiO / SiN / SiO / SIN / Al 2 O 3 / SiCN stack, or the like. In some embodiments, the materials of the multiple isolation layers in the isolation structure IS may be selected from inorganic materials such as SiO, SiN, SiON, and SiCN, metal oxides such as Al 2 O 3 , NbO, and TiO, and organic glue. In some embodiments, the materials of each adjacent isolation layer in the multiple isolation layers are different.

[0289] For example, the isolation structure IS may include one or more first isolation layers and one or more second isolation layers stacked alternately in a direction perpendicular to the main surface of the substrate. For example, it may include a first isolation layer 201a, a second isolation layer 202a, a first isolation layer 201b, and a second isolation layer 202b stacked in sequence. In some embodiments, the plurality of first isolation layers 201a and 201b may include the same or different materials, and the materials of the two layers have a low etch selectivity in the etching process for forming the isolation openings; the plurality of second isolation layers 202a and 202b may include the same or different materials, and the materials of the two layers have a low etch selectivity in the etching process for forming the isolation openings. The first isolation layers 201a, 201b and the second isolation layers 202a, 202b may include different materials, and the first isolation layers and the second isolation layers may have a high etch selectivity in the etching process for forming the isolation openings.

[0290] In some embodiments, the plurality of second isolation layers 202a and 202b each have extensions ex01 and ex02 extending beyond the edges of the plurality of first isolation layers 201a and 201b in a direction parallel to the primary surface of the substrate. In other words, the plurality of first isolation layers 201a and 201b are laterally indented relative to adjacent second isolation layers 202a and 202b, forming undercut structures uc01 and uc02, respectively. The undercut structure uc01 is located between the second isolation layer 202a and the bottom structure 200 in a direction perpendicular to the primary surface of the substrate, while the undercut structure uc02 is located between adjacent second isolation layers 202a and 202b in a direction perpendicular to the primary surface of the substrate.

[0291] In some embodiments, the sizes of multiple undercut structures uc01, uc02 may be the same or different from each other. For example, the widths of multiple undercut structures uc01, uc02 in a direction parallel to the main surface of the substrate may be the same or different from each other, and the heights of multiple undercut structures uc01, uc02 in a direction perpendicular to the main surface of the substrate may also be the same or different from each other.

[0292] In some embodiments, the isolation height of each isolation portion in isolation structure IS may be defined by the sum of the thickness of the extension portion of the isolation layer and the height of the undercut structure. For example, in this example, the isolation height of isolation structure IS may be defined by the sum of the thickness of the extension portions ex01 and ex02 of second isolation layers 202a and 202b and the height of the undercut structures uc01 and uc02. For example, the heights of the undercut structures uc01 and uc02 may be substantially equal to the thickness of first isolation layers 201a and 201b, respectively.

[0293] In the example shown in FIG13 , the second isolation layer has extensions on both opposing sides parallel to the main surface of the substrate, and the first isolation layer has undercut structures on both opposing sides, but the present disclosure is not limited thereto. In other embodiments, one or more isolation portions in the isolation structure may have an extension and an undercut structure on only one side, and may not have either extension or undercut structure on the other side.

[0294] It should be understood that the isolation structure shown in Figure 13 can be applied to one or more isolation parts of the isolation structure of any one of the display panels 500a to 500e, so that the one or more isolation parts have multiple undercut structures, which can help further ensure that the charge generation layers in the light-emitting stacking parts of adjacent sub-pixels are disconnected from each other through the isolation parts.

[0295] In some embodiments, for the undercut structure of the isolation structure, if the width of the undercut structure is too small, it may not be possible to effectively achieve the isolation of adjacent sub-pixels. If the width of the undercut structure is too large, it may cause the isolation structure (e.g., the extension) to collapse or be damaged during subsequent processes. In some embodiments, the width of the undercut structure can be controlled within a suitable range by adjusting relevant process parameters (e.g., etching process parameters), thereby ensuring that the effective isolation of adjacent sub-pixels is achieved while avoiding the collapse of the isolation structure or damage during subsequent processes. For example, the width W of each undercut structure in the isolation structure can be set within the range of about 0.05μm to 0.5μm, thereby ensuring the structural stability of the isolation structure while achieving effective isolation of adjacent sub-pixels. It should be understood that the undercut structure in the isolation portion of various embodiments of the present disclosure can be set within the above range.

[0296] In the isolation structures of various embodiments of the present disclosure, the range of the first isolation height can be set to about 300 angstroms to 1250 angstroms, about 300 angstroms to 750 angstroms, or about 750 angstroms to 1250 angstroms; the range of the second isolation height can be set to about 600 angstroms to 1650 angstroms, about 700 angstroms to 1650 angstroms, or about 1000 angstroms to 1650 angstroms.

[0297] The present disclosure provides a display device comprising the display panel described in any of the above embodiments. The display device has the corresponding technical effects described above for the display panel, which will not be described in detail here. For example, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, and the embodiments of the present disclosure are not limited thereto.

[0298] There are a few points to note:

[0299] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0300] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0301] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel having a pixel region including a plurality of sub-pixel regions and a pixel spacing region located between adjacent sub-pixel regions, and comprising: substrate substrate; A plurality of sub-pixels are arranged on the substrate and are respectively located in the plurality of sub-pixel regions, wherein each sub-pixel comprises a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, each light-emitting device comprises a first electrode, a charge generation layer and a second electrode stacked in sequence, and the plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel adjacent to each other and used to display different colors; A pixel defining structure, disposed on the base substrate and having a plurality of sub-pixel openings to define light-emitting areas of the plurality of sub-pixels, wherein at least a portion of each light-emitting device is located in a corresponding sub-pixel opening; as well as An isolation structure is located in at least one of the pixel area and the pixel spacing area, and includes a portion with a first isolation height and a portion with a second isolation height, wherein the second isolation height is greater than the first isolation height, wherein the charge generation layers of adjacent sub-pixels among the multiple sub-pixels are disconnected from each other by at least one of the portion with the first isolation height and the portion with the second isolation height in the isolation structure.

2. The display panel according to claim 1, wherein the light-emitting devices of the first sub-pixel, the second sub-pixel and the third sub-pixel further include a first light-emitting layer, a second light-emitting layer and a third light-emitting layer located on a side of the respective charge generation layers close to the base substrate; The thickness of the second light-emitting layer and the thickness of the third light-emitting layer are greater than the thickness of the first light-emitting layer; and The charge generation layers of the first sub-pixel and the adjacent second sub-pixel or the third sub-pixel are disconnected from each other by at least a portion of the isolation structure having the first isolation height, and the charge generation layers of the second sub-pixel and the third sub-pixel are disconnected from each other by a portion of the isolation structure having the second isolation height.

3. The display panel according to claim 1 or 2, wherein The portion of the isolation structure having the first isolation height includes an isolation portion disposed in at least one of a first sub-pixel region where the first sub-pixel is located and a pixel spacing region between the first sub-pixel and an adjacent sub-pixel; The portion of the isolation structure having the second isolation height includes at least an isolation portion disposed in a pixel spacing region between the second sub-pixel and the third sub-pixel.

4. The display panel according to claim 3, wherein the portion of the isolation structure having the second isolation height also includes an isolation portion arranged in a pixel spacing region between the second sub-pixel and the first sub-pixel or in a pixel spacing region between the third sub-pixel and the first sub-pixel.

5. The display panel according to any one of claims 1-4, wherein the isolation structure comprises a plurality of pixel region isolation parts, which are respectively located in the plurality of sub-pixel regions, and at least a first pixel region isolation part located in a first sub-pixel region among the plurality of pixel region isolation parts has the first isolation height.

6. The display panel according to claim 5, wherein The plurality of pixel region isolating parts include a second pixel region isolating part and a third pixel region isolating part, which are respectively located in the sub-pixel regions where the second sub-pixel and the third sub-pixel are located; and The second pixel region isolating portion and the third pixel region isolating portion have the first isolation height, or at least a portion of the second pixel region isolating portion and the third pixel region isolating portion has the second isolation height.

7. The display panel according to any one of claims 1 to 6, wherein the isolation structure comprises an inter-pixel isolation portion located between adjacent sub-pixels, and the inter-pixel isolation portion comprises: A first inter-pixel isolation portion is located between the first sub-pixel and the second sub-pixel or in a pixel spacing region between the first sub-pixel and the third sub-pixel; as well as The second inter-pixel isolation portion is located in the pixel spacing region between the second sub-pixel and the third sub-pixel. 8 . The display panel according to claim 7 , wherein the first inter-pixel isolation portion and the second inter-pixel isolation portion have the same second isolation height. 9 . The display panel according to claim 7 , wherein the first inter-pixel isolation portion has the first isolation height, and the second inter-pixel isolation portion has the second isolation height.

10. The display panel according to claim 7, wherein the first inter-pixel isolation portion and the second inter-pixel isolation portion are connected to or disconnected from each other, and the inter-pixel isolation portion includes an annular portion in a closed ring shape or an open ring shape, and the light-emitting area of ​​one or more sub-pixels among the multiple sub-pixels is surrounded by the annular portion in a direction parallel to the main surface of the base substrate.

11. The display panel according to any one of claims 7 to 10, wherein at least one of the first inter-pixel isolation portion and the second inter-pixel isolation portion each includes a plurality of isolation sub-portions arranged side by side between adjacent sub-pixels along an arrangement direction of the adjacent sub-pixels.

12. The display panel according to any one of claims 1 to 11, wherein the isolation structure comprises: A first annular portion surrounds a light emitting area of ​​a corresponding one of the plurality of sub-pixels in a direction parallel to the main surface of the base substrate; as well as The second annular portion is located on a side of the first annular portion away from the sub-pixel and surrounds the first annular portion and the sub-pixel in a direction parallel to the main surface of the base substrate.

13. The display panel according to any one of claims 1 to 12, wherein the plurality of sub-pixels include a plurality of pixel units arranged in an array, and include: A first pixel column, comprising a plurality of said first sub-pixels arranged along a first direction; as well as A second pixel column comprises a plurality of the second sub-pixels and a plurality of the third sub-pixels alternately arranged along a first direction, one or more of the first pixel columns and one or more of the second pixel columns are alternately arranged along a second direction intersecting the first direction, wherein each first sub-pixel in the first pixel column and one second sub-pixel and one third sub-pixel in the second pixel column are adjacent to each other and form a pixel unit, Each of the light-emitting regions in the plurality of sub-pixels is surrounded by a corresponding isolation portion in the isolation structure in the sub-pixel arrangement direction.

14. The display panel according to claim 13, wherein The isolation structure includes at least one of a plurality of pixel region isolation parts and inter-pixel isolation parts; The plurality of pixel region isolation parts respectively surround the light emitting regions of the plurality of sub-pixels in a direction parallel to the main surface of the base substrate; The inter-pixel isolation portion comprises: A first inter-pixel isolation portion extending along the first direction and located between adjacent first pixel columns and second pixel columns in the second direction; as well as The second inter-pixel isolation portion extends along the second direction and is located between the adjacent second sub-pixel and third sub-pixel in the first direction.

15. The display panel according to claim 14, wherein the first inter-pixel isolation portion extends continuously along the first direction and is connected to a plurality of the second inter-pixel isolation portions; or The first pixel isolation portion and the second pixel isolation portion are disconnected from each other, and the first The inter-pixel isolation portion has a gap and includes a plurality of first pixel isolation portions disconnected from each other, each of which is located between a corresponding first sub-pixel and an adjacent second sub-pixel and / or between the first sub-pixel and an adjacent third sub-pixel.

16. The display panel according to claim 15, wherein an orthographic projection of the first subpixel on a first reference plane extending along the first direction has a first overlapping portion with an orthographic projection of the second subpixel on the first reference plane, and has a second overlapping portion with an orthographic projection of the third subpixel on the first reference plane; The orthographic projection of the notch of the first inter-pixel isolation portion on the first reference plane is offset from the first overlapping portion and the second overlapping portion, and the first overlapping portion and the second overlapping portion are respectively located within the orthographic projection of the corresponding first inter-pixel isolation portion on the first reference plane.

17. A display panel according to any one of claims 14 to 16, wherein an overlapping portion of the orthographic projections of adjacent second sub-pixels and third sub-pixels located in the same second pixel column on the second reference plane extending along the second direction is located within the orthographic projection of the second inter-pixel isolation portion on the second reference plane.

18. The display panel according to any one of claims 1 to 17, further comprising a common electrode structure, and the second electrodes of the plurality of sub-pixels share the common electrode structure, wherein the common electrode structure comprises: A second electrode layer is disposed on a side of the charge generating layer away from the substrate; as well as The auxiliary electrode layer is arranged on a side of the second electrode layer away from the base substrate and is electrically connected to the second electrode layer, and the orthographic projection of the auxiliary electrode layer on the base substrate overlaps with the orthographic projection of the isolation structure on the base substrate. 19 . The display panel according to claim 18 , wherein an orthographic projection of at least a portion of the isolation structure on the base substrate is located within an orthographic projection of the auxiliary electrode layer on the base substrate. 20 . The display panel according to claim 18 , wherein the second electrode layer includes a portion disconnected at the isolation structure, and the disconnected portion of the second electrode layer is electrically connected through the auxiliary electrode layer.

21. The display panel according to any one of claims 18 to 20, wherein The auxiliary electrode layer includes at least one of a first auxiliary electrode layer and a second auxiliary electrode layer; The first auxiliary electrode layer extends in the pixel area and the pixel spacing area, and the orthographic projection of the second electrode layer on the base substrate is located within the orthographic projection of the first auxiliary electrode layer on the base substrate; and The orthographic projection of the second auxiliary electrode layer on the base substrate overlaps with the orthographic projection of at least part of the isolation structure on the base substrate, and is offset from the orthographic projection of at least part of the light emitting areas of the plurality of sub-pixels on the base substrate.

22. The display panel according to any one of claims 1 to 21, comprising a light emitting stacked layer, wherein the light emitting stacked layer comprises: A first light-emitting stacked portion, comprising at least a charge generation layer of the first sub-pixel; A second light-emitting stacked portion, comprising at least a charge generation layer of the second sub-pixel; A third light-emitting stacked portion, comprising at least a charge generation layer of the third sub-pixel; as well as a dummy stacking portion, located between adjacent light-emitting stacking portions among the first light-emitting stacking portion, the second light-emitting stacking portion and the third light-emitting stacking portion, wherein the first light emitting stack portion, the second light emitting stack portion and the third light emitting stack portion each include a first stack sub-portion and a second stack sub-portion; In each light-emitting stacking portion, the first stacking sub-portion is located in a light-emitting area defined by a sub-pixel opening of the pixel defining structure, and the second stacking sub-portion is located on a side of the portion of the pixel defining structure defining the sub-pixel opening away from the base substrate. 23 . The display panel of claim 22 , wherein the charge generation layers of the first stack sub-portion and the second stack sub-portion of the first light emitting stack portion are disconnected from each other by a first pixel region isolating portion of the isolation structure. 24 . The display panel according to claim 23 , wherein a step difference between the charge generation layers of the first stacking sub-section and the second stacking sub-section of the first light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the first isolation height. 25 . The display panel of claim 22 , wherein the charge generation layers of the first stack sub-section and the second stack sub-section of the first light emitting stack section are connected to each other.

26. The display panel according to claim 22, wherein The charge generation layers of the first stack sub-section and the second stack sub-section of the second light emitting stack section are connected to each other or disconnected from each other; The charge of the first stack sub-section and the second stack sub-section of the third light emitting stack section The layers are generated to be connected to each other or disconnected from each other.

27. The display panel according to any one of claims 22 to 26, wherein the dummy stacking portion comprises: The first dummy stacking portion is located in a pixel spacing region between a first sub-pixel and a second sub-pixel adjacent to each other, and includes a first dummy charge generating layer, and the first dummy charge generating layer and the charge generating layers in the first light-emitting stacking portion and the second light-emitting stacking portion are disconnected from each other by a first inter-pixel isolation portion of the isolation structure.

28. A display panel according to claim 27, wherein the step difference between the first virtual charge generating layer and the charge generating layer in the second stacking sub-section of the first light-emitting stacking section or the second light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the first isolation height or the second isolation height.

29. The display panel according to any one of claims 22 to 28, wherein the dummy stacking portion comprises: The second dummy stacking part is located in the pixel spacing area between the second sub-pixel and the third sub-pixel adjacent to each other, and includes a second dummy charge generating layer, and the second dummy charge generating layer and the charge generating layers in the second light-emitting stacking part and the third light-emitting stacking part are disconnected from each other by the second inter-pixel isolation part of the isolation structure.

30. The display panel according to claim 29, wherein the step difference between the second dummy charge generating layer and the charge generating layer in the second stacking sub-section of the second light-emitting stacking section or the third light-emitting stacking section in a direction perpendicular to the main surface of the base substrate is defined by the second isolation height. 31 . The display panel according to claim 22 , wherein at least one of the dummy stacked parts is connected to a dummy electrode, and the dummy electrode and the first electrode are disposed in the same electrode layer and are electrically isolated from each other.

32. The display panel according to any one of claims 1 to 31, wherein The pixel defining structure at least includes a first pixel defining layer and a second pixel defining layer, wherein the second pixel defining layer is located on a side of the first pixel defining layer away from the base substrate and includes an extension portion, wherein the extension portion extends beyond an edge of the first pixel defining layer in a direction parallel to a main surface of the base substrate and has an undercut structure between the extension portion and a material layer located on a side of the first pixel defining layer close to the base substrate, The isolation structure includes at least the extension portion and the undercut structure.

33. The display panel according to claim 32, further comprising: A planarization structure is disposed on the base substrate, wherein the plurality of first electrodes of the plurality of sub-pixels are located on a side of the planarization structure away from the base substrate; The pixel defining structure is located on a side of the planarization structure and the plurality of first electrodes away from the base substrate, and the plurality of sub-pixel openings respectively expose portions of the plurality of first electrodes. The pixel defining structure further includes an isolation opening located in a pixel spacing region between adjacent sub-pixels and exposing a portion of the surface of the planarization structure.

34. The display panel according to claim 33, wherein the pixel defining structure comprises: a sub-pixel opening defining portion defining the sub-pixel opening and serving as a pixel region isolating portion of the isolation structure, the sub-pixel opening defining portion comprising a first extending portion and having a first undercut structure between the first extending portion and the first electrode; and The isolation opening defining portion defines the isolation opening and serves as an inter-pixel isolation portion of the isolation structure. The isolation opening defining portion includes a second extension portion and has a second undercut structure between the second extension portion and the planarization structure. 35 . The display panel according to claim 34 , wherein the planarization structure has a recess, the recess is spatially connected to the isolation opening, and the sum of the depth of the isolation opening and the depth of the recess defines the second isolation height.

36. The display panel according to claim 34 or 35 further includes a dummy electrode located between the planarization structure and the isolation opening defining portion, the dummy electrode having an electrode opening, the electrode opening being spatially connected to the isolation opening, and the sum of the depth of the isolation opening and the depth of the electrode opening defining the second isolation height.

37. The display panel according to claim 32, wherein the pixel defining structure further comprises: a pixel defining body layer, located on a side of the first pixel defining layer close to the base substrate, defining the sub-pixel opening, and comprising a first body portion located between the first sub-pixel and the adjacent second sub-pixel or the third sub-pixel and a second body portion located between the second sub-pixel and the third sub-pixel, The first pixel defining layer and the second pixel defining layer include a first isolation portion and a second isolation portion respectively located on the first main portion and the second main portion, each isolation portion includes the extension portion of the second pixel defining layer, and has an undercut structure between the extension portion and the pixel defining main layer.

38. The display panel according to claim 37, wherein The first isolation portion has a first isolation opening, exposing a portion of the surface of the first main portion, and the depth of the first isolation opening defines the first isolation height; and The second isolation portion has a second isolation opening that exposes a portion of the surface of the second main body portion, and the second main body portion has a main body recess that is spatially connected to the second isolation opening. The sum of the depth of the second isolation opening and the main body recess defines the second isolation height.

39. The display panel according to claim 32, wherein the pixel definition structure comprises a plurality of pixel definition layers sequentially stacked in a direction perpendicular to the main surface of the base substrate, and the second pixel definition layer is one of the plurality of pixel definition layers farthest from the base substrate, and the pixel definition structure comprises a sub-pixel opening definition portion and an isolation opening definition portion; In the sub-pixel opening defining portion, the side walls of the plurality of pixel defining layers are connected to each other and together constitute the side walls defining the sub-pixel opening; The isolation opening defining portion includes the extension portion and the undercut structure constituting the isolation structure.

40. The display panel according to claim 39, wherein the pixel defining structure comprises: A first pixel stacking portion is located between the first sub-pixel and the second sub-pixel and has a first recess including one or more first isolation openings; as well as A second pixel stacking portion, located between the second sub-pixel and the third sub-pixel, and having a second recess including one or more second isolation openings; The edge portion of each pixel stacking portion serves as a sub-pixel opening defining portion to define a portion of a corresponding sub-pixel opening, and the recessed portion of each pixel stacking portion serves as an isolation opening defining portion and includes one or more pixel defining layer extensions and one or more undercut structures. The display panel according to claim 40 , wherein a depth of the first recess is smaller than a depth of the second recess.

42. A display panel according to claim 32, wherein the pixel defining structure includes a plurality of first pixel defining layers and a plurality of second pixel defining layers alternately stacked in a direction perpendicular to the main surface of the base substrate, and includes a plurality of undercut structures, each undercut structure being located on a side of an extension portion of a corresponding second pixel defining layer close to the base substrate.

43. The display panel of claim 32, wherein the first pixel-defining layer and the second pixel-defining layer comprise different materials.

44. The display panel of claim 43, wherein at least one of the first pixel-defining layer and the second pixel-defining layer comprises an inorganic material.

45. The display panel according to claim 43 or 44, wherein One of the first pixel defining layer and the second pixel defining layer includes aluminum oxide, and the other of the first pixel defining layer and the second pixel defining layer includes silicon nitride or silicon oxide; or One of the first pixel defining layer and the second pixel defining layer includes silicon oxide, and the other of the first pixel defining layer and the second pixel defining layer includes silicon carbonitride; or One of the first pixel defining layer and the second pixel defining layer includes titanium oxide, and the other of the first pixel defining layer and the second pixel defining layer includes niobium oxide.

46. ​​The display panel of claim 32, wherein a width of the undercut structure in a direction parallel to the main surface of the base substrate ranges from 0.05 μm to 0.5 μm.

47. The display panel according to any one of claims 1-46, wherein the first isolation height ranges from 300 angstroms to 1250 angstroms, and the second isolation height ranges from 600 angstroms to 1650 angstroms.

48. A display device comprising the display panel according to any one of claims 1-47.

49. A method for manufacturing a display panel, the display panel having a pixel region including a plurality of sub-pixel regions and a pixel spacing region between adjacent sub-pixel regions, the manufacturing method comprising: providing a substrate base plate; Forming a plurality of sub-pixels on the substrate, the plurality of sub-pixels are respectively located in the plurality of sub-pixel regions, wherein each sub-pixel comprises a light-emitting device and a sub-pixel circuit for driving the light-emitting device to emit light, each light-emitting device comprises a first electrode, a charge generation layer and a second electrode stacked in sequence, and the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel adjacent to each other and for displaying different colors; forming a pixel defining structure having a plurality of sub-pixel openings to define light-emitting areas of the plurality of sub-pixels, wherein at least a portion of each light-emitting device is located in a corresponding sub-pixel opening; as well as An isolation structure is formed in at least one of the pixel area and the pixel spacing area, the isolation structure including a portion having a first isolation height and a portion having a second isolation height, the second isolation height being greater than the first isolation height, wherein the charge generation layers of adjacent sub-pixels among the multiple sub-pixels are disconnected from each other by the isolation structure.

50. The method for manufacturing a display panel according to claim 49, wherein forming the pixel defining structure and the isolation structure comprises: Sequentially forming a first pixel defining layer and a second pixel defining layer on one side of the planarization structure on the base substrate; Performing a first removal process to remove a portion of the second pixel definition layer and form an opening in the second pixel definition layer, wherein the opening is defined by an extension of the second pixel definition layer and exposes a portion of the surface of the first pixel definition layer; as well as A second removal process is performed to remove the portion of the first pixel defining layer exposed by the opening and the portion covered by the extension portion of the second pixel defining layer, and an undercut structure is formed on a side of the extension portion close to the base substrate, wherein the isolation structure includes the extension portion and the undercut structure. 51 . The method for manufacturing a display panel according to claim 50 , wherein after the second removing process, isolation openings exposing a portion of the surface of the planarization structure are formed in the first pixel defining layer and the second pixel defining layer.

52. The method for manufacturing a display panel according to claim 51, further comprising: A third removal process is performed to remove the portion of the planarization structure exposed by the isolation opening and form a recess in the planarization structure.

53. The method for manufacturing a display panel according to claim 50, wherein forming the pixel defining structure further comprises: forming a pixel defining body layer before forming the first pixel defining layer, wherein after the second removing process, a plurality of openings in the first pixel defining layer and the second pixel defining layer expose a portion of a surface of the pixel defining body layer; as well as A third removing process is performed to remove portions of the pixel defining body layer exposed by some of the openings to form a recess in a partial region of the pixel defining body layer.

54. The method for manufacturing a display panel according to claim 50, wherein forming the pixel defining structure and the isolation structure comprises: forming a plurality of pixel defining layers in sequence on the base substrate; Performing a first removal process on a first pixel stacking portion of the plurality of pixel defining layers located in a first pixel spacing region to remove portions of at least two pixel defining layers among the plurality of pixel defining layers, and forming a first recess including one or more first isolation openings in the first pixel stacking portion; as well as The second pixel stacking portion of the plurality of pixel defining layers located in the second pixel spacing region is subjected to a first A second removal process is used to remove portions of at least three pixel definition layers among the plurality of pixel definition layers, and to form a second recess including one or more second isolation openings in the second pixel stacking portion.

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