Prediction model training method and apparatus, resistance-state retention restoration method and apparatus, and device

Abstract

Provided in the present disclosure are a prediction model training method and apparatus, a resistance-state retention restoration method and apparatus, and a device. The prediction model training method comprises: performing a first preset number of erase / write operations on all M resistive random access memories in a conductive state, so as to obtain M first resistive random access memories and erase / write operation voltages respectively corresponding to the M first resistive random access memories; for each of the M first resistive random access memories, performing, within a first preset duration, a continuous read operation on the first resistive random access memory at every second preset duration, so as to obtain first resistance-state data; performing a step-by-step read operation on the first resistive random access memory at every second preset duration, so as to obtain second resistance-state data; on the basis of the first resistance-state data, second resistance-state data and erase / write operation voltage corresponding to each of the M first resistive random access memories, obtaining training sample data; and on the basis of the training sample data, training a resistance-state retention prediction model, so as to obtain a target prediction model.

Description

Prediction model training method, resistance state retention repair method, device and equipment Technical Field

[0001] The present disclosure relates to the fields of computer technology, artificial intelligence technology, and microelectronics technology, and in particular to a prediction model training method, a resistance state retention repair method, a device and equipment, a medium, and a program product. Background Art

[0002] Resistive Random Access Memory (RRAM) is a type of embedded non-volatile memory (NVM) suitable for advanced process nodes. Due to its compatibility with CMOS processes, low power consumption, and high reliability, RRAM holds great promise for applications in edge computing and IoT devices.

[0003] In related technologies, it is difficult to determine whether RRAM information storage is stable. Therefore, the stability of RRAM information storage has become a major factor hindering the industrialization of RRAM. There is an urgent need to find a method to accurately predict the information storage stability of RRAM and a method to repair RRAM in an unstable state.

[0004] Summary of the Invention

[0005] In view of the above problems, the present disclosure provides a prediction model training method, a resistance state preservation repair method, an apparatus and equipment, a medium and a program product.

[0006] According to a first aspect of the present disclosure, a method for training a resistance state retention prediction model is provided, comprising:

[0007] Performing a first preset number of erase / write operations on the M resistive random access memories in the on state to obtain M first resistive random access memories and erase / write operation voltages corresponding to the M first resistive random access memories;

[0008] For each of the M first resistive memories, continuously read the first resistive memory every second preset time period within a first preset time period to obtain first resistance state data;

[0009] Performing a step-by-step read operation on the first resistive random access memory at intervals of a second preset time to obtain second resistive state data;

[0010] Obtaining training sample data according to each of the first resistance state data, each of the second resistance state data, and the erase / write operation voltage corresponding to the M first resistive random access memories;

[0011] The resistance state retention prediction model is trained according to the above training sample data;

[0012] When the resistance state retention prediction model predicts the resistance state retention of the M first resistive random access memories with an accuracy greater than or equal to a first preset value, a target prediction model is obtained.

[0013] A second aspect of the present disclosure provides a method for repairing resistance state retention, comprising:

[0014] Performing a first preset number of erase / write operations on a target resistive random access memory in a conductive state to obtain a first target resistive random access memory and an erase / write operation voltage corresponding to the first target resistive random access memory;

[0015] Performing a continuous read operation on the first target resistive random access memory to obtain third resistive state data;

[0016] Performing a step-by-step read operation on the first target resistive random access memory to obtain fourth resistive state data;

[0017] Obtaining target resistance state data according to the third resistance state data, the fourth resistance state data, and the erase / write operation voltage corresponding to the first target resistive random access memory;

[0018] Inputting the target resistance state data into the target prediction model to obtain a resistance state retention prediction result corresponding to the first target resistive random access memory;

[0019] When the retention prediction result indicates that the first target resistive random access memory fails after a preset time period, a repair operation is performed on the first target resistive random access memory to obtain a second target resistive random access memory.

[0020] A third aspect of the present disclosure provides a training device for a resistance state retention prediction model, comprising:

[0021] A first obtaining module is configured to perform a first preset number of erase / write operations on each of the M resistive random access memories in the on state, to obtain M first resistive random access memories and erase / write operation voltages corresponding to the M first resistive random access memories;

[0022] a second obtaining module, configured to perform a continuous read operation on each of the M first resistive random access memories within a first preset time period and at intervals of a second preset time period to obtain first resistance state data;

[0023] a third obtaining module, configured to perform a step-by-step reading operation on the first resistive random access memory at intervals of a second preset time to obtain second resistance state data;

[0024] A fourth obtaining module is configured to obtain training sample data according to each of the first resistance state data, each of the second resistance state data, and the erase / write operation voltage corresponding to each of the M first resistive random access memories;

[0025] A training module, used for training the resistance state retention prediction model based on the above training sample data;

[0026] The fifth obtaining module is configured to obtain a target prediction model when the resistance state retention prediction model has a prediction accuracy rate for the resistance state retention of the M first resistive random access memories greater than or equal to a first preset value.

[0027] A fourth aspect of the present disclosure provides a resistance-state-maintaining repair device, comprising:

[0028] A first target resistive memory and an erase / write operation voltage obtaining module is used in a sixth obtaining module for performing a first preset number of erase / write operations on the target resistive memory in the on state to obtain the first target resistive memory and an erase / write operation voltage corresponding to the first target resistive memory;

[0029] A third resistance state data obtaining module is configured to perform a continuous read operation on the first target resistive random access memory to obtain third resistance state data;

[0030] a fourth resistance state data obtaining module, configured to perform a step-by-step read operation on the first target resistive random access memory to obtain fourth resistance state data;

[0031] a target resistance state data obtaining module, configured to obtain target resistance state data according to the third resistance state data, the fourth resistance state data and the erase / write operation voltage corresponding to the first target resistive random access memory;

[0032] A prediction result obtaining module, configured to input the target resistance state data into the target prediction model to obtain a resistance state retention prediction result corresponding to the first target resistive random access memory;

[0033] The second target resistive random access memory obtaining module is configured to perform a repair operation on the first target resistive random access memory to obtain a second target resistive random access memory when the retention prediction result indicates that the first target resistive random access memory fails after a preset time period.

[0034] The fifth aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors execute the training method of the resistive state retention prediction model and the resistive state retention repair method.

[0035] The sixth aspect of the present disclosure further provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to execute the above-mentioned training method of the resistance state retention prediction model and the resistance state retention repair method.

[0036] The seventh aspect of the present disclosure further provides a computer program product, including a computer program, which, when executed by a processor, implements the training method of the resistance state retention prediction model and the resistance state retention repair method. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] FIG1 schematically illustrates an application scenario of a method for training a resistance state retention prediction model and a method for repairing resistance state retention according to an embodiment of the present disclosure;

[0039] FIG2 schematically shows a flow chart of a method for training a resistance state retention prediction model according to an embodiment of the present disclosure;

[0040] FIG3 schematically shows a schematic diagram of N identical first preset voltages according to an embodiment of the present disclosure;

[0041] FIG4 schematically shows a schematic diagram of P gradually increasing second preset voltages according to an embodiment of the present disclosure;

[0042] FIG5 schematically shows a flow chart of collecting resistance state data of a first resistive memory according to an embodiment of the present disclosure;

[0043] FIG6 schematically shows a flow chart of a method for training a resistance state retention prediction model according to another embodiment of the present disclosure;

[0044] FIG7 schematically shows a schematic diagram of a resistance value of a resistive random access memory device drifting toward a low resistance according to an embodiment of the present disclosure;

[0045] FIG8 schematically shows a schematic diagram of a resistive memory array according to an embodiment of the present disclosure;

[0046] FIG9 schematically shows a flow chart of a method for repairing resistance state retention according to an embodiment of the present disclosure;

[0047] FIG10 schematically shows a flow chart of a method for repairing resistance state retention according to another embodiment of the present disclosure;

[0048] FIG11 schematically shows a schematic diagram of a repair voltage used in a repair operation according to an embodiment of the present disclosure;

[0049] FIG12 schematically shows a schematic diagram of reference resistance values ​​of M first resistive memories after every second preset time period according to an embodiment of the present disclosure;

[0050] FIG13 schematically illustrates the training results of the retention prediction model according to an embodiment of the present disclosure;

[0051] FIG14 schematically shows the test results of the retention prediction model according to an embodiment of the present disclosure;

[0052] FIG15 schematically shows a structural block diagram of a training device for a resistance state retention prediction model according to an embodiment of the present disclosure;

[0053] FIG16 schematically shows a structural block diagram of a resistance state preserving repair device according to an embodiment of the present disclosure; and

[0054] FIG17 schematically shows a block diagram of an electronic device suitable for implementing a method for training a resistance state retention prediction model and a method for repairing resistance state retention according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0056] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0057] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0058] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0059] In related technologies, it is difficult to determine whether RRAM information storage is stable. Therefore, the stability of RRAM information storage has become a major factor hindering the industrialization of RRAM. There is an urgent need to find a method to accurately predict the information storage stability of RRAM and a method to repair RRAM in an unstable state.

[0060] According to the embodiments of the present disclosure, the retention of the resistive state is a key characteristic of RRAM and an important indicator for measuring the stability of RRAM information storage. For example, in an IoT terminal device, if the resistive state of the RRAM fails, the RRAM becomes unstable, which can lead to data storage errors in the RRAM chip of the IoT terminal device. For edge computing, if the resistive state of the RRAM fails, the RRAM becomes unstable, which can cause changes in the network weights of the neural network stored in the RRAM, ultimately affecting the accuracy of the neural network algorithm.

[0061] Therefore, the stability of information storage in RRAM can be determined by judging the resistance state retention of RRAM. Then, if it is determined that the resistance state of RRAM is about to fail, the RRAM with the resistance state about to fail can be repaired to obtain RRAM with better resistance state retention, thereby obtaining RRAM in a stable state.

[0062] In order to at least partially solve the technical problems existing in the related art, the embodiments of the present disclosure provide a prediction model training method, a resistance state retention repair method, an apparatus and equipment, a medium and a program product, which can be applied to the fields of computer technology, artificial intelligence technology and microelectronics technology.

[0063] According to the embodiments of the present disclosure, resistance state failure caused by the decrease in the resistance state retention of RRAM mainly occurs in the high resistance state. Therefore, the training method of the resistance state retention prediction model and the resistance state retention repair method provided in the embodiments of the present disclosure are mainly aimed at predicting the resistance state retention of RRAM in the high resistance state and repairing RRAM that is about to fail in the high resistance state.

[0064] According to an embodiment of the present disclosure, retention characterizes the ability of the resistive memory to remain in the high-resistance state after being placed in the high-resistance state for a second preset time period when the resistive memory is in the high-resistance state. It can also be called the ability of the resistive memory to remain in the high-resistance state within the second preset time period.

[0065] FIG1 schematically shows an application scenario diagram of a method for training a resistance state retention prediction model and a method for repairing resistance state retention according to an embodiment of the present disclosure.

[0066] As shown in Figure 1, an application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 is a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables.

[0067] The user may use at least one of the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications may be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (only as examples).

[0068] The first terminal device 101 , the second terminal device 102 , and the third terminal device 103 may be various electronic devices having display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, and the like.

[0069] The server 105 may be a server that provides various services, such as a background management server (for example only) that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103. The background management server may analyze and process received user requests and other data, and feed back processing results (e.g., web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0070] It should be noted that the training method of the resistance state retention prediction model and the resistance state retention repair method provided in the embodiments of the present disclosure can generally be executed by the server 105. Accordingly, the training device of the resistance state retention prediction model and the resistance state retention repair method provided in the embodiments of the present disclosure can generally be set in the server 105. The training method of the resistance state retention prediction model and the resistance state retention repair method provided in the embodiments of the present disclosure can also be executed by a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105. Accordingly, the training device of the resistance state retention prediction model and the resistance state retention repair method provided in the embodiments of the present disclosure can also be set in a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105.

[0071] It should be understood that the number of terminal devices, networks, and servers in Figure 1 is merely illustrative and any number of terminal devices, networks, and servers may be provided as required.

[0072] The following will describe in detail the training method of the resistance state retention prediction model and the resistance state retention repair method of the disclosed embodiment through Figures 2 to 14 based on the scenario described in Figure 1.

[0073] FIG2 schematically shows a flow chart of a method for training a resistance state retention prediction model according to an embodiment of the present disclosure.

[0074] As shown in FIG. 2 , the method for training the resistance state retention prediction model of this embodiment includes operations S210 to S260 .

[0075] In operation S210 , a first preset number of erase / write operations are performed on M resistive memories in a conductive state to obtain M first resistive memories and erase / write operation voltages corresponding to the M first resistive memories.

[0076] According to the embodiments of the present disclosure, M can be selected according to actual conditions and is not limited here. For example, M can be 200, 300, or 400.

[0077] According to an embodiment of the present disclosure, the M resistive random access memories may be M oxide-based RRAMs.

[0078] According to an embodiment of the present disclosure, M resistive memories in a conducting state can be obtained by performing a forming operation, ie, a FORMING operation, on each of the M resistive memories.

[0079] According to an embodiment of the present disclosure, the FORMING operation may include: for each of the M resistive memories, applying a 1.7V / 3us voltage pulse to the source line end (SL end) of the resistive memory, then applying a 0.3V / 700ns voltage pulse to the bit line end (BL end) of the resistive memory, and then reading the resistance value of the resistive memory. If the resistance value of the resistive memory is less than 700KΩ, it indicates that the forming operation is successful, and a resistive memory in a conductive state is obtained.

[0080] According to the embodiment of the present disclosure, the first preset number can be selected according to actual conditions and is not limited here. For example, the first preset number can be 10, 30, 50, 100, 500, 1000, etc.

[0081] According to an embodiment of the present disclosure, after performing a first preset number of erase and write operations on each of the M resistive random access memories in the on state, the resulting M first resistive random access memories are all in a high-resistance state. The first resistive random access memories can be characterized as being in a high-resistance state when their resistance is greater than 80 kΩ.

[0082] According to an embodiment of the present disclosure, before performing a first preset number of erase and write operations on M resistive memories, quality inspection is performed on the M resistive memories to ensure that after performing the first preset number of erase and write operations on the M resistive memories, the resistance values ​​of the M resistive memories are all greater than 80kΩ. At the same time, it can be preliminarily determined that the M resistive memories are all qualified devices and can be used in actual edge computing and Internet of Things terminal devices.

[0083] According to an embodiment of the present disclosure, performing a first preset number of erase and write operations on M resistive memories in an on state to obtain M first resistive memories and erase and write operation voltages corresponding to the M first resistive memories includes: performing a first preset number of incremental step-pulse programming (ISPP) operations on the M resistive memories in an on state.

[0084] According to an embodiment of the present disclosure, each ISPP operation performed on each resistive random access memory in the on state includes: performing a set sub-operation on the resistive random access memory using at least one set voltage, and then performing a reset sub-operation on the resistive random access memory using at least one reset voltage.

[0085] According to an embodiment of the present disclosure, the erase / write operation voltage may include a set sub-operation voltage and a reset sub-operation voltage. The erase / write operation voltage may also include a set sub-operation voltage, a reset sub-operation voltage, and a last reset sub-operation voltage. The last set voltage in each ISPP operation may be used as the set sub-operation voltage, and the last reset voltage may be used as the reset sub-operation voltage.

[0086] According to an embodiment of the present disclosure, using at least one set voltage to perform a set sub-operation on a resistive random access memory includes: for each of the M resistive random access memories in the on state, applying a 1.2V / 700ns voltage pulse to the BL end of the resistive random access memory, and then applying a 0.3V / 700ns voltage pulse to the BL end of the resistive random access memory, and then reading the resistance value of the resistive random access memory. When the resistance value of the resistive random access memory is less than 40KΩ, it indicates that the resistive random access memory is in a low resistance state, the set sub-operation is successful, and at least one subsequent reset sub-operation can be performed. When the resistance value of the resistive random access memory is greater than or equal to 40KΩ, the set voltage 1.2V is increased by 0.1V to obtain a second set voltage of 1.3V. Subsequently, the set sub-operation can be continued on the resistive random access memory according to the second set voltage 1.3V, and so on, until the set sub-operation is successful or the number of set sub-operations reaches 7 times.

[0087] According to an embodiment of the present disclosure, using at least one reset voltage to perform a reset sub-operation on a resistive random access memory includes: for each resistive random access memory after a set operation, applying a 1.6V / 700ns voltage pulse to the SL end of the resistive random access memory, and then applying a 0.3V / 700ns voltage pulse to the BL end of the resistive random access memory, reading the resistance value of the resistive random access memory; when the resistance value of the resistive random access memory is greater than 80kΩ, the reset sub-operation is successful, and a first resistive random access memory is obtained; when the resistance value of the resistive random access memory is less than or equal to 80kΩ, the reset voltage 1.6V is increased by 0.1V to obtain a second reset voltage of 1.7V; and subsequently, the reset sub-operation can be continued on the resistive random access memory according to the second reset voltage 1.7V, and so on, until the set sub-operation is successful or the number of set sub-operations reaches 7 times.

[0088] According to an embodiment of the present disclosure, in the last ISPP operation performed on each resistive memory, the reset sub-operation included in the last ISPP operation can successfully reset the resistive memory, thereby obtaining a first resistive memory with a resistance greater than 80 kΩ.

[0089] In operation S220 , for each of the M first resistive memories, a continuous read operation is performed on the first resistive memory every second preset time period within a first preset time period to obtain first resistive state data.

[0090] According to an embodiment of the present disclosure, the first preset duration can be selected according to actual conditions and is not limited here. For example, the first preset duration can be 540 minutes, 1080 minutes, 2 days, 3 days or 5 days.

[0091] According to an embodiment of the present disclosure, the second preset duration can be selected according to actual conditions and is not limited here. For example, the second preset duration can be 60 minutes, 360 minutes, or 600 minutes.

[0092] According to an embodiment of the present disclosure, during a continuous read operation on the first resistive memory, the multiple read operation voltages applied to the first resistive memory during the continuous read operation are the same. Therefore, the obtained first resistance state data can reflect the fluctuation of the resistance value of the first resistive memory under the same read operation voltage.

[0093] In operation S230 , a read operation is performed on the first resistive memory at intervals of a second preset time to obtain second resistive state data.

[0094] According to an embodiment of the present disclosure, during a step-by-step read operation on the first resistive memory, the multiple read operation voltages applied to the first resistive memory by the step-by-step read operation are different. Therefore, the obtained second resistance state data can reflect the fluctuation of the resistance value of the second resistive memory under different read operation voltages.

[0095] In operation S240 , training sample data is obtained according to the first resistance state data, the second resistance state data, and the erase / write operation voltages respectively corresponding to the M first resistive memories.

[0096] According to an embodiment of the present disclosure, the first resistance state data of each first resistive memory at each second preset time length, the second resistance state data at each second preset time length, and the erase operation voltage in the erase operation can be spliced ​​and normalized to obtain training sample data of each first resistive memory at each second preset time length.

[0097] In operation S250 , a resistance state retention prediction model is trained according to training sample data.

[0098] According to an embodiment of the present disclosure, the training sample data and the training sample data of each first resistive memory at each second preset time length can be used as input respectively to train the resistance state retention prediction model, so that the resistance state retention prediction model can fully learn the first resistive memory in a high resistance state, within the preset time length, and after every second preset time length, the fluctuation characteristics of the resistance value of the first resistive memory and the setting characteristics of the erase operation voltage in the erase operation.

[0099] In operation S260 , when the resistance state retention prediction model predicts the resistance state retention of the M first resistive random access memories with an accuracy greater than or equal to a first preset value, a target prediction model is obtained.

[0100] According to the embodiment of the present disclosure, the first preset value can be selected according to actual conditions and is not limited here. For example, the first preset value can be 90%, 95% or 98%.

[0101] According to an embodiment of the present disclosure, by continuously reading each of the M first resistive random access memories at intervals of a second preset time within a first preset time, and obtaining first resistance state data, fluctuations in the resistance value of each first resistive random access memory under the same read operation voltage can be obtained. By gradually reading the first resistive random access memories at intervals of the second preset time, and obtaining second resistance state data, fluctuations in the resistance value of each second resistive random access memory under different read operation voltages can be obtained. Then, the resistance state retention prediction model is trained based on the training sample data obtained from the first resistance state data, the second resistance state data and the erase and write operation voltages corresponding to the M first resistive memories, so that the resistance state retention prediction model can fully learn the first resistive memory in a high resistance state, within a preset time length, and after each second preset time length, the fluctuation characteristics of the resistance value of the first resistive memory and the setting characteristics of the erase and write operation voltage in the erase and write operation, so that the obtained target prediction model can accurately predict the resistance state retention result of the first resistive memory after the second preset time length, and further accurately predict the stability of information storage of the first resistive memory after the second preset time length.

[0102] According to an embodiment of the present disclosure, for operation S220 shown in FIG2 , for each of the M first resistive random access memories, continuously reading the first resistive random access memory every second preset time period within a first preset time period to obtain first resistive state data may include the following operations:

[0103] At every second preset time duration, for each first resistive memory, continuously applying N identical first preset voltages to the first resistive memory, and reading the resistance value of the first resistive memory after each application of the first preset voltage to the first resistive memory, to obtain N first resistance values;

[0104] Calculating the variance of the N first resistance values ​​to obtain a first variance;

[0105] Calculating an average of the N first resistance values ​​to obtain a first average value;

[0106] Calculating local fluctuations of N first resistance values ​​to obtain a first local fluctuation;

[0107] The first variance, the first mean, and the first local fluctuation are concatenated to obtain first resistance state data.

[0108] For example, the first preset voltage may be 0.3V.

[0109] According to the embodiments of the present disclosure, N can be selected according to actual conditions and is not limited here. For example, N can be 50, 100, or 200.

[0110] According to an embodiment of the present disclosure, the first local fluctuation amount may be obtained by subtracting the minimum value from the maximum value of the N first resistance values.

[0111] FIG3 schematically shows a schematic diagram of N identical first preset voltages according to an embodiment of the present disclosure.

[0112] As shown in FIG3 , the magnitude of N identical first preset voltages is 0.3V, and N may be 100.

[0113] For example, for the first first resistive memory after a second preset time period, 100 0.3V voltages as shown in Figure 3 can be continuously applied to the BL end of the first first resistive memory, and after each 0.3V voltage is applied, the resistance value of the first first resistive memory is read to obtain 100 first resistance values ​​of the first first resistive memory after a second preset time period.

[0114] According to an embodiment of the present disclosure, the first resistance state data obtained by concatenating the first variance, the first mean, and the first local fluctuation can fully reflect the fluctuation of the resistance value of the first resistive memory under the same read voltage.

[0115] According to an embodiment of the present disclosure, for operation S230 shown in FIG2 , performing a step-by-step read operation on the first resistive memory every second preset time period to obtain second resistive state data may include the following operations:

[0116] At every second preset time duration, for each first resistive random access memory, continuously applying P second preset voltages that gradually increase to the first resistive random access memory, and after each application of the second preset voltage to the first resistive random access memory, reading the resistance value of the first resistive random access memory to obtain P second resistance values;

[0117] Calculate the variance of the P first resistance values ​​to obtain a second variance;

[0118] Calculate the average of the P first resistance values ​​to obtain a second average value;

[0119] Calculating the local fluctuations of P first resistance values ​​to obtain a second local fluctuation;

[0120] The second variance, the second mean, and the second local fluctuation are concatenated to obtain second resistance state data.

[0121] According to an embodiment of the present disclosure, the second local fluctuation amount may be obtained by subtracting the minimum value from the maximum value of the P second resistance values.

[0122] According to the embodiments of the present disclosure, P can be selected according to actual conditions and is not limited here. For example, P can be 5, 9, 11 or 15, etc.

[0123] According to an embodiment of the present disclosure, the P gradually increasing second preset voltages can be selected according to actual conditions and are not limited herein. For example, the P gradually increasing second preset voltages can be a voltage between 0.1V and 0.5V.

[0124] FIG4 schematically shows a schematic diagram of P gradually increasing second preset voltages according to an embodiment of the present disclosure.

[0125] As shown in FIG4 , the P gradually increasing second preset voltages are voltages between 0.1V and 0.5V, including 0.1V and 0.5V, and the difference between two adjacent second preset voltages is 0.05V. In this case, P is 9.

[0126] For example, for the first first resistive memory after a second preset time period, nine gradually increasing second preset voltages of 0.1V, 0.15V, 0.2V, 0.25V, 0.3V, 0.35V, 0.4V, 0.45V and 0.5V as shown in Figure 4 can be continuously applied to the BL end of the first first resistive memory, and after applying each second preset voltage, the resistance value of the first first resistive memory is read to obtain nine second resistance values ​​of the first first resistive memory after a second preset time period.

[0127] According to the embodiments of the present disclosure, the second resistance state data obtained by concatenating the second variance, the second mean, and the second local fluctuation can fully reflect the fluctuation of the resistance value of the second resistive memory under different read voltages.

[0128] According to an embodiment of the present disclosure, for operation S240 shown in FIG. 2 , obtaining training sample data based on the first resistance state data, the second resistance state data, and the erase / write operation voltages corresponding to the M first resistive memories may include the following operations:

[0129] For each first resistive random access memory, concatenating an erase / write operation voltage corresponding to the first resistive random access memory, first resistance state data corresponding to an i-th second preset time duration, and second resistance state data corresponding to an i-th second preset time duration to obtain an i-th resistance state data vector, where i is an integer greater than or equal to 1 and less than or equal to R, and R is the integer obtained by dividing the first preset time duration by the second preset time duration;

[0130] Each vector value included in the i-th resistive data vector is normalized to obtain i-th training sample data corresponding to the first resistive memory.

[0131] According to an embodiment of the present disclosure, the first resistance-state data corresponding to the i-th second preset duration represents the first resistance-state data corresponding to the first resistive memory collected after the first resistive memory is placed for the i-th second preset duration. Similarly, the second resistance-state data corresponding to the i-th second preset duration can be collected.

[0132] For example, when the first preset time length is 540 minutes and the second preset time length is 60 minutes, R is 9.

[0133] According to an embodiment of the present disclosure, by splicing the erase and write operation voltage corresponding to the first resistive memory, the first resistance state data corresponding to the i-th second preset time length, and the second resistance state data corresponding to the i-th second preset time length for each first resistive memory, an i-th resistance state data vector is obtained, and then the various vector values ​​included in the i-th resistance state data vector are normalized to obtain the i-th training sample data corresponding to the first resistive memory. The i-th training sample data reflecting the fluctuation characteristics of the resistance value of the first resistive memory after the i-th second preset time length and the setting characteristics of the erase and write operation voltage in the erase operation can be obtained.

[0134] According to an embodiment of the present disclosure, the M first resistive random access memories may be continuously baked at a preset temperature within a first preset time period.

[0135] According to the embodiments of the present disclosure, the preset temperature can be selected according to actual conditions and is not limited here. For example, the preset temperature can be 100° C., 125° C., or 150° C., etc.

[0136] According to the embodiments of the present disclosure, since high temperature will accelerate the speed at which the high resistance of the first resistive random access memory drifts to low resistance, before obtaining the training sample data, the M first resistive random access memories are continuously baked at a preset temperature. This can accelerate the M first resistive random access memories to reach a resistance state of a target preset time length by placing them at room temperature, thereby improving the speed of collecting training sample data.

[0137] For example, the first preset time period may be 540 minutes, and the normal temperature may be 25° C. When the M first resistive memories are baked continuously for 540 minutes at a high temperature of 125° C., it is equivalent to placing the M first resistive memories at normal temperature for 9216 minutes.

[0138] FIG5 schematically shows a flow chart of collecting resistance state data of a first resistive memory according to an embodiment of the present disclosure.

[0139] As shown in FIG. 5 , in step S510 , a forming operation and a first preset number of erase / write operations are performed on M resistive memories to obtain M first resistive memories and erase / write operation voltages corresponding to the M first resistive memories.

[0140] In step S520 , under high temperature baking, for each of the M first resistive memories, a step-by-step read operation and 100 consecutive read operations are performed on the first resistive memories every 60 minutes within a first preset time period.

[0141] As shown in Figure 5, the first preset time length is R x 60 minutes. Step S520 includes steps S521, S522, S523 and S524. Steps S521, S522, S523 and S524 are all step-by-step reading and 100 consecutive reading operations.

[0142] According to an embodiment of the present disclosure, the training method for the resistance state retention prediction model shown in FIG2 may include the following operations before performing a continuous read operation on each of the M first resistive random access memories at intervals of a second preset time within a first preset time to obtain first resistance state data:

[0143] Applying a first preset voltage to each first resistive random access memory once every second preset time period, and reading the resistance value of the first resistive random access memory to obtain L reference resistance values ​​corresponding to the first resistive random access memory, where L is obtained by dividing the first preset time period by the second preset time period, rounding the result, and adding the result to the second preset value;

[0144] For any two adjacent reference resistance values ​​among the L reference resistance values, subtract the second reference resistance value from the first reference resistance value and round the result to obtain a resistance deviation, wherein the any two adjacent reference resistance values ​​include the first reference resistance value and the second reference resistance value, and a time when the first reference resistance value is read is earlier than a time when the second reference resistance value is read;

[0145] calculating a ratio between the resistance deviation and a first reference resistance;

[0146] According to the size relationship between the ratio and the third preset value, the resistance state retention classification label corresponding to the target sample data is determined, wherein the target sample data represents the training sample data within the second preset time length corresponding to the first reference resistance value.

[0147] For example, the second preset value may be 1. When the first preset duration is 540 minutes and the second preset duration is 60 minutes, L may be 10.

[0148] According to the embodiment of the present disclosure, the third preset value can be selected according to actual conditions and is not limited here. For example, the third preset value can be 10%, 20% or 30%.

[0149] For example, when the third preset value is 10%, if the ratio is greater than 10%, it indicates that after the second preset time period, the resistance value of the first resistive memory drifts toward a low resistance value by more than 10% of its own resistance value, the first resistive memory remains failed, and the training sample data corresponding to the first resistive memory is labeled as 0. If the ratio is less than or equal to 10%, it indicates that after the second preset time period, the resistance value of the first resistive memory drifts toward a low resistance value by less than 10% of its own resistance value, the first resistive memory remains intact, and the training sample data corresponding to the first resistive memory is labeled as 1.

[0150] According to an embodiment of the present disclosure, after obtaining the resistance state retention classification label corresponding to each target sample data, the resistance state retention classification result of the training sample data corresponding to each first resistive random access memory after each second preset time period can be obtained.

[0151] According to an embodiment of the present disclosure, with respect to operation S250 shown in FIG2 , training the resistance state retention prediction model according to the training sample data may include the following operations:

[0152] In each round of training of the resistance state retention prediction model, the training sample data corresponding to the j-th second preset time length is input into the resistance state retention prediction model in batches to obtain the resistance state retention prediction results corresponding to each batch of training sample data, where j is an integer greater than or equal to 1 and less than or equal to S, and S is the first preset time length divided by the second preset time length and rounded;

[0153] Calculate the loss value corresponding to each batch of training sample data based on the resistance preservation prediction results corresponding to each batch of training sample data and the resistance preservation classification labels corresponding to each batch of training sample data;

[0154] Updating the model parameters of the resistance state preservation prediction model according to the loss value corresponding to each batch of training sample data;

[0155] Increment j and return to the operation of training the retention prediction model based on the training sample data corresponding to the j-th second preset time length.

[0156] For example, when the first preset time length is 540 minutes and the second preset time length is 60 minutes, S is 9.

[0157] According to an embodiment of the present disclosure, the training sample data corresponding to the jth second preset time period represents the training sample data corresponding to the first resistive memory collected after the first resistive memory is placed for the jth second preset time period.

[0158] For example, when M is 300, in the first round of training of the resistance state retention prediction model, the 300 training sample data corresponding to the first and second preset time lengths can be divided into 10 batches, and 30 training sample data are used in each batch to train the resistance state retention prediction model, and the model parameters of the resistance state retention prediction model are updated, so as to achieve 10 parameter updates of the resistance state retention prediction model based on the 300 training sample data within the first and second preset time lengths. Similarly, the 300 training sample data corresponding to the second and second preset time lengths are divided into 10 batches, the resistance state retention prediction model is trained and the parameters are updated 10 times... The 300 training sample data corresponding to the Sth second preset time length are divided into 10 batches, the resistance state retention prediction model is trained and the parameters are updated 10 times.

[0159] According to an embodiment of the present disclosure, the resistance state retention prediction result finally output by the resistance state retention prediction model can be 0 or 1. When the resistance state retention prediction result is 0, it indicates that the first resistive random access memory is predicted to have failed. When the resistance state retention prediction result is 1, it indicates that the first resistive random access memory is predicted to have not failed.

[0160] According to an embodiment of the present disclosure, when calculating the loss value corresponding to each batch of training sample data based on the resistance state retention prediction results corresponding to each batch of training sample data and the resistance state retention classification labels corresponding to each batch of training sample data, the resistance state retention prediction results use the decimal predicted by the resistance state retention prediction model corresponding to the resistance state retention prediction result 0 or 1 finally output by the resistance state retention prediction model.

[0161] According to an embodiment of the present disclosure, a binary cross entropy loss function can be used to calculate the loss value corresponding to each batch of training sample data based on the resistance state preservation prediction results corresponding to each batch of training sample data and the resistance state preservation classification labels corresponding to each batch of training sample data.

[0162] According to an embodiment of the present disclosure, the resistance state retention prediction model is a long short-term memory network model (LSTM), and the last layer of the long short-term memory network model is a fully connected layer.

[0163] According to the embodiments of the present disclosure, the long short-term memory network model can better capture the long-term dependencies in the training sample data by introducing a gating mechanism and a long-term memory mechanism, and obtain a more accurate resistance state retention prediction result.

[0164] FIG6 schematically shows a flow chart of a method for training a resistance state retention prediction model according to another embodiment of the present disclosure.

[0165] It can be seen from the t-th training sample data input in each round in Figure 6 that each training sample data input in each round includes: a first variance, a first mean, a first local fluctuation, a second variance, a second mean, a second local fluctuation, a set sub-operation voltage, a reset sub-operation voltage and a last reset sub-operation voltage, where t is an integer greater than or equal to 1.

[0166] As shown in FIG6 , first, the t-th training sample data 611, the t+1-th training sample data 612, and the t+2-th training sample data 613 are obtained for each round of input. Then, the t-th training sample data 611, the t+1-th training sample data 612, and the t+2-th training sample data 613 are sequentially input into the resistance state retention prediction model 620, where the resistance state retention prediction model is an LSTM model.

[0167] As shown in Figure 6, in the process of inputting the t-th training sample data 611 into the resistance state retention prediction model 620, the t-th training sample data 611 will be input into the resistance state retention prediction model 620 together with the t-1th hidden state and the t-1th unit state included in the t-1th intermediate parameter 631 for calculation, and the t-th hidden state and the t-th unit state included in the t-1th intermediate parameter 641 will be output, wherein the t-1th intermediate parameter 631 is the intermediate parameter obtained by the resistance state retention prediction model 620 processing the t-1th training sample data.

[0168] Then, the t-th intermediate parameter 641 and the first training sample data are processed by the fully connected layer 650, and the t-th resistance state retention prediction result 661 is output, wherein the t-th resistance state retention prediction result 661 is retention failure (label 0) or retention non-failure (label 1).

[0169] During the input of the t+1th training sample data 611 into the resistance state retention prediction model 620, the t+1th training sample data 612 is input into the resistance state retention prediction model 620 along with the tth hidden state and the tth unit state included in the tth intermediate parameter 632 for computation, outputting the t+1th hidden state and the t+1th unit state included in the t+1th intermediate parameter 642. The t+1th intermediate parameter 642 and the first training sample data are then processed by the fully connected layer 650, and the t+1th resistance state retention prediction result 662 is output. The t+1th resistance state retention prediction result 662 indicates either a retention failure (label 0) or a non-failure (label 1).

[0170] Similarly, the t+2th training sample data 613 performs the same training process on the resistance state retention prediction model 620 as the tth training sample data 611 and the t+1th training sample data 611 .

[0171] According to an embodiment of the present disclosure, when t is 1, there is no t-1th training sample data. At this time, the t-1th hidden state and the t-1th unit state included in the t-1th intermediate parameter 631 are both 0, that is, the initial values ​​of the hidden state and the unit state are 0.

[0172] FIG. 7 schematically shows a schematic diagram of the resistance value of the resistive random access memory drifting toward low resistance according to an embodiment of the present disclosure.

[0173] As shown in FIG7 , hourglass-shaped conductive filaments are present in the low-resistance resistive memory 710. At high temperatures, the lateral drift of oxygen ions in the low-resistance resistive memory 710 is smaller than the generation of oxygen vacancies in the oxygen storage layer, causing the hourglass-shaped conductive filaments to become increasingly thicker. The thicker the hourglass-shaped conductive filaments, the lower the resistance of the low-resistance resistive memory 710. Therefore, after the low-resistance resistive memory 710 is baked at high temperature, the hourglass-shaped conductive filaments become even thicker, and the resulting baked low-resistance resistive memory 720 remains in the low-resistance state.

[0174] The hourglass-shaped conductive filaments in the high-resistance state of the resistive random access memory 730 are broken. Under high-temperature baking, the lateral drift of oxygen ions in the high-resistance state of the resistive random access memory 730 is smaller than the generation of oxygen vacancies in the oxygen storage layer, causing the hourglass-shaped conductive filaments to connect vertically, causing the resistance value of the high-resistance state of the resistive random access memory 730 to drift toward the low-resistance state, resulting in the resistive random access memory 740 in the intermediate resistance state.

[0175] As shown in FIG7 , under high-temperature baking, the resistance value of the resistive random access memory in the high-resistance state drifts toward the low-resistance state. When the resistance value of the resistive random access memory in the high-resistance state drifts toward the low-resistance state by more than a third preset value, it is considered that the retention of the resistive random access memory in the high-resistance state has failed, and the data stored in the resistive random access memory in the high-resistance state has errors. Therefore, in the process of using the resistive random access memory in the high-resistance state, it is necessary to timely predict the retention of the resistive random access memory in the high-resistance state and repair it before the retention of the resistive random access memory in the high-resistance state fails to avoid errors in the data stored in the resistive random access memory in the high-resistance state.

[0176] According to the embodiments of the present disclosure, when a resistive random access memory in a high resistance state is placed at room temperature, the resistance state of the resistive random access memory will drift toward low resistance. The high temperature condition in FIG. 7 will only accelerate the speed of drifting the resistance state toward low resistance.

[0177] FIG8 schematically shows a schematic diagram of a resistive memory array according to an embodiment of the present disclosure.

[0178] As shown in FIG8 , the RRAM array includes multiple resistive random access memories 810 arranged in an array. The multiple resistive random access memories 810 in FIG8 can be processed according to the resistance state retention prediction model training method provided in an embodiment of the present disclosure to obtain a target prediction model. Furthermore, during the application of the multiple resistive random access memories 810 in FIG8 , the multiple resistive random access memories 810 can be individually repaired according to the resistance state retention repair method provided in an embodiment of the present disclosure.

[0179] FIG9 schematically shows a flow chart of a method for repairing resistance state retention according to an embodiment of the present disclosure.

[0180] As shown in FIG. 9 , the resistance state retention repair method of this embodiment includes operations S910 to S960 .

[0181] In operation S910, a first preset number of erase / write operations are performed on a target resistive memory in a conductive state to obtain a first target resistive memory and an erase / write operation voltage corresponding to the first target resistive memory.

[0182] According to an embodiment of the present disclosure, the erase / write operation performed on the target resistive memory in operation S910 is similar to the erase / write operation performed on any resistive memory in operation S210 , and thus will not be described in detail herein.

[0183] In operation S920 , a continuous read operation is performed on the first target resistive memory to obtain third resistive state data.

[0184] According to an embodiment of the present disclosure, the continuous read operation performed on the first target resistive memory in operation S920 is similar to the continuous read operation performed on any first resistive memory of any preset time length in operation S220, and is not described again herein.

[0185] In operation S930 , a step-by-step read operation is performed on the first target resistive memory to obtain fourth resistive state data.

[0186] According to an embodiment of the present disclosure, the step-by-step reading operation performed on the first target resistive memory in operation S930 is similar to the step-by-step reading operation performed on any first resistive memory of any preset time length in operation S230, and is not described again herein.

[0187] In operation S940 , target resistance state data is obtained according to the third resistance state data, the fourth resistance state data, and an erase / write operation voltage corresponding to the first target resistive memory.

[0188] According to an embodiment of the present disclosure, the third resistance state data, the fourth resistance state data, and the erase / write operation voltage corresponding to the first target resistive memory may be concatenated and normalized to obtain target resistance state data.

[0189] According to an embodiment of the present disclosure, the operation of obtaining the target resistive state data in operation S940 is similar to the operation of obtaining the training sample data corresponding to each first resistive memory and each second preset time length in operation S250, and is not repeated here.

[0190] In operation S950 , the target resistance state data is input into a target prediction model to obtain a resistance state retention prediction result corresponding to the first target resistive random access memory.

[0191] According to an embodiment of the present disclosure, a target prediction model may be obtained according to the training method of the resistance state retention prediction model shown in FIG2 .

[0192] In operation S960 , when the retention prediction result indicates that the first target resistive random access memory fails after a preset time period, a repair operation is performed on the first target resistive random access memory to obtain a second target resistive random access memory.

[0193] According to an embodiment of the present disclosure, the preset duration may be equal to the second preset duration.

[0194] According to an embodiment of the present disclosure, a reset voltage may be cyclically applied to a first target resistive random access memory, and a repair operation may be performed on the first target resistive random access memory to obtain a second target resistive random access memory.

[0195] According to an embodiment of the present disclosure, during the process of repairing the resistance state retention of a target resistive random access memory, the target resistive random access memory may be continuously baked at a preset temperature, wherein the preset temperature may be 125°C.

[0196] According to an embodiment of the present disclosure, by inputting the target resistive state data into the target prediction model, a resistive state retention prediction result corresponding to the first target resistive memory is obtained, and the resistive state retention prediction result can be obtained quickly and accurately. Then, when the retention prediction result indicates that the first target resistive memory fails after a preset time period, the first target resistive memory is repaired in a timely manner to obtain a second target resistive memory, and a second target resistive memory with better resistive state retention after the preset time period is obtained, thereby obtaining a second target resistive memory in a stable state.

[0197] According to an embodiment of the present disclosure, when a retention prediction result indicates that a first target resistive random access memory fails after a preset time period, performing a repair operation on the first target resistive random access memory to obtain a second target resistive random access memory includes:

[0198] Performing a k-th reset operation on the first target resistive random access memory, where k is an integer greater than or equal to 1;

[0199] Reading a repair resistance value of the first target resistive random access memory after the kth reset operation;

[0200] When the repair resistance value is less than or equal to the preset resistance value, k is incremented and the process returns to performing the kth reset operation on the first target resistive random access memory;

[0201] When the repaired resistance value is greater than the preset resistance value, a second target resistive random access memory is obtained.

[0202] According to the embodiment of the present disclosure, the preset resistance value can be selected according to actual conditions and is not limited here. For example, the preset resistance value can be 80 kΩ.

[0203] FIG10 schematically shows a flow chart of a resistance state retention repair method according to another embodiment of the present disclosure.

[0204] As shown in FIG. 10 , in step S1010 , it is determined that the first target resistive random access memory fails after a preset time period according to the retention prediction result.

[0205] In step S1020, a reset operation is performed on the first target resistive random access memory, and a repair resistance value of the first target resistive random access memory after the reset operation is read.

[0206] In step S1030, is it determined whether the repair resistance is greater than 80 kΩ?

[0207] When it is determined that the repair resistance value is greater than 80 kΩ, the repair is successful, and the repair operation is stopped in step S1040.

[0208] When it is determined that the repair resistance is ≤80 kΩ, the process returns to step S1020 to continue repairing the first target resistive random access memory.

[0209] FIG. 11 schematically shows a schematic diagram of a repair voltage used in a repair operation according to an embodiment of the present disclosure.

[0210] Step S1020 in FIG10 may include applying a voltage pulse of 1.35 V / 50 ns in FIG11 to the SL terminal of the first target resistive memory, and then applying a voltage pulse of 0.3 V / 50 ns to the BL terminal of the first target resistive memory, and then reading the repair resistance value of the first target resistive memory.

[0211] The following will illustrate the reference resistance value obtained by the training method of the resistance state retention prediction model according to the embodiment of the present disclosure, as well as the training results and test results of the resistance state retention prediction model obtained based on the experimental results of Figures 12 to 14.

[0212] FIG. 12 schematically shows a schematic diagram of reference resistance values ​​of M first resistive memories after every second preset time period according to an embodiment of the present disclosure.

[0213] The calculation process for the reference resistance values ​​in FIG12 is as follows: After performing 10 erase / write operations on each of the 300 resistive random access memories (RRAMs), 300 first RRAMs are obtained. Then, at a high temperature of 125° C., a first preset voltage of 0.3 V is applied to each of the 300 first RRAMs every 60 minutes for 540 minutes. The resistance value of each first RRAM is read to obtain a reference resistance value corresponding to each first RRAM. Ten reference resistance values ​​corresponding to each first RRAM are obtained within 540 minutes.

[0214] In FIG12 , the horizontal axis represents the reference resistance of the first resistive random access memory, and the vertical axis represents the ratio of the number of 300 first resistive random access memories at each reference resistance after every second preset time period to 300. Therefore, the vertical axis can also be referred to as a resistance distribution. The circular dotted line represents the resistance distribution corresponding to 0 minutes, the square dotted line represents the resistance distribution corresponding to 60 minutes, the regular triangle dotted line represents the resistance distribution corresponding to 120 minutes, the inverted triangle dotted line represents the resistance distribution corresponding to 180 minutes, the diamond dotted line represents the resistance distribution corresponding to 240 minutes, the hexagonal dotted line represents the resistance distribution corresponding to 300 minutes, the star dotted line represents the resistance distribution corresponding to 360 minutes, the triangle dotted line with the vertex pointing left represents the resistance distribution corresponding to 420 minutes, the pentagonal dotted line represents the resistance distribution corresponding to 480 minutes, and the triangle dotted line with the vertex pointing right represents the resistance distribution corresponding to the second preset time period of 540 minutes. The resistance distribution corresponding to 0 minutes represents the resistance distribution corresponding to the first second preset time period.

[0215] As shown in FIG12 , after 10 erase and write operations are performed on the 300 resistive random access memories, the resistance values ​​of the 300 first resistive random access memories are all greater than 80 kΩ, indicating that the 300 resistive random access memories are all qualified devices.

[0216] In FIG2 , if the resistance value of the first resistive memory drifts toward a low resistance by more than 10% of its own resistance value, the first resistive memory may be considered to remain failed. If the resistance value of the first resistive memory drifts toward a low resistance by more than 20% of its own resistance value, the first resistive memory may be considered to remain failed. If the resistance value of the first resistive memory drifts toward a low resistance by more than 30% of its own resistance value, the first resistive memory may be considered to remain failed.

[0217] FIG13 schematically illustrates the training results of the retention prediction model according to an embodiment of the present disclosure.

[0218] Under the experimental conditions of Figures 3, 4, 5, and 12, training sample data is obtained according to the process in Figure 1. 200 of the 300 resistive random access memories are selected as the training set.

[0219] As shown in Figure 13, the experiment trained three resistance state retention prediction models. Among them, the prediction model corresponding to the square dotted line can predict the resistance state retention when the resistance value of the first resistive random access memory drifts toward low resistance by more than 10% of its own resistance value, and the first resistive random access memory is considered to have failed. The model corresponding to the circular dotted line can predict the resistance state retention when the resistance value of the first resistive random access memory drifts toward low resistance by more than 20% of its own resistance value, and the first resistive random access memory is considered to have failed. The model corresponding to the triangular dotted line can predict the resistance state retention when the resistance value of the first resistive random access memory drifts toward low resistance by more than 30% of its own resistance value, and the first resistive random access memory is considered to have failed.

[0220] In FIG13 , the horizontal axis represents the prediction span, i.e., the number of the second preset time duration, and the vertical axis represents the model prediction accuracy.

[0221] As can be seen from Figure 13, as the prediction span increases, that is, as the second preset time length increases, the prediction accuracy of the three prediction models becomes higher and higher, and the final prediction accuracy is greater than or equal to 95%, indicating that after training, the three resistance state retention prediction models can accurately predict whether the resistance state of the first resistive memory will fail after being placed for the second preset time length.

[0222] FIG14 schematically shows the test results of the retention prediction model according to an embodiment of the present disclosure.

[0223] The remaining 100 of the 300 resistive random access memories are selected as a test set, and the three resistive state retention prediction models obtained in FIG13 are tested to obtain the test results shown in FIG14 .

[0224] In FIG14 , the horizontal axis represents the prediction span, i.e., the number of the second preset time duration, and the vertical axis represents the model prediction accuracy.

[0225] As can be seen from Figure 14, as the prediction span increases, that is, as the second preset time length increases, the prediction accuracy of the three resistive state retention prediction models for the test set is equivalent to the prediction accuracy of the three resistive state retention prediction models for the training set, which further shows that the three resistive state retention prediction models can accurately predict whether the first resistive memory will fail after being placed for the second preset time length, and three target prediction models are obtained that can accurately predict whether the first resistive memory will fail after being placed for the second preset time length.

[0226] It should be noted that, unless it is explicitly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present disclosure, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order between multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0227] Based on the above-mentioned training method of the resistance state retention prediction model, the present disclosure further provides a training device for the resistance state retention prediction model. The device will be described in detail below with reference to FIG15 .

[0228] FIG15 schematically shows a structural block diagram of a training device for a resistance state retention prediction model according to an embodiment of the present disclosure.

[0229] As shown in FIG15 , the training device 1500 for the resistance state retention prediction model of this embodiment includes a first obtaining module 1510 , a second obtaining module 1520 , a third obtaining module 1530 , a fourth obtaining module 1540 , a training module 1550 and a fifth obtaining module 1560 .

[0230] The first obtaining module 1510 is configured to perform a first preset number of erase / write operations on each of the M resistive random access memories in the on state, thereby obtaining the M first resistive random access memories and erase / write operation voltages corresponding to the M first resistive random access memories. In one embodiment, the first obtaining module 1510 may be configured to execute operation S210 described above, and will not be further described herein.

[0231] The second obtaining module 1520 is configured to continuously read each of the M first resistive random access memories at intervals of a second preset time duration within a first preset time duration to obtain first resistive state data. In one embodiment, the second obtaining module 1520 can be configured to perform operation S220 described above, which will not be further described herein.

[0232] The third obtaining module 1530 is configured to perform a step-by-step read operation on the first resistive memory at intervals of a second preset time to obtain the second resistive state data. In one embodiment, the third obtaining module 1530 may be configured to execute the operation S230 described above, which will not be described in detail herein.

[0233] The fourth obtaining module 1540 is configured to obtain training sample data based on the first resistance state data, the second resistance state data, and the erase / write operation voltage corresponding to each of the M first resistive random access memories. In one embodiment, the fourth obtaining module 1540 may be configured to perform operation S240 described above, which will not be described in detail herein.

[0234] The training module 1550 is configured to train the resistance state retention prediction model according to the training sample data. In one embodiment, the training module 1550 may be configured to execute the operation S250 described above, which will not be described in detail here.

[0235] The fifth obtaining module 1560 is configured to obtain a target prediction model when the resistance state retention prediction model predicts the resistance state retention of the M first resistive random access memories with an accuracy greater than or equal to a first preset value. In one embodiment, the fifth obtaining module 1560 may be configured to perform operation S260 described above, which will not be further described herein.

[0236] According to an embodiment of the present disclosure, the second obtaining module includes a first resistance value obtaining submodule, a first variance obtaining submodule, a first mean value obtaining submodule, a first local fluctuation quantity obtaining submodule and a first resistance state data obtaining submodule.

[0237] The first resistance value obtaining submodule is used to continuously apply N identical first preset voltages to each first resistive memory at every second preset time length, and read the resistance value of the first resistive memory after each application of the first preset voltage to the first resistive memory to obtain N first resistance values.

[0238] The first variance obtaining submodule is configured to calculate the variance of N first resistance values ​​to obtain the first variance.

[0239] The first average value obtaining submodule is used to calculate the average of N first resistance values ​​to obtain a first average value.

[0240] The first local fluctuation amount obtaining submodule is used to calculate the local fluctuation amounts of N first resistance values ​​to obtain the first local fluctuation amount.

[0241] The first resistance state data obtaining submodule is used to splice the first variance, the first mean and the first local fluctuation to obtain the first resistance state data.

[0242] According to an embodiment of the present disclosure, the third obtaining module includes a second resistance value obtaining submodule, a second variance obtaining submodule, a second mean value obtaining submodule, a second local fluctuation quantity obtaining submodule and a second resistance state data obtaining submodule.

[0243] The second resistance value obtaining submodule is used to continuously apply P gradually increasing second preset voltages to each first resistive memory at every second preset time length, and read the resistance value of the first resistive memory after each application of the second preset voltage to the first resistive memory to obtain P second resistance values.

[0244] The second variance obtaining submodule is used to calculate the variance of P first resistance values ​​to obtain the second variance.

[0245] The second mean value obtaining submodule is used to calculate the mean of P first resistance values ​​to obtain a second mean value.

[0246] The second local fluctuation obtaining submodule is configured to calculate the local fluctuations of P first resistance values ​​to obtain the second local fluctuations.

[0247] The second resistance state data obtaining submodule is used to splice the second variance, the second mean and the second local fluctuation to obtain the second resistance state data.

[0248] According to an embodiment of the present disclosure, the fourth obtaining module includes a resistance state data vector obtaining submodule and a training sample data obtaining submodule.

[0249] The resistance state data vector obtaining submodule is used to splice the erase and write operation voltage corresponding to the first resistive memory, the first resistance state data corresponding to the i-th second preset time length, and the second resistance state data corresponding to the i-th second preset time length for each first resistive memory to obtain the i-th resistance state data vector, wherein i is an integer greater than or equal to 1 and less than or equal to R, and R is the first preset time length divided by the second preset time length and rounded.

[0250] The training sample data obtaining submodule is used to normalize each vector value included in the i-th resistive data vector to obtain the i-th training sample data corresponding to the first resistive memory.

[0251] According to an embodiment of the present disclosure, for each of the M first resistive random access memories, within a first preset time period, a continuous read operation is performed on the first resistive random access memory every second preset time period to obtain first resistance state data, and a training device for a resistance state retention prediction model includes a reference resistance value obtaining module, a resistance value deviation obtaining sub-module, a ratio obtaining sub-module and a labeling determination sub-module.

[0252] The reference resistance obtaining module is used to apply a first preset voltage to each first resistive random access memory once every second preset time, read the resistance value of the first resistive random access memory, and obtain L reference resistance values ​​corresponding to the first resistive random access memory, where L is obtained by dividing the first preset time by the second preset time, rounding the result, and adding the result to the second preset value.

[0253] The resistance deviation obtaining submodule is used to obtain the resistance deviation for any two adjacent reference resistance values ​​among the L reference resistance values ​​by subtracting the second reference resistance value from the first reference resistance value and rounding the result. The any two adjacent reference resistance values ​​include the first reference resistance value and the second reference resistance value, and the time when the first reference resistance value is read is earlier than the time when the second reference resistance value is read.

[0254] The ratio obtaining submodule is used to calculate the ratio between the resistance deviation and the first reference resistance.

[0255] The label determination submodule is used to determine the resistance state maintenance classification label corresponding to the target sample data based on the size relationship between the ratio and the third preset value, wherein the target sample data represents the training sample data within the second preset time length corresponding to the first reference resistance value.

[0256] According to an embodiment of the present disclosure, the training module includes a prediction result obtaining submodule, a loss value obtaining submodule, a model parameter updating submodule and a return training operation submodule.

[0257] The prediction result obtaining submodule is used to input the training sample data corresponding to the j-th second preset time length into the resistance state retention prediction model in batches in each round of training of the resistance state retention prediction model, and obtain the resistance state retention prediction results corresponding to each batch of training sample data, wherein j is an integer greater than or equal to 1 and less than or equal to S, and S is the first preset time length divided by the second preset time length and rounded.

[0258] The loss value obtaining submodule is used to calculate the loss value corresponding to each batch of training sample data based on the resistance state preservation prediction results corresponding to each batch of training sample data and the resistance state preservation classification labels corresponding to each batch of training sample data.

[0259] The model parameter updating submodule is used to update the model parameters of the resistance state retention prediction model according to the loss value corresponding to each batch of training sample data.

[0260] The training operation submodule is returned, which is used to increment j and return the operation of training the retention prediction model based on the training sample data corresponding to the j-th second preset time length.

[0261] According to an embodiment of the present disclosure, the M first resistive random access memories are continuously baked at a preset temperature within a first preset time period.

[0262] According to an embodiment of the present disclosure, the resistance state retention prediction model is a long short-term memory network model, and the last layer of the long short-term memory network model is a fully connected layer.

[0263] According to an embodiment of the present disclosure, any multiple modules of the first obtaining module 1510, the second obtaining module 1520, the third obtaining module 1530, the fourth obtaining module 1540, the training module 1550, and the fifth obtaining module 1560 can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the first obtaining module 1510, the second obtaining module 1520, the third obtaining module 1530, the fourth obtaining module 1540, the training module 1550, and the fifth obtaining module 1560 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware in any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation modes of software, hardware, and firmware, or in an appropriate combination of any of them. Alternatively, at least one of the first obtaining module 1510, the second obtaining module 1520, the third obtaining module 1530, the fourth obtaining module 1540, the training module 1550 and the fifth obtaining module 1560 can be at least partially implemented as a computer program module, which can perform the corresponding function when it is executed.

[0264] Based on the above-mentioned resistance state retention repair method, the present disclosure further provides a resistance state retention repair device, which will be described in detail below in conjunction with FIG16 .

[0265] FIG16 schematically shows a structural block diagram of a resistance-state preserving repair device according to an embodiment of the present disclosure.

[0266] As shown in Figure 16, the resistance state retention repair device 1600 of this embodiment includes a first target resistive memory and erase operation voltage acquisition module 1610, a third resistance state data acquisition module 1620, a fourth resistance state data acquisition module 1630, a target resistance state data acquisition module 1640, a prediction result acquisition module 1650 and a second target resistive memory acquisition module 1660.

[0267] The first target resistive memory and erase / write operation voltage obtaining module 1610 is used in the sixth obtaining module to perform a first preset number of erase / write operations on the target resistive memory in the on state to obtain the first target resistive memory and the erase / write operation voltage corresponding to the first target resistive memory. In one embodiment, the first target resistive memory and erase / write operation voltage obtaining module 1610 can be used to perform operation S910 described above and will not be further described here.

[0268] The third resistance state data obtaining module 1620 is configured to perform a continuous read operation on the first target resistive random access memory to obtain third resistance state data. In one embodiment, the third resistance state data obtaining module 1620 may be configured to perform the operation S920 described above, which will not be described in detail here.

[0269] The fourth resistance state data obtaining module 1630 is configured to perform a step-by-step read operation on the first target resistive memory to obtain fourth resistance state data. In one embodiment, the fourth resistance state data obtaining module 1630 may be configured to perform the operation S930 described above, which will not be described in detail here.

[0270] The target resistance state data obtaining module 1640 is configured to obtain the target resistance state data based on the third resistance state data, the fourth resistance state data, and the erase / write operation voltage corresponding to the first target resistive memory. In one embodiment, the target resistance state data obtaining module 1640 can be configured to perform the operation S940 described above, which will not be described in detail here.

[0271] The prediction result obtaining module 1650 is configured to input the target resistance state data into the target prediction model to obtain a resistance state retention prediction result corresponding to the first target resistive random access memory. In one embodiment, the prediction result obtaining module 1650 may be configured to perform the operation S950 described above, which will not be described in detail here.

[0272] The second target resistive random access memory module 1660 is configured to, when the retention prediction result indicates that the first target resistive random access memory has failed after a preset period of time, perform a repair operation on the first target resistive random access memory to obtain a second target resistive random access memory. In one embodiment, the second target resistive random access memory module 1660 can be configured to perform operation S960 described above and will not be further described here.

[0273] According to an embodiment of the present disclosure, the second target resistive memory obtaining module includes a reset operation submodule, a resistance value reading submodule, a return reset operation submodule and a second target resistive memory obtaining submodule.

[0274] The reset operation submodule is configured to perform a k-th reset operation on the first target resistive random access memory, where k is an integer greater than or equal to 1.

[0275] The resistance reading submodule is used to read the repair resistance of the first target resistive random access memory after the kth reset operation.

[0276] The return reset operation submodule is used to increment k and return to performing the kth reset operation on the first target resistive random access memory when the repair resistance value is less than or equal to the preset resistance value.

[0277] The second target resistive random access memory obtaining submodule is configured to obtain the second target resistive random access memory when the repair resistance value is greater than the preset resistance value.

[0278] According to an embodiment of the present disclosure, any multiple modules among the first target resistive memory and erase / write operation voltage obtaining module 1610, the third resistive state data obtaining module 1620, the fourth resistive state data obtaining module 1630, the target resistive state data obtaining module 1640, the prediction result obtaining module 1650, and the second target resistive memory obtaining module 1660 can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the first target resistive memory and erase / write operation voltage obtaining module 1610, the third resistive state data obtaining module 1620, the fourth resistive state data obtaining module 1630, the target resistive state data obtaining module 1640, the prediction result obtaining module 1650 and the second target resistive memory obtaining module 1660 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware such as any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation methods of software, hardware and firmware, or in an appropriate combination of any of them. Alternatively, at least one of the first target resistive memory and erase / write operation voltage obtaining module 1610, the third resistive state data obtaining module 1620, the fourth resistive state data obtaining module 1630, the target resistive state data obtaining module 1640, the prediction result obtaining module 1650 and the second target resistive memory obtaining module 1660 can be at least partially implemented as a computer program module, which can execute corresponding functions when the computer program module is run.

[0279] FIG17 schematically shows a block diagram of an electronic device suitable for implementing a method for training a resistance state retention prediction model and a method for repairing resistance state retention according to an embodiment of the present disclosure.

[0280] As shown in Figure 17, the electronic device 1700 according to an embodiment of the present disclosure includes a processor 1701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1702 or a program loaded from a storage portion 1708 into a random access memory (RAM) 1703. The processor 1701 may, for example, include a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a dedicated microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1701 may also include an onboard memory for caching purposes. The processor 1701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0281] Various programs and data required for the operation of the electronic device 1700 are stored in the RAM 1703. The processor 1701, the ROM 1702, and the RAM 1703 are connected to each other via a bus 1704. The processor 1701 performs various operations of the method flow according to the embodiment of the present disclosure by executing the programs in the ROM 1702 and / or the RAM 1703. It should be noted that the programs may also be stored in one or more memories other than the ROM 1702 and the RAM 1703. The processor 1701 may also perform various operations of the method flow according to the embodiment of the present disclosure by executing the programs stored in the one or more memories.

[0282] According to an embodiment of the present disclosure, electronic device 1700 may further include an input / output (I / O) interface 1705, which is also connected to bus 1704. Electronic device 1700 may further include one or more of the following components connected to I / O interface 1705: an input portion 1706 including a keyboard, a mouse, etc.; an output portion 1707 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage portion 1708 including a hard disk; and a communication portion 1709 including a network interface card such as a LAN card or a modem. Communication portion 1709 performs communication processing via a network such as the Internet. A drive 1710 is also connected to I / O interface 1705 as needed. Removable media 1711, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in drive 1710 as needed, so that computer programs read from the removable media can be installed into storage portion 1708 as needed.

[0283] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, and when executed, implements the method according to the embodiments of the present disclosure.

[0284] According to an embodiment of the present disclosure, a computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, it may include but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present disclosure, a computer-readable storage medium may include the ROM 1702 and / or RAM 1703 described above and / or one or more memories other than ROM 1702 and RAM 1703.

[0285] Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for executing the method shown in the flowchart. When the computer program product is executed in a computer system, the program code is used to cause the computer system to implement the method for training a resistance state retention prediction model and the method for repairing resistance state retention provided in the embodiments of the present disclosure.

[0286] The computer program executes the above functions defined in the system / device of the embodiment of the present disclosure when the computer program is executed by the processor 1701. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0287] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal over a network medium, downloaded and installed via the communication portion 1709, and / or installed from removable media 1711. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0288] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1709 and / or installed from the removable medium 1711. When the computer program is executed by the processor 1701, the above-described functions defined in the system of the embodiment of the present disclosure are performed. According to the embodiment of the present disclosure, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0289] According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0290] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0291] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0292] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for training a resistance retention prediction model, comprising: Performing a first preset number of erasing and writing operations on the M resistive memories in the on state to obtain M first resistive memories and erasing and writing operation voltages respectively corresponding to the M first resistive memories; For each of the M first resistive memories, within a first preset time length, and at intervals of a second preset time length, a continuous read operation is performed on the first resistive memory to obtain first resistance state data; Performing a step-by-step read operation on the first resistive memory at intervals of a second preset time to obtain second resistive state data; Obtaining training sample data according to each of the first resistance state data, each of the second resistance state data and the erase / write operation voltage respectively corresponding to the M first resistive random access memories; Training the resistance state retention prediction model according to the training sample data; When the prediction accuracy of the resistance state retention prediction model for the resistance state retention of the M first resistive random access memories is greater than or equal to a first preset value, a target prediction model is obtained.

2. The method according to claim 1, wherein: For each of the M first resistive memories, within a first preset time length, and at intervals of a second preset time length, continuously reading the first resistive memory to obtain first resistance state data includes: At every second preset time length, for each first resistive memory, N identical first preset voltages are continuously applied to the first resistive memory, and after each application of the first preset voltage to the first resistive memory, the resistance value of the first resistive memory is read to obtain N first resistance values; Calculating the variance of the N first resistance values ​​to obtain a first variance; Calculating an average of the N first resistance values ​​to obtain a first average value; Calculating the local fluctuations of the N first resistance values ​​to obtain a first local fluctuation; The first variance, the first mean, and the first local fluctuation are concatenated to obtain the first resistive state data.

3. The method according to claim 1, wherein: The stepwise reading operation is performed on the first resistive memory at every second preset time to obtain the second resistance state data, which includes: At every second preset time length, for each first resistive memory, continuously applying P second preset voltages that gradually increase to the first resistive memory, and after each application of the second preset voltage to the first resistive memory, reading the resistance value of the first resistive memory to obtain P second resistance values; Calculating the variance of the P first resistance values ​​to obtain a second variance; Calculating the average of the P first resistance values ​​to obtain a second average value; Calculating the local fluctuations of the P first resistance values ​​to obtain a second local fluctuation; The second variance, the second mean, and the second local fluctuation are concatenated to obtain the second resistive state data.

4. The method according to claim 1, wherein: The obtaining of training sample data according to each of the first resistance state data, each of the second resistance state data and the erase / write operation voltage respectively corresponding to the M first resistive memories comprises: For each of the first resistive memory, the erase / write operation voltage corresponding to the first resistive memory, the first resistance state data corresponding to the i-th second preset time length, and the second resistance state data corresponding to the i-th second preset time length are concatenated to obtain an i-th resistance state data vector, wherein i is an integer greater than or equal to 1 and less than or equal to R, and R is obtained by dividing the first preset time length by the second preset time length and rounding the result; Each vector value included in the i-th resistive data vector is normalized to obtain i-th training sample data corresponding to the first resistive memory.

5. The method according to claim 1, wherein: Before the step of performing a continuous read operation on each of the M first resistive memories within a first preset time period and at intervals of a second preset time period to obtain first resistive state data includes: At every second preset time, a first preset voltage is applied to each of the first resistive memory cells, and a resistance value of the first resistive memory cells is read to obtain L reference resistance values ​​corresponding to the first resistive memory cells, wherein L is obtained by dividing the first preset time length by the second preset time length, rounding the result, and adding the result to the second preset value; For any two adjacent reference resistance values ​​among the L reference resistance values, subtract the second reference resistance value from the first reference resistance value and round the result to obtain a resistance deviation, wherein the any two adjacent reference resistance values ​​include the first reference resistance value and the second reference resistance value, and the time of reading the first reference resistance value is earlier than the time of reading the second reference resistance value; Calculating a ratio between the resistance deviation and the first reference resistance; According to the magnitude relationship between the ratio and the third preset value, a resistance state retention classification label corresponding to the target sample data is determined, wherein the target sample data represents training sample data within a second preset time length corresponding to the first reference resistance value.

6. The method according to claim 1, wherein: The training of the resistance state retention prediction model according to the training sample data comprises: In each round of training of the resistance state retention prediction model, the training sample data corresponding to the j-th second preset time length is input into the resistance state retention prediction model in batches to obtain the resistance state retention prediction results corresponding to each batch of training sample data, wherein j is an integer greater than or equal to 1 and less than or equal to S, and S is the first preset time length divided by the second preset time length and rounded; Calculate the loss value corresponding to each batch of training sample data according to the resistance state preservation prediction result corresponding to each batch of training sample data and the resistance state preservation classification label corresponding to each batch of training sample data; Updating the model parameters of the resistance state retention prediction model according to the loss value corresponding to each batch of training sample data; Increment j and return to the operation of training the retention prediction model based on the training sample data corresponding to the j-th second preset duration.

7. The method according to claim 1, wherein: The M first resistive random access memories are continuously baked at a preset temperature within a first preset time period.

8. The method according to claim 1, wherein: The resistance state retention prediction model is a long short-term memory network model, and the last layer of the long short-term memory network model is a fully connected layer.

9. A method for repairing resistance state retention, comprising: Performing a first preset number of erase / write operations on a target resistive memory in a conducting state to obtain a first target resistive memory and an erase / write operation voltage corresponding to the first target resistive memory; Performing a continuous read operation on the first target resistive memory to obtain third resistive state data; Performing a step-by-step read operation on the first target resistive memory to obtain fourth resistive state data; Obtaining target resistance state data according to the third resistance state data, the fourth resistance state data and the erase / write operation voltage corresponding to the first target resistance random access memory; Inputting the target resistance state data into the target prediction model according to any one of claims 1 to 8 to obtain a resistance state retention prediction result corresponding to the first target resistive memory; When the retention prediction result indicates that the first target resistive random access memory fails after a preset time period, a repair operation is performed on the first target resistive random access memory to obtain a second target resistive random access memory.

10. The method according to claim 9, wherein: When the retention prediction result indicates that the first target resistive memory fails after a preset time period, performing a repair operation on the first target resistive memory to obtain a second target resistive memory includes: Performing a k-th reset operation on the first target resistive random access memory, where k is an integer greater than or equal to 1; Reading a repair resistance value of the first target resistive random access memory after the kth reset operation; When the repair resistance is less than or equal to the preset resistance, k is incremented and the process returns to performing the kth reset operation on the first target resistive random access memory; When the repair resistance is greater than the preset resistance, the second target resistive random access memory is obtained.

11. A training device for a resistance retention prediction model, comprising: A first obtaining module is used to perform a first preset number of erase / write operations on M resistive random access memories in a conducting state to obtain M first resistive random access memories and erase / write operation voltages respectively corresponding to the M first resistive random access memories; The second obtaining module is used for obtaining, for each of the M first resistive switching memories, Within a set time length, the first resistive memory is continuously read every second preset time length to obtain first resistance state data; A third obtaining module is used to perform a step-by-step reading operation on the first resistive memory at intervals of a second preset time length to obtain second resistance state data; A fourth obtaining module, configured to obtain training sample data according to each of the first resistance state data, each of the second resistance state data and the erase / write operation voltage respectively corresponding to the M first resistive random access memories; A training module, used for training the resistance state retention prediction model according to the training sample data; The fifth obtaining module is used to obtain a target prediction model when the prediction accuracy of the resistance state retention prediction model for the resistance state retention of the M first resistive random access memories is greater than or equal to a first preset value.

12. A resistance-state-maintaining repair device, comprising: A first target resistive memory and an erase / write operation voltage obtaining module, configured to perform a first preset number of erase / write operations on a target resistive memory in a conducting state, to obtain a first target resistive memory and an erase / write operation voltage corresponding to the first target resistive memory; A third resistance state data obtaining module, configured to perform a continuous read operation on the first target resistive memory to obtain third resistance state data; A fourth resistance state data obtaining module, configured to perform a step-by-step read operation on the first target resistive memory to obtain fourth resistance state data; a target resistance state data obtaining module, configured to obtain target resistance state data according to the third resistance state data, the fourth resistance state data and the erase / write operation voltage corresponding to the first target resistive random access memory; A prediction result obtaining module, used for inputting the target resistance state data into the target prediction model according to any one of claims 1 to 8 to obtain a resistance state retention prediction result corresponding to the first target resistive random access memory; The second target resistive memory obtaining module is used to perform a repair operation on the first target resistive memory to obtain a second target resistive memory when the retention prediction result indicates that the first target resistive memory fails after a preset time period.

13. An electronic device, comprising: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to execute the method according to any one of claims 1 to 10.

Images