Layout structure of static random access memory

Abstract

Provided in the present invention is a layout structure of a static random access memory. The layout structure comprises: a first active region and a second active region, which both extend in a direction perpendicular to a horizontal direction; a gate of a first PD transistor, which gate is located on the first active region, a first portion of the gate of the first PD transistor being perpendicular to the extension direction of the first active region, and the clockwise angle between a second portion of the gate of the first PD transistor and the first portion of the gate of the first PD transistor being less than 180 degrees; and a gate of a second PD transistor, which gate is located on the second active region, a first portion of the gate of the second PD transistor being perpendicular to the extension direction of the second active region, the clockwise angle between a second portion of the gate of the second PD transistor and the first portion of the gate of the second PD transistor being less than 180 degrees, and the second portion of the gate of the second PD transistor and the second portion of the gate of the first PD transistor being opposite each other and at a relative distance that meets photolithography requirements. The present invention reduces the area of the static random access memory under the condition of the gate length being not reduced and the photolithography requirements being met.

Description

Layout structure of static random access memory Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout structure of a static random access memory. Background Art

[0002] With the continuous development of modern high-tech industries, represented by electronic communications technology, the global integrated circuit industry's total output value has grown at a rate exceeding 30% annually. Static random access memory (SRAM), as a key storage device, is widely used in digital and communications circuit design. SRAM is a key component in logic circuits, widely used for data storage due to its low power consumption and high read speed. An SRAM cell has a matrix structure consisting of multiple SRAM devices, including at least one PG transistor, at least one PD transistor, and at least one PU transistor.

[0003] Referring to Figure 1 , a portion of the layout structure of a static random access memory (SRAM) in the prior art includes: an active area, a PD tube, a PG tube, and a PU transistor located on the active area. The number of PD tubes, PG tubes, and PU transistors depends on the specific process. The PD tube and the PG tube are spaced a certain distance apart, and the PD tube and the PU transistor can be in contact. There may be multiple active areas, separated by shallow trench isolation structures. Taking two active areas as an example, namely the first active area 110 and the second active area 120, the extension directions of the first active area 110 and the second active area 120 are both perpendicular to the horizontal direction. Multiple PD tubes can be designed on both the first active area 110 and the second active area 120, including the gate of the PD tube. For example, the gate 130 of the first PD tube is designed on the first active area 110. The gate 130 of the first PD tube is in the shape of a straight strip, radially perpendicular to the extension direction of the first active area 110. The gate 140 of the second PD tube is designed on the second active area 120. The gate 140 of the second PD tube is in the shape of a straight strip and is radially perpendicular to the extension direction of the second active area 120. The gate 130 of the first PD tube and the gate 140 of the second PD tube are opposite to each other, and the shortest distance between them meets the lithography requirements.

[0004] However, in the layout structure of the prior art SRAM, if one wishes to reduce the SRAM area, particularly to reduce the horizontal spacing, it is necessary to reduce the extension length of the gate 130 of the first PD tube and / or the gate 140 of the second PD tube outside the first active area 110 and / or the second active area 120, or to reduce the relative horizontal distance between the gate 130 of the first PD tube and the gate 140 of the second PD tube. However, reducing the length will cause the gate shape to be affected by the optical proximity effect, affecting the stability of the channel length. If the relative horizontal distance is reduced, the photolithography requirements may not be met, resulting in insufficient exposure between the gate 130 of the first PD tube and the gate 140 of the second PD tube, causing a short circuit. In other words, without reducing the horizontal extension length of the gate 130 of the first PD tube and / or the gate 140 of the second PD tube and meeting the photolithography requirements, the layout structure of the prior art SRAM cannot be reduced.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to provide a layout structure of a static random access memory, which can reduce the layout area of ​​the static random access memory without reducing the extension length of the gate 130 of the first PD tube and / or the gate 140 of the second PD tube and meeting the lithography requirements.

[0007] In order to achieve the above object, the present invention provides a layout structure of a static random access memory, comprising:

[0008] A first active region and a second active region, wherein the first active region and the second active region are separated by a shallow trench isolation structure, and extension directions of the first active region and the second active region are both perpendicular to a horizontal direction;

[0009] a gate of a first PD tube located on the first active region, wherein the gate of the first PD tube is divided into two parts, wherein the gate of the first PD tube in the first part is perpendicular to the extension direction of the first active region, and the gate of the first PD tube in the second part is connected to the gate of the first PD tube in the first part and the clockwise angle between the gate and the gate of the first PD tube in the first part is less than 180°;

[0010] a gate of a second PD tube located on the second active region, wherein the gate of the second PD tube is divided into two parts, wherein the gate of the second PD tube in the first part is perpendicular to the extension direction of the second active region, and the gate of the second PD tube in the second part is connected to the gate of the second PD tube in the first part and the clockwise angle between the gate and the gate of the second PD tube in the first part is less than 180°;

[0011] The gate of the second PD tube in the second part is opposite to the gate of the first PD tube in the second part, and the relative distance therebetween meets the photolithography requirements.

[0012] Optionally, the layout structure of the static random access memory further includes a gate of a PG transistor, and the gate of the PG transistor is connected across the first active area and the second active area.

[0013] Optionally, in the layout structure of the static random access memory, the shortest distances between the gate of the first PD tube and the gate of the second PD tube and the gate of the PG tube all meet the photolithography requirements.

[0014] Optionally, in the layout structure of the static random access memory, the clockwise angle between the gate of the first PD tube in the second part and the gate of the first PD tube in the first part is 90° to 165°.

[0015] Optionally, in the layout structure of the static random access memory, the clockwise angle between the gate of the second PD tube in the second part and the gate of the second PD tube in the first part is 90° to 165°.

[0016] Optionally, in the layout structure of the static random access memory, the clockwise angle of the gate of the first PD tube of the second part and the gate of the first PD tube of the first part and the clockwise angle of the gate of the second PD tube of the second part and the gate of the second PD tube of the first part are the same or different.

[0017] Optionally, in the layout structure of the static random access memory, the width of the gate of the first PD tube in the second part is less than or equal to the width of the gate of the first PD tube in the first part.

[0018] Optionally, in the layout structure of the static random access memory, the width of the gate of the second PD tube in the second part is less than or equal to the width of the gate of the second PD tube in the first part.

[0019] Optionally, in the layout structure of the static random access memory, there are at least two gates of the first PD tubes, and there is a certain distance between the gates of all the first PD tubes.

[0020] Optionally, in the layout structure of the static random access memory, there are at least two gates of the second PD tube, and there is a certain distance between the gates of all the second PD tubes.

[0021] The layout structure of the static random access memory provided by the present invention includes: a first active area and a second active area, the first active area and the second active area being separated by a shallow trench isolation structure, and the extension directions of the first active area and the second active area being perpendicular to the horizontal direction; a gate of a first PD tube located on the first active area, the gate of the first PD tube being divided into two parts, the gate of the first PD tube in the first part being perpendicular to the extension direction of the first active area, the gate of the first PD tube in the second part being connected to the gate of the first PD tube in the first part and the clockwise angle with the gate of the first PD tube in the first part being less than 180°; a gate of a second PD tube located on the second active area, the gate of the second PD tube being divided into two parts, the gate of the second PD tube in the first part being perpendicular to the extension direction of the second active area, the gate of the second PD tube in the second part being connected to the gate of the second PD tube in the first part and the clockwise angle with the gate of the second PD tube in the first part being less than 180°; the gate of the second PD tube in the second part being opposite to the gate of the first PD tube in the second part, and the shortest distance between the two in the horizontal direction meeting the photolithography requirements. The present invention divides the gates of the first and second PD transistors into two equal parts, with the angle between the two parts being less than 180°. This allows the gates of the first and second PD transistors to be bent, without reducing the horizontal extension of the gates. Furthermore, provided that the relative distance between the gates of the first and second PD transistors meets photolithography requirements, the horizontal distance between the gates of the first and second PD transistors can be reduced. Consequently, the layout area of ​​the static random access memory is reduced without reducing the length of the gates of the first and / or second PD transistors and while meeting photolithography requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of a layout structure of a static random access memory in the prior art;

[0023] FIG2 is a schematic diagram of a layout structure of a static random access memory according to an embodiment of the present invention;

[0024] In the figure: 110-first active area, 120-second active area, 130-gate of the first PD tube, 140-gate of the second PD tube, 210-first active area, 220-second active area, 230-gate of the first PD tube, 231-gate of the first PD tube in the first part, 232-gate of the first PD tube in the second part, 240-gate of the second PD tube, 241-gate of the second PD tube in the first part, 242-gate of the second PD tube in the second part, 250-gate of the PG tube. DETAILED DESCRIPTION

[0025] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0026] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0027] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0028] Referring to FIG. 2 , the present invention provides a layout structure of a static random access memory, including:

[0029] A first active area 210 and a second active area 220 , wherein the first active area 210 and the second active area 220 are separated by a shallow trench isolation structure, and the extension directions of the first active area 210 and the second active area 220 are both perpendicular to the horizontal direction;

[0030] The gate 230 of the first PD tube is located on the first active area 210. The gate 230 of the first PD tube is divided into two parts. The gate 231 of the first PD tube in the first part is perpendicular to the extension direction of the first active area 210. The gate 232 of the first PD tube in the second part is connected to the gate 231 of the first PD tube in the first part and the clockwise angle between the gate 231 of the first PD tube and the gate 232 is less than 180 degrees.

[0031] The gate 240 of the second PD tube is located on the second active area 220. The gate 240 of the second PD tube is divided into two parts. The gate 241 of the second PD tube in the first part is perpendicular to the extension direction of the second active area 220. The gate 242 of the second PD tube in the second part is connected to the gate 241 of the second PD tube in the first part and the clockwise angle between the gate 241 of the second PD tube and the gate 242 is less than 180 degrees.

[0032] The gate 242 of the second PD tube in the second part is opposite to the gate 232 of the first PD tube in the second part and the relative distance (referring to the vertical distance between the end faces opposite to each other) meets the photolithography requirements.

[0033] Preferably, the layout structure of the static random access memory in the embodiment of the present invention also includes a gate 250 for a PG transistor. The gate 250 of the PG transistor is connected across the first active area 210 and the second active area 220, and together with the first active area 210 and the second active area 220, forms a PG transistor. The shortest distances between the gate 230 of the first PD transistor and the gate 240 of the second PD transistor and the gate 250 of the PG transistor meet photolithography requirements. Since the layout of the gate of the PG transistor is designed, photolithography conditions must also be met in actual production. Specifically, referring to Figure 2, the embodiment of the present invention has gates 250 for the PG transistor designed at the top and bottom. The gates 232 of the first PD transistor in the second section and the gates 242 of the second PD transistor in the second section are closest to the gate 250 of the PG transistor. Therefore, the shortest distance between the gate 232 of the first PD transistor in the second section and the gate 250 of the PG transistor must meet photolithography requirements, and the shortest distance between the gate 242 of the second PD transistor in the second section and the gate 250 of the PG transistor must also meet photolithography requirements. The shortest distance refers to the shortest distance between a point on the edge of the gate 232 of the first PD tube in the second section or the gate 242 of the second PD tube in the second section and a point on the edge of the gate 250 of the PG tube. In other embodiments of the present invention, the gate oxide layer between the active region and the gate of the PD tube, as well as the sidewalls on both sides of the gate of the PD tube, may also be included. Similarly, the gate oxide layer between the active region and the gate of the PG tube, as well as the sidewalls on both sides of the gate of the PG tube, may also be included.

[0034] In the embodiment of the present invention, the clockwise angle between the gate 232 of the second portion of the first PD tubes and the gate 231 of the first portion of the first PD tubes is 90° to 165°, for example, 135°. The clockwise angle between the gate 242 of the second portion of the second PD tubes and the gate 231 of the first portion of the second PD tubes is 90° to 165°, for example, 135°. The clockwise angle between the gate 232 of the second portion of the first PD tubes and the gate 231 of the first portion of the first PD tubes may be the same as or different from the clockwise angle between the gate 242 of the second portion of the second PD tubes and the gate 241 of the first portion of the second PD tubes.

[0035] In the embodiment of the present invention, the width of the gate 232 of the second portion of the first PD tubes is less than or equal to the width of the gate 231 of the first portion of the first PD tubes. The width of the gate 242 of the second portion of the second PD tubes is less than or equal to the width of the gate 241 of the first portion of the second PD tubes.

[0036] In this embodiment of the present invention, there are multiple gates 230 for first PD tubes, all of which are spaced apart. If there are at least two gates 230 for first PD tubes, the first active region 210 is exposed between the gates 230 of adjacent first PD tubes. There are multiple gates 240 for second PD tubes, all of which are spaced apart. If there are at least two gates 240 for second PD tubes, the second active region 220 is exposed between the gates 240 of adjacent second PD tubes. Because multiple PD tubes can be designed simultaneously, the specific number depends on actual production needs and may be one, two, or more. Therefore, multiple gates 230 for first PD tubes and multiple gates 240 for second PD tubes are designed herein. All of the gates 230 for first PD tubes can be bent in the same direction, preferably at the same bending angle. All of the gates 240 for second PD tubes can be bent in a direction opposite to the bending direction of the gates 230 of the first PD tubes, preferably at the same bending angle. Accordingly, the gate 230 of each first PD tube includes a gate 231 of the first portion of the first PD tube and a gate 232 of the second portion of the first PD tube. Each second PD tube's gate 240 must have opposing portions, including a gate 241 of the first portion of the second PD tube and a gate 242 of the second portion of the second PD tube. Furthermore, the gate 232 of the second portion of the first PD tube faces the gate 242 of the second portion of the second PD tube. Naturally, the shortest distance between the end faces of any gate 232 of the second portion of the first PD tube and any gate 242 of the second portion of the second PD tube meets the requirements of photolithography. If the vertical distance between the end faces of the gates of the first and second PD tubes in the prior art is D, which can be the minimum dimension required by photolithography, then if the vertical distance between the end faces of the gates of the first and second PD tubes is also maintained at D, the horizontal distance between the gates 230 and 240 of the first and second PD tubes, or the horizontal distance between the gates 232 and 242 of the second portion of the first and second PD tubes, is H, which is necessarily less than D. Therefore, compared to the prior art, the horizontal distance between the gates 230 and 240 of the first and second PD tubes is shortened. It can also be considered that, when the gates 230 and 240 of the first and second PD tubes are curved and their horizontal extension lengths remain unchanged, their horizontal distance is reduced. Therefore, if the gates 230 and 240 of the first and second PD tubes in the present embodiment are the same length as those of the prior art and the relative distance between their end faces meets the photolithography requirements, the area of ​​the static random access memory is reduced.

[0037] In summary, the layout structure of the static random access memory provided in the embodiment of the present invention includes: a first active area and a second active area, the first active area and the second active area are separated by a shallow trench isolation structure, and the extension directions of the first active area and the second active area are both perpendicular to the horizontal direction; a gate of the first PD tube located on the first active area, the gate of the first PD tube is divided into two parts, the gate of the first PD tube in the first part is perpendicular to the extension direction of the first active area, the gate of the first PD tube in the second part is connected to the gate of the first PD tube in the first part and the clockwise angle with the gate of the first PD tube in the first part is less than 180°; a gate of the second PD tube located on the second active area, the gate of the second PD tube is divided into two parts, the gate of the second PD tube in the first part is perpendicular to the extension direction of the second active area, the gate of the second PD tube in the second part is connected to the gate of the second PD tube in the first part and the clockwise angle with the gate of the second PD tube in the first part is less than 180°; the gate of the second PD tube in the second part is opposite to the gate of the first PD tube in the second part and the shortest distance between the two in the horizontal direction meets the lithography requirements. The present invention divides the gates of the first and second PD transistors into two equal parts, with the angle between the two parts being less than 180°. This allows the gates of the first and second PD transistors to be curved. Without reducing the gate lengths, and provided the relative distance between the gates of the first and second PD transistors meets photolithography requirements, the horizontal distance between the gates of the first and second PD transistors can be reduced. Consequently, the layout area of ​​the static random access memory is reduced without reducing the horizontal extension lengths of the gates of the first and / or second PD transistors and while meeting photolithography requirements.

[0038] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A layout structure of a static random access memory, characterized in that: include: A first active region and a second active region, wherein the first active region and the second active region are separated by a shallow trench isolation structure, and the extension directions of the first active region and the second active region are both perpendicular to the horizontal direction; A gate of a first PD tube located on the first active region, wherein the gate of the first PD tube is divided into two parts, wherein the gate of the first PD tube in the first part is perpendicular to the extension direction of the first active region, and the gate of the first PD tube in the second part is connected to the gate of the first PD tube in the first part and the clockwise angle with the gate of the first PD tube in the first part is less than 180°; as well as A gate of a second PD tube located on the second active region, wherein the gate of the second PD tube is divided into two parts, wherein the gate of the second PD tube in the first part is perpendicular to the extension direction of the second active region, and the gate of the second PD tube in the second part is connected to the gate of the second PD tube in the first part and the clockwise angle with the gate of the second PD tube in the first part is less than 180°; The gate of the second PD tube in the second part is opposite to the gate of the first PD tube in the second part, and the relative distance meets the photolithography requirements.

2. The layout structure of the static random access memory according to claim 1, characterized in that: It also includes a gate of a PG tube, and the gate of the PG tube is connected across the first active area and the second active area.

3. The layout structure of the static random access memory as claimed in claim 2, characterized in that: The shortest distances between the gate of the first PD tube and the gate of the second PD tube and the gate of the PG tube all meet the photolithography requirements.

4. The layout structure of the static random access memory according to claim 1, characterized in that: The clockwise angle between the gate of the first PD tube in the second part and the gate of the first PD tube in the first part is 90° to 165°.

5. The layout structure of the static random access memory according to claim 1, characterized in that: The clockwise angle between the gate of the second PD tube in the second part and the gate of the second PD tube in the first part is 90° to 165°.

6. The layout structure of the static random access memory according to claim 1, characterized in that: The clockwise angle between the gate of the first PD tube in the second part and the gate of the first PD tube in the first part is the same as the clockwise angle between the gate of the second PD tube in the second part and the gate of the second PD tube in the first part.

7. The layout structure of the static random access memory according to claim 1, characterized in that: The clockwise angle between the gate of the first PD tube in the second part and the gate of the first PD tube in the first part is different from the clockwise angle between the gate of the second PD tube in the second part and the gate of the second PD tube in the first part.

8. The layout structure of the static random access memory according to claim 1, characterized in that: The width of the gate of the first PD tube in the second part is less than or equal to the width of the gate of the first PD tube in the first part.

9. The layout structure of the static random access memory according to claim 1, characterized in that: The width of the gate of the second PD tube in the second part is less than or equal to the width of the gate of the second PD tube in the first part.

10. The layout structure of the static random access memory according to claim 1, characterized in that: There are at least two grid electrodes of the first PD tubes, and there is a certain distance between the grid electrodes of all the first PD tubes.

11. The layout structure of the static random access memory according to claim 1, characterized in that: There are at least two grid electrodes of the second PD tubes, and there is a certain distance between the grid electrodes of all the second PD tubes.

12. The layout structure of the static random access memory according to claim 10, characterized in that: The grid electrodes of all the first PD tubes are bent in the same direction with the same bending angle.

13. The layout structure of the static random access memory according to claim 12, characterized in that: There are at least two gates of the second PD tubes, and the gates of all the second PD tubes are bent in a direction opposite to the bending direction of the gate of the first PD tube.

Images