Gate drive unit and display panel

Abstract

A gate drive unit and a display panel. When the display panel displays at a low refresh rate, a display period corresponding to a display picture includes a plurality of holding frames (HF) in addition to a writing frame (WF). In the writing frame (WF) of the display panel, a clock signal (CK) has a plurality of transitions between an active level state and an inactive level state; and within the plurality of holding frames (HF) of the display panel, the clock signal (CK) has a plurality of first stages (S1) maintaining the inactive level state, and the clock signal (CK) has a plurality of transitions between the active level state and the inactive level state in a second stage (S2) corresponding to two adjacent first stages (S1).

Description

Gate drive unit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving unit and a display panel. Background Art

[0002] When a display panel uses a low refresh rate for display drive, switching the clock signal to a DC state can reduce the display panel's power consumption. However, due to the characteristics of semiconductor devices, transistor leakage current increases in high-temperature environments, causing charge loss at key points in the gate drive circuit that uses the transistor and clock signal. This causes potential changes at key points, leading to abnormal gate control signals output by the gate drive circuit. This in turn causes display anomalies on the display panel that uses the gate control signals, affecting the display quality of the display panel. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a gate driving unit and a display panel, which can improve the problem that the gate control signal becomes abnormal due to the influence of semiconductor device characteristics, thereby affecting the display effect.

[0004] An embodiment of the present application provides a gate drive unit, comprising a plurality of gate drive circuits, wherein the plurality of gate drive circuits are configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of a display panel; each gate drive circuit comprises a start transistor and a first output transistor, wherein the control terminal of the start transistor is configured to receive a corresponding clock signal, the input terminal of the start transistor is configured to receive a start signal, the output terminal of the start transistor is electrically connected to the control terminal of the first output transistor, the input terminal of the first output transistor is electrically connected to a first power supply terminal, and the output terminal of the first output transistor is electrically connected to the first output terminal of the gate drive circuit at this stage. In a write frame of the display panel, the clock signal has multiple transitions between a valid level state and an invalid level state; in multiple hold frames of the display panel, the clock signal has multiple first stages in which the invalid level state is maintained, and the clock signal has multiple transitions between the valid level state and the invalid level state in a second stage between two adjacent first stages.

[0005] The embodiment of the present application also provides a display panel, comprising any of the above-mentioned gate drive units and a plurality of sub-pixels. Each of the sub-pixels includes a light-emitting device and a pixel drive circuit, the pixel drive circuit includes a drive transistor and a data transistor, the drive transistor is configured to generate a drive current for driving the light-emitting device to emit light according to a corresponding data signal, the input end of the data transistor is configured to receive the data signal, and the output end of the data transistor is electrically connected to the input end of the drive transistor. The plurality of gate drive circuits are configured to generate a plurality of gate control signals to be output to the control ends of the data transistors of the plurality of sub-pixels; in the write frame, the data transistors of the plurality of sub-pixels transmit the data signal to the input end of the drive transistor according to the corresponding gate control signal; in the hold frame, the data transistors of the plurality of sub-pixels are cut off according to the corresponding gate control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG1 is a schematic structural diagram of a gate driving unit provided in an embodiment of the present application;

[0007] 2A to 2D are schematic structural diagrams of a gate drive circuit provided in an embodiment of the present application;

[0008] FIG3 is a timing diagram of a clock signal provided in an embodiment of the present application;

[0009] FIG4A is a simulation timing diagram of the gate drive circuit shown in FIG2A ;

[0010] FIG4B is a simulation timing diagram of the gate drive circuit shown in FIG2B ;

[0011] FIG4C is a diagram showing the relationship between the threshold voltage and the potential change of the first node provided in an embodiment of the present application;

[0012] 4D to 4E are simulation timing diagrams of the gate drive circuit under extreme environments provided by an embodiment of the present application;

[0013] 5A to 5G are timing diagrams of corresponding gate drive circuits provided in embodiments of the present application;

[0014] FIG6 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0015] FIG7 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application;

[0016] FIG8 is a timing diagram corresponding to the sub-pixel shown in FIG7 ;

[0017] FIG9 is a simulation verification timing diagram provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0018] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0019] Embodiments of the present application provide a gate drive unit and a display panel. In the writing frame of the display panel, a clock signal is made to have multiple jumps between a valid level state and an invalid level state, so that the gate control signals output by multiple gate drive circuits all have valid pulses; in multiple holding frames of the display panel, the clock signal is made to have multiple first stages of maintaining an invalid level state to save power consumption; and by controlling the clock signal to have multiple jumps between a valid level state and an invalid level state in a second stage corresponding to two adjacent first stages, the problem of abnormal gate control signals output by the gate drive circuit caused by the change in the potential of the control terminal of the first output transistor, which causes the first output transistor to be unable to be fully turned on, is improved.

[0020] Specifically, as shown in Figure 1, which is a structural schematic diagram of a gate driving unit provided in an embodiment of the present application, the present application provides a gate driving unit, including multiple gate driving circuits GDC, and the multiple gate driving circuits GDC are configured to generate multiple gate control signals Scan to output to multiple sub-pixels of a display panel.

[0021] 2A to 2D are schematic structural diagrams of gate drive circuits provided in embodiments of the present application; each gate drive circuit GDC includes at least a start transistor Ts and a first output transistor Tto1.

[0022] The control terminal of the start transistor Ts is configured to receive the corresponding clock signal CK, the input terminal of the start transistor Ts is configured to receive the start signal ST, and the output terminal of the start transistor Ts is electrically connected to the control terminal of the first output transistor Tto1.

[0023] Among them, the multi-stage gate driving circuit cascaded after the first-stage gate driving circuit can receive the first control signal Sc1 output by the previous-stage gate driving circuit from the first output terminal out1 as the start signal ST, and the first-stage gate driving circuit of the multi-stage gate driving circuit can receive the control signal STV generated by devices such as a timing controller as the start signal ST.

[0024] Optionally, the n-th stage gate driver circuit GDC(n) receives the first control signal Sc1(nA) outputted from the first output terminal out1(nA) of the nA-th stage gate driver circuit GDC(nA) as the start signal ST, where A ≥ 1. If the multi-stage gate driver circuit GDC adopts a row-by-row cascade design, the n-th stage gate driver circuit GDC(n) receives the first control signal Sc1(n-1) outputted from the first output terminal out1(n-1) of the n-1-th stage gate driver circuit GDC(n-1) as the start signal ST.

[0025] An input terminal of the first output transistor Tto1 is electrically connected to the first power supply terminal VGL, and an output terminal of the first output transistor Tto1 is electrically connected to the first output terminal out1 of the current-stage gate driving circuit GDC.

[0026] Alternatively, in some embodiments, if the transistor in the display panel that applies the gate control signal Scan output by the gate drive circuit GDC is a P-type transistor, then the input terminal of the first output transistor Tto1 may also be electrically connected to the second power terminal VGH. Optionally, the voltage of the second power terminal VGH is greater than the voltage of the first power terminal VGL.

[0027] 2A to 2D , the gate driving circuit GDC further includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second output transistor Tto2, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0028] The control end of the first transistor T1 is electrically connected to the control end of the start-up transistor Ts, and the input end of the first transistor T1 is electrically connected to the first power end VGL.

[0029] The control end of the second transistor T2 is electrically connected to the output end of the start transistor Ts, the input end of the second transistor T2 is electrically connected to the control end of the start transistor Ts, and the output end of the second transistor T2 is electrically connected to the output end of the first transistor T1.

[0030] The control end of the third transistor T3 is electrically connected to the output end of the first transistor T1 .

[0031] The control terminal of the fourth transistor T4 is electrically connected to the input terminal of the third transistor T3 , and the input terminal of the fourth transistor T4 is electrically connected to the output terminal of the third transistor T3 .

[0032] The control end of the fifth transistor T5 is electrically connected to the output end of the start transistor Ts, the input end of the fifth transistor T5 is electrically connected to the second power supply end VGH, and the output end of the fifth transistor T5 is electrically connected to the output end of the fourth transistor T4.

[0033] The control end of the sixth transistor T6 is electrically connected to the output end of the first transistor T1 , and the input end of the sixth transistor T6 is electrically connected to the second power supply end VGH.

[0034] An input terminal of the seventh transistor T7 is electrically connected to the input terminal of the third transistor T3 , and an output terminal of the seventh transistor T7 is electrically connected to the output terminal of the sixth transistor T6 .

[0035] Optionally, the control terminal of the seventh transistor T7 is electrically connected to the control terminal of the first output transistor Tto1 , as shown in FIG2A .

[0036] 2A to 2D , the control terminal of the second output transistor Tto2 is electrically connected to the output terminal of the fourth transistor T4 , the input terminal of the second output transistor Tto2 is electrically connected to the second power supply terminal VGH , and the output terminal of the second output transistor Tto2 is electrically connected to the output terminal of the first output transistor Tto1 .

[0037] Optionally, in some embodiments, the input terminal of the first output transistor Tto1 is electrically connected to the second power supply terminal VGH, and the input terminal of the second output transistor Tto2 is electrically connected to the first power supply terminal VGL.

[0038] 2A to 2D , the first end of the first capacitor C1 is electrically connected to the control end of the third transistor T3 , and the second end of the first capacitor C1 is electrically connected to the output end of the third transistor T3 .

[0039] A first end of the second capacitor C2 is electrically connected to the control end of the seventh transistor T7 , and a second end of the second capacitor C2 is electrically connected to the output end of the seventh transistor T7 .

[0040] A first end of the third capacitor C3 is electrically connected to the control end of the second output transistor Tto2 , and a second end of the third capacitor C3 is electrically connected to the input end of the second output transistor Tto2 .

[0041] Alternatively, referring to Figures 1 and 2A to 2D, the clock signal CK includes a first clock signal CK1 and a second clock signal CK2. The control terminal of the enable transistor Ts is configured to receive one of the first clock signal CK1 and the second clock signal CK2, and the control terminal of the fourth transistor T4 is configured to receive the other of the first clock signal CK1 and the second clock signal CK2. CKa in Figure 1 corresponds to the control terminal of the enable transistor Ts, and CKb corresponds to the control terminal of the fourth transistor T4.

[0042] Optionally, the control end of the start transistor Ts of one gate drive circuit GDC in the two adjacent gate drive circuits is configured to receive the first clock signal CK1, and the control end of the fourth transistor T4 is configured to receive the second clock signal CK2; the control end of the start transistor Ts of the other gate drive circuit GDC in the two adjacent gate drive circuits GDC is configured to receive the second clock signal CK2, and the control end of the fourth transistor T4 is configured to receive the first clock signal CK1.

[0043] Optionally, the control end of the start transistor Ts of the odd-level gate drive circuit GDC is configured to receive the first clock signal CK1, and the control end of the start transistor Ts of the even-level gate drive circuit GDC is configured to receive the second clock signal CK2; the control end of the fourth transistor T4 of the odd-level gate drive circuit GDC is configured to receive the second clock signal CK2, and the control end of the fourth transistor T4 of the even-level gate drive circuit GDC is configured to receive the first clock signal CK1.

[0044] Optionally, please continue to refer to FIG. 2A to FIG. 2D , the gate driving circuit GDC further includes a first shielding transistor Ta1 and a second shielding transistor Ta2 .

[0045] The input end of the first shielding transistor Ta1 is electrically connected to the output end of the first transistor T1 , and the output end of the first shielding transistor Ta1 is electrically connected to the control end of the third transistor T3 .

[0046] The input end of the second shielding transistor Ta2 is electrically connected to the output end of the start-up transistor Ts, and the output end of the second shielding transistor Ta2 is electrically connected to the control end of the first output transistor Tto1.

[0047] Optionally, the first shielding transistor Ta1 and the second shielding transistor Ta2 are P-type transistors, the control terminal of the first shielding transistor Ta1 is electrically connected to the first power supply terminal VGL, and the control terminal of the second shielding transistor Ta2 is electrically connected to the first power supply terminal VGL. The first shielding transistor Ta1 and the second shielding transistor Ta2 are N-type transistors, the control terminal of the first shielding transistor Ta1 and the control terminal of the second shielding transistor Ta2 are electrically connected to the second power supply terminal VGH.

[0048] Optionally, please continue to refer to FIG. 2B to FIG. 2D , the gate driving circuit GDC further includes an eighth transistor T8 and a ninth transistor T9 .

[0049] The control end of the eighth transistor T8 and the input end of the eighth transistor T8 are electrically connected to the control end of the seventh transistor T7 , and the output end of the eighth transistor T8 is electrically connected to the control end of the first output transistor Tto1 .

[0050] The control end of the ninth transistor T9 is electrically connected to the control end of the start transistor Ts, the input end of the ninth transistor T9 is electrically connected to the input end of the start transistor Ts, and the output end of the ninth transistor T9 is electrically connected to the control end of the seventh transistor T7.

[0051] Optionally, referring to Figures 2B to 2D , the gate drive circuit GDC further includes a third shielding transistor Ta3. The input terminal of the third shielding transistor Ta3 is electrically connected to the output terminal of the ninth transistor T9, and the output terminal of the third shielding transistor Ta3 is electrically connected to the control terminal of the eighth transistor T8. Optionally, the third shielding transistor Ta3 is a P-type transistor, and the control terminal of the third shielding transistor Ta3 is electrically connected to the first power supply terminal VGL. The third shielding transistor Ta3 is an N-type transistor, and the control terminal of the third shielding transistor Ta3 is electrically connected to the second power supply terminal VGH.

[0052] Optionally, please continue to refer to Figures 2A to 2D. The gate drive circuit GDC also includes a tenth transistor Tai, the control end of the tenth transistor Tai is electrically connected to the power-on reset control line CL, the input end of the tenth transistor Tai is electrically connected to the second power supply end VGH, and the output end of the tenth transistor Tai is electrically connected to the control end of the first output transistor Tto1.

[0053] Optionally, please continue to refer to Figures 2C to 2D. The gate drive circuit GDC also includes a first frequency-dividing transistor Tf1, the control end of the first frequency-dividing transistor Tf1 is electrically connected to the first frequency-dividing control line that transmits the first frequency-dividing control signal FD1, the input end of the first frequency-dividing transistor Tf1 is electrically connected to the output end of the fourth transistor T4, and the output end of the first frequency-dividing transistor Tf1 is electrically connected to the control end of the second output transistor Tto2.

[0054] Optionally, referring to FIG. 2D , the gate driving circuit GDC further includes a second frequency dividing transistor Tf2 , a third frequency dividing transistor Tf3 , a fourth frequency dividing transistor Tf4 , a third output transistor Tto3 , a fourth output transistor Tto4 and a fourth capacitor C4 .

[0055] The control terminal of the second frequency-dividing transistor Tf2 is electrically connected to the output terminal of the start-up transistor Ts, and the input terminal of the second frequency-dividing transistor Tf2 is electrically connected to the second frequency-dividing control line transmitting the second frequency-dividing control signal FD2.

[0056] The control end of the third frequency-dividing transistor Tf3 is electrically connected to the output end of the second frequency-dividing transistor Tf2 , and the input end of the third frequency-dividing transistor Tf3 is electrically connected to the control end of the second output transistor Tto2 .

[0057] The control end of the fourth frequency-dividing transistor Tf4 is electrically connected to the control end of the second frequency-dividing transistor Tf2, the input end of the fourth frequency-dividing transistor Tf4 is electrically connected to the second power supply end VGH, and the output end of the fourth frequency-dividing transistor Tf4 is electrically connected to the output end of the third frequency-dividing transistor Tf3.

[0058] The control end of the third output transistor Tto3 is electrically connected to the control end of the first output transistor Tto1, the input end of the third output transistor Tto3 is electrically connected to the first power supply end VGL, and the output end of the third output transistor Tto3 is electrically connected to the second output end out2 of the current stage gate drive circuit GDC.

[0059] The control end of the fourth output transistor Tto4 is electrically connected to the output end of the third frequency-dividing transistor Tf3 , the input end of the fourth output transistor Tto4 is electrically connected to the second power supply end VGH , and the output end of the fourth output transistor Tto4 is electrically connected to the output end of the third output transistor Tto3 .

[0060] Optionally, in some embodiments, the input terminal of the third output transistor Tto3 is electrically connected to the second power supply terminal VGH; the input terminal of the fourth output transistor Tto4 is electrically connected to the first power supply terminal VGL.

[0061] A first end of the fourth capacitor C4 is electrically connected to the input end of the fourth output transistor Tto4 , and a second end of the fourth capacitor C4 is electrically connected to the control end of the fourth output transistor Tto4 .

[0062] Optionally, please continue to refer to Figure 2D, the gate driving circuit GDC also includes a fifth capacitor C5, a first end of the fifth capacitor C5 is electrically connected to the output end of the second frequency dividing transistor Tf2, and a second end of the fifth capacitor C5 is electrically connected to the input end of the fourth output transistor Tto4.

[0063] Figure 3 is a timing diagram of clock signals provided in an embodiment of the present application. Data1 represents the data signal corresponding to the write frame WF when the display panel uses a high refresh rate (e.g., a refresh rate ≥ 120 Hz) for display. Data2 represents the data signal corresponding to the write frame WF when the display panel uses a low refresh rate (e.g., a refresh rate < 120 Hz) for display.

[0064] When the display panel uses a low refresh rate (such as a refresh rate of less than 120Hz) for display, the display panel includes, in addition to the write frame WF, at least one frame corresponding to the hold frame HF in a display cycle corresponding to the display of the same picture. Specifically, within the write frame WF, the display picture is displayed according to the received data signal; within the hold frame HF, the display picture is displayed according to the data signal received by the write frame WF of the same display cycle. Therefore, during the duration corresponding to the hold frame HF, if the clock signal CK still maintains the jump between the valid level state and the invalid level state at the same frequency as the write frame WF (as shown in timing ① in Figure 3), then the display panel using the gate drive unit will have a large power consumption.

[0065] Therefore, to reduce power consumption of a display panel employing a gate driver unit, the clock signal CK employed by the gate driver unit may have a first phase S1 during the display panel's hold frame HF, during which it remains at an inactive level. For example, if both the enable transistor Ts and the fourth transistor T4 are P-type transistors, the clock signal CK may have a first phase S1 during the hold frame HF during which it remains at a high level, thereby turning off the enable transistor Ts and the fourth transistor T4 during the hold frame HF. Correspondingly, when the clock signal CK is at an active level, the enable transistor Ts is turned on.

[0066] It can be understood that when the display panel adopts a low refresh frequency for display, the display panel may include a plurality of hold frames HF corresponding to one display cycle.

[0067] Optionally, within a plurality of hold frames HF of the display panel, the clock signal CK has at least one first phase S1 of maintaining an inactive level state, so as to reduce power consumption of the display panel using the gate driving unit.

[0068] Optionally, the clock signal CK has a first stage S1 in which it maintains an invalid level state, and the duration corresponding to the first stage S1 is equal to the sum of the durations of all maintained frames HF in a display cycle, as shown in timing ② in Figure 3, so as to minimize the power consumption of the display panel.

[0069] Optionally, when the display panel adopts low-frequency display, the corresponding refresh frequency of the display panel may be equal to 90 Hz, 60 Hz, 30 Hz, 10 Hz, 1 Hz, etc. Optionally, when the display panel adopts low-frequency display, the corresponding refresh frequency of the display panel may be less than 1 Hz.

[0070] However, the lower the refresh rate of the display panel, the longer the clock signal CK remains in an inactive state, and the more likely the reliability of the display panel will be affected. For example, if the display panel uses a 120Hz frequency as the high refresh rate and a 1Hz frequency as the low refresh rate, then when the refresh rate of the display panel is 1Hz, the number of frames corresponding to the write frame WF is 1 frame, and the number of frames corresponding to the hold frame HF is 119 frames. Accordingly, the clock signal CK needs to remain in an inactive state for 119 frames. During the period when the clock signal CK remains in an inactive state, some transistors in the gate drive circuit GDC (such as the start transistor Ts) are subject to bias for a long time, causing the threshold voltage to drift, which in turn causes the leakage current of the transistor to increase. As a result, the gate control signal Scan output by the gate drive circuit GDC deviates from expectations, resulting in reliability issues for the display panel using the gate drive unit.

[0071] Therefore, in order to reduce the power consumption of the display panel while reducing the probability of reliability problems, the transition frequency of the clock signal CK corresponding to at least one holding frame HF between the valid level state and the invalid level state is made smaller than the transition frequency between the valid level state and the invalid level state of the write frame WF in the same display cycle, as shown in timing ③ in FIG3 .

[0072] Optionally, the transition frequencies of the clock signal CK between the active level state and the inactive level state corresponding to different hold frames HF in the same display period may be different or the same.

[0073] However, due to the jump between the valid level state and the invalid level state of the clock signal CK corresponding to the maintenance frame HF, some transistors of the gate driving circuits GDC of each level of the gate driving unit will continue to experience the cycle of on and off states, and some transistors of the multi-level gate driving circuits GDC experience the same cycle period of on and off states, resulting in the display panel using the gate driving unit still having a large power consumption. For example, if the control end of the start transistor Ts of the odd-level gate drive circuit GDC receives the first clock signal CK1, the control end of the fourth transistor T4 of the odd-level gate drive circuit GDC receives the second clock signal CK2, the control end of the start transistor Ts of the even-level gate drive circuit GDC receives the second clock signal CK2, and the control end of the fourth transistor T4 of the even-level gate drive circuit GDC receives the first clock signal CK1, within a hold frame HF, when the first clock signal CK1 has a valid level state and the second clock signal CK2 has an invalid level state, then the start transistor Ts of the odd-level gate drive circuit GDC is turned on at the same time, and the fourth transistor T4 of the even-level gate drive circuit GDC is turned on at the same time; when the first clock signal CK1 has an invalid level state and the second clock signal CK2 has a valid level state, the start transistor Ts of the even-level gate drive circuit GDC is turned on at the same time, and the fourth transistor T4 of the odd-level gate drive circuit GDC is turned on at the same time. Therefore, when the first clock signal CK1 has multiple transitions between the valid level state and the invalid level state within the holding frame HF, the second clock signal CK2 also correspondingly has multiple transitions between the invalid level state and the valid level state, thereby causing the starting transistor Ts, the fourth transistor T4 and other transistors of the multi-stage gate drive circuit GDC to continuously experience the cycle of on and off states, and the number of transistors corresponding to on-state in the same period is relatively large, resulting in higher power consumption of the display panel.

[0074] Furthermore, due to transistor characteristics, at high temperatures (e.g., 85°C), transistor leakage current increases, leading to charge loss at key nodes in the gate driver circuit GDC (e.g., first node N1 corresponding to the control terminal of the first output transistor Tto1). This causes potential variations, leading to abnormalities in the first control signal Sc1 output by the gate driver circuit GDC, thus affecting the display quality of the display panel. For the gate driver circuit GDC shown in FIG2D , potential variations at the first node N1 also cause abnormalities in the second control signal Sc2 output by the gate driver circuit GDC.

[0075] The gate drive circuit GDC shown in Figures 2A to 2D provided in this application has better stability for the potential of key nodes (such as the first node N1) than the gate drive circuit GDC shown in Figure 2A. Figure 4A is a simulation timing diagram of the gate drive circuit shown in Figure 2A, Figure 4B is a simulation timing diagram of the gate drive circuit shown in Figure 2B, and Figure 4C is a diagram showing the relationship between the threshold voltage and the potential change of the first node provided in an embodiment of this application. Among them, Scan (1) represents the gate control signal output by the first-level gate drive circuit GDC (1); Scan (2) represents the gate control signal output by the second-level gate drive circuit GDC (2); Scan (3) represents the gate control signal output by the third-level gate drive circuit GDC (3); and the second node N2 corresponds to the output end of the start transistor.

[0076] The inventors conducted simulation verification using the first output transistor Tto1 as a P-type transistor as an example. The simulation results show that when the clock signal CK has a first phase S1 in which it maintains an inactive level state, and the duration corresponding to the first phase S1 is equal to the sum of the durations of all hold frames HF in a display cycle (as shown in timing ② in FIG3 ), the voltage of the first node N1 of the gate drive circuit GDC shown in FIG2A is approximately -6.66 V. Furthermore, as shown in FIG4C , as the threshold voltage Vth of the transistor becomes more negative, the voltage of the first node N1 is more affected by the threshold voltage of the transistor, resulting in a faster rise in the potential of the first node N1, which prevents the first output transistor Tto1 from fully conducting. As a result, the first power signal transmitted by the first power terminal VGL cannot be effectively transmitted to the first output terminal out1, which in turn causes the voltage value of the first control signal Sc1 output by the first output terminal out1 to gradually rise. In severe cases, the first control signal Sc1 cannot meet the usage requirements. When the clock signal CK has a first stage S1 in which it maintains an invalid level state, and the duration corresponding to the first stage S1 is equal to the sum of the durations of all the holding frames HF of a display cycle (as shown in timing ② in Figure 3), the voltage of the first node N1 of the gate drive circuit GDC shown in Figure 2B can be stabilized at -21.1V, enabling the first output transistor Tto1 to be fully turned on, and the first power supply signal can be effectively transmitted to the first output terminal out1.

[0077] Therefore, the gate drive circuit GDC shown in Figures 2B to 2D can lower the potential of the first node N1 compared to the gate drive circuit GDC shown in Figure 2A. When the clock signal CK has a first phase S1 in which it remains in an inactive state, and the first phase S1 corresponds to the duration of multiple hold frames HF, the gate drive circuit GDC shown in Figures 2B to 2D can still ensure that the potential of the first node N1 meets the requirements, thereby allowing the first power supply signal to be transmitted to the first output terminal out1 of the gate drive circuit GDC, achieving complete output of the first power supply signal.

[0078] However, under extreme conditions such as high temperatures, the leakage current of the transistors can increase by orders of magnitude, causing the charge at the first node N1 of the gate drive circuit GDC shown in Figures 2B to 2D to exchange charge through transistors such as the eighth transistor T8 and the second shielding transistor Ta2. This causes the voltage of the first node N1 to increase, resulting in the first output transistor Tto1 not being fully turned on. This in turn prevents the first power signal from being effectively transmitted to the first output terminal out1, causing the voltage of the first control signal Sc1 output from the first output terminal out1 to gradually increase. For the gate drive circuit GDC shown in Figure 2D, the increase in the voltage at the first node N1 also causes the voltage of the second control signal Sc2 output from the second output terminal out2 to gradually increase.

[0079] Figures 4D through 4E are simulation timing diagrams of the gate drive circuit provided by the present invention under extreme environments (e.g., high temperature environments). The simulation timing diagrams show that, under extreme environments such as high temperature, the potential of the first node N1 is not maintained as expected, affecting the gate control signal Scan output by the gate drive circuit GDC, causing the gate control signal Scan to spike and become high when it should remain low.

[0080] Therefore, in order to reduce power consumption while ensuring that the potentials of key nodes of the gate drive circuit GDC can still meet the expected usage requirements in extreme environments such as high temperatures, within multiple hold frames HF of the display panel, the clock signal CK has multiple first stages S1 in which it maintains an invalid level state, and the clock signal CK has multiple jumps between the valid level state and the invalid level state in the second stage S2 corresponding to the interval between two adjacent first stages S1. The potentials of key nodes in the gate drive circuit GDC are refreshed multiple times through the changes in the clock signal CK corresponding to the second stage S2, thereby resetting the potentials of key nodes in the gate drive circuit GDC to the expected state, thereby improving the potential stability of key nodes in the gate drive circuit GDC, and ensuring that the potentials of key nodes in the gate drive circuit GDC can meet the expected usage requirements in extreme environments such as high temperatures while achieving power consumption reduction.

[0081] In the writing frame WF of the display panel, the clock signal CK has multiple jumps between the valid level state and the invalid level state, so that the multi-level gate drive circuit GDC cooperates with the valid pulse of the start signal ST received by the start transistor Ts of the first-level gate drive circuit GDC to generate multiple gate control signals Scan with valid pulses to be output to the display panel, thereby assisting the display panel to realize functions such as writing data signals.

[0082] Optionally, the holding frame HF includes a display phase dt and a vertical blanking interval phase bt. The second phase S2 corresponds to at least the vertical blanking interval phase bt. By making the clock signal CK have multiple jumps between the valid level state and the invalid level state during the vertical blanking interval phase bt, the potential of the key node in the gate drive circuit GDC is refreshed multiple times, so that the potential of the key node in the gate drive circuit GDC is reset to the expected state during the vertical blanking interval phase bt. Moreover, since the duration of the display phase dt is longer than the duration of the vertical blanking interval phase bt, the number of times that some transistors in the multi-stage gate drive circuit GDC switch between the on state and the off state according to the clock signal CK is reduced, so that the number of times the display panel controls multiple transistors to be turned on at the same time is reduced. Therefore, compared with the design shown in timing ③ in Figure 3, the design shown in timing ④ in Figure 3 of the present application is more conducive to reducing the power consumption of the display panel.

[0083] Optionally, in the same vertical blanking interval bt, the number of valid pulses of the clock signal CK is greater than or equal to 1. That is, in the same vertical blanking interval bt, the clock signal CK has at least one valid level state. For example, in the same vertical blanking interval bt, the number of valid pulses of the clock signal CK is equal to 2, 5, 10, 12, etc.

[0084] Optionally, the write frame WF also includes a display phase dt and a vertical blanking interval phase bt. In the vertical blanking interval phase bt of the write frame WF, the clock signal CK can correspond to multiple jumps between a valid level state and an invalid level state, so that the clock signal CK maintains the same change pattern within the write frame WF, so as to effectively complete the control of the data writing phase of the latter few rows of sub-pixels Pi in the display panel, so that the write frame WF has a better display effect.

[0085] Optionally, during the vertical blanking interval bt of the writing frame WF, the clock signal CK may also be kept at an inactive level.

[0086] Optionally, during the same vertical blanking interval bt of the hold frame HF, the frequency of the clock signal CK can be varied so that the duration of each active state of the clock signal CK varies. That is, during the vertical blanking interval bt of the hold frame HF, when the clock signal CK transitions between an active state and an inactive state multiple times, the durations of at least two active states can vary.

[0087] Optionally, after the duration of the hold frame HF, the potential offset of the key node accumulates, resulting in a large potential offset of the key node. Therefore, in order to effectively and quickly restore the potential of the key node to the expected state, during the same vertical blanking interval bt of the hold frame HF, the frequency of the clock signal CK can be gradually increased so that the duration of the first inactive level state of the clock signal CK is greater than the duration of any one of the multiple inactive level states following the first inactive level state, so that the potential of the key node continues to receive the corresponding control signal during the duration corresponding to the first inactive level state of the clock signal CK, thereby controlling the corresponding transistor to restore to the expected operating state.

[0088] For example, if the control terminal of the start transistor Ts receives the first clock signal CK1, during the same vertical blanking interval bt of the frame HF, the duration of the first invalid level state of the first clock signal CK1 is greater than the duration of any other invalid level state. Then, during the duration of the first invalid level state of the first clock signal CK1, the start transistor Ts is turned on. Since the start signal ST is in an effective level state that can turn on the first output transistor Tto1, the potential of the first node N1 is reset by the start signal ST, so that the first power supply signal can be effectively output to the first output terminal out1, leaving a time margin for the potential recovery of the first node N1 and the recovery of the first control signal Sc1 output from the first output terminal out1, so that the potential of the first node N1 and the first output terminal out1 can be effectively and quickly restored to the expected level.

[0089] Optionally, during the same vertical blanking interval bt of the frame HF, the frequency of the clock signal CK may also be kept the same to reduce control complexity.

[0090] Optionally, the number of times the clock signal CK switches between the active level state and the inactive level state corresponding to the vertical blanking intervals bt of different hold frames HF may be the same or different. The duration of the active level state of the clock signal CK corresponding to the vertical blanking intervals bt of different hold frames HF may be the same or different.

[0091] Optionally, in order to make the display effect of the display panel using the gate driving unit similar in each holding frame HF, the duration of multiple first stages S1 can be made equal, so that the clock signal CK has multiple jumps between the valid level state and the invalid level state after a fixed duration, so that the potential of the key node in the gate driving circuit GDC is reset to the expected state after a fixed duration.

[0092] Alternatively, referring to FIG. 3 , to ensure that the gate control signal Scan output by the gate drive unit sequentially has valid pulses during the write frame WF, the first clock signal CK1 and the second clock signal CK2 are inverted during the write frame WF. During the hold frame HF, the first phase S1 in which the first clock signal CK1 remains in an inactive state overlaps with the first phase S1 in which the second clock signal CK2 remains in an inactive state, and the second phase S2 of the first clock signal CK1 overlaps with the second phase S2 of the second clock signal CK2. This ensures that the operating states of the multi-stage gate drive circuit GDC are consistent. This means that some transistors (such as the start transistor Ts and the first transistor T1) of the multi-stage gate drive circuit GDC are all in an off state during the first phase S1, thereby reducing power consumption of the display panel. Meanwhile, some transistors (such as the start transistor Ts and the first transistor T1) of the multi-stage gate drive circuit GDC (such as the odd-stage gate drive circuit GDC and / or the even-stage gate drive circuit GDC) are all in an on state during the second phase S2, resetting the potentials of key nodes (such as the first node N1) to the expected state.

[0093] Optionally, in order to reduce the demand on the display panel driving side and reduce power consumption, in the second stage S2 corresponding to the first clock signal CK1, the first clock signal CK1 and the second clock signal CK2 are inverted so that the reset action of the key node potential of the multi-stage gate drive circuit GDC does not occur at the same time.

[0094] Optionally, in the second phase S2 corresponding to the first clock signal CK1 , the first clock signal CK1 may also be in phase with the second clock signal CK2 .

[0095] Optionally, during the display phase dt of the frame HF, the clock signal CK may also have a second phase S2 to reset the potential of the key node of the gate driving circuit GDC during the display phase dt of the frame HF.

[0096] Continuing with Figures 2A and 2B , the first control signal Sc1 outputted from the first output terminal out1 can be transmitted to the display panel as the gate control signal Scan. In the gate drive circuit GDC shown in Figure 2C , although the gate drive circuit GDC can be used to implement different refresh rates for different display areas of the display panel, the first control signal Sc1 outputted from the first output terminal out1 of the gate drive circuit GDC is still transmitted to the display panel as the gate control signal Scan. Furthermore, in the gate drive unit shown in Figures 2A to 2C , the first control signal Sc1 outputted from the first output terminal out1 of the current-stage gate drive circuit GDC can also be reused as the start signal ST for the next-stage gate drive circuit GDC, thereby implementing a multi-stage gate drive circuit GDC stage transmission configuration.

[0097] In the gate driver circuit GDC shown in FIG2D , the gate driver circuit GDC can be used to implement a display panel having different refresh rates for different display areas. A first control signal Sc1 outputted from a first output terminal out1 of the gate driver circuit GDC serves as a start signal ST for a subsequent gate driver circuit GDC, thereby implementing a multi-stage gate driver circuit GDC configuration. A second control signal Sc2 outputted from a second output terminal out2 of the gate driver circuit GDC serves as a gate control signal Scan and is transmitted to the display panel.

[0098] Figures 5A to 5D are timing diagrams of the gate drive circuit provided in an embodiment of the present application. Figure 5A corresponds to the timing diagram of the gate drive circuit shown in Figure 2A , Figure 5B corresponds to the timing diagram of the gate drive circuit shown in Figures 2B to 2C , Figure 5C corresponds to the timing diagram of the gate drive circuit shown in Figure 2C , and Figures 5D to 5F correspond to the timing diagram of the gate drive circuit shown in Figure 2D .

[0099] Taking the case where all transistors included in each gate drive circuit GDC are P-type, the transistors in the display panel that apply the gate control signal Scan are N-type, the first shielding transistor Ta1 and the second shielding transistor Ta2 are always kept in the on state, the control end of the start transistor Ts of the n-th stage gate drive circuit GDC(n) receives the first clock signal CK1, and the control end of the fourth transistor T4 receives the second clock signal CK2 as an example, the working principle of the gate drive circuit GDC is explained.

[0100] First working phase t1: the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST (such as Sc1 (n-1)) received by the n-th stage gate driving circuit GDC(n) is at a low level.

[0101] In the gate drive circuit GDC shown in FIG2A , the fourth transistor T4 of the n-th stage gate drive circuit GDC(n) is turned off, the first transistor T1 and the start transistor Ts are turned on, and the start signal ST received by the n-th stage gate drive circuit GDC(n) is transmitted to the first node N1. The second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1 are turned on. The third transistor T3 and the sixth transistor T6 are turned on in response to the first power signal and the first clock signal CK1. The second clock signal CK2 is transmitted to the first capacitor C1, which is electrically connected to the input terminal of the fourth transistor T4. The second power signal is transmitted to the output terminal of the sixth transistor T6 to charge the second capacitor C2. The second power signal is transmitted to the control terminal of the second output transistor Tto2, turning the second output transistor Tto2 off. The second clock signal CK2 is also transmitted to the output terminal of the sixth transistor T6. The first output transistor Tto1 is turned on, causing the first power signal to be output to the first output terminal out1 of the n-th stage gate drive circuit GDC(n).

[0102] In the gate driving circuit GDC shown in FIG. 2B to FIG. 2C , the ninth transistor T9 and the eighth transistor T8 of the n-th stage gate driving circuit GDC(n) are also turned on.

[0103] In the gate drive circuit GDC shown in Figure 2D, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the n-th stage gate drive circuit GDC(n) are also turned on, the first power supply signal is output to the second output terminal out2, and the fourth output transistor Tto4 is turned off.

[0104] In the second working phase t2 , the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the start signal ST received by the n-th gate driving circuit GDC(n) is at a low level.

[0105] In the gate drive circuit GDC shown in FIG2A , the first transistor T1 and the start-up transistor Ts of the n-stage gate drive circuit GDC(n) are turned off, and the fourth transistor T4 is turned on. A second capacitor C2 maintains the conduction of the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1. The third transistor T3 and the sixth transistor T6 are turned off in response to the second clock signal CK2. The second clock signal CK2 is coupled to the potential of the input terminal of the fourth transistor T4 via the first capacitor C1, and the second output transistor Tto2 is turned off. The second clock signal CK2 is coupled via the second capacitor C2, further lowering the potential at the first node N1. The first output transistor Tto1 remains on, and the first power supply signal is output to the first output terminal out1 of the n-stage gate drive circuit GDC(n) via the first output transistor Tto1.

[0106] In the gate driving circuit GDC shown in FIG. 2B to FIG. 2D , the ninth transistor T9 of the n-th stage gate driving circuit GDC(n) is turned off, and the second capacitor C2 also keeps the eighth transistor T8 turned on.

[0107] In the gate drive circuit GDC shown in Figure 2D, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the n-th stage gate drive circuit GDC(n) remain turned on, the first power supply signal is output to the second output terminal out2, and the fourth output transistor Tto4 is turned off.

[0108] In the gate driver circuit GDC shown in FIG2D , if the third frequency-dividing transistor Tf3 of the n-th-stage gate driver circuit GDC(n) is turned on according to the second frequency-dividing control signal FD2, the control terminal of the fourth output transistor Tto4 is electrically connected to the control terminal of the second output control transistor. If the third frequency-dividing transistor Tf3 of the n-th-stage gate driver circuit GDC(n) is turned off according to the second frequency-dividing control signal FD2, the control terminal of the fourth output transistor Tto4 is electrically disconnected from the control terminal of the second output control transistor.

[0109] In the third working phase t3 , the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST received by the n-th gate driving circuit GDC(n) is at a high level.

[0110] In the gate drive circuit GDC shown in FIG2A , the fourth transistor T4 of the n-th stage gate drive circuit GDC(n) is turned off; the first transistor T1 and the start transistor Ts are turned on, and the start signal ST received by the n-th stage gate drive circuit GDC(n) is transmitted to the first node N1. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the first output transistor Tto1 are turned off, while the third transistor T3 and the sixth transistor T6 are turned on. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 via the third transistor T3, and the second power supply signal charges the second capacitor C2 via the sixth transistor T6. The third capacitor C3 maintains the second output transistor Tto2 in the off state. The gate control signal Scan(n) output by the n-th stage gate drive circuit GDC(n) maintains the output state of the previous stage.

[0111] In the gate driving circuit GDC shown in FIG. 2B to FIG. 2D , the ninth transistor T9 of the n-th stage gate driving circuit GDC(n) is turned on, the start signal ST is transmitted to the control terminal of the eighth transistor T8 , and the eighth transistor T8 is turned off.

[0112] In the gate driving circuit GDC shown in FIG2D , the third output transistor Tto3 , the second frequency dividing transistor Tf2 , and the fourth frequency dividing transistor Tf4 are turned off, the fourth output transistor Tto4 remains in the off state, and the third frequency dividing transistor Tf3 remains in the same state as in the second stage S2 .

[0113] In the fourth working phase t4 , the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the start signal ST received by the n-th gate driving circuit GDC(n) is at a high level.

[0114] In the gate drive circuit GDC shown in FIG2A , the first transistor T1 and the start transistor Ts of the n-stage gate drive circuit GDC(n) are turned off, the fourth transistor T4 is turned on, and the second capacitor C2 keeps the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1 turned off. The first capacitor C1 keeps the third transistor T3 turned on. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 via the third transistor T3, and is coupled through the first capacitor C1 to lower the potential of the control terminal of the third transistor T3, thereby turning on the sixth transistor T6. The second power signal is coupled through the second capacitor C2 to raise the potential of the first node N1. The second output transistor Tto2 is turned on, and the second power signal is transmitted to the first output terminal out1 of the n-stage gate drive circuit GDC(n).

[0115] In the gate driving circuit GDC shown in FIG. 2B to FIG. 2D , the ninth transistor T9 and the eighth transistor T8 of the n-th stage gate driving circuit GDC(n) are turned off.

[0116] In the gate drive circuit GDC shown in FIG2C , if the first frequency-dividing transistor Tf1 of the n-th stage gate drive circuit GDC(n) is turned off according to the first frequency-dividing control signal FD1, then the second output transistor Tto2 remains turned off, and the gate control signal Scan(n) outputted from the first output terminal out1 maintains the same state as in the third stage, as shown in FIG5C . Thus, in a display panel using the gate drive unit, the transistor controlled by the gate control signal Scan(n) is rendered non-conductive, thereby facilitating the display panel to achieve different refresh frequencies for different display areas. If the first frequency-dividing transistor Tf1 of the n-th stage gate drive circuit GDC(n) is turned on according to the first frequency-dividing control signal FD1, then the second output transistor Tto2 is turned on, and the second power supply signal is transmitted to the first output terminal out1 of the n-th stage gate drive circuit GDC(n), as shown in FIG5B .

[0117] In the gate driving circuit GDC shown in FIG2D , the third output transistor Tto3 , the second frequency dividing transistor Tf2 and the fourth frequency dividing transistor Tf4 of the n-th stage gate driving circuit GDC(n) are turned off, and the third frequency dividing transistor Tf3 maintains the same state as in the second stage S2 .

[0118] In the gate driver circuit GDC shown in FIG2D , if the first frequency-dividing transistor Tf1 of the n-th-stage gate driver circuit GDC(n) is turned off, then when the third frequency-dividing transistor Tf3 is turned on, the first control signal Sc1(n) outputted by the first output terminal out1 maintains the same state as in the third stage, resulting in no valid pulses in the start signal ST received by the gate driver circuit GDC cascaded after the n-th-stage gate driver circuit GDC(n), thereby preventing the subsequent-stage gate driver circuit GDC from outputting a control signal that implements the cascade design. The second control signal Sc2 outputted by the second output terminal out2 maintains the same state as in the third stage, resulting in no valid pulses in the gate control signal Scan(n) outputted by the gate driver circuit GDC from the second output terminal out2, as shown in FIG5D . This results in the transistors within the display panel controlled by the gate control signal Scan(n) being turned off, thereby facilitating different refresh rates for different display areas of the display panel. When the third frequency-dividing transistor Tf3 is turned off, the fourth output transistor Tto4 remains turned off because the first frequency-dividing transistor Tf1 is turned off, causing the second control signal Sc2 output from the second output terminal out2 to maintain the same state as in the third stage. The gate control signal Scan(n) output from the second output terminal out2 by the gate drive circuit GDC has no valid pulses, as shown in FIG5D . This causes the transistors in the display panel controlled by the gate control signal Scan(n) to be non-conductive, thereby facilitating the display panel to achieve different refresh rates for different display areas. That is, regardless of whether the second frequency-dividing signal FD2 is in an active level state that turns on the third frequency-dividing transistor Tf3 or in an inactive level state that turns off the third frequency-dividing transistor Tf3, the fourth output transistor Tto4 cannot receive the corresponding control signal and thus turns on due to the off-state of the first frequency-dividing transistor Tf1, resulting in no valid pulses in the gate control signal Scan(n) output from the second output terminal out2.

[0119] If the first frequency-dividing transistor Tf1 of the n-stage gate driver circuit GDC(n) is turned on, then when the third frequency-dividing transistor Tf3 is turned on, the second output transistor Tto2 is turned on, and the second power supply signal is transmitted to the first output terminal out1 of the n-stage gate driver circuit GDC(n), causing the first control signal Sc1(n) output from the first output terminal out1 to have a valid pulse. The gate driver circuit GDC, cascaded to the n-stage gate driver circuit GDC(n), implements a cascade design based on the first control signal Sc1(n) output from the n-stage gate driver circuit GDC(n), as shown in FIG5E . The second power supply signal is transmitted to the second output terminal out2 of the n-stage gate driver circuit GDC(n), causing the second control signal Sc2 output from the second output terminal out2 to have a valid pulse, as shown in FIG5E . This turns on the transistors within the display panel controlled by the gate control signal Scan(n), thereby maintaining the refresh rate of the corresponding display area of ​​the display panel. When the third frequency-dividing transistor Tf3 is turned off, the first frequency-dividing transistor Tf1 is turned on, and thus the first control signal Sc1(n) outputted from the first output terminal out1 still has valid pulses, as shown in FIG5F . This allows the gate drive circuit GDC, which is cascaded to the n-th stage gate drive circuit GDC(n), to implement a cascade design based on the first control signal Sc1(n) outputted from the n-th stage gate drive circuit GDC(n). Since the third frequency-dividing transistor Tf3 is turned off, the fourth output transistor Tto4 remains off, causing the second control signal Sc2 outputted from the second output terminal out2 to maintain the same state as in the third stage. The gate control signal Scan(n) outputted from the second output terminal out2 by the gate drive circuit GDC has no valid pulses, as shown in FIG5F . This causes the transistors in the display panel controlled by the gate control signal Scan(n) to be turned off, and subsequently causes the refresh frequency of the corresponding display area in the display panel to begin to vary, thereby facilitating different refresh frequencies for different display areas of the display panel.

[0120] Fifth working phase t5: the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST received by the n-th stage gate driving circuit GDC(n) is at a low level.

[0121] In the gate drive circuit GDC shown in FIG2A , the fourth transistor T4 of the n-th stage gate drive circuit GDC(n) is turned off, the first transistor T1 and the start transistor Ts are turned on, and the start signal ST is transmitted to the first node N1. However, because the first node N1 is electrically connected to the second capacitor C2, when the first node N1 changes from a high potential to a low potential, the potential of the first node N1 is affected by the charging rate of the second capacitor C2, resulting in the first node N1 not reaching a state that fully turns on the first output transistor Tto1. As a result, the first output transistor Tto1 is partially turned on. The second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned on in response to the signal at the second node N2. The third transistor T3 and the sixth transistor T6 are turned on in response to the third voltage and the first clock signal CK1. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 via the third transistor T3, the second power signal is transmitted to the output terminal of the sixth transistor T6, and the second power signal is transmitted to the control terminal of the second output transistor Tto2, turning the second output transistor Tto2 off. The seventh transistor T7 is turned on, causing the second clock signal CK2 to be transmitted to the output terminal of the seventh transistor T7. When the first output transistor Tto1 is turned on, the first power signal is output to the first output terminal out1 of the n-th gate driver circuit GDC(n). Due to the charging rate of the second capacitor C2, the first control signal Sc1(n) output by the n-th gate driver circuit GDC(n) has a charging delay.

[0122] In the gate drive circuit GDC shown in Figures 2B to 2D, the eighth transistor T8 and the ninth transistor T9 of the n-th stage gate drive circuit GDC(n) are also turned on, and the charge at the first node N1 simultaneously flows out through the second shielding transistor Ta2 and the eighth transistor T8. Since the first node N1 is not directly connected to the second capacitor C2, the potential of the first node N1 decreases faster than that of the gate drive circuit GDC shown in Figure 2A. Therefore, the first control signal Sc1(n) outputted from the first output terminal out1 exhibits a lower step voltage.

[0123] In the gate drive circuit GDC shown in FIG2D , the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the n-th stage gate drive circuit GDC(n) are turned on, causing the first power signal to be transmitted to the second output terminal out2. The conduction state of the third frequency-dividing transistor Tf3 is controlled by the second frequency-dividing control signal FD2. The second power signal is transmitted to the output terminal of the fourth transistor T4, causing the fourth output transistor Tto4 to be turned off.

[0124] Therefore, by controlling the first frequency-dividing control signal FD1, the position where the refresh frequency variation begins within the display panel can be controlled accordingly. For example, if a sub-pixel Pi located in the nth row of the display panel receives the gate control signal Scan(n) output by the nth-stage gate driver circuit GDC(n) to implement a data signal writing operation, then the first frequency-dividing control signal FD1 correspondingly controls the first frequency-dividing transistor Tf1 of the nth-stage gate driver circuit GDC(n) to be turned off, thereby rendering the gate control signal Scan(n) output by the nth-stage gate driver circuit GDC(n) without a valid pulse. Furthermore, since the multi-stage gate driver circuits GDC located after the nth-stage gate driver circuit GDC(n) receive no valid pulses in the start signal ST, the multi-stage gate driver circuits GDC located after the nth-stage gate driver circuit GDC(n) also output no valid pulses in the gate control signals. Consequently, the sub-pixels Pi located before the nth row of the display panel can implement the data signal writing operation, while the sub-pixels Pi located in the nth row and thereafter cannot implement the data signal writing operation based on the corresponding gate control signal Scan. Therefore, within a frame duration, the sub-pixels Pi located before the nth row perform the write frame WF operation, while the sub-pixels Pi located on and after the nth row perform the hold frame HF operation. Accordingly, within a display cycle duration, the refresh frequency corresponding to the sub-pixels Pi located before the nth row is different from the refresh frequency of the sub-pixels Pi located on and after the nth row, thereby enabling the display panel to achieve different refresh frequencies for different display areas. Similarly, by controlling the display panel to achieve changes in refresh frequency from different positions within each frame duration, the display panel can be controlled to achieve a design with multiple refresh frequencies for multiple display areas within a display cycle.

[0125] 5G is a timing diagram of multiple gate control signals Scan output by the gate driving unit when the second frequency-dividing control signal FD2 is in the valid level state and the first frequency-dividing control signal FD1 switches between the valid level state and the invalid level state, provided by the present application. Wherein, p1 represents a valid pulse.

[0126] The gate control signals Scan(n-2)~Scan(n-1) output by the n-2th gate driving circuit GDC(n-2)~n-1th gate driving circuit GDC(n-1) have valid pulses in each frame, and the sub-pixels Pi in the display panel that receive the gate control signals Scan(n-2)~Scan(n-1) output by the n-2th gate driving circuit GDC(n-2)~n-1th gate driving circuit GDC(n-1) have the operation of performing data signal writing in each frame. The gate control signals Scan(n)~Scan(n+1) output by the nth-level gate driving circuit GDC(n)~n+1th-level gate driving circuit GDC(n+1) have valid pulses in the writing frame WF and the partial holding frame HF. The sub-pixels Pi in the display panel that receive the gate control signals Scan(n)~Scan(n+1) output by the nth-level gate driving circuit GDC(n)~n+1th-level gate driving circuit GDC(n+1) have the operation of performing data signal writing in the writing frame WF and the partial holding frame HF. The gate control signals Scan(n+2)~Scan(n+3) output by the n+2-level gate driving circuit GDC(n+2)~n+3-level gate driving circuit GDC(n+3) have valid pulses in the write frame WF, and the sub-pixels Pi in the display panel that receive the gate control signals Scan(n+2)~Scan(n+3) output by the n+2-level gate driving circuit GDC(n+2)~n+3-level gate driving circuit GDC(n+3) have the operation of performing data signal writing in the write frame WF, thereby enabling the display panel to achieve the purpose of having different refresh frequencies in different display areas.

[0127] Similarly, the position where the refresh frequency variation starts to occur in the display panel can be controlled by controlling the second frequency division control signal FD2.

[0128] Optionally, when the gate driver circuit GDC shown in FIG2C is employed to implement a display panel design with different refresh frequencies in different display areas, the clock signal CK undergoes multiple transitions between an inactive state and an active state before the corresponding first frequency-dividing control signal FD1 begins to have an inactive state. For example, in a frame duration, sub-pixels Pi located before the nth row perform a write operation to frame WF, while sub-pixels Pi located on and after the nth row perform a hold operation to frame HF. In the period before the first frequency-dividing control signal FD1 has an inactive state, the clock signal CK undergoes multiple transitions between an inactive state and an active state, as shown in FIG5G . This allows the gate control signals Scan(n) output by the first-stage gate driver circuit GDC through the n-1th-stage gate driver circuit GDC to output gate control signals Scan(n) having valid pulses, thereby enabling the sub-pixels Pi located on and after the nth row to perform a data signal write operation. After the first frequency-dividing control signal FD1 has an inactive state, the clock signal CK correspondingly remains in an inactive state, thereby saving power.

[0129] Therefore, when applying the gate drive circuit GDC shown in Figure 2C to enable the display panel to be designed with different refresh frequencies in different display areas, within a hold frame HF, the clock signal CK can first enter the first stage S1 (that is, the clock signal CK has multiple jumps between the invalid level state and the valid level state), and then enter the second stage S2 where the invalid level state is maintained.

[0130] Similarly, when the gate driving circuit GDC shown in FIG. 2D is applied to enable the display panel to realize a design in which different display areas have different refresh frequencies, within a hold frame HF, the clock signal CK may first enter the first stage S1 and then enter the second stage S2.

[0131] Optionally, the multi-stage gate drive circuit GDC shares the same first frequency-divided control signal FD1, and the multi-stage gate drive circuit GDC shares the same second frequency-divided control signal FD2, so as to reduce the number of control signals used by the gate drive unit and save wiring layout space.

[0132] Optionally, the multi-stage gate driving circuit GDC may apply different first frequency-divided control signals FD1 , and the multi-stage gate driving circuit GDC may apply different second frequency-divided control signals FD2 .

[0133] 6 is a schematic structural diagram of a display panel provided in an embodiment of the present application. An embodiment of the present application further provides a display panel, comprising any of the above-mentioned gate driving units and a plurality of sub-pixels Pi.

[0134] FIG7 is a schematic structural diagram of a sub-pixel Pi provided in an embodiment of the present application. Each sub-pixel Pi includes a light-emitting device Di and a pixel driving circuit.

[0135] Optionally, the light emitting device Di includes one of an organic light emitting diode, a sub-millimeter light emitting diode, and a micro light emitting diode.

[0136] The pixel driving circuit includes a driving transistor Tdr and a compensation transistor Tc.

[0137] The input and output terminals of the driving transistor Tdr and the light emitting device Di are electrically connected between the first voltage terminal VDD and the second voltage terminal VSS. The driving transistor Tdr is configured to generate a driving current for driving the light emitting device Di to emit light according to the corresponding data signal Data.

[0138] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0139] Optionally, the plurality of gate driving circuits GDC are configured to generate a plurality of gate control signals Scan to be output to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Pi, so that the compensation transistors Tc are turned on or off according to the corresponding gate control signals Scan.

[0140] Optionally, the pixel driving circuit further includes a data transistor Tda, a first reset transistor Ti1, a second reset transistor Ti2, a first switch transistor Ts1, a second switch transistor Ts2 and a first storage capacitor Cst1.

[0141] The control end of the data transistor Tda is configured to receive the corresponding first scan signal Pscan1 , the input end of the data transistor Tda is configured to receive the corresponding data signal Data, and the output end of the data transistor Tda is electrically connected to the input end of the driving transistor Tdr.

[0142] In the writing frame WF, the data transistors Tda of the plurality of sub-pixels Pi transmit the data signal Data to the input end of the driving transistor Tdr according to the corresponding first scanning signal Pscan1 .

[0143] An input terminal of the first reset transistor Ti1 is configured to receive a first reset signal Vi1 , and an output terminal of the first reset transistor Ti1 is electrically connected to a control terminal of the driving transistor Tdr.

[0144] The control end of the second reset transistor Ti2 is configured to receive the corresponding second scan signal Pscan2, the input end of the second reset transistor Ti2 is configured to receive the second reset signal Vi2, and the output end of the second reset transistor Ti2 is electrically connected to the output end of the second switch transistor Ts2.

[0145] The control terminal of the first switch transistor Ts1 is configured to receive a corresponding light emitting control signal EM, the input terminal of the first switch transistor Ts1 is electrically connected to the first voltage terminal VDD, and the output terminal of the first switch transistor Ts1 is electrically connected to the input terminal of the driving transistor Tdr.

[0146] The control end of the second switch transistor Ts2 is configured to receive a corresponding light emitting control signal EM, the input end of the second switch transistor Ts2 is electrically connected to the output end of the driving transistor Tdr, and the output end of the second switch transistor Ts2 is electrically connected to the light emitting device Di.

[0147] A first end of the first storage capacitor Cst1 is electrically connected to the first voltage terminal VDD, and a second end of the first storage capacitor Cst1 is electrically connected to the control terminal of the driving transistor Tdr.

[0148] The cathode of the light emitting device Di is electrically connected to the second voltage terminal VSS.

[0149] Optionally, the gate control signal Scan received by the control terminal of the compensation transistor Tc and the gate control signal Scan received by the control terminal of the first reset transistor Ti1 are generated by gate drive circuits GDC at different levels of the same gate drive unit. Optionally, the control terminal of the first reset transistor Ti1 of the sub-pixel Pi located in the nth row is configured to receive the gate control signal Scan(n-1) generated by the n-1th level gate drive circuit GDC(n-1), and the control terminal of the compensation transistor Tc of the sub-pixel Pi located in the nth row is configured to receive the gate control signal Scan(n) generated by the nth level gate drive circuit GDC(n).

[0150] Optionally, the gate control signal Scan received by the control terminal of the compensation transistor Tc and the gate control signal Scan received by the control terminal of the first reset transistor Ti1 are generated by different gate driving units.

[0151] If the display panel includes a first gate driving unit and a second gate driving unit, the circuit structures of the first gate driving unit and the second gate driving unit can be any of those shown in Figures 2A to 2D . The first gate driving unit generates a plurality of first gate control signals Scana and outputs them to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Pi; the second gate driving unit generates a plurality of second gate control signals Scanb and outputs them to the control terminals of the first reset transistors Ti1 of the plurality of sub-pixels Pi.

[0152] Optionally, the first scanning signal Pscan1 and the second scanning signal Pscan2 may be the same signal or different signals.

[0153] Optionally, the control terminals of the first switching transistor Ts1 and the second switching transistor Ts2 may share the same light emitting control signal EM, or may use different light emitting control signals EM.

[0154] Optionally, the pixel driving circuit further includes a third reset transistor Ti3, wherein an input terminal of the third reset transistor Ti3 is configured to receive a third reset signal Vi3, an output terminal of the third reset transistor Ti3 is electrically connected to an input terminal of the driving transistor Tdr, and a control terminal of the third reset transistor Ti3 is electrically connected to a control terminal of the second reset transistor Ti2.

[0155] Optionally, the pixel driving circuit further includes a second storage capacitor Cst2, a first end of the second storage capacitor Cst2 is electrically connected to the control end of the data transistor Tda, and a second end of the second storage capacitor Cst2 is electrically connected to the control end of the driving transistor Tdr.

[0156] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an oxide transistor.

[0157] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an N-type transistor.

[0158] FIG8 is a timing diagram corresponding to the sub-pixel shown in FIG7. Referring to FIG8, the working principle of the pixel driving circuit is described with the control terminal of the compensation transistor Tc receiving the first gate control signal Scana and the control terminal of the first reset transistor Ti1 receiving the second gate control signal Scanb.

[0159] In the first reset stage tim1, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on according to the second scan signal Pscan2, and the compensation transistor Tc is turned on according to the first gate control signal Scana, so that the anode of the light-emitting device Di is reset according to the second reset signal Vi2, and the input end, output end and control end of the driving transistor Tdr are reset according to the third reset signal Vi3.

[0160] In the second reset stage tim2 , the first reset transistor Ti1 is turned on according to the second gate control signal Scanb, and the compensation transistor Tc is turned on according to the first gate control signal Scana, so that the output terminal and the control terminal of the driving transistor Tdr are reset according to the first reset signal Vi1 .

[0161] In the data writing phase tim3 , the data transistor Tda is turned on according to the corresponding first scan signal Pscan1 , and the compensation transistor Tc is turned on according to the corresponding first gate control signal Scana , so that the control terminal of the driving transistor Tdr is written with the data signal Data.

[0162] In the light emitting stage tim4 , the first switching transistor Ts1 and the second switching transistor Ts2 are turned on according to the light emitting control signal EM, so that the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0163] Optionally, a third reset phase tin is further included between the light-emitting phase tim4 and the data writing phase tim3. In the third reset phase tin, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on according to the second scan signal Pscan2, so that the anode of the light-emitting device Di is reset according to the second reset signal Vi2, and the input and output ends of the driving transistor Tdr are reset according to the third reset signal Vi3.

[0164] Among them, when the gate control signal Scan output by the corresponding gate driving circuit GDC controlled by the first frequency-division control signal FD1 and / or the second frequency-division control signal FD2 has no valid pulse, the compensation transistor Tc and the first reset transistor Ti1 of the sub-pixel Pi applying the gate control signal Scan are cut off, so that the sub-pixel Pi cannot reset the control end of the driving transistor Tdr in the first reset stage tim1 and the second reset stage tim2, and cannot transmit the data signal Vdata to the control end of the driving transistor Tdr in the data writing stage tim3, so that the sub-pixel Pi applying the gate control signal Scan can achieve the display function of maintaining the frame HF.

[0165] Figure 9 is a simulation timing diagram of an embodiment of the present invention. During the vertical blanking interval bt, the inventors caused the clock signal CK to transition between active and inactive states 10 times. The simulation results show that the potential of the first node N1 can be pulled down to -20V and then gradually increased. Accordingly, the gate control signal Scan is also pulled down to equal the first power supply signal, after which the potentials of the first output terminal out1 and the second output terminal out2 are raised again.

[0166] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate driving unit, in, comprising a plurality of gate driving circuits, wherein the plurality of gate driving circuits are configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of a display panel; Each of the gate drive circuits includes a start transistor and a first output transistor, the control end of the start transistor is configured to receive a corresponding clock signal, the input end of the start transistor is configured to receive a start signal, the output end of the start transistor is electrically connected to the control end of the first output transistor, the input end of the first output transistor is electrically connected to the first power supply end, and the output end of the first output transistor is electrically connected to the first output end of the gate drive circuit at this stage; Wherein, in a writing frame of the display panel, the clock signal has multiple transitions between a valid level state and an invalid level state; In a plurality of holding frames of the display panel, the clock signal has a plurality of first stages for maintaining the invalid level state, and the clock signal has a plurality of jumps between the valid level state and the invalid level state in a second stage between two adjacent first stages.

2. The gate driving unit according to claim 1, in, The holding frame includes a display phase and a vertical blanking interval phase; The second stage at least corresponds to the vertical blanking interval stage.

3. The gate driving unit according to claim 1, in, The durations of the multiple first stages are equal.

4. The gate driving unit according to claim 1, in, The clock signal includes a first clock signal and a second clock signal; The control end of the start transistor of the gate drive circuit of the odd-numbered stage is configured to receive the first clock signal, and the control end of the start transistor of the gate drive circuit of the even-numbered stage is configured to receive the second clock signal; Wherein, in the write frame, the first clock signal and the second clock signal are in opposite phases; In the holding frame, the first phase in which the first clock signal maintains the inactive level state overlaps with the first phase in which the second clock signal maintains the inactive level state, and the second phase of the first clock signal overlaps with the second phase of the second clock signal.

5. The gate driving unit according to claim 4, in, In the second phase corresponding to the first clock signal, the first clock signal and the second clock signal are inverted.

6. The gate driving unit according to claim 4, in, The gate drive circuit further includes: a first transistor, wherein a control terminal of the first transistor is electrically connected to a control terminal of the start-up transistor, and an input terminal of the first transistor is electrically connected to the first power terminal; a second transistor, wherein a control terminal of the second transistor is electrically connected to the output terminal of the start-up transistor, an input terminal of the second transistor is electrically connected to the control terminal of the start-up transistor, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is electrically connected to an output terminal of the first transistor; A fourth transistor, a control terminal of the fourth transistor is electrically connected to an input terminal of the third transistor, and an input terminal of the fourth transistor is electrically connected to an output terminal of the third transistor; A fifth transistor, a control terminal of the fifth transistor is electrically connected to an output terminal of the start transistor, an input terminal of the fifth transistor is electrically connected to a second power supply terminal, and an output terminal of the fifth transistor is electrically connected to an output terminal of the fourth transistor; A sixth transistor, a control terminal of the sixth transistor is electrically connected to an output terminal of the first transistor, and an input terminal of the sixth transistor is electrically connected to the second power supply terminal; A seventh transistor, an input terminal of the seventh transistor is electrically connected to an input terminal of the third transistor, and an output terminal of the seventh transistor is electrically connected to an output terminal of the sixth transistor; An eighth transistor, a control terminal and an input terminal of the eighth transistor are electrically connected to a control terminal of the seventh transistor, and an output terminal of the eighth transistor is electrically connected to a control terminal of the first output transistor; A ninth transistor, a control terminal of the ninth transistor is electrically connected to a control terminal of the start transistor, an input terminal of the ninth transistor is electrically connected to an input terminal of the start transistor, and an output terminal of the ninth transistor is electrically connected to a control terminal of the seventh transistor; A second output transistor, a control terminal of the second output transistor is electrically connected to an output terminal of the fourth transistor, an input terminal of the second output transistor is electrically connected to the second power supply terminal, and an output terminal of the second output transistor is electrically connected to an output terminal of the first output transistor; A first capacitor, a first end of the first capacitor is electrically connected to a control terminal of the third transistor, and a second end of the first capacitor is electrically connected to an output terminal of the third transistor; A second capacitor, a first end of the second capacitor is electrically connected to a control terminal of the seventh transistor, and a second end of the second capacitor is electrically connected to an output terminal of the seventh transistor; and A third capacitor, a first end of the third capacitor is electrically connected to a control terminal of the second output transistor, and a second end of the third capacitor is electrically connected to an input terminal of the second output transistor; Wherein, the control terminal of the fourth transistor of the odd-level gate driving circuit is configured to receive the second clock signal, and the control terminal of the fourth transistor of the even-level gate driving circuit is configured to receive the first clock signal.

7. The gate driving unit according to claim 6, Wherein, The gate driving circuit further includes: A first shielding transistor, a control terminal of the first shielding transistor is electrically connected to the first power supply terminal, an input terminal of the first shielding transistor is electrically connected to an output terminal of the first transistor, and an output terminal of the first shielding transistor is electrically connected to a control terminal of the third transistor; A second shielding transistor, a control terminal of the second shielding transistor is electrically connected to the first power supply terminal, an input terminal of the second shielding transistor is electrically connected to an output terminal of the startup transistor, and an output terminal of the second shielding transistor is electrically connected to a control terminal of the first output transistor; A third shielding transistor, a control terminal of the third shielding transistor is electrically connected to the first power supply terminal, an input terminal of the third shielding transistor is electrically connected to an output terminal of the ninth transistor, and an output terminal of the third shielding transistor is electrically connected to a control terminal of the eighth transistor; and A tenth transistor, a control terminal of the tenth transistor is electrically connected to a power-on reset control line, an input terminal of the tenth transistor is electrically connected to the second power supply terminal, and an output terminal of the tenth transistor is electrically connected to a control terminal of the first output transistor.

8. The gate driving unit according to claim 6, wherein, the gate driving circuit further includes: A first frequency-dividing transistor, a control terminal of the first frequency-dividing transistor is electrically connected to a first frequency-dividing control line, an input terminal of the first frequency-dividing transistor is electrically connected to an output terminal of the fourth transistor, and an output terminal of the first frequency-dividing transistor is electrically connected to a control terminal of the second output transistor.

9. The gate driving unit according to claim 6, wherein, the gate driving circuit further includes: A second frequency-dividing transistor, a control terminal of the second frequency-dividing transistor is electrically connected to an output terminal of the startup transistor, and an input terminal of the second frequency-dividing transistor is electrically connected to a second frequency-dividing control line; A third frequency-dividing transistor, a control terminal of the third frequency-dividing transistor is electrically connected to an output terminal of the second frequency-dividing transistor, and an input terminal of the third frequency-dividing transistor is electrically connected to a control terminal of the second output transistor; A fourth frequency-dividing transistor, a control terminal of the fourth frequency-dividing transistor is electrically connected to a control terminal of the second frequency-dividing transistor, an input terminal of the fourth frequency-dividing transistor is electrically connected to the second power supply terminal, and an output terminal of the fourth frequency-dividing transistor is electrically connected to an output terminal of the third frequency-dividing transistor; A third output transistor, a control terminal of the third output transistor is electrically connected to a control terminal of the first output transistor, an input terminal of the third output transistor is electrically connected to the first power supply terminal, and an output terminal of the third output transistor is electrically connected to a second output terminal of the gate driving circuit of this stage; A fourth output transistor, a control terminal of the fourth output transistor is electrically connected to an output terminal of the third frequency-dividing transistor, an input terminal of the fourth output transistor is electrically connected to the second power supply terminal, and an output terminal of the fourth output transistor is electrically connected to an output terminal of the third output transistor; A fourth capacitor, a first end of the fourth capacitor is electrically connected to an input terminal of the fourth output transistor, and a second end of the fourth capacitor is electrically connected to a control terminal of the fourth output transistor; and A fifth capacitor, wherein a first end of the fifth capacitor is electrically connected to the output end of the second frequency-dividing transistor, and a second end of the fifth capacitor is electrically connected to the input end of the fourth output transistor.

10. A display panel, in, include: A gate driving unit, comprising a plurality of gate driving circuits, wherein the plurality of gate driving circuits are configured to generate a plurality of gate control signals to be output to a plurality of sub-pixels of the display panel; Each of the gate drive circuits includes a start transistor and a first output transistor, the control end of the start transistor is configured to receive a corresponding clock signal, the input end of the start transistor is configured to receive a start signal, the output end of the start transistor is electrically connected to the control end of the first output transistor, the input end of the first output transistor is electrically connected to the first power supply end, and the output end of the first output transistor is electrically connected to the first output end of the gate drive circuit at this stage; wherein, in a writing frame of the display panel, the clock signal has multiple jumps between a valid level state and an invalid level state; within multiple holding frames of the display panel, the clock signal has multiple first stages of maintaining the invalid level state, and the clock signal has multiple jumps between the valid level state and the invalid level state in a second stage between two adjacent first stages; and A plurality of sub-pixels, each of which includes a light-emitting device and a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor and a compensation transistor, wherein the driving transistor is configured to generate a driving current for driving the light-emitting device to emit light according to a corresponding data signal, wherein an input terminal of the compensation transistor is electrically connected to an output terminal of the driving transistor, and an output terminal of the compensation transistor is electrically connected to a control terminal of the driving transistor; The plurality of gate driving circuits are configured to generate a plurality of gate control signals to be output to control terminals of the compensation transistors of the plurality of sub-pixels.

11. The display panel according to claim 10, in, The pixel driving circuit further includes: a first reset transistor, wherein an input terminal of the first reset transistor is configured to receive a first reset signal, and an output terminal of the first reset transistor is electrically connected to a control terminal of the driving transistor; The gate control signal received by the control end of the compensation transistor and the gate control signal received by the control end of the first reset transistor are generated by the gate driving circuits of different levels of the same gate driving unit.

12. The display panel according to claim 10, in, The holding frame includes a display phase and a vertical blanking interval phase; wherein the second phase at least corresponds to the vertical blanking interval phase.

13. The display panel according to claim 10, in, The durations of the multiple first stages are equal.

14. The display panel according to claim 10, in, The clock signal includes a first clock signal and a second clock signal; The control terminal of the start transistor of the odd-level gate driving circuit is configured to receive the first clock signal, and the control terminal of the start transistor of the even-level gate driving circuit is configured to receive the second clock signal; Wherein, in the writing frame, the first clock signal and the second clock signal are inverted; In the holding frame, the first stage in which the first clock signal maintains the invalid level state overlaps with the first stage in which the second clock signal maintains the invalid level state, and the second stage of the first clock signal overlaps with the second stage of the second clock signal.

15. The display panel according to claim 14, Wherein, In the second stage corresponding to the first clock signal, the first clock signal and the second clock signal are inverted.

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