Vertical semiconductor device and manufacturing method therefor

Abstract

The present application relates to a vertical semiconductor device and a manufacturing method therefor. The vertical semiconductor device comprises: a semiconductor material layer; a first shielding structure, located on the semiconductor material layer and comprising a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; a first doped region, located on the semiconductor material layer, the first doped region having a first conductivity type; and a first gate structure, adjacent to the first doped region. The depth of the first gate structure is smaller than the depth of the first shielding structure and greater than the depth of the first doped region. The first shielding dielectric layer region is divided into an upper part and a lower part by taking the bottom of the first gate structure as a boundary line, and the first gate structure is adjacent to the upper part. The upper part has a first thickness at a first surface of the semiconductor material layer, the first thickness is smaller than a second thickness of the lower part, and the sum of the first thickness of the upper part and a third thickness of the first gate structure at the first surface is greater than the second thickness of the lower part.

Description

Vertical semiconductor device and manufacturing method thereof Technical Field

[0001] The present invention relates to a vertical semiconductor device and a manufacturing method thereof, and more particularly to a vertical semiconductor device having a gate electrode structure partially located in a mesa region and partially located in a shield trench structure and a manufacturing method thereof. Background Art

[0002] Trench-MOSFETs have a gate electrode buried in a trench in the substrate, creating a vertical channel. The main advantage of this structure is the absence of the junction field effect (JFET). As semiconductors evolve, as the minimum size of manufacturable components decreases, the number of interconnected devices per unit area also increases. This limits the permissible contact area between conductive elements in the current conduction path, leading to increased device resistance or decreased product reliability. For example, when the gate area of ​​a trench MOSFET is limited, the gate resistance is large, resulting in lower efficiency and slower switching speeds. Increasing the gate area will reduce the spacing between the shield electrode and the gate, which in turn will reduce the sustainable voltage between the gate and source, resulting in decreased reliability.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure relates to a vertical semiconductor device, comprising: a semiconductor material layer having a first surface and a second surface opposite to each other; a first shielding structure located in the semiconductor material layer and extending from the first surface to the second surface, the first shielding structure comprising a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; a first doped region located in the semiconductor material layer and adjacent to the first surface, wherein the first doped region has a first conductivity type; and a first gate structure located in the semiconductor material layer and extending from the first surface to the second surface, the first gate structure adjacent to the first doped region, the depth of the first gate structure being less than the depth of the first shielding structure and greater than the depth of the first doped region. The first shielding dielectric layer is divided into an upper portion and a lower portion with the bottom of the first gate structure as the boundary, and the first gate structure is adjacent to the upper portion of the first shielding dielectric layer. The upper portion of the first shielding dielectric layer has a first thickness located on the first surface of the semiconductor material layer. The first thickness is less than the second thickness of the lower portion of the first shielding dielectric layer, and the sum of the first thickness of the upper portion of the first shielding dielectric layer and the third thickness of the first gate structure located on the first surface is greater than the second thickness of the lower portion of the first shielding dielectric layer.

[0005] In some embodiments, the first gate structure includes a first gate electrode and a first gate dielectric layer, wherein the first gate electrode contacts the upper portion of the first shielding dielectric layer, and the first gate dielectric layer is located between the first gate electrode and the semiconductor material layer.

[0006] In some embodiments, a width of a top portion of the first gate electrode is greater than a width of a bottom portion of the first gate electrode.

[0007] In some embodiments, a sum of a width of the first gate electrode at the first surface and the first thickness of the upper portion of the first shielding dielectric layer is greater than or equal to the second thickness of the lower portion of the first shielding dielectric layer.

[0008] In some embodiments, the first gate structure has a first sidewall away from the first shield structure and a second sidewall adjacent to the first shield structure, the first sidewall is a flat sidewall, and the second sidewall is a sidewall with a stepped configuration.

[0009] In some embodiments, from a top view, a portion of the first gate structure overlaps the first shielding structure, and a portion of the first gate structure is located outside the coverage of the first shielding structure.

[0010] In some embodiments, the upper portion of the first shielding dielectric layer has a first partial sidewall extending along a first direction, a second partial sidewall approximately parallel to the first partial sidewall, and a third partial sidewall connecting the first partial sidewall and the second partial sidewall and extending along a second direction, wherein the angle between the second direction and the first direction is between 30 and 90 degrees.

[0011] In some embodiments, the vertical semiconductor device further includes: a second shielding structure, located in the semiconductor material layer and extending from the first surface to the second surface, the second shielding structure is arranged adjacent to the first shielding structure, wherein the first doped region is at least located between the first shielding structure and the second shielding structure, and the second shielding structure includes a second shielding dielectric layer, and a second shielding electrode surrounded by the second shielding dielectric layer; and a second gate structure, located in the semiconductor material layer and extending from the first surface to the second surface, and the configuration of the second gate structure is roughly symmetrical with the configuration of the first gate structure.

[0012] In some embodiments, the vertical semiconductor device further includes: a second doped region located in the semiconductor material layer and adjacent to the first surface, the second doped region being located in the first doped region and having a second conductivity type different from the first conductivity type, and the depth of the first doped region being greater than the depth of the second doped region.

[0013] In some embodiments, the vertical semiconductor device further includes: a source electrode layer, disposed on the first surface of the semiconductor material layer; a first conductive plug, electrically connected to the first shielding structure; and a third doped region, located in the first shielding electrode and adjacent to the first conductive plug, wherein the doping concentration of the first conductive type ions in the third doped region is greater than the doping concentration of the first conductive type ions in the first doped region.

[0014] Embodiments of the present disclosure relate to a method for manufacturing a vertical semiconductor device. The method includes: forming a first shielding structure in a lightly doped region of a semiconductor material layer, wherein the lightly doped region has a first conductivity type and the first shielding structure includes a first shielding electrode and a first shielding dielectric layer located between the first shielding electrode and the semiconductor material layer; forming a first patterned layer on the semiconductor material layer, wherein the first patterned layer has a first opening, a first sidewall of the first opening is located above the first shielding dielectric layer between the first shielding electrode and the semiconductor material layer, and a first sidewall of the first shielding dielectric layer is located within the coverage of the opening; performing a first etching process on the first shielding dielectric layer to form a first recess in the first shielding dielectric layer, wherein the first recess exposes a portion of the semiconductor material layer; performing a second etching process on the semiconductor material layer to form a second recess in the semiconductor material layer, wherein the second recess has a depth greater than the depth of the first recess, the second recess exposes a portion of the first sidewall of the first shielding dielectric layer located below the first recess, and the first recess connects to the second recess to define a third recess; and forming a first gate structure in the third recess.

[0015] In some embodiments, forming the first shielding structure in the semiconductor material layer includes: forming a first trench in the semiconductor layer; forming the first shielding dielectric layer in the first trench along the sidewall of the first trench; and forming the first shielding electrode in the first trench, wherein the top surface of the first shielding electrode, the top surface of the first shielding dielectric layer, and the top surface of the semiconductor material layer are at approximately the same level.

[0016] In some embodiments, the manufacturing method further includes: after forming the first gate structure, performing a first ion implantation process on the semiconductor material layer to form a body doped region, wherein the body doped region has a second conductivity type different from that of the lightly doped region.

[0017] In some embodiments, a depth of the body doping region is less than a depth of the first gate structure.

[0018] In some embodiments, the manufacturing method further includes: performing a second ion implantation process on the semiconductor material layer to form a source doping region, wherein the source doping region has the same first conductivity type as the lightly doped region, and the doping concentration of the first conductivity type ions in the source doping region is greater than the doping concentration of the first conductivity type ions in the lightly doped region.

[0019] In some embodiments, the second groove exposes a portion of the semiconductor material layer adjacent to the first shielding structure, and the manufacturing method further includes: forming a first sacrificial layer on the exposed portion of the semiconductor material layer in the second groove after the second etching process; and removing the first sacrificial layer before forming the first gate structure.

[0020] In some embodiments, forming the first gate structure includes: forming a first gate dielectric layer on the semiconductor material layer in the third groove; and forming a first gate electrode in the third groove, wherein the width of the upper portion of the first gate electrode is greater than the width of the lower portion of the first gate electrode.

[0021] In some embodiments, the width of the upper portion of the first gate electrode is between 0.6 micrometers and 0.8 micrometers.

[0022] In some embodiments, a thickness of the first shield dielectric layer adjacent to the upper portion of the first gate electrode is between 0.1 micrometers and 0.2 micrometers.

[0023] In some embodiments, the thickness of the first shielding dielectric layer below the first gate electrode is between 0.6 micrometers and 0.8 micrometers.

[0024] In some embodiments, the manufacturing method further includes: forming a first conductive plug electrically connected to the first shielding structure; and forming a second conductive plug electrically connected to the first gate structure.

[0025] In some embodiments, a depth at which the first conductive plug or the second conductive plug is located in the semiconductor material layer is greater than a depth of a source doping region in the semiconductor material layer.

[0026] In some embodiments, at least one of the first etching process and the second etching process includes a dry etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The aspects of several embodiments of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale. In fact, the dimensions of the various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0028] 1-27 are cross-sectional views illustrating one or more stages in a method of manufacturing a vertical semiconductor device according to certain embodiments of the present invention;

[0029] FIG28 is a top view of a vertical semiconductor device according to some embodiments of the present invention;

[0030] FIG. 29 is a cross-sectional view of a vertical semiconductor device according to some embodiments of the present disclosure.

[0031] The same or similar components are denoted by the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be restrictive. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0033] The following describes embodiments of the present disclosure in detail. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0034] The present disclosure provides a structure for a semiconductor rectifier device and a method for manufacturing the same. Compared to conventional methods for manufacturing semiconductor rectifier devices, the semiconductor rectifier device disclosed herein has a Schottky barrier structure. Furthermore, the Schottky barrier junction rectifier disclosed herein has a lower electric field strength at the metal-semiconductor interface, thereby achieving the effect of maintaining a low VF while also reducing IR, thereby improving reverse leakage. Therefore, the structure disclosed herein can achieve the effect of reducing IR without increasing VF, providing a rectifier device with improved reverse leakage.

[0035] 1 to 28 illustrate one or more stages in a method of manufacturing a vertical semiconductor device 1 according to some embodiments of the present disclosure. At least some of these figures have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0036] Referring to Figure 1 , the method for manufacturing a vertical semiconductor device 1 includes forming a semiconductor material layer 12 on a surface 11A of a substrate 11, and forming a doped region 25 in the semiconductor material layer 12. The semiconductor material layer 12 is formed, for example, by epitaxial growth on the surface 11A of the substrate 11. The substrate 11 has opposing surfaces 11A and 11B. In some embodiments, surfaces 11A and 11B may be horizontal. For ease of explanation, the direction perpendicular to surfaces 11A and 11B is defined as the vertical direction, while the direction perpendicular to the vertical direction is defined as the horizontal direction. In some embodiments, surface 11A is the top surface of the substrate 11, and surface 11B is the bottom surface of the substrate 11. In some embodiments, surface 11A is the top surface of a silicon wafer. The substrate 11 shown in Figure 1 may be only the portion of the silicon wafer near the top surface. The material of the substrate 11 may be polycrystalline silicon or single crystal silicon. The substrate 11 may include a doped region 24. For example, the substrate 11 may include a p-type doped region configured for an n-type transistor and an n-type doped region configured for a p-type transistor. The N-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The P-type doped region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The N-type or P-type doped region can be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping process. The doped region 24 of the substrate 11 extends from the surface 11A to the surface 11B. In some embodiments, the doped region 24 of the substrate 11 covers the entire surface 11A. In some embodiments, the doped region 24 of the substrate 11 has a first conductivity type. For ease of explanation, the first type is described below as N-type and the second type is described below as P-type, but the present disclosure is not limited thereto. The N-type (first type) or P-type (second type) substrate 11 can be adjusted based on the conductivity type of the vertical semiconductor device 1. It should be noted that the substrate 11 shown in FIG. 1 may only be a portion of the silicon wafer near the top surface, or in other words, FIG. 1 only shows a portion of the doped region 24 of the substrate 11. In some embodiments, the doped region 24 of the substrate 11 serves as the cathode doped region of the vertical semiconductor device 1.

[0037] The semiconductor material layer 12 has the same conductivity type as the substrate 11, that is, first-type doping. The material of the substrate 11 can be polycrystalline silicon, single crystal silicon, silicon carbide, silicon germanium or other suitable semiconductor materials. In some embodiments, ions with N-type electrical properties are introduced into the epitaxial growth to form an N-type semiconductor material layer 12 without additional ion implantation. Therefore, the N-type electrical ions can be distributed throughout the semiconductor material layer 12 to form a doped region 25 located throughout the semiconductor material layer 12. The semiconductor material layer 12 may have a surface 12A and a surface 12B opposite to the surface 12A. In some embodiments, the surface 12A and the surface 12B may be horizontal planes. In some embodiments, the surface 12A is the top surface of the semiconductor material layer 12, and the surface 12B is the bottom surface of the semiconductor material layer 12. In some embodiments, the surface 12B of the semiconductor material layer 12 contacts the surface 11A of the substrate 11.

[0038] The thickness and doping concentration of the semiconductor material layer 12 can be adjusted according to the voltage requirements of the device. In some embodiments, the semiconductor material layer 12 can have a uniform doping concentration. In some embodiments, ions with N-type electrical properties are uniformly introduced during the epitaxial growth process to form a semiconductor material layer 12 with a uniform doping concentration, wherein the ion concentration introduced during the epitaxial growth process does not change over time. In some embodiments, the semiconductor material layer 12 can have a doping concentration gradient that increases or decreases from surface 12A to surface 12B. In some embodiments, the increasing or decreasing doping concentration gradient can be adjusted according to the withstand voltage and resistance required by the product. In some embodiments, ions with N-type electrical properties are introduced during the epitaxial growth process, wherein the concentration of the introduced ions decreases or increases over the time of epitaxial growth to form a semiconductor material layer 12 with a decreasing or increasing doping concentration. Regardless of whether the semiconductor material layer 12 has a uniform or non-uniform doping concentration, the doping concentration of the substrate 11 will still be greater than the doping concentration of the semiconductor material layer 12. For convenience of explanation, the doped region 25 is collectively referred to as the lightly doped region 25 below.

[0039] 2 , the manufacturing method of the vertical semiconductor device 1 includes forming a patterned layer 51 on the surface 12A of the semiconductor material layer 12, exposing a portion of the semiconductor material layer 12. The patterned layer 51 is used to define the position of the trench of the shielding electrode structure to be formed later. In some embodiments, the patterned layer 51 has an opening 511 and an opening 512 exposing a portion of the semiconductor material layer 12. The patterned layer 51 can be a photoresist layer, a hardening layer, a dielectric layer (such as an oxide layer or a nitride layer), or other material layer suitable for use as a mask for a subsequent etching process. In some embodiments, the patterned layer 51 includes an oxide (such as silicon oxide). In some embodiments, an oxide layer is formed to cover the entire surface 12A of the semiconductor material layer 12, a patterned photoresist layer is formed on the oxide layer, the patterned photoresist layer is used to remove a portion of the oxide layer, and then the patterned photoresist layer is removed to form a patterned layer 51 exposing a portion of the silicon carbide layer 12.

[0040] 3 , the manufacturing method of the vertical semiconductor device 1 includes performing an etching process on the semiconductor material layer 12 using the patterned layer 51 as a mask to form a plurality of grooves 65 (e.g., including grooves 651 and 652). The plurality of grooves 65 are adjacent to each other and extend from the surface 12A to the surface 12B of the semiconductor material layer 12. Since they are formed through the same etching step, the grooves 651 and 652 have approximately the same depth D65. In some embodiments, the depth D65 of the groove 651 or the groove 652 is between 5 and 30 μm. In some embodiments, the depth D65 of the groove 651 or the groove 652 is between 8 and 10 μm. The width of the grooves 651 and 652 can be determined by the openings 511 and 512. In some embodiments, the groove 651 and the groove 652 have approximately the same width W65. In some embodiments, the width W65 of the groove 651 or the groove 652 is between 0.5 and 5 μm. In some embodiments, the width W65 of the trench 651 or the trench 652 is between 2 and 3 μm. The width and depth of the trench 651 and the trench 652 can be configured and adjusted based on the voltage required by the device. Within the scope of the embodiments disclosed above, a larger depth D65 of the trenches 651 and 652 can reduce the resistivity of the semiconductor material layer 12.

[0041] 4 , the manufacturing method of the vertical semiconductor device 1 includes forming a dielectric layer 13 filling trenches 651 and 652. In some embodiments, the dielectric layer 13 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some embodiments, the dielectric layer 13 can be formed by thermal oxidation. In some embodiments, the dielectric layer 13 underlies the trenches 651 and 652. In some embodiments, the dielectric layer 13 can be conformally deposited on the inner surfaces of the trenches 651 and 652 (including the opposing sidewalls and the bottom extending between the sidewalls) and the surface 12A of the semiconductor material layer 12. In some embodiments, the dielectric layer 13 can be deposited into the trenches 651 and 652, followed by lithography and etching processes to partially remove the dielectric layer 13, thereby forming at least one recess in the dielectric layer 13. The thickness of the dielectric layer 13 can be set and adjusted according to the voltage required by the device. In some embodiments, the thickness of the dielectric layer 13 is between 0.1 μm and 2 μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.2 μm and 1.2 μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.6 μm and 0.8 μm.

[0042] The voltage of the vertical semiconductor device 1 is generally determined by the doping concentration of the semiconductor material layer 12 and the thickness of the dielectric layer 13 . Therefore, the steps shown in FIG. 1 and FIG. 4 determine the voltage of the vertical semiconductor device 1 .

[0043] Referring to Figure 5 , the method for fabricating a vertical semiconductor device 1 includes forming an electrode material layer 14 within trenches 651 and 652. In some embodiments, electrode material layer 14 can be formed by physical vapor deposition (PVD), CVD, or other deposition processes. In some embodiments, electrode material layer 14 completely fills trenches 651 and 652 and covers surface 12A of semiconductor material layer 12. In some embodiments, electrode material layer 14 comprises a semiconductor material, such as polysilicon.

[0044] 6 , the method for manufacturing the vertical semiconductor device 1 includes removing portions of the electrode material layer 14 and the dielectric layer 13 outside the trenches 651 and 652 . In some embodiments, the electrode material layer 14 outside the trenches 651 and 652 is removed to form a first electrode layer 141 and a second electrode layer 142 in the trenches 651 and 652 , respectively. In some embodiments, the electrode material layer 14 is subjected to a grinding process, such as a chemical mechanical polishing (CMP) process, to remove the electrode material layer 14 outside the trenches 651 and 652 . In other embodiments, the method for removing the portion of the electrode material layer 14 outside the trenches 651 and 652 may also include an etching process, such as a wet etching process or a dry etching process. In some embodiments, after removing the electrode material layer 14 on the surface 12A of the semiconductor material layer 12 , a similar process is performed on the dielectric layer 13 to form a first dielectric layer 131 and a second dielectric layer 132 in the trenches 651 and 652 , respectively. In some embodiments, the top surfaces of the etched dielectric layer 13 and the electrode material layer 14 are located at approximately the same horizontal height. In some embodiments, the top surfaces of the etched dielectric layer 13 and the electrode material layer 14 are aligned with the surface 12A. The vertical semiconductor device 1 includes a dual-trench gate semiconductor power element, wherein the dielectric layer 13 (including the first dielectric layer 131 and the second dielectric layer 132) serves as a shielding dielectric layer of the shielding electrode structure 15, and the electrode material layer 14 (including the first electrode layer 141 and the second electrode layer 142) serves as a shielding electrode layer of the shielding electrode structure 15. The first dielectric layer 131 surrounds the first electrode layer 141, and the second dielectric layer 132 surrounds the second electrode layer 142, respectively defining different shielding structures 15 of the vertical semiconductor device 1. For convenience of description, the first electrode layer 141 and the first dielectric layer 131 are collectively referred to as the first shielding structure 151. Similarly, the second electrode layer 142 and the second dielectric layer 132 are collectively referred to as the second shielding structure 152. In some embodiments, the upper surfaces of the first electrode layer 141 and the second electrode layer 142 are flush with the surface 12A. In some embodiments, the upper surfaces of the first dielectric layer 131 and the second dielectric layer 132 are flush with the surface 12A. In some embodiments, the first electrode layer 141 and the second electrode layer 142 have approximately the same width W14. In some embodiments, the width W14 ranges from 0.3 to 3 μm. In some embodiments, the width W14 ranges from 0.6 to 1 μm. In some embodiments, the ratio of the width W14 to the width W651 of the trench 65 is greater than or equal to 3:1.

[0045] 7 , the manufacturing method of the vertical semiconductor device 1 includes forming a hardening layer 16 on the surface 12A of the semiconductor material layer 12. The hardening layer 16 covers the first shielding structure 151, the second shielding structure 152 and the surface 12A of the semiconductor material layer 12. The hardening layer 16 may include a dielectric material (such as an oxide layer or a nitride layer) or other material layer suitable as a mask for subsequent etching processes. In the subsequent step of defining the gate structure, portions of the dielectric layers 131 and 132 will be removed. In some embodiments, in order to simplify the steps and manufacturing costs, the hardening layer 16 may be made of the same dielectric material as the dielectric layer 13. In some embodiments, the material of the hardening layer 16 is an oxide (such as silicon oxide).

[0046] 8 , the method for manufacturing a vertical semiconductor device 1 includes forming a patterned layer 52 on the top surface of a hardening layer 16. The patterned layer 52 has a plurality of openings (e.g., 521, 522, 523, and 524 in FIG. 8 ) located above opposing sidewalls of a shielding structure. For example, the first shielding structure 151 has opposing sidewalls 151C and 151D. The opening 521 of the patterned layer 52 is located above the sidewall 151C, and the opening 522 of the patterned layer 52 is located above the sidewall 151D. In some embodiments, the sidewall 151C is within the coverage of a vertical projection of the opening 521, and the sidewall 151D is within the coverage of a vertical projection of the sidewall 522. In some embodiments, the opening 521 has opposing sidewalls 521C and 521D, and the vertical extension of the sidewall 151C is located between the extension lines of the sidewalls 521C and 521D. In some embodiments, opening 522 has two opposing sidewalls 522C and 522D, with the vertical extension of sidewall 151D located between the extensions of sidewall 522C and sidewall 522D. Similarly, for example, second shielding structure 152 has two opposing sidewalls 152C and 152D, with opening 523 located above sidewall 152C and opening 524 located above sidewall 152D. In some embodiments, sidewall 152C is within the coverage of a vertical projection of opening 523, and sidewall 152D is within the coverage of a vertical projection of sidewall 524. In some embodiments, opening 523 has two opposing sidewalls 523C and 523D, with the vertical extension of sidewall 152C located between the extensions of sidewall 523C and sidewall 523D. In some embodiments, the opening 524 has two sidewalls 524C and 524D opposite to each other, and an extension line of the sidewall 152D in the vertical direction is located between an extension line of the sidewall 524C and an extension line of the sidewall 524D.

[0047] 9 , the manufacturing method for the vertical semiconductor device 1 includes performing a first etching process on the hardened layer 16 and the dielectric layer 13 using the patterned layer 52 as a mask to form openings in the hardened layer 16 and grooves in the first dielectric layer 131 and the second dielectric layer 132. Since the first shielding structure 151 and the second shielding structure 152 have similar configurations, and the corresponding positions of the openings 523 and 524 in the second shielding structure 152 are similar to the corresponding positions of the openings 521 and 522 in the first shielding structure 151, for simplicity, the following description of the manufacturing steps will focus primarily on the first shielding structure 151 and the openings 521 and 522. Subsequent steps for the second shielding structure 152 can refer to the first shielding structure 151.

[0048] The first etching process partially removes the hardened layer 16 and the first dielectric layer 131 below the openings 521 and 522 to form a plurality of openings in the hardened layer 16 and a plurality of recesses 61 in the first dielectric layer 131. For example, openings 161 and 162 corresponding to the openings 521 and 522 are formed in the hardened layer 16, and recesses 611 and 612 located below the openings 161 and 162 are formed in the first dielectric layer 131. Recess 611 connects to the bottom of opening 161 and communicates with opening 161, while recess 612 connects to the bottom of opening 162 and communicates with opening 162. Recess 611 exposes a portion of the semiconductor material layer 12 adjacent to surface 12A and adjacent to sidewall 151C, while recess 612 exposes a portion of the semiconductor material layer 12 adjacent to surface 12A and adjacent to sidewall 151D. The first etching process removes the dielectric material and stops at the semiconductor material layer 12. In some embodiments, the hardened layer 16 and the first dielectric layer 131 have the same dielectric material, or the materials of the hardened layer 16 and the first dielectric layer 131 have a low selectivity to the etchant of the first etching process, so that the hardened layer 16 can be removed together with the first dielectric layer 131. In some embodiments, the first etching process includes a dry etching process, which exposes a portion of the surface 12 of the semiconductor material layer 12 located in the openings 161 and 162, and exposes a portion of the semiconductor material layer 12 in contact with the sidewalls of the first dielectric layer 131 by the recesses 611 and 612.

[0049] Referring to FIG. 10 , the method for fabricating a vertical semiconductor device 1 includes removing the patterned layer 52 . In some embodiments, the openings 611 and 612 have approximately the same depth D61 vertically from the surface 12A. In some embodiments, the depth D61 ranges from 0.5 to 1.5 μm. The openings 611 and 612 define the locations of portions of the gate structure. Therefore, the depth D61 of the openings 611 and 612 can be adjusted to achieve the desired breakdown voltage (BV) of the vertical semiconductor device 1 by adjusting the parameters of the etching step (e.g., energy, time, etc.) described in FIG. Furthermore, the openings 161 and 162 expose portions of the surface 12A of the semiconductor material layer 12 . In some embodiments, the exposed portions of the semiconductor material layer 12 have a width D1 . In some embodiments, the width D1 ranges from greater than 0 to less than 2 μm. In some embodiments, the width D1 ranges from 0.1 to 0.15 μm. The width D1 can be adjusted based on the distance D2 between the first shielding structure 151 and the second shielding structure 152 . In some embodiments, the distance D2 ranges from 0.5 μm to 3 μm. In some embodiments, the distance D2 ranges from 1 μm to 2 μm.

[0050] Referring to Figure 11, the manufacturing method includes performing a second etching process on the semiconductor material layer 12 using the hardening layer 16 and the dielectric layer 13 as masks. The semiconductor material layer 12 is partially removed to form a plurality of grooves 62 in the semiconductor material layer 12. In some embodiments, the second etching process includes a dry etching process, such as an isotropic or anisotropic dry etching process. The plurality of grooves 62 have approximately the same depth D62 vertically from the surface 12A, and the depth D62 is greater than the depth D61 of the groove 61. In some embodiments, the grooves 62 expose portions of the sidewalls 151C and 151D of the first dielectric layer 131 below the grooves 61. Each groove 62 is horizontally connected to the groove 61. The plurality of grooves 62 include, for example, grooves 621 and 622 located in the first dielectric layer 131. In some embodiments, the groove 621 is horizontally connected to the groove 611 and has a depth greater than the depth of the groove 611. In some embodiments, the groove 622 is horizontally connected to the groove 612 and has a depth greater than the depth of the groove 612.

[0051] Depending on the configuration and position of the dielectric layer 13, for example, with the bottom of the groove 62 as the boundary, the dielectric layer 13 can be divided into an upper portion 13U and a lower portion 13L. For example, the first dielectric layer 131 located on one side of the first electrode layer 141 has an upper portion 13U with a narrow upper portion and a wide lower portion. In other words, the thickness of the top of the upper portion 13U is less than the thickness of the bottom of the upper portion 13U. In some embodiments, the upper portion 13U has a thickness T135 in the horizontal direction at the level of the surface 12A of the semiconductor material layer 12, and the upper portion 13U has a thickness T136 in the horizontal direction at the junction of the semiconductor material layer 12 and the first dielectric layer 131, wherein the thickness T135 is less than the thickness T136. In some embodiments, the thickness T135 ranges from 0.1 to 0.2 μm. Depending on the second etching process, the upper portion 13U can have a smooth sidewall configuration with increasing thickness from the surface 12A to the surface 12B in the vertical direction, or a stepped configuration as shown in Figure 11. The lower portion 13L of the first dielectric layer 131 has a uniform thickness, and the thickness of the lower portion 13L of the first dielectric layer 131 is approximately the same as the thickness of the dielectric layer 13 in FIG4 . In some embodiments, the thickness T138 of the lower portion 13L is approximately equal to the thickness T136 . In other words, the thickness T138 of the lower portion 13L is greater than the thickness T135 of the upper portion 13U.

[0052] The grooves 61 and 62 together define the position of the gate structure to be formed later, and therefore the grooves 61 and 62 can be collectively referred to as gate trenches 63. The depth of the gate trench 63 is less than the depth of the shield structure 15. Each gate trench 63 can have a similar configuration. The gate trench 63 has a first sidewall 63G away from the shield structure 15, a second sidewall (including 63C, 63E, and 63D) adjacent to the shield structure 15, and a bottom surface 63F connecting the first sidewall 63G and the second sidewall, wherein the first sidewall 63G is a flat sidewall defined by the semiconductor material layer 12, and the second sidewall is a sidewall with a stepped configuration defined by the upper portion 13U of the dielectric layer 13.

[0053] FIG12 is an enlarged view of the location indicated by the dashed box in FIG11 , according to some embodiments of the present disclosure. The second sidewall of gate trench 63 (i.e., the sidewall of upper portion 13U of dielectric layer 13) includes a first partial sidewall 63C extending along a first direction, a second partial sidewall 63D approximately parallel to first partial sidewall 63C, and a third partial sidewall 63E connecting first and second partial sidewalls 63C and extending along a second direction. In some embodiments, the first direction is substantially parallel to the vertical direction. In some embodiments, the angle between the first and second directions is between 30 and 90 degrees. In some embodiments, the angle θ1 between first and third partial sidewalls 63C and 63E is between 30 and 90 degrees. In some embodiments, the angle θ2 between third and second partial sidewalls 63E and 63D is between 30 and 90 degrees. The angles θ1 and θ2 can be approximately the same (e.g., within a range of 5 degrees or less) or different (e.g., within a range of 5 degrees or more). The bottom surface 63B can extend substantially horizontally or have an arc-shaped configuration, without limitation. In some embodiments, the sidewall of the lower portion 13L of the dielectric layer 13 (exemplified by 132 in FIG. 12 ) adjacent to the semiconductor material layer 12 and the second portion sidewall 63D of the upper portion 13U are continuous sidewalls.

[0054] 11 and 12 illustrate gate trenches 63 with stepped sidewalls according to some embodiments of the present disclosure. In other embodiments, the openings 61 and 62 formed by the first and second etching processes can be controlled to have the same depth, so that the gate trenches 63 have a columnar configuration.

[0055] FIG14 illustrates a gate trench 63 having a columnar configuration according to some embodiments of the present disclosure. In the embodiment of FIG14 , the second sidewall of gate trench 63 is defined by a first partial sidewall 63C, and does not include a second partial sidewall 63D or a third partial sidewall 63E. The first partial sidewall 63C of gate trench 63 connects to a bottom surface 63B of gate trench 63, where bottom surface 63B is defined by a portion of dielectric layer 13 and a portion of semiconductor material layer 12.

[0056] As described above, the thickness of the dielectric layer 13 determines the voltage of the vertical semiconductor device 1. If the width of the gate structure within the dielectric layer 13 is too large, the withstand voltage performance of the vertical semiconductor device 1 will be affected. Therefore, the depth D61 of the opening 61 is preferably less than or equal to the depth D62 of the opening 62. In actual operation, the etching process will more or less have over-etching. Therefore, to ensure that the depth D61 of the opening 61 does not exceed the depth D62 of the opening 62, the etching depth is set to be less than the etching depth set in the second etching process when controlling the first etching process.

[0057] 14-15 , the manufacturing method includes forming a sacrificial layer 31 on the exposed portion of the semiconductor material layer 12 in the gate trench 63 after the second etching process in FIG. 12 , and removing the sacrificial layer 31 before forming the gate structure. In some embodiments, the sacrificial layer 31 comprises an oxide (e.g., silicon oxide). In some embodiments, the exposed semiconductor material layer 12 is subjected to a thermal oxidation process to form the sacrificial layer 31. The previous multiple processes may damage the surface of the semiconductor material layer 12. The sacrificial layer 31 can flatten the surface of the exposed semiconductor material layer 12, thereby helping the subsequently formed gate structure to have better performance.

[0058] 16 , the manufacturing method includes forming a gate dielectric layer 32 on the exposed portion of the semiconductor material layer 12. The method for forming the gate dielectric layer 32 can refer to the method for forming the dielectric layer 13, the first dielectric layer 131, and the second dielectric layer 132, and no repeated description is given. In some embodiments, a thermal oxidation process is performed to form the gate dielectric layer 32, and the gate dielectric layer 32 is only formed on the exposed portion of the semiconductor material layer 12. In some embodiments, a deposition process is performed to form the gate dielectric layer 32, and the gate dielectric layer 32 is conformally formed on the surface of the structure shown in FIG16 (including on the exposed portion of the semiconductor material layer 12 and the dielectric layer 13). The embodiment shown in FIG16 is a gate dielectric layer 32 formed by a thermal oxidation process. In some embodiments, the thickness of the gate dielectric layer 32 is less than the thickness T135 in FIG11 . In the embodiment where the gate dielectric layer 32 is formed by a deposition process, part of the gate dielectric layer 32 is located on the dielectric layer 13 , but as long as the total thickness of the gate dielectric layer 32 and the dielectric layer 13 meets the range of thickness T135 and thickness T136 mentioned above, it will be sufficient.

[0059] 17-18 , the manufacturing method includes forming a gate electrode 34 in a gate trench 63. A gate dielectric layer 32 surrounds the gate electrode 34. In some embodiments, the gate electrode 34 can be formed by physical vapor deposition, such as sputtering or spraying. In some embodiments, the gate electrode 34 can be formed by electroplating or CVD. In some embodiments, an electrode material layer 33 is formed to fill the gate trench 63 and cover the surface 12A, and then a grinding process, such as a chemical mechanical polishing process, is performed to grind and remove the electrode material layer 33 outside the gate trench 63 to form a plurality of gate electrodes 34 (including 341, 342, 343, and 344) in each gate trench 63. In some embodiments, the gate electrode 34 is adjacent to the upper portion 13U of the dielectric layer 13 of the shield structure 15.

[0060] In some embodiments, the electrode material layer 33 is partially removed while the hardening layer 16 on the surface 12A is removed to expose the surface 12A. In some embodiments, the electrode material layer comprises polysilicon. In some embodiments, the upper surface of the gate electrode 34 is flush with the surface 12A. For ease of description, each gate electrode 34 and each gate dielectric layer 32 may be collectively referred to as a gate structure 35.

[0061] Each gate structure 35 has a similar configuration, defined by the configuration of the gate trench 63. Therefore, the gate structure 35 has a configuration that is wide at the top and narrow at the bottom. For example, with the third portion sidewall 63E of Figure 11 as the boundary, the width T351 of the upper portion of the gate structure 35 is greater than the width T352 of the lower portion of the gate structure 35. In some embodiments, the width T351 of the upper portion of the gate structure 35 ranges from 0.6 to 0.8 μm. In some embodiments, the thickness T137 of the dielectric layer 13 adjacent to the upper portion of the gate structure 35 ranges from 0.1 to 0.2 μm. It should be noted that the thickness T135 of Figure 11 is measured at the level of the surface 12A, and the thickness T137 of Figure 18 can be the thickness of the dielectric layer 13 anywhere above the third portion sidewall 63E, including the thickness at the level of the surface 12A.

[0062] Measured horizontally at the same height, the sum of the width of the gate structure 35 and the thickness of the upper portion 13U of the dielectric layer 13 is greater than or equal to the thickness T138 of the lower portion 13L of the dielectric layer 13. In some embodiments, the ratio of the sum of the width T351 and the thickness T137 to the thickness T138 of the lower portion 13L of the dielectric layer 13 (i.e., (T351 + T137):T138) is greater than or equal to 1:1. In some embodiments, the width T351 may be the width of the upper portion of the gate structure 35 at the level of the surface 12A. Because the gate dielectric layer 32 has a uniform thickness, the profile of the gate electrode 34 is consistent with the profile of the gate trench 63, or the spacing between the gate electrode 34 and the gate trench 63 is conformal. In some embodiments, the sum of the width of the gate electrode 34 at the level of the surface 12A and the thickness T135 of the upper portion 13U of the dielectric layer 13 at the level of the surface 12A is greater than or equal to the thickness T138 of the lower portion 13L of the dielectric layer 13.

[0063] The semiconductor material layer 12 between adjacent shielding structures 15 has a platform-like profile, also known as a mesa region. The gate structure 35 of the vertical semiconductor device 1 of this embodiment is partially located in the mesa region, while the other portion is located in the dielectric layer 13 of the shielding structure 15. By controlling the width of the gate structure 35 in the mesa region and in the dielectric layer 13, the effective area of ​​the gate structure 35 (i.e., the cross-sectional area shown in FIG. 18 ) can be increased without affecting product specifications, thereby achieving the goal of improving gate resistance.

[0064] Referring to Figure 19 , the manufacturing method includes forming an oxide layer 37 on surface 12A of semiconductor material layer 12. In some embodiments, oxide layer 37 covers semiconductor material layer 12, gate structure 35, and shield structure 15. In some embodiments, oxide layer 37 can protect the surface of semiconductor material layer 12 during subsequent ion implantation, reducing surface damage, and controlling the thickness of oxide layer 37 does not affect ion implantation efficiency. In some embodiments, the gate structures 35 on both sides of electrode material layer 14 within shield structure 15 are substantially symmetrical. In some embodiments, the gate structures 35 on both sides of the mesa are substantially symmetrical.

[0065] 20-21 , the fabrication method includes performing a first ion implantation process on the semiconductor material layer 12 to form a body-doped region 21, and a second ion implantation process to form a source-doped region 22. The body-doped region 21 has a different conductivity type than the lightly-doped region 25. The depth of the body-doped region 21 determines the channel region. The body-doped region 21 is located between adjacent gate structures 35, vertically adjacent to the surface 12A and horizontally adjacent to the gate structure 35. The body-doped region 21 has a depth D21 vertically from the surface 12A, and the depth D21 is less than the depth D62 of the recess 62. In some embodiments, a distance D3 (i.e., the difference between the depth D62 and the depth D21) is between the bottom of the body-doped region 21 and the bottom of the gate structure 35, where the distance D3 ranges from 0.1 to 0.2 μm. The source-doped region 22 has the same conductivity type as the lightly-doped region 25, and the doping concentration of the first conductivity type ions in the source-doped region 22 is greater than the doping concentration of the first conductivity type ions in the lightly-doped region 25. The source doped region 22 is located between adjacent gate structures 35 and adjacent to the surface 12A. The source doped region 22 has a depth D22 vertically from the surface 12A, and the depth D22 is less than the depth D22 of the body doped region 21. In some embodiments, the doping concentration of the first conductive type ions in the source doped region 22 is greater than the doping concentration of the second conductive type ions in the body doped region 21. In some embodiments, a thermal annealing process is performed after forming the body doped region 21 to diffuse ions and activate the body doped region 21. In some embodiments, a thermal annealing process is performed after forming the source doped region 22 to diffuse ions and activate the body source doped region 22.

[0066] 22 , the manufacturing method includes forming an interlayer dielectric layer (ILD) 41 on the surface 12A of the semiconductor material layer 12. The interlayer dielectric layer 41 may be formed by ALD, CVD or other deposition processes.

[0067] 23-24 , the manufacturing method includes partially removing the interlayer dielectric layer 41 and partially removing the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142 using the interlayer dielectric layer 41 as a mask. In some embodiments, a patterned layer 52 is formed on the interlayer dielectric layer 41, and an etching process is performed on the interlayer dielectric layer 41 using the patterned layer 52 as a mask. The patterned layer 52 may be a photoresist layer. In some embodiments, the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142 include polysilicon, and the partial removal can be performed using a single etching process. In some embodiments, the patterned layer 52 is removed before the partial removal of the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142. In some embodiments, openings 411, 412, and 413 are formed in the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142, respectively. In some embodiments, the openings 411, 412, and 413 have approximately the same depth. In some embodiments, the depth of the opening 412 is greater than the depth D21 of the source doped region 21 .

[0068] 25 , the manufacturing method includes performing an ion implantation process on the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142 according to the openings 411, 412, and 413 to form a plurality of heavily doped regions 23 (e.g., 231, 232, and 233). Ions are implanted vertically into the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142 at the bottoms of the openings 411, 412, and 413. The heavily doped regions 231 and 233 are formed in the electrode material layer 14 adjacent to the bottoms of the openings 411 and 413, respectively, and the heavily doped region 232 is formed in the semiconductor material layer 12 adjacent to the bottoms of the opening 412. In some embodiments, the ion implantation process is followed by an annealing process to form the heavily doped regions 231, 232, and 233 shown in FIG. 25 .

[0069] 26 , the manufacturing method includes forming a plurality of conductive plugs 42 (including 421 , 422 , 423 ) in the openings 411 , 412 , and 413 . The conductive plugs 42 may be formed by filling the openings 411 , 412 , and 413 with a conductive material by electroplating or CVD. The material of the conductive plugs 16 may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), aluminum copper (Al x Cu y ), silicon copper (Si x Cu y ), alloys thereof or combinations thereof.

[0070] 27 , the manufacturing method includes forming a source electrode layer 44 and a drain electrode layer 47 on opposite sides of the semiconductor material layer 12. The source electrode layer 44 is formed on the interlayer dielectric layer 41 and the conductive plug 42. The source electrode layer 44 may include a suitable metal material or alloy, such as titanium tungsten (TiW), aluminum (Al), aluminum silicon alloy (AlSi), aluminum silicon copper alloy (AlSiCu) or a combination thereof, without limitation. After the source electrode layer 44 is formed, the source electrode layer 44 may be etched to form a desired pattern. Since the etching step is performed according to the desired circuit design, the etching step is not shown in the figure, and those skilled in the art can adjust the etching step according to the above content of the present disclosure to form the desired pattern of the source electrode layer 44.

[0071] A drain electrode layer 47 is formed on the bottom surface 11B of the substrate 11. The drain electrode layer 47 may include the same metal material or alloy as the source electrode layer 44. After forming the drain electrode layer 47, the drain electrode layer 47 may be etched to form a desired pattern. Because the etching step is performed based on the desired circuit design, the figure does not depict the etching step. Those skilled in the art can adjust the etching step based on the above disclosure to form the desired pattern of the drain electrode layer 47.

[0072] FIG28 is a top view of a vertical semiconductor device 1 according to some embodiments of the present disclosure. FIG1-27 is a cross-sectional view of multiple stages in a manufacturing method along the A-A' cut line according to some embodiments of the present disclosure. In the step of forming the conductive plug 42, a plurality of gate conductive plugs 43 are formed at the same time to electrically connect the gate structure 35. In the step of forming the source electrode layer 44, the gate electrode layer 45 can be formed simultaneously through an etching step. In some embodiments, the gate electrode layer 45 and the source electrode layer 44 are located at approximately the same horizontal height. From the top view of FIG28, a portion of the gate structure 35 overlaps with the shielding structure 15, and another portion of the gate structure 35 is located outside the coverage of the shielding structure.

[0073] FIG29 is a cross-sectional view of a manufacturing method along the BB' line in FIG28 according to some embodiments of the present disclosure. In some embodiments, the depth of gate conductive plug 43 is approximately the same as the depth of conductive plug 42. In some embodiments, gate conductive plug 43 includes regions 431, 432, 433, and 434, respectively connected to gate electrodes 341, 342, 343, and 344. In some embodiments, heavily doped region 23 also includes regions 234, 235, 236, and 237, respectively formed in gate electrodes 341, 342, 343, and 344, and adjacent to the bottoms of gate conductive plugs 431, 432, 433, and 434.

[0074] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," "left," "right," etc. may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating, in addition to the orientation depicted in the accompanying drawings. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or intervening components may be present.

[0075] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely as well as instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may refer to a position difference between two surfaces positioned along the same plane that is within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of the position difference positioned along the same plane. When a value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average value of the value.

[0076] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure can be readily used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A vertical semiconductor device, characterized in that: include: A semiconductor material layer having a first surface and a second surface opposite to each other; A first shielding structure, located in the semiconductor material layer and extending from the first surface to the second surface, the first shielding structure comprising a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; A first doped region, located in the semiconductor material layer and adjacent to the first surface, wherein the first doped region has a first conductivity type; as well as A first gate structure is located in the semiconductor material layer and extends from the first surface to the second surface. The first gate structure is adjacent to the first doped region. The depth of the first gate structure is less than the depth of the first shielding structure and greater than the depth of the first doped region. The first shielding dielectric layer is divided into an upper portion and a lower portion with the bottom of the first gate structure as a boundary, and the first gate structure is adjacent to the upper portion of the first shielding dielectric layer. The upper portion of the first shielding dielectric layer has a first thickness located at the first surface of the semiconductor material layer, and the first thickness is less than a second thickness of the lower portion of the first shielding dielectric layer, and A sum of the first thickness of the upper portion of the first shielding dielectric layer and a third thickness of the first gate structure located on the first surface is greater than the second thickness of the lower portion of the first shielding dielectric layer.

2. The vertical semiconductor device according to claim 1, wherein the first gate structure comprises: a first gate electrode, wherein the first gate electrode contacts the upper portion of the first shield dielectric layer; as well as The first gate dielectric layer is located between the first gate electrode and the semiconductor material layer. 3 . The vertical semiconductor device according to claim 2 , wherein a width of a top portion of the first gate electrode is greater than a width of a bottom portion of the first gate electrode.

4. The vertical semiconductor device according to claim 2 or 3, wherein the sum of the width of the first gate electrode located at the first surface and the first thickness of the upper portion of the first shielding dielectric layer is greater than or equal to the second thickness of the lower portion of the first shielding dielectric layer.

5. A vertical semiconductor device according to any one of the preceding claims, wherein the first gate structure has a first sidewall away from the first shielding structure and a second sidewall adjacent to the first shielding structure, the first sidewall is a flat sidewall, and the second sidewall is a sidewall with a stepped configuration. 6 . The vertical semiconductor device according to claim 1 , wherein from a top view, a portion of the first gate structure overlaps the first shielding structure, and a portion of the first gate structure is located outside the coverage of the first shielding structure.

7. A vertical semiconductor device according to any one of the preceding claims, wherein the upper portion of the first shielding dielectric layer has a first portion side wall extending along a first direction, a second portion side wall approximately parallel to the first portion side wall, and a third portion side wall connecting the first portion side wall and the second portion side wall and extending along a second direction, and the angle between the second direction and the first direction is between 30 and 90 degrees.

8. The vertical semiconductor device according to any one of the preceding claims, further comprising: a second shielding structure, located in the semiconductor material layer and extending from the first surface to the second surface, the second shielding structure being arranged adjacent to the first shielding structure, wherein the first doped region is at least located between the first shielding structure and the second shielding structure, and the second shielding structure comprises a second shielding dielectric layer, and a second shielding electrode surrounded by the second shielding dielectric layer; as well as The second gate structure is located in the semiconductor material layer and extends from the first surface to the second surface, and the configuration of the second gate structure is substantially symmetrical to that of the first gate structure.

9. The vertical semiconductor device according to any one of the preceding claims, further comprising: The second doping region is located in the semiconductor material layer and adjacent to the first surface. The second doping region is located in the first doping region and has a second conductivity type different from the first conductivity type. The depth of the first doping region is greater than the depth of the second doping region.

10. The vertical semiconductor device according to any one of the preceding claims, further comprising: A source electrode layer, disposed on the first surface of the semiconductor material layer; a first conductive plug electrically connected to the first shielding structure; as well as The third doping region is located in the first shielding electrode and adjacent to the first conductive plug, wherein the doping concentration of the first conductive type ions in the third doping region is greater than the doping concentration of the first conductive type ions in the first doping region.

11. A method for manufacturing a vertical semiconductor device, characterized in that: include: forming a first shielding structure in a lightly doped region of a semiconductor material layer, wherein the lightly doped region has a first conductivity type, and the first shielding structure comprises a first shielding electrode, and a first shielding dielectric layer located between the first shielding electrode and the semiconductor material layer; A first patterned layer is formed on the semiconductor material layer, wherein the first patterned layer has a first opening, and a first sidewall of the first opening is located at a first shielding electrode between the first shielding electrode and the semiconductor material layer. The first shielding dielectric layer is above the dielectric layer, and the first sidewall of the first shielding dielectric layer is located within the coverage of the opening; performing a first etching process on the first shielding dielectric layer to form a first groove in the first shielding dielectric layer, wherein the first groove exposes a portion of the semiconductor material layer; Performing a second etching process on the semiconductor material layer to form a second groove in the semiconductor material layer, wherein the depth of the second groove is greater than the depth of the first groove, the second groove exposes the first sidewall of the first shielding dielectric layer below the first groove, and the first groove is connected to the second groove to define a third groove; and A first gate structure is formed in the third groove.

12. The manufacturing method according to claim 11, wherein forming the first shielding structure in the semiconductor material layer comprises: forming a first trench in the semiconductor layer; forming the first shielding dielectric layer in the first trench along the sidewalls of the first trench; as well as The first shielding electrode is formed in the first trench, wherein a top surface of the first shielding electrode, a top surface of the first shielding dielectric layer, and a top surface of the semiconductor material layer are located at approximately the same level.

13. The manufacturing method according to claim 11 or 12, further comprising: After forming the first gate structure, a first ion implantation process is performed on the semiconductor material layer to form a body doped region, wherein the body doped region has a second conductivity type different from that of the lightly doped region. The manufacturing method according to claim 13 , wherein a depth of the body doping region is smaller than a depth of the first gate structure.

15. The manufacturing method according to claim 13 or 14, further comprising: A second ion implantation process is performed on the semiconductor material layer to form a source doped region, wherein the source doped region has the same first conductivity type as the lightly doped region, and the doping concentration of the first conductivity type ions in the source doped region is greater than the doping concentration of the first conductivity type ions in the lightly doped region.

16. The manufacturing method according to any one of claims 11 to 15, wherein the second groove exposes a portion of the semiconductor material layer adjacent to the first shielding structure, and the manufacturing method further comprises: After the second etching process, forming a first sacrificial layer on the exposed portion of the semiconductor material layer in the second groove; as well as Before forming the first gate structure, the first sacrificial layer is removed.

17. The manufacturing method according to any one of claims 11 to 16, wherein forming the first gate structure comprises: forming a first gate dielectric layer on the semiconductor material layer in the third groove; as well as A first gate electrode is formed in the third groove, wherein a width of an upper portion of the first gate electrode is greater than a width of a lower portion of the first gate electrode. 18 . The manufacturing method according to claim 17 , wherein the width of the upper portion of the first gate electrode is between 0.6 μm and 0.8 μm. 19 . The manufacturing method according to claim 17 , wherein a thickness of a portion of the first shield dielectric layer adjacent to the upper portion of the first gate electrode is between 0.1 μm and 0.2 μm. 20 . The manufacturing method according to claim 11 , wherein a thickness of the first shielding dielectric layer under the first gate electrode is between 0.6 μm and 0.8 μm.

21. The manufacturing method according to any one of claims 11 to 20, further comprising: forming a first conductive plug electrically connected to the first shielding structure; as well as A second conductive plug is formed to be electrically connected to the first gate structure. 22 . The manufacturing method according to claim 21 , wherein a depth of the first conductive plug or the second conductive plug in the semiconductor material layer is greater than a depth of a source doping region in the semiconductor material layer.

23. The manufacturing method according to any one of claims 11 to 22, wherein at least one of the first etching process and the second etching process comprises a dry etching process.

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