Data access method and memory

Abstract

A data access method and a memory. In the present application, the memory can receive a write request from a processor, wherein the write request is used for requesting the writing of data. The method comprises: a memory acquiring data carried in a write request; and after the data is compressed, executing an EEC operation for the compressed data to generate a first check code, and storing the compressed data, the first check code and a first identifier, wherein the first identifier is used for indicating that the stored data has been compressed. After data is compressed, storage space occupied by the data in a memory is reduced, thus allowing the generation of a first check code with a longer length, and the longer the length of a first check code is, the better an error correction capability thereof is. Compressing data can improve the reliability of the memory, and in the process, it is not necessary to add a memory die to the memory, so that the cost of the memory is ensured, and the reliability of the memory is also ensured.

Description

Data access method and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on November 22, 2023, with application number 202311593029.0 and application name "A Data Access Method and Memory", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a data access method and a memory. Background Art

[0004] Within a computing device, the memory of the computing device includes multiple storage particles for storing user data, and also includes one or more storage particles for storing check codes for the user data. In the event of an error in the user data, the check code can provide a certain error correction capability to correct the erroneous data.

[0005] When designing a computing device's memory, it's important to consider the error probabilities at various stages throughout the memory's lifecycle. If the memory is designed solely for the lower error probability during its initial use, then the memory will only include a small number of storage granules used to store user data checksums. This approach will increase the error probability later in the lifecycle, leading to reduced reliability. If the memory is designed solely for the higher error probability later in its lifecycle, then the memory will include a larger number of storage granules used to store user data checksums. This approach will result in higher costs and will not fully utilize the advantages of these multiple storage granules in the early stages of its lifecycle.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a data access method and a memory for improving the error correction capability of the memory without increasing the cost of the memory.

[0008] In a first aspect, an embodiment of the present application provides a data access method, which can be executed by a memory. The memory can receive a write request from a processor, the write request being used to request writing data.

[0009] The memory obtains the data carried in the write request, compresses the data, and then performs an ECC operation on the compressed data to generate a first check code. For example, the memory may invoke a first ECC error correction algorithm to generate the first check code for the compressed data. After generating the first check code, the memory may store the compressed data, the first check code, and a first flag bit, where the first flag bit is used to indicate that the stored data has been compressed.

[0010] Through the above method, when writing data into the memory, the memory can compress the data and generate a first check code for the compressed data. Since the data is compressed, the storage space occupied by the data in the memory is reduced, allowing the generation of a first check code with a longer length. The longer the first check code is, the better its error correction capability is. By compressing the data, the reliability of the memory can be improved. In this process, there is no need to increase storage particles in the memory, which not only ensures the cost of the memory but also ensures the reliability of the memory.

[0011] In one possible implementation, the storage medium of the memory is divided according to the wear status of different areas in the storage medium. The storage medium of the memory may include multiple first areas with different wear statuses. When storing compressed data, a first check code, and a first flag bit, the memory determines a first area for storing the compressed data, the first check code, and the first flag bit based on the wear statuses of the multiple first areas, and stores the compressed data, the first check code, and the first flag bit in the determined first area. The memory may determine a first area based on the wear statuses of the multiple first areas, allocate a first physical address to the compressed data, the first check code, and the first flag bit within the first area, and store the compressed data, the first check code, and the first flag bit at the first physical address.

[0012] Through the above method, the memory can assign a first physical address to the compressed data, the first check code and the first mark bit in combination with the wear status of different areas in the storage medium, and store the compressed data and the first check code to ensure that the compressed data, the first check code and the first mark bit can be stored in a more suitable first area.

[0013] In one possible implementation, because the first check code has a higher error correction capability, the compressed data, the first check code, and the first flag bit can be stored in an area with more wear. For example, the first area storing the compressed data, the first check code, and the first flag bit is the first area with the most wear among the first areas with free space. This ensures the memory's error correction capability while improving the utilization of each first area in the storage medium.

[0014] In one possible implementation, a storage medium of a memory is divided according to error rate ranges of different regions within the storage medium. The storage medium of the memory includes multiple second regions, and different second regions have different error rate ranges. When storing compressed data, a first check code, and a first flag bit, the memory determines a second region for storing the compressed data, the first check code, and the first flag bit based on the error rate ranges of the multiple second regions, and stores the compressed data, the first check code, and the first flag bit in the determined second region. The memory may determine a second region from the multiple second regions, assign a first physical address to the compressed data and the first check code within the second region, and store the compressed data and the first check code at the first physical address.

[0015] Through the above method, the memory can allocate a first physical address to the compressed data, the first check code and the first mark bit in combination with the error rate range of different areas in the storage medium, and store the compressed data, the first check code and the first mark bit to ensure that the compressed data, the first check code and the first mark bit can be stored in the second area with a suitable error rate range.

[0016] In one possible implementation, since the first check code has a higher error correction capability, it may be considered to store the compressed data, the first check code, and the first flag bit in an area with a larger error rate range. For example, the second area storing the compressed data, the first check code, and the first flag bit is the first area with the largest error rate range in the second area with free space. In the embodiment of the present application, the size of the error rate range refers to the size of the boundary value of the error rate range. This can not only ensure the error correction capability of the memory, but also improve the utilization rate of each area in the storage medium.

[0017] In a possible implementation, after compressing the data, if the ratio of the compressed data to the data is less than or equal to a compression rate threshold, the memory may perform an ECC operation on the compressed data to generate a first check code.

[0018] Through the above method, when the ratio of compressed data to data meets the compression rate threshold, it means that more storage space can be reserved for the first check code, effectively ensuring that the first check code is longer and has better error correction capability.

[0019] In one possible implementation, if the ratio of compressed data to data is greater than the compression rate threshold, the memory performs an ECC operation on the data to generate a second check code, stores the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and stores the data and the second check code.

[0020] If the ratio of compressed data to data does not meet a certain compression ratio threshold through the above method, and sufficient storage space cannot be reserved for the first check code, in this case, a second check code can be directly generated for the data. When storing the data and the second check code, a first region with less wear (e.g., the first region with the least wear in the first region with free space) and / or a second region with a smaller error rate range (e.g., the second region with the smallest error rate range in the second region with free space) can be selected.

[0021] In a possible implementation, when the memory stores the compressed data and the second check code, it may store the second check code and a second flag, where the second flag is used to indicate that the stored data is not compressed.

[0022] Through the above method, the second flag bit can be used to conveniently determine whether the data is compressed, so as to facilitate processing of the data when the data is read again later.

[0023] In one possible implementation, a memory receives a read request sent by a processor, the read request being used to request to read data. The memory obtains compressed data and a first check code. The memory first verifies the compressed data using the first check code. If the verification succeeds, indicating that the compressed data contains no errors, the memory decompresses the compressed data, obtains data, and feeds back the data to the processor. If the verification fails, indicating that the compressed data is erroneous, the memory corrects the compressed data using the first check code, and, if the correction succeeds, decompresses the corrected data, obtains data, and feeds back the data to the processor.

[0024] Through the above method, the memory can decompress the compressed data when the processor needs to read the data, ensuring that the memory can accurately feed back the data to the processor.

[0025] In a second aspect, the present application further provides a memory having the function of implementing the behavior in the method example of the first aspect. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The storage device includes a controller and a storage medium.

[0026] Storage media, used to store data.

[0027] The controller may receive a write request sent by the processor, the write request being used to request writing data. After receiving the write request, the controller compresses the data carried in the write request. After compressing the data, the controller performs an ECC operation on the compressed data to generate a first check code, and stores the compressed data, the first check code, and a first flag bit in a storage medium. The first flag bit is used to indicate that the stored data has been compressed.

[0028] In one possible implementation, the storage medium includes multiple first areas. When storing the compressed data, the first check code, and the first mark bit, the controller determines the first area for storing the compressed data, the first check code, and the first mark bit based on the wear status of the multiple first areas, and stores the compressed data, the first check code, and the first mark bit in the determined first area.

[0029] In a possible implementation, the first area storing the compressed data, the first check code, and the first flag bit is the first area with the greatest wear among the first areas with free space.

[0030] In one possible implementation, the storage medium includes multiple second areas, and different second areas have different error rate ranges. When storing the compressed data, the first check code, and the first mark bit, the controller determines the second area for storing the compressed data, the first check code, and the first mark bit based on the error rate ranges of the multiple second areas, and stores the compressed data, the first check code, and the first mark bit in the determined second area.

[0031] In a possible implementation, the second region storing the compressed data, the first check code, and the first flag bit is the first region with the largest error rate range among the second regions with free space.

[0032] In a possible implementation, the ratio of the compressed data to the data is less than a compression rate threshold.

[0033] In one possible implementation, if the ratio of compressed data to data is greater than the compression rate threshold, the controller can perform an ECC operation on the data to generate a second check code, store the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and store the data and the second check code.

[0034] In a possible implementation, when the controller stores the data and the second check code in the storage medium, it may store the data, the second check code, and a second flag, where the second flag is used to indicate that the stored data is not compressed.

[0035] In one possible implementation, the controller may receive a read request sent by the processor, where the read request is used to request to read data. The controller obtains compressed data and a first check code from the storage medium. The controller then verifies the compressed data using the first check code. If the verification succeeds, the controller decompresses the compressed data, obtains data, and feeds it back to the processor. If the verification fails, the controller corrects errors in the compressed data using the first check code. If the error correction succeeds, the controller decompresses the corrected data, obtains data, and feeds it back to the processor.

[0036] In a third aspect, the present application also provides a storage device, the functions of which can be implemented by hardware or by executing corresponding software through hardware. The hardware or software includes one or more units corresponding to the above functions. In one possible design, the structure of the storage device includes a compression module, a first encoding module, and a storage module, and optionally, a second encoding module. These modules can perform the corresponding functions of the storage device in the method example of the first aspect above. For details, please refer to the detailed description in the method example, which will not be repeated here.

[0037] In a fourth aspect, the present application also provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, it enables the computer to execute the method in the above-mentioned first aspect and various possible implementations of the first aspect.

[0038] In a fifth aspect, the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect and various possible implementations of the first aspect.

[0039] In a sixth aspect, the present application also provides a computer chip, which is connected to a memory and is used to read and execute a software program stored in the memory, and to execute the methods in the above-mentioned first aspect and various possible implementations of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of the structure of a data access system provided by this application;

[0041] FIG2 is a schematic diagram of the structure of a memory provided by the present application;

[0042] FIG3 is a schematic diagram of the structure of a storage particle provided by the present application;

[0043] FIG4 is a schematic diagram of a data access method provided by this application;

[0044] FIG5 is a schematic diagram of a storage device provided in this application. DETAILED DESCRIPTION

[0045] As shown in FIG1 , it is a schematic structural diagram of a data access system 10 provided in an embodiment of the present application. The system includes a processor 100 and a memory 200 .

[0046] Processor 100 is the computing core of the system. Processor 100 is capable of performing primary data computing operations. While performing data computing operations, processor 100 can access memory 200 to read or write data to memory 200. For example, processor 100 can read data from memory 200 and perform data computing on the read data; processor 100 can also store the resulting data in memory 200.

[0047] When accessing the memory 200 , the processor 100 sends a read request or a write request to the memory 200 . The read request or the write request carries a logical address of data to instruct the memory 200 to read or write data at the logical address.

[0048] The embodiments of the present application do not limit the specific type of processor 100. The processor 100 may be a central processing unit (CPU) or other specific integrated circuit. The processor 100 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0049] The memory 200 has a data storage function. The memory 200 can store data required by the processor 100 for data calculations, and can also store data generated by the processor 100 after data calculations. Exemplarily, the memory 200 receives and processes read requests or write requests from the processor 100, reads and writes data according to the logical address of the data, writes the data calculated by the processor 100 to the logical address, or reads the data required by the processor 100 for data calculations from the logical address, and feeds the read data back to the processor 100.

[0050] In the embodiment of the present application, the memory 200 has the following capabilities:

[0051] Capability 1. ECC capability.

[0052] The memory 200 with the ECC capability can perform ECC operations on the data and generate a checksum for the data when data needs to be written into the memory 200 (such as when the processor 100 initiates a write request). For example, the memory 200 can call an ECC error correction algorithm (such as the first ECC error correction algorithm and the second ECC error correction algorithm mentioned in the embodiment of the present application) to generate a checksum for the data, and store the data and the checksum for the data. Accordingly, when the data needs to be read (such as when the processor 100 initiates a read request), the memory 200 reads the data and the checksum for the data, and uses the checksum for the data to verify and correct the data. After verification or error correction, subsequent operations are performed, for example, data that has been successfully verified or corrected is transmitted to the processor 100, and for example, after error correction fails, the processing data is notified of an error. Verification refers to determining whether there is an error in the data, and error correction refers to correcting erroneous data in the data. Here, the ECC algorithm represents a class of algorithms that can be used to generate check codes. The embodiments of the present application do not limit the specific type of ECC algorithm, for example, Hamming code, Reed-Solomon (RS), and BCH (Bose-Chaudhuri-Hocquenghem) algorithm.

[0053] The memory 200 with the ECC capability can correct erroneous data in the internally stored data to ensure the accuracy of the data.

[0054] Ability 2: Data compression and decompression capabilities.

[0055] The memory 200, which has compression and decompression capabilities, can compress data before writing it into the memory. If the compression is successful, the compressed data is written to the memory 200. If the compression fails, the data is written to the memory 200. Compression success means that the ratio of the compressed data to the uncompressed data (referred to as the data compression ratio) is less than or equal to the compression ratio threshold, and compression failure means that the ratio of the compressed data to the uncompressed data (referred to as the data compression ratio) is greater than the compression ratio threshold.

[0056] Correspondingly, when data needs to be read, if the data is successfully compressed when being written into the memory 200 , the memory 200 will read the compressed data and decompress the compressed data.

[0057] In addition, the memory 200 may also set a first flag bit for the data that has been compressed successfully, and the first flag bit is used to indicate that the data has been compressed. The embodiment of the present application does not limit the setting method of the first flag bit. For example, the first flag bit may be stored in the memory 200 together with the compressed data. For another example, the first flag bit may be added to the mapping relationship between the logical address and the physical address of the data. When the data is subsequently read, when the physical address of the data is queried, the first flag bit recorded in the mapping relationship can be used to determine that the data has been compressed.

[0058] For data that fails to be compressed, the memory 200 may further set a second flag bit for the data, the second flag bit being used to indicate that the data is not compressed. Similar to the first flag bit, the embodiment of the present application does not limit the setting method of the second flag bit. For example, the second flag bit may be stored in the memory 200 together with the data. For another example, the second flag bit may be added to the mapping relationship between the logical address and the physical address of the data. When the data is subsequently read and the physical address of the data is queried, the second flag bit recorded in the mapping relationship may be used to determine that the data is not compressed.

[0059] The memory 200 having compression and decompression capabilities can reduce redundant data in the data, thereby reducing the storage space occupied by the data.

[0060] Given that the memory 200 has both of the above capabilities, when storing data, the memory 200 can compress the data and then generate a check code for the compressed data, that is, perform an ECC operation on the compressed data to generate a check code, and the check code for the compressed data is the check code generated for the compressed data (such as the first check code mentioned in the embodiment of the present application), and store the compressed data and the check code of the compressed data (optionally, the first flag bit can also be stored). The memory 200 may also not compress the data, generate a check code for the data, store the data and the check code for the data (optionally, the second flag bit can also be stored).

[0061] Accordingly, when data in the memory 200 needs to be retrieved, the memory 200 can retrieve the compressed data and the check code of the compressed data, and after successfully verifying the compressed data using the check code of the compressed data, decompress the compressed data. The memory 200 can also retrieve the data and the check code of the data and verify the data using the check code of the data.

[0062] Ability 3: Assign physical addresses to data.

[0063] The processor 100 specifies the storage location of data in the memory 200 using the data's logical address. A logical address can be understood as the address provided by the memory 200 to an external device (such as the processor 100) to locate the data's storage location. The memory 200 can assign an actual storage location (physical address) to the data based on the data's logical address. In other words, the memory 200 can convert logical addresses into physical addresses. A physical address is the address used within the memory 200 to locate the storage location of data.

[0064] In memory 200, data is written and read by changing the voltage of the internal circuit of memory 200. The number of read and write operations or the frequency of the read and write operations will cause wear on the storage medium 220 in memory 200. Different degrees of wear will also lead to different actual error rates of data within each region. In storage medium 220, the number of read and write operations occurring in different regions varies, and the wear state of each region also varies. A region with a high number of read and write operations has a high actual error rate and a poor wear state; a region with a low number of read and write operations has a low actual error rate and a good wear state. The actual error rate indicates the probability of erroneous data occurring when reading and writing data at that location or region. In the embodiments of the present application, the specific calculation method of the actual error rate is not limited. The actual error rate of a location or region can be equal to the ratio of the number of bits that are erroneous during a set number of data read and write operations to the total number of bits read and written during the set number of data read and write operations, or it can be equal to the ratio of the number of bits that are erroneous during multiple data read and write operations performed per unit time to the total number of bits read and written during the set number of data read and write operations.

[0065] In the embodiment of the present application, the memory 200 is capable of monitoring the wear status of each region within the storage medium 220 within the memory 200. When converting logical addresses to physical addresses, the memory 200 assigns physical addresses to data based on the wear status of each region within the storage medium 220 and establishes a mapping relationship between logical addresses and physical addresses. The wear status of a region indicates the number of read and write operations within that region or its actual error rate.

[0066] For example, the memory 200 may preferentially write compressed data into an area in a less worn state, and write uncompressed data into an area in a more worn state.

[0067] Due to factors such as the wiring pattern of the internal circuits of memory 200 and the design of the drive voltage within memory 200, the error rates of different areas of storage medium 220 vary. This means that when storage medium 220 is further divided into multiple areas based on the data error rate, the error rate range within each area is the same, while the error rate ranges of different areas are different. The error rate here is different from the error rate described above in the description of wear and tear. The error rate described above refers to the error rate calculated by recording errors during the reading and writing processes of the memory 200 during operation (after leaving the factory), and is the actual error rate of the memory 200. The error rate here refers to the error rate of different areas of storage medium 220, which is caused by factors such as the wiring structure of the internal circuits of memory 200 and the design of the driving voltage within memory 200. This error rate is determined based on the properties of memory 200 itself. This error rate is determined based on the hardware characteristics of memory 200. It can be estimated before memory 200 leaves the factory or obtained through professional evaluation software testing. It is not the error rate obtained by actual measurement during the operation of memory 200. For the sake of convenience, this error rate is referred to as the estimated error rate.

[0068] When converting a logical address into a physical address, the memory 200 may allocate a physical address to the data in combination with the error rate ranges of different regions and the state of the data itself.

[0069] For example, the memory 200 may preferentially write compressed data into an area with a higher error rate, and write uncompressed data into an area with a lower error rate.

[0070] It should be noted that the area division criteria mentioned in "the memory 200 monitors the wear status of each area in the storage medium 220 in the memory 200" and the area division criteria mentioned in "the error rate range of different areas in the storage medium 220" may be different. For example, when dividing areas according to the wear status, the memory 200 can monitor the number of read and write times or the actual error rate at each physical address in the storage medium 220 in the memory 200, and divide it into multiple areas according to the number of read and write times or the actual error rate at each physical address in the storage medium 220. Assume that the memory 200 is divided into multiple areas according to the number of read and write times at each physical address in the storage medium 220. The number of read and write times of physical addresses in different areas is different. Each area corresponds to a read and write number range, that is, for any area, the number of read and write times of the physical addresses in the area belongs to the read and write number range corresponding to the area.

[0071] The areas referred to in the “error rate ranges of different areas within the storage medium 220” may be areas determined based on specific values ​​of the estimated error rate range.

[0072] In order to conveniently distinguish between these two different areas, in an embodiment of the present application, the area mentioned in "the memory 200 monitors the wear status of each area in the storage medium 220 in the memory 200" is referred to as the first area, and the storage medium 220 may include multiple first areas, and the number of read and write times at each physical address in each first area belongs to the range of read and write times corresponding to the first area. The wear status of different first areas is different. The embodiment of the present application does not limit the division method of the first area and the number of first areas. For example, the interior of the memory 200 can be divided according to the number of read and write times at different physical addresses in the storage medium 220, and the storage medium 220 is divided into ten first areas, each first area corresponding to a range of read and write times. As the memory 200 interacts with the processor 100, the number of read and write times at different physical addresses in the storage medium 220 will change, and the coverage of the first area (that is, the physical address covered by the first area) will also change.

[0073] The area mentioned in "the error rate range of different areas in the storage medium 220" is referred to as the second area. The storage medium 220 may include multiple second areas, each second area corresponds to an error rate range, and the error rate ranges of different second areas are different. The division of the second areas of different error rate ranges in the storage medium 220 is related to multiple factors such as the wiring of the circuit inside the memory 200 and the design of the driving voltage in the memory 200. The number of second areas included in the storage medium 220 and the error rate range of each second area are related to the circuit structure inside the memory 200. In addition, when using dedicated evaluation software to test its estimated error rate, the number of second areas of different error rate ranges in the memory 200 and the error rate range of each second area will also change due to the setting of the test parameters. For example, during a specific test, if a higher accuracy or more error rate gears can be selected, the number of second areas included in the storage medium 220 may also increase.

[0074] From the above definitions of the two areas, it can be seen that there is no direct relationship between the first area and the second area. The first area may include one or more second areas, and the first area may also include parts of the second area. The second area may include one or more first areas, and the second area may also include parts of one or more first areas.

[0075] The embodiment of the present application does not limit the specific type of the memory 200. The memory 200 may be a phase change memory 200 (PCM), a dynamic random access memory 200 (DRAM), or other types of memory.

[0076] As shown in FIG2 , a schematic diagram of the structure of a memory provided in an embodiment of the present application is shown. The memory 200 includes a controller 210 and a storage medium 220.

[0077] In the memory 200, the storage medium 220 is the main component for storing data. The embodiment of the present application does not limit the specific type of the storage medium 220. The specific type of the storage medium 220 is related to the type of the memory 200. For example, when the memory 200 is PCM or DRAM, the storage medium 220 is the storage particle 230 of the PCM or DRAM.

[0078] The following describes the structure of storage medium 220, taking PCM or DRAM as an example. As shown in Figure 3, storage medium 220 includes multiple storage chips 230. From a hardware perspective, a storage chip 230 is the smallest physical unit for storing data in memory 200. The storage space within any storage chip 230 can be further divided. Each storage chip 230 includes multiple banks, each of which can be viewed as a storage matrix, similar to a grid array. This "grid array" has many columns and many rows. To access data from memory 200, one only needs to specify the bank, the row within the bank, and the column. The size, number of rows, and number of columns of each bank are relatively fixed, meaning that the logical address range covered by each bank is fixed.

[0079] In a memory 200 such as PCM or DRAM, the multiple storage granules 230 included in the memory 200 share the same set of logical addresses. That is, after receiving a read / write request carrying a logical address, the controller 210 within the memory 200 converts the logical address into a physical address and sends the physical address to each storage granule 230. Each storage granule 230 then parses the physical address to extract information pointing to the bank, column, and row, and then reads or writes data to the bank, column, and row indicated by the information.

[0080] When there are multiple storage particles 230 in the memory 200, each storage particle 230 can contribute part of the data. For example, each storage particle 230 contributes 8 bytes of data. In this way, the amount of data read or written in each data read or write operation in the memory 200 is the sum of the data contributed by each storage particle 230. For example, the amount of data read or written in a data read or write operation is the product of the number of storage particles 230 and 8. The data at the logical address is physically distributed among the storage particles 230 in the memory 200.

[0081] The controller 210 is the control center of the memory 200, and manages or controls the storage medium 220. For example, the controller 210 writes data or reads data in the storage medium 220, or implements data compression or decompression, or implements conversion between logical addresses and physical addresses.

[0082] The controller 210 can support various capabilities of the memory 200. The following describes how the controller 210 supports various capabilities of the memory 200:

[0083] Capability 1. ECC capability.

[0084] Within the memory 200, after receiving a write request for writing data sent by a device external to the memory 200 (such as the processor 100) to the memory 200, the controller 210 determines that the data needs to be written to the storage medium 220, performs an ECC operation on the data, generates a check code for the data, and stores the data and the check code. Exemplarily, the controller 210 invokes an ECC error correction algorithm to generate the check code for the data, and writes the data and the check code to the storage medium 220.

[0085] After receiving a read request from a device outside of memory 200 to read data from memory 200, controller 210 not only reads the data from storage medium 220 but also reads a checksum for the data from storage medium 220. It then uses an ECC (Electronic Code Computing) algorithm to verify the data read from storage medium 220 based on the checksum to determine whether the data read from storage medium 220 is erroneous. If the verification indicates no errors in the data, controller 210 feeds the data back to the device requesting the data. If the verification indicates errors in the data, controller 210 uses the checksum to correct the data. If the correction is successful, controller 210 feeds the corrected data back to the device requesting the data. If the correction fails, controller 210 notifies the device of the data read error.

[0086] Ability 2: Data compression and decompression capabilities.

[0087] Within the memory 200, upon receiving a write request from a device external to the memory 200 (e.g., the processor 100) requesting to write data to the memory 200, the controller 210 determines that the data needs to be written to the storage medium 220, compresses the data, and, if successful, stores the compressed data in the storage medium 220. If the compression fails, the data is stored in the storage medium 220. Upon receiving a read request from a device external to the memory 200 requesting to read data from the memory 200, the controller 210 needs to read the data from the storage medium 220. If the data is successfully compressed when written to the storage medium 220, the controller 210 reads the compressed data from the storage medium 220, decompresses the compressed data, obtains the data, and feeds the data back to the device requesting the data. If the data is uncompressed when written to the storage medium 220, the controller 210 reads the data from the storage medium 220 and feeds the data back to the device requesting the data.

[0088] Inside the memory 200, the controller 210 can implement the setting and storage of the first flag bit and the second flag bit. The setting and storage methods of the first flag bit and the second flag bit can be referred to the above description and will not be repeated here.

[0089] Since the memory 200 has both of the above capabilities, when storing data, the memory 200 can generate a check code for the compressed data after the data is successfully compressed. The memory 200 can also generate a check code for the data without compressing the data.

[0090] Within the memory 200, if data needs to be written to the storage medium 220, the controller 210 may first compress the data. If the compression is successful, the controller 210 obtains the compressed data, performs an ECC operation on the compressed data to generate a check code for the compressed data, and stores the compressed data and the check code in the storage medium 220. If the compression fails, the controller 210 performs an ECC operation on the data to generate a check code for the data, and stores the data and the check code in the storage medium 220.

[0091] Accordingly, when it is necessary to obtain data from the memory 200, inside the memory 200, if it is necessary to read data from the storage medium 220, if the data is successfully compressed when written, the controller 210 reads the compressed data and the check code of the compressed data from the storage medium 220, and calls the ECC error correction algorithm to verify the read data according to the check code. If it is found through verification that there is no error in the compressed data, the controller 210 can decompress the compressed data, obtain the data, and feed the data back to the device requesting the data. If it is found through verification that there is an error in the compressed data, the controller 210 will use the check code of the compressed data to correct the compressed data; when the error correction is successful, the controller 210 continues to decompress the data obtained after the error correction, obtain the data, and feed the data back to the device requesting the data; when the error correction fails, the controller 210 notifies the device requesting the data that an error has occurred in the data reading.

[0092] Ability 3: Assign physical addresses to data.

[0093] Within the memory 200, the controller 210 can convert logical addresses into physical addresses. When converting logical addresses into physical addresses, the controller 210 can assign physical addresses to data based on the wear status of each first region in the storage medium 220 and establish a mapping relationship between logical and physical addresses. The controller 210 can also assign physical addresses to data based on the error rate ranges of different second regions and the status of the data itself.

[0094] 4 , a data access method provided by an embodiment of the present application is described below. The method includes two parts: one part is a data writing process, see steps 401 to 408 , and the other part is a data reading process, see steps 409 to 411 .

[0095] Step 401: The processor 100 sends a write request to the memory 200. The write request is used to request writing data, and the write request includes the data and the logical address of the data.

[0096] Step 402: After receiving the write request, the memory 200 compresses the data contained in the write request. If the data compression is successful, step 403 is executed. If the data compression fails, step 406 is executed. This step may be executed by the controller 210.

[0097] When compressing data, the data compression rate (i.e., the ratio of the compressed data to the uncompressed data) is related to the data compression method and the data itself. For example, for data such as images and videos with less repetitive data, the data compression rate is lower and the amount of data that can be compressed is smaller. For file and text data, such data usually contains more repetitive data, the compression rate of such data is higher, and the amount of data that can be compressed is larger. In addition, the data compression method used by the memory 200 is not limited in the embodiments of the present application, and any method that can compress data is applicable to the embodiments of the present application.

[0098] A compression ratio threshold is set within memory 200. After compressing the data, memory 200 determines the ratio of the compressed data to the uncompressed data, i.e., the data compression ratio, and compares the data compression ratio with the compression ratio threshold. If the data compression ratio is less than or equal to the compression ratio threshold, compression is successful, and memory 200 executes step 403. If the data compression ratio is greater than the compression ratio threshold, compression fails, and memory 200 executes step 406.

[0099] The embodiment of the present application does not limit the number of compression rate thresholds set inside the memory 200. One compression rate threshold or multiple compression rate thresholds can be set inside the memory 200. When multiple compression rate thresholds are set inside the memory 200, when the compression rate of the data is less than or equal to any compression rate threshold, the compression is considered to be successful. When the compression rate of the data is greater than all compression rate thresholds, the compression is considered to have failed. Among them, the situation where the compression rate of the data is equal to the compression rate threshold can be considered as a special case. In actual applications, it can be considered that the compression is successful when the compression rate of the data is equal to the compression rate threshold, or it can be considered that the compression fails when the compression rate of the data is equal to the compression rate threshold.

[0100] Each compression rate threshold corresponds to an ECC operation. An ECC operation refers to a method of generating a checksum based on data. Different compression rate thresholds can correspond to different ECC operations. Different ECC operations may generate different checksums for the same data, such as different checksum lengths. This ECC operation can be understood as an ECC error correction algorithm. To put it another way, each compression rate threshold corresponds to a first ECC error correction algorithm, and different compression rate thresholds may correspond to different first ECC error correction algorithms. When the compression rate of data is less than or equal to one of multiple compression rate thresholds, the data's compression rate may be less than another of the multiple compression rate thresholds. In other words, multiple compression rate thresholds may all be greater than or equal to the data's compression rate. For example, five compression rate thresholds are set: compression rate threshold A, compression rate threshold B, compression rate threshold C, compression rate threshold D, and compression rate threshold E. When the data's compression rate is less than or equal to compression rate threshold B, the data's compression rate is also necessarily less than compression rate threshold A. In the subsequent step 403 , step 403 may be performed by performing an ECC operation (or a first ECC error correction algorithm) corresponding to a minimum compression rate threshold among multiple compression rate thresholds greater than the compression rate of the data.

[0101] Step 403: After the data is successfully compressed, the memory 200 performs an ECC operation on the compressed data to generate a check code for the compressed data. For ease of description, in this embodiment of the application, the check code generated for the compressed data is referred to as a first check code.

[0102] In the embodiment of the present application, the ECC error correction algorithm used to generate the first check code is referred to as a first ECC error correction algorithm. The embodiment of the present application does not limit the specific type of the first ECC error correction algorithm. In other words, step 403 can be understood as the memory 200 calling the first ECC error correction algorithm on the compressed data to generate the first check code.

[0103] For any ECC error correction algorithm, the ECC error correction algorithm can encode data and generate a check code for the data. Different ECC error correction algorithm types or different parameter values ​​in the ECC error correction algorithm can generate different lengths of the check code for the data.

[0104] In the embodiment of the present application, for the first ECC error correction algorithm corresponding to any compression rate threshold, when the data compression rate is equal to the compression rate threshold, the first checksum generated by the first ECC error correction algorithm for the compressed data and the total data length of the compressed data are no longer than the data length that the controller 210 can write to the storage medium 220 at one time. Taking PCM as an example, the data length that the controller 210 can write to the storage medium 220 at one time is equal to the product of the number of storage particles 230 in the storage medium 220 and the bit width of each storage particle 230, where the bit width of a storage particle 230 is equal to the data length that can be written by the storage particle 230 at one time.

[0105] When the memory 200 executes step 403, if the data compression rate is less than the compression rate threshold corresponding to the first ECC error correction algorithm, then the total data length of the first check code generated by the first ECC error correction algorithm for the compressed data and the compressed data may be less than the data length that the controller 210 writes to the storage medium 220 at one time. In this case, the controller 210 may first pad the compressed data with zeros, that is, add one or more zeros to the compressed data to ensure that the total data length of the first check code generated by the first ECC error correction algorithm for the zero-padded data and the zero-padded data is equal to the data length that the controller 210 writes to the storage medium 220 at one time. The controller 210 may also first generate the first check code for the compressed data by the first ECC error correction algorithm, and then pad the compressed data and the first check code with zeros, so that the total data length of the compressed data and the first check code after the zero-padded data is equal to the data length that the controller 210 writes to the storage medium 220 at one time.

[0106] For the memory 200, when the storage space provided by the storage medium 220 within the memory 200 is fixed (e.g., the size and number of the storage particles 230 are fixed), during a data read / write operation, the total amount of data and its checksum written by the memory 200 to the storage medium 220 (i.e., the length of data that the controller 210 can write to the storage medium 220 at one time) is typically fixed. For example, under the Double Data Rate (DDR) 4 standard, 8 or 16 storage particles 230 are allowed to store data, and 1 or 2 storage particles 230 are allowed to store the checksum of the data. When 8 storage particles 230 store data and 1 storage particle 230 stores the checksum of the data, each storage particle 230 provides 8 bytes of space for storing the data or the checksum of the data. When 16 storage particles 230 store data and 2 storage particles 230 store the checksum of the data, each storage particle 230 provides 4 bytes of space for storing the data or the checksum of the data. Regardless of which method is used, the total amount of data read and written in the memory 200 in one data read and write operation is 64 bytes of data and an 8-byte check code, that is, the total amount of data is 72 bytes of data.

[0107] In the embodiment of the present application, when the memory 200 executes step 403, since the data has been compressed successfully, the memory 200 can generate a first check code with a longer data length for the compressed data. For example, still taking the DDR4 standard as an example, for 64 bytes of data, when not compressed, the maximum data length of the check code of the data allowed within the memory 200 is 8 bytes. If the 64 bytes of data are compressed and become 56 bytes of data, the maximum data length of the check code of the data allowed within the memory 200 is 16 bytes. The increase in the check code can effectively improve the error correction capability of the memory 200.

[0108] Step 404: The memory 200 allocates a first physical address to the compressed data and the first check code, and records a mapping relationship between the first physical address and the logical address.

[0109] After the memory 200 obtains the compressed data and generates the first check code, the memory 200 can execute step 404. The embodiment of the present application does not limit the way in which the memory 200 executes step 404. The following lists several ways in which the memory 200 provided in the embodiments of the present application allocates the first physical address to the compressed data and the first check code.

[0110] Method 1: The memory 200 allocates a first physical address to the compressed data and the first check code according to the wear status of each first area in the storage medium 220 .

[0111] Since the data length of the first check code is long and the error correction performance of the first check code is better, the memory 200 can select the first physical address in the first area with more wear (that is, the wear state is worse) from multiple first areas when allocating the first physical address for the compressed data and the first check code. The embodiment of the present application does not limit the way in which the memory 200 selects the first area where the first physical address is located from the multiple first areas. For example, the memory 200 can select the first area with the greatest wear from the first area with free space, and allocate the first physical address to the compressed data and the first check code from the first area. For another example, the memory 200 can select the first area with medium wear (that is, the wear is between the maximum wear and the minimum wear) from the first area with free space, and allocate the first physical address to the compressed data and the first check code from the first area.

[0112] For example, the memory 200 divides the area within the storage medium 220 into two first areas, a first area A and a first area B, based on the number of read and write times at each physical address. The number of read and write times of the physical addresses in the first area A is greater than the number of read and write times of the physical addresses in the first area B. If there is an unoccupied physical address in the first area A, the memory 200 assigns the first physical address in the first area A to the compressed data and the first check code. If there is no unoccupied physical address in the first area A, the memory 200 assigns the first physical address in the first area B to the compressed data and the first check code.

[0113] For example, based on the number of read and write times at each first physical address, the memory 200 divides the area within the storage medium 220 into three first areas, namely, the first area A1, the first area A2, and the first area A3. The number of read and write times of the first physical address of each first area is sorted from large to small as follows: the first area A1, the first area A2, and the first area A3.

[0114] If there are unoccupied physical addresses in the first area A1, the memory 200 allocates the first physical address in the first area A1 to the compressed data and the first check code. If there are no unoccupied physical addresses in the first area A1, and there are unoccupied physical addresses in the first area A2, the memory 200 allocates the first physical address in the first area A2 to the compressed data and the first check code. If there are no unoccupied physical addresses in the first area A1 and the first area A2, and there are unoccupied physical addresses in the first area A3, the memory 200 allocates the first physical address in the first area A3 to the compressed data and the first check code.

[0115] Method 2: The memory 200 allocates a first physical address to the compressed data and the first check code according to the error rate range of each second area in the storage medium 220 .

[0116] Since the data length of the first check code is longer and the error correction performance of the first error correction code is better, the memory 200 can select the first physical address in the second area with a higher error rate range from multiple second areas when allocating the first physical address for the compressed data and the first check code. The embodiment of the present application does not limit the manner in which the memory 200 selects the second area where the first physical address is located from the multiple second areas. For example, the memory 200 can select the second area with the largest error rate range from the second area with free space, and allocate the first physical address to the compressed data and the first check code from the second area. For another example, the memory 200 can select the second area with a middle error rate range from the second area with free space, and allocate the first physical address to the compressed data and the first check code from the second area.

[0117] For example, for each bank in the storage element 230 in the memory 200, each bank is divided into two second regions, a second region A and a second region B. The error rate range of the first region A is greater than the error rate range of the first region B (that is, the lower limit of the error rate range of the first region A is greater than the upper limit of the error rate range of the first region B). If there is an unoccupied physical address in the second region A, the memory 200 allocates the first physical address in the second region A to the compressed data and the first check code. If there is no unoccupied physical address in the second region A, the memory 200 allocates the first physical address in the second region B to the compressed data and the first check code.

[0118] For example, the memory 200 divides each BANK in the storage particle 230 into three second areas, namely, the second area A1, the second area A2, and the second area A3. The error rate ranges of the second areas are sorted from large to small as follows: the second area A1, the second area A2, and the second area A3.

[0119] If there are unoccupied physical addresses in the second area A1, the memory 200 allocates the first physical address in the second area A1 to the compressed data and the second check code. If there are no unoccupied physical addresses in the second area A1, and there are unoccupied physical addresses in the second area A2, the memory 200 allocates the physical addresses in the second area A2 to the compressed data and the second check code. If there are no unoccupied physical addresses in the second area A1 and the second area A2, and there are unoccupied physical addresses in the second area A3, the memory 200 allocates the first physical address in the second area A3 to the compressed data and the second check code.

[0120] Method three: the memory 200 allocates a first physical address to the compressed data and the first check code according to the wear status of each first area in the storage medium 220 and the error rate range of each second area.

[0121] Since the data length of the first check code is longer and the error correction performance of the first error correction code is better, when the memory 200 assigns the first physical address to the compressed data and the first check code, it can select a first area with more wear (that is, a worse wear state) from multiple first areas, such as selecting the first area with the most wear. After selecting the first area, if the first area includes one or more second areas (or partial areas in the second area), the memory 200 can further select a second area with a larger error rate range (partial area in the second area) from the first area. For example, if the second area with the largest error rate range is selected, the memory 200 can assign the first physical address to the compressed data and the first check code from the second area.

[0122] When allocating the first physical address to the compressed data and the first check code, the memory 200 may also select a second area with a larger error rate range from multiple second areas, such as selecting the second area with the largest error rate range. After selecting the second area, if the second area includes one or more first areas (or partial areas in the first area), the memory 200 may further select a first area (partial area in the first area) with a worse wear state (i.e., more wear) from the second area. For example, if the first area with the most wear is selected, the memory 200 may allocate a first physical address to the compressed data and the first check code from the first area.

[0123] The embodiment of the present application does not limit the manner in which the memory 200 selects the second region where the first physical address is located from the plurality of second regions, nor the manner in which the memory 200 selects the first region where the first physical address is located from the plurality of first regions. Any manner in which the first physical address can be assigned based on the wear status of each first region in the storage medium 220 and the error rate range of each second region for compressed data and the first check code is applicable to the embodiment of the present application.

[0124] For example, the area within the storage medium 220 is divided into two first areas, a first area A and a first area B, and the number of read and write times of the physical address in the first area A is greater than the number of read and write times of the first physical address in the first area B. If there is an unoccupied first physical address in the first area A, and the first area A covers one or more second areas (or partial areas in the second areas), the memory 200 determines a second area in the first area A that has a minimum error rate range and an unoccupied physical address, and the memory 200 assigns the first physical address in the second area to the compressed data and the first check code.

[0125] Step 405: The memory 200 stores the compressed data and the first check code according to the first physical address.

[0126] After determining the first physical address, the memory 200 stores the compressed data and the first check code at the location indicated by the first physical address. Taking the memory 200 as a PCM as an example, since each storage cell 230 within the memory 200 shares the same physical address, the controller 210 transmits the first physical address and the data to be stored in each storage cell 230 to each storage cell 230. Each storage cell 230 locates the row and column of the bank within the storage cell 230 based on the first physical address and inputs a control voltage to the devices or circuits on the row and column of the bank within the storage cell 230, thereby writing data to the row and column of the bank within the storage cell 230.

[0127] Optionally, the memory 200 can set and store a first flag bit for the compressed data, and the first flag bit is used to indicate that the stored data has been compressed. The embodiment of the present application does not limit the setting method of the first flag bit. For example, after generating the first check code, the memory 200 can add a first flag bit for characterizing that the data has been compressed to the compressed data, and the compressed data, the first check code and the first flag bit can be stored on the first physical address. For another example, when the memory 200 records the mapping relationship between the physical address (such as the first physical address) and the logical address, the memory 200 can add a first flag bit for indicating that the data is not compressed to the mapping relationship, and the first flag bit is stored in the mapping relationship.

[0128] Step 406: After the data compression fails, the memory 200 performs an ECC operation on the data to generate a check code for the data. For ease of explanation, in this embodiment of the present application, the check code generated for the data is referred to as a second check code. The ECC operation performed in step 406 is different from the ECC operation performed in step 404, and the check code generated is also different.

[0129] In the embodiment of the present application, the ECC error correction algorithm used to generate the second check code is referred to as a second ECC error correction algorithm. The embodiment of the present application does not limit the specific type of the second ECC error correction algorithm. In other words, step 403 can be understood as the memory 200 calling the second ECC error correction algorithm on the compressed data to generate the second check code.

[0130] The way in which the memory 200 executes step 406 is similar to the way in which the memory 200 executes step 403 , except that the data for which the check code needs to be generated is different, that is, the data in step 406 is uncompressed data, and the data in step 403 is compressed data.

[0131] Step 407: The memory 200 allocates a second physical address to the data and the second check code.

[0132] After the memory 200 obtains the data and generates the second check code, the memory 200 can execute storage of the data and the second check code. The embodiment of the present application does not limit the manner in which the memory 200 executes step 407. Similar to the manner in which the memory 200 executes step 404, the memory 200 can allocate a second physical address to the data and the second check code by any of the methods listed below.

[0133] Method 1: The memory 200 allocates a second physical address to the data and the second check code according to the wear status of each first area in the storage medium 220 .

[0134] Compared with the first check code, the data length of the second check code is smaller, and the error correction performance of the second check code is poor. When the memory 200 allocates the second physical address for the data and the second check code, it can select the second physical address in the first area with less wear (that is, better wear status) from the multiple first areas. The embodiment of the present application does not limit the manner in which the memory 200 selects the first area where the second physical address is located from the multiple first areas. For example, the memory 200 can select the first area with the least wear from the first area with free space, and allocate the second physical address for the data and the second check code from the first area.

[0135] Method 2: The memory 200 allocates second physical addresses to the data and the second check code according to the error rate range of each second area in the storage medium 220 .

[0136] When assigning the second physical address to the data and the second check code, the memory 200 may select a second physical address in a second region with a lower error rate range from the multiple second regions. The embodiment of the present application does not limit the manner in which the memory 200 selects the second region where the second physical address is located from the multiple second regions. For example, the memory 200 may select a second region with the lowest error rate range from among the second regions with free space, and assign the second physical address to the data and the second check code from this second region.

[0137] Method three: allocating a second physical address to the compressed data and the first check code according to the wear status of each area in the storage medium 220 and the error rate range of each area.

[0138] When allocating a second physical address to the data and the second check code, the memory 200 can select a first area with less wear from multiple second areas, such as selecting the first area with the least wear. After selecting the first area, if the first area includes one or more second areas (or partial areas in the second area), the memory 200 can further select a second area with a smaller error rate range (partial area in the second area) from the first area. For example, if the second area has the smallest error rate range, the memory 200 can allocate a second physical address to the data and the second check code from within the second area.

[0139] When the memory 200 assigns a second physical address to the data and the second check code, it may also select a second area with a smaller error rate range from multiple second areas. After selecting the second area, if the second area includes one or more first areas (or partial areas in the first area), the memory 200 may further select a first area (partial area in the first area) with better wear status (i.e., less wear) from the second area, and the memory 200 may assign a second physical address to the data and the second check code from the first area.

[0140] The embodiments of the present application do not limit the manner in which the memory 200 selects the second region where the first physical address is located from the plurality of second regions, nor the manner in which the memory 200 selects the first region where the first physical address is located from the plurality of first regions. Any manner in which the second physical addresses can be assigned to the data and the second check code in combination with the wear status of each first region in the storage medium 220 and the error rate range of each second region is applicable to the embodiments of the present application.

[0141] Step 408: The memory 200 stores the data and the second check code according to the second physical address, and records the mapping relationship between the second physical address and the logical address. The manner in which the memory 200 performs step 405 is similar to the manner in which the memory 200 performs step 408. For details, please refer to the above content and will not be repeated here.

[0142] Optionally, the memory 200 can set and store a second flag bit for the data, and the second flag bit is used to indicate that the stored data is not compressed. The embodiment of the present application does not limit the setting method of the second flag bit. For example, after generating the first check code, the memory 200 can add a second flag bit to the data to represent that the data is not compressed, and the data, the second check code and the second flag bit can be stored on the second physical address. For another example, when the memory 200 records the mapping relationship between the physical address (such as the second physical address) and the logical address, the memory 200 can add a second flag bit to the mapping relationship to indicate that the data is not compressed, and the second flag bit is stored in the mapping relationship.

[0143] Steps 403 to 405 describe the process of writing data to memory 200 after successful data compression, while steps 406 to 408 describe the process of writing data to memory 200 after unsuccessful data compression. As can be seen from the above steps, memory 200 provides two different data writing methods. For data whose compressed data meets the compression rate threshold, memory 200 can compress such data and generate a first checksum with better error correction performance based on the compressed data, ensuring that the data can be effectively corrected in the event of subsequent data errors. Memory 200 can also store the compressed data and the first checksum at a first physical address with a higher error rate or poor wear condition. Even if the data stored at the first physical address is faulty, the first checksum can still be used to correct errors. For data whose compressed data does not meet the compression rate threshold, memory 200 may not compress such data and instead directly generate a second checksum for the data. This data and the second checksum are then stored at a second physical address with a lower error rate or better wear condition, reducing the probability of errors in the data stored at the second physical address.

[0144] Step 409: The processor 100 sends a read request to the memory 200. The read request is used to request to read data, and the read request includes a logical address of the data.

[0145] Step 410 : After receiving the read request, the memory 200 reads the data according to the logical address of the data.

[0146] If the data is successfully compressed during writing, the memory 200 determines the first physical address based on the logical address of the data, reads the compressed data and the first check code from the first physical address, and can determine that the data was successfully compressed during writing by identifying the first flag bit set for the data. The compressed data is verified using the first check code. If the verification is successful, the memory 200 decompresses the compressed data. If the verification fails, the memory 200 uses the first check code to correct errors in the compressed data. If the error correction is successful, the corrected data is decompressed to obtain the data. If the error correction fails, the data read fails, and the memory 200 can notify the processor 100 of the data read failure.

[0147] If data compression fails during writing, the memory 200 determines a second physical address based on the logical address of the data, reads the data and the second check code from the second physical address, and can determine that the data was not compressed during writing by identifying the second flag bit set for the data. The memory 200 verifies the compressed data using the second check code. If the verification is successful, the memory 200 obtains the data and executes step 411. If the verification fails, the memory 200 corrects the data using the second check code. If the correction is successful, the corrected data is the data. If the correction fails, the data read fails, and the memory 200 can notify the processor 100 of the data read failure.

[0148] Step 411 : The memory 200 feeds back the data to the processor 100 .

[0149] Based on the same inventive concept as the method embodiment, the present application embodiment further provides a storage device for executing the memory execution method of the method embodiment shown in FIG5 . The relevant features can be found in the method embodiment described above and are not further described here. As shown in FIG5 , the storage device 500 includes a compression module 501, a first encoding module 502, a storage module 503, and a second encoding module 504.

[0150] The compression module 501 is configured to receive a write request sent by a processor, where the write request is used to request writing data, and compress the data.

[0151] The first encoding module 502 is configured to perform an ECC operation on the compressed data to generate a first check code.

[0152] The storage module 503 is configured to store the compressed data, a first check code, and a first flag bit in a storage medium, where the first flag bit is configured to indicate that the stored data has been compressed.

[0153] In one possible embodiment, the storage medium includes multiple first areas, and the storage module 503 determines the first area for storing compressed data and the first check code based on the wear status of the multiple first areas, and stores the compressed data, the first check code and the first mark bit in the determined first area.

[0154] In a possible implementation manner, the first area storing the compressed data, the first check code, and the first flag bit is the first area with the greatest wear among the first areas with free space.

[0155] In one possible embodiment, the storage medium includes multiple second areas, and the error rate ranges of different second areas are different. The storage module 503 determines the second area for storing compressed data and the first check code based on the error rate ranges of the multiple second areas, and stores the compressed data, the first check code and the first mark bit in the determined second area.

[0156] In a possible implementation manner, the second region storing the compressed data, the first check code, and the first flag bit is the first region with the largest error rate range among the second regions with free space.

[0157] In a possible implementation, the ratio of compressed data to data is less than or equal to a compression rate threshold.

[0158] In one possible implementation, if the ratio of the compressed data to the data is greater than the compression ratio threshold, the storage device further includes a second encoding module 504 that performs an ECC operation on the data to generate a second check code, wherein the length of the first check code is greater than the length of the second check code. The storage module 503 stores the data and the second check code.

[0159] In a possible implementation, when the storage module 503 stores data and the second check code, it stores the data, the second check code, and a second flag, where the second flag is used to indicate that the stored data is not compressed.

[0160] In one possible implementation, the compression module 501 receives a read request sent by the processor, where the read request is used to request to read data. The storage module 503 retrieves the compressed data and a first check code from the storage medium. The first encoding module 502 uses the first check code to verify or correct errors in the compressed data. After the first encoding module 502 successfully verifies or corrects the compressed data using the first check code, the compression module 501 decompresses the compressed data, retrieves data, and feeds it back to the processor.

[0161] It should be noted that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. The functional modules in the embodiments of the present application may be integrated into a single processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The integrated modules may be implemented in either hardware or software functional modules.

[0162] The above embodiments can be implemented in whole or in part through software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, hard disk, tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0163] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0164] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0165] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0166] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0167] Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations.

Claims

1. A data access method, characterized in that: include: The memory receives a write request sent by the processor, wherein the write request is used to request to write data; After compressing the data, the memory performs an ECC operation on the compressed data to generate a first check code, and stores the compressed data, the first check code and a first flag bit, where the first flag bit is used to indicate that the stored data has been compressed.

2. The method according to claim 1, characterized in that The storage medium of the memory includes a plurality of first areas, and the memory stores the compressed data and the first check code, including: The memory determines a first area for storing the compressed data and the first check code according to the wear status of the multiple first areas, and stores the compressed data, the first check code and the first mark bit in the determined first area.

3. The method according to claim 2, characterized in that The first area storing the compressed data, the first check code and the first mark bit is the first area with the most wear among the first areas with free space.

4. The method according to any one of claims 1 to 3, characterized in that: The storage medium of the memory includes a plurality of second areas, and different second areas have different error rate ranges. The memory stores the compressed data, the first check code, and the first flag bit, including: The memory determines a second area for storing the compressed data, the first check code and the first mark bit according to the error rate range of the multiple second areas, and stores the compressed data, the first check code and the first mark bit in the determined second area.

5. The method according to claim 4, characterized in that The second area storing the compressed data, the first check code and the first flag bit is the first area with the largest error rate range in the second area with free space.

6. The method according to any one of claims 1 to 5, characterized in that: The ratio of the compressed data to the data is less than or equal to a compression rate threshold.

7. The method according to claim 6, characterized in that If the ratio of the compressed data to the data is greater than the compression rate threshold, the method further includes: The memory performs an ECC operation on a second check code for the data, stores the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and stores the data and the second check code.

8. The method according to claim 7, characterized in that The memory stores the data and the second check code, and further includes: The memory stores the data, the second check code and a second marker, wherein the second marker is used to indicate that the stored data is not compressed.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: The memory receives a read request sent by the processor, where the read request is used to request to read the data; The memory acquires the compressed data and the first check code; After successfully verifying or correcting the compressed data using the first verification code, the memory decompresses the compressed data, obtains the data, and feeds it back to the processor.

10. A memory, characterized in that: The memory includes a controller and a storage medium; The storage medium is used to store data; The controller is used to receive a write request sent by the processor, wherein the write request is used to request writing data; after compressing the data, an ECC operation is performed on the compressed data to generate a first check code, and the compressed data, the first check code and a first mark bit are stored, wherein the first mark bit is used to indicate that the stored data has been compressed.

11. The memory according to claim 10, wherein: The storage medium includes a plurality of first areas, and the controller is configured to: The memory determines a first area for storing the compressed data and the first check code according to the wear status of the multiple first areas, and stores the compressed data, the first check code and the first mark bit in the determined first area.

12. The memory according to claim 11, wherein: The first area storing the compressed data, the first check code and the first mark bit is the first area with the most wear among the first areas with free space.

13. The memory according to any one of claims 10 to 12, characterized in that: The storage medium includes a plurality of second areas, and different second areas have different error rate ranges. The controller is used to: A second area for storing the compressed data, the first check code and the first mark bit is determined according to the error rate range of the multiple second areas, and the compressed data, the first check code and the first mark bit are stored in the determined second area.

14. The memory according to claim 13, wherein: The second area storing the compressed data, the first check code and the first flag bit is the first area with the largest error rate range in the second area with free space.

15. The memory according to any one of claims 10 to 14, characterized in that: The ratio of the compressed data to the data is less than or equal to a compression rate threshold.

16. The memory according to claim 15, wherein: If the ratio of the compressed data to the data is greater than the compression rate threshold, the controller is further configured to: An ECC operation is performed on the data to generate a second check code, and the data and the second check code are stored, wherein the length of the first check code is greater than the length of the second check code, and the data and the second check code are stored.

17. The memory according to claim 16, wherein: The controller is used to: The data, the second check code and a second marker are stored, wherein the second marker is used to indicate that the stored data is not compressed.

18. The memory according to any one of claims 10 to 17, characterized in that: The controller is further used for: receiving a read request sent by the processor, wherein the read request is used to request to read the data; Acquire the compressed data and the first check code from the storage medium; After the compressed data is successfully verified or error-corrected using the first verification code, the compressed data is decompressed, and the data is acquired and fed back to the processor.

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