Pixel circuit and image sensor

Abstract

A pixel circuit (100) comprises a floating diffusion (102) configured to be connected to a photosensitive element (11), the photosensitive element (11) being configured to generate charges in response to incident radiation (15). The pixel circuit (100) further comprises a reset transistor (105) connected to the floating diffusion (102) for resetting the floating diffusion (102) to a predetermined voltage. The pixel circuit (100) further comprises a capacitor arrangement (120) comprising capacitors (121, 123) for storing charges and a first transistor (110). A gate electrode (111) of the first transistor (110) is electrically connected to the floating diffusion (102), and a source region (112) of the first transistor (110) is electrically connected to the capacitor arrangement (120). The pixel circuit further comprises a switch (130) for electrically connecting a drain region (113) of the first transistor (110) to a supply voltage.

Description

[0001] PIXEL CIRCUIT AND IMAGE SENSOR

[0002] Voltage domain global shutter image sensors are used in a variety of applications , including e . g . machine vision applications . Due their fast read out , their low parasitic light sensitivity ( PLS ) and the possibility of pipelining integration and read out , these image sensors are increasingly employed .

[0003] Generally, attempts are being made to improve the performance of these image sensors .

[0004] It is an obj ect of the present invention to provide an improved pixel circuit and improved image sensor .

[0005] According to embodiments , the above obj ects are achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0006] According to embodiments , a pixel circuit comprises a floating di f fusion configured to be connected to a photosensitive element , the photosensitive element being configured to generate charges in response to incident radiation . The pixel circuit further comprises a reset transistor connected to the floating di f fusion for resetting the floating di f fusion to a predetermined voltage . The pixel circuit further comprises a capacitor arrangement comprising capacitors for storing charges and a first transistor . A gate electrode of the first transistor is electrically connected to the floating di f fusion and a source region of the first transistor is electrically connected to the capacitor arrangement . The pixel circuit further comprises a switch for electrically connecting a drain region of the first transistor to a supply voltage . Due to the presence of the switch, the drain region of the first transistor may be selectively electrically connected to or disconnected from the supply voltage .

[0007] For example , the switch may comprise a first switching transistor configured to connect the drain region of the first transi stor to VH . A terminal of the first switching transistor may be connected to a node that is connected to the drain region of the first transistor .

[0008] According to embodiments , the switch may further comprise a second switching transistor that is configured to connect the drain region of the first transi stor to VL . A terminal of the second switching transistor may be connected to the node .

[0009] For example , the pixel circuit may be configured to discharge the capacitors of the capacitor arrangement while electrically connecting the drain region of the first transistor to VL .

[0010] According to embodiments , the node may be further connected to a drain terminal of the reset transistor .

[0011] For example , an output of the capacitor arrangement may be connected to the gate electrode of a second transistor . A first terminal of the second transistor may be connectable to a column output .

[0012] For example , the node is connected to a second terminal of the second transistor .

[0013] According to embodiments , a selection transistor may be disconnected from the first terminal of the second transistor . According to further embodiments , the pixel circuit may further comprise a selection transistor connected to the first terminal of the second transistor .

[0014] According to embodiments , the pixel circuit may further comprise a precharge transistor electrically connected to the source region of the first transistor .

[0015] According to further embodiments , a precharge transistor may be disconnected from the source region of the first transistor .

[0016] For example , the capacitor arrangement may comprise a first and a second capacitor, connected in parallel .

[0017] By way of example , the capacitor arrangement further comprises a first sampling transistor and a second sampling transistor . A node that is connected to the first and second sampling transistors is connected to the first capacitor . A further node that is connected to the second sampling transistor is connected to the second capacitor .

[0018] According to further embodiments , the first sampling transistor may be connected in series with the first capacitor, and the second sampling transistor may be connected in series with the second capacitor . A third transistor may be connected to a node connected to the first sampling transistor .

[0019] An image sensor comprises an array of pixels , each of the pixel s comprising a photosensitive element , and a pixel circuit . At least one of the pixel circuits comprises a floating di f fusion configured to be connected to the photosensitive element , the photosensitive element being configured to generate charges in response to incident radiation . The pixel circuit further comprises a reset transistor connected to the floating di f fusion for resetting the floating di f fusion to a predetermined voltage and a first transistor . A gate electrode of the first transistor is electrically connected to the floating di f fusion, and a source region of the first transistor is electrically connected to a capacitor arrangement for storing charges . The pixel circuit further comprises a switch for electrically connecting a drain region of the first transistor of at least one of the pixel circuits to a supply voltage .

[0020] For example , the switch may be shared between pixels .

[0021] According to embodiments , the switch is shared between columns of pixels , between all pixels , or between pixels in di f ferent layers .

[0022] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

[0023] Fig . 1A shows an example of an equivalent circuit diagram of a pixel circuit according to embodiments .

[0024] Fig . IB shows a timing for sampling global shutter signals when operating the pixel circuit illustrated e . g . in Fig . 1A. Fig . 1C shows an example of a timing for sampling global shutter signals when operating the pixel circuit illustrated e . g . in Fig . 1A.

[0025] Fig . ID shows an equivalent circuit diagram of a pixel circuit according to further embodiments .

[0026] Fig . 2 shows an equivalent circuit diagram of a pixel circuit according to further embodiments .

[0027] Figs . 3A to 3B show further examples of equivalent circuit diagrams of a pixel circuit .

[0028] Figs . 4A to 4B show equivalent circuit diagrams of pixel circuits according to further embodiments .

[0029] Figs . 5A to 5C show equivalent circuit diagrams of a pixel circuit according to further embodiments .

[0030] Fig . 6 shows an equivalent circuit diagram of a pixel circuit according to further embodiments .

[0031] Fig . 7 shows an equivalent circuit diagram of a pixel circuit according to further embodiments .

[0032] Fig . 8 shows a portion of an array of pixel circuits that may be a component of an image sensor according to embodiments .

[0033] Fig . 9 shows an example of an image sensor according to embodiments .

[0034] In the following detailed description reference is made to the accompanying drawings , which form a part hereof and in which are illustrated by way of illustration speci fic embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0035] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0036] The pixel circuit 100 of Fig. 1A comprises a floating diffusion 102 that is configured to be connected to a photosensitive element 11. The photosensitive element 11 is configured to generate charges in response to incident radiation 15.

[0037] For example, the photosensitive element 11 may comprise a photodiode or any other suitable photosensitive element. The floating diffusion 102 may be connected to the photosensitive element 11 e.g. via a transfer transistor 107. The transfer transistor 107 may also be a component of the pixel circuit 100. According to implementations, the floating diffusion 102 may be implemented as a capacitor and may implement a sense node. For example, charges generated by the photosensitive element 11 due to irradiation with incident radiation 15 may be transferred to the floating diffusion 102.

[0038] The pixel circuit 100 further comprises a reset transistor 105 which is connected to the floating diffusion 102. The reset transistor 105 is configured to reset the floating di f fusion 102 to a predetermined voltage .

[0039] The pixel circuit 100 further comprises a first transistor 110 . A gate electrode 111 of the first transistor 110 is electrically connected to the floating di f fusion 102 . The source region 112 of the first transistor 110 is electrically connected to a capacitor arrangement 120 for storing charges . The first transistor 110 implements a source follower, e . g . a source follower 1 . The source region 112 of the first transistor 110 is electrically connected to the capacitor arrangement 120 via a transistor . For example , thi s transi stor may be the first sampling transistor 122 which wil l be explained in more detail below . According to further embodiments , this transistor may by the third transistor 125 which will be explained in more detail below with reference to Fig . 6 .

[0040] The pixel circuit 100 further comprises a switch 130 for electrically connecting a drain region 113 of the first transistor 110 to a supply voltage e . g . VH or VDD .

[0041] As is illustrated in Fig . 1A, the switch 130 may comprise a first switching transistor 131 which is configured to connect the drain region 113 of the first trans istor 110 to VH . A terminal of the first switching transistor 131 is connected to a node 133 which is connected to the drain region 113 of the first transistor 110 . Another terminal of the first switching transistor 131 is connected to VH . The switch 130 may further comprise a second switching trans istor 132 which is configured to connect the drain region 113 of the first transistor 110 to VL, e . g . a reference voltage or GND . A terminal of the second switching transistor 132 is connected to the node 133 . Another terminal of the second switching transistor 132 is connected to VL . As is further illustrated in Fig . 1A, the pixel circuit 100 may further comprise a precharge transistor 116 . A source region 117 of the precharge transistor 116 may be connected to VL . According to all embodiments disclosed herein, the VL at the terminal connected to the source region 117 of the precharge transistor 116 does not need to be necessarily the same as the VL at the terminal of the second switching transistor 132 . A drain region of the precharge transistor 116 is connected to a node 118 which connected to the source region 112 of the first transistor 110 and further to the capacitor arrangement 120 . The precharge transistor 116 is biased to discharge the capacitor arrangement 120 . As a result , the correct voltages on the capacitors of the capacitor arrangement 120 are sampled . Due to the presence of the switch 130 , the first transistor 110 is pulled low or floating when the precharge transistor 116 is active . In more detail , the switch 130 cuts the connection to the high supply voltage . Hence , the DC current path for the precharge transistor 116 current is cut .

[0042] As a consequence , the discharge of the capacitor may be accelerated and the current needed to perform this precharge operation is reduced . Accordingly, the ef ficiency of the precharge operation is increased . Further, the discharge of the capacitors is less sensitive to mismatch of the precharge transistor 116 among the pixel circuits 100 in the image sensor . The maximum discharge current to VL may be controlled by controlling the high voltage on the gate electrode of the second switching transistor 132 implementing a current source .

[0043] The capacitor arrangement 120 may comprise a first capacitor 121 and a second capacitor 123 . For example , the capacitor arrangement 120 may further comprises a first sampling transistor 122 which is arranged between the node 118 and a further node that is connected to the first capacitor 121. Moreover, a second sampling transistor 124 may be arranged between the node that is connected to the first capacitor 121 and a further node that is connected to the second capacitor 123. An output of the capacitor arrangement 120 may be electrically connected to a gate electrode 134 of a second transistor 135. A source region 136 of the second transistor 135 may be electrically connected to the column output 16, e.g. via a selection transistor 138. A drain region of the second transistor 135 may be electrically connected to VH.

[0044] For example, the second transistor 135 may implement a second source follower, e.g. source follower 2. The selection transistor 138 may be arranged between the second transistor 135 and the column output 16. For example, a source region 139 of the selection transistor 138 may be electrically connected to the source region 136 of the second transistor 135. A drain region 140 of the selection transistor 138 may be electrically connected to the column output 16. The gate electrode of the selection transistor 138 may be supplied with a selection signal .

[0045] Fig. IB shows waveforms of signals supplied to the single transistors during different phases of a sampling global shutter signal. In Fig. IB S100 denotes the reset of the floating diffusion 102, S110 denotes a reset of the capacitors 121 and 123 and S120 denotes the reset sampling process. Moreover, S130 denotes the transfer process, S140 denotes the reset of the first capacitor 121, and S150 denotes the signal sampling process.

[0046] Between S100 and S110, the reset transistor 105 is switched off, thus releasing the floating diffusion 102 from resetting. As a result, a reset noise is preserved in the floating diffusion 102.

[0047] From S100 to S150, the first sampling transistor 122 is switched on. Further, during phases S100, S110, and S120, the second sampling transistor 124 is switched on. Hence, the reset level is sampled on both capacitors 121 and 123. Further, after sampling, the second sampling transistor 124 is switched off and the reset level remains stored on the second capacitor 123.

[0048] Then the generated electrons are transferred from the photosensitive element 11 to the floating diffusion 102 by switching on the transfer transistor 107. During the complete transfer process, the first sampling transistor 122 is still switched on. Accordingly, the light signal which is converted in the floating diffusion 102 is also sampled on the first capacitor 121.

[0049] After signal sampling (S150) , the first sampling transistor 122 is turned off so that the light signal is preserved on the first capacitor 121. The pixel is ready for the start of the integration of the next frame. During integration, the floating diffusion 102 remains in the reset state, and the transfer gate can act as an anti-blooming drain.

[0050] As is further shown in Fig. IB, during discharge of the capacitors 121 and 123, the first switching transistor 131 is switched off, whereas the second switching transistor 132 is switched on. Accordingly, the drain region 113 of the first transistor 110 is connected to VL . As a result, there is no direct path from the capacitor arrangement 120 to the supply voltage. As a consequence, the current needed to perform the discharge operation is reduced.

[0051] Figure 1C shows waveforms of signals during read RST S210 and read SIG S220. As is shown during S210 and S220, the selection transistor 138 is switched on so that the reset level which is stored in the second capacitor 123, is read out first. Afterwards, between S 210 and S 220, the second sampling transistor 124 is switched on to short the first and the second capacitors 121, 123. Accordingly, the photosignal stored on the first capacitor 121, is attenuated by half if the first capacitor 121 has the same capacitance as the second capacitor 123. Afterwards, the attenuated signal is read out as the light signal. During these processes, the first switching transistor 131 is switched on whereas the second switching transistor 132 is switched off. Accordingly, during the processes S200 (previous row) to S230 (next row) , the drain region 113 of the first transistor 110 is connected to high voltage level (VH) as is conventional.

[0052] Fig. ID shows a further example of the pixel circuit 100. The elements illustrated in Fig. ID are similar to those illustrated in Fig. 1A. Differing from embodiments illustrated in Fig. 1A, the switch 130 comprises one single first transistor 131 which is connected to VH. The functionality of the pixel circuit 100 illustrated in Fig. ID is similar to the functionality of the pixel circuit 100 illustrated in Fig. 1A, since due to the presence of the switch 130 the drain region of the first transistor 110 is only temporarily connected to VH.

[0053] Fig. 2 shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. As is shown in Fig. 2, elements of the pixel circuit 100 are similar or identical to those illustrated in Fig. 1A. Differing from embodiments illustrated in Fig. 1A, the precharge transistor 116 is dispensed with. Accordingly, a precharge transistor 116 is disconnected from the pixel circuit 100. According to embodiments illustrated in Fig. 2, the first transistor 110 may be operable to act as a precharge transistor for precharging the capacitor arrangement 120. Accordingly, the number of transistors needed is reduced in comparison to a pixel circuit as e.g. illustrated in Fig. 1A.

[0054] The pixel circuit 100 of Fig. 2 may also be implemented comprising a different switch 130, e.g. the switch 130 illustrated in Fig. ID.

[0055] Fig. 3A shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 3A are similar to those illustrated in Fig. ID. As is shown, differing from embodiments illustrated in Fig. ID, the node 133 is connected to a drain region of the reset transistor 105. Since the reset transistor 105 and the first transistor 110 are arranged very close to each other in layout, this may result in a significant layout advantage.

[0056] Fig. 3B shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 3B are similar to those illustrated in Fig. 1A. Differing from embodiments illustrated e.g. in Fig. 1A, the node 133 that is connected to the first and second switching transistors 131, 132 is connected to the drain of the reset transistor 105.

[0057] Fig. 4A shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 4A are similar to those illustrated in Fig. 1A. Differing from embodiments illustrated in Fig. 1A, the switch 130 and the node 133 are electrically connected to the drain region of the second transistor 135. In this way, the supply layout may be simplified.

[0058] Fig. 4B shows an equivalent circuit diagram of a pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 4B are similar to those illustrated in Fig 1A. As is shown, differing from embodiments illustrated in

[0059] Fig 1A, the node 133 is connected to the drain region 137 of the second transistor 135.

[0060] Fig. 5A shows an example of an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 5A are similar to those illustrated in Fig. 3B. As is shown, differing from embodiments illustrated e.g. in Fig. 3B, the node 133 is connected to the drain region 137 of the second transistor 135. Further, the node 133 is also connected to the drain region of the reset transistor 105. In this way, the supply layout may be simplified.

[0061] Fig. 5B shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. The elements illustrated in Fig. 5B are similar to those illustrated in Fig. ID. As is shown, differing from embodiments illustrated e.g. in Fig. ID, the node 133 is connected to the drain region of the reset transistor 105 and additionally to the drain region 137 of the second transistor 135.

[0062] Fig. 5C shows an equivalent circuit diagram of the pixel circuit 100 according to further embodiments. As is shown, the pixel circuit 100 is similar the pixel circuit illustrated in Fig. 5A. Differing from embodiments illustrated in Fig. 5A, the precharge transistor 116 is disconnected from the pixel circuit 100. As is clearly to be understood, the switch 130 may also be implemented in an alternative manner e.g. as illustrated in Fig. 5B .

[0063] Fig. 6 further shows an alternative implementation of the capacitor arrangement 120. As is shown, the capacitor arrangement 120 as illustrated in Fig. 6 comprises a first capacitor 121 which is connected in series with the first sampling transistor 122. Further, the capacitor arrangement 120 comprises a second capacitor 123 which is connected in series with the second sampling transistor 124. A node that is connected to the arrangement of the capacitor 121 and the first sampling transistor 122, is connected to the source of the first transistor 110 via a third transistor 125. The node that is connected to the first capacitor 121 and the first sampling transistor 122 is connected to a further node through the second sampling transistor 124. This further node is connected to the gate electrode 134 of the second transistor 135. The node is further connected to the arrangement of the second capacitor 123 and the second sampling transistor 124. This specific capacitor arrangement 120 may be applied to all embodiments described herein .

[0064] Fig. 7 shows a further example of the pixel circuit 100. Elements of the pixel circuit 100 are similar to the pixel circuit 100 shown in e.g. Fig. 6. As is shown, differing from embodiments illustrated in Fig. 6, a selection transistor 138 is disconnected from the pixel circuit 100. According to these embodiments, a toggling of the signal applied to the drain region 137 of the second transistor 135 may be used for triggering a connection of the second transistor 135 to the column output 16. The toggling may be induced by the special signals that are supplied by the switch 130. Accordingly, a selection transistor 138 may be dispensed with. As a consequence, further transistors may be saved.

[0065] Fig. 8 shows an example of a configuration of an array of pixels 10, when the switch 130 is shared among different pixels 10. The pixel circuit 100 comprises the switch 130 which may be implemented as e.g. illustrated in Fig. 1A or ID. As is indicated in Fig. 8, according to embodiments, the switch 130 may be shared by further pixels 10. For example, a node 133 connected to the drain region 113 of the first transistor 110 may be connectable to the switch 130 . For example , the pixels 10 sharing the switch may be arranged in a row or may be arranged in di f ferent pixel layers .

[0066] Fig . 9 shows a schematic diagram of an image sensor 20 . The image sensor 20 comprises an array of pixels 10 . To be more speci fic, each of the pixels 10 of the array of pixels comprises a photosensitive element (not shown in Fig . 9 ) and a pixel circuit 100 . Each of the pixel circuits 100 may be implemented in the manner as has been described above . According to embodiments , as has been described with reference to Fig . 8 , the switch 130 may be shared among pixels . The image sensor 20 may further comprise a row selection line drive 150 for selecting a line to be read out and a controller 151 . The controller 151 may e . g . be configured to generate the signals illustrated in Figs . IB and 1C . The image sensor may further comprise a column processing device 152 and a pixel data proces sing device 153 . As a result of the processing, image data 17 may be output .

[0067] As has been described, due to the presence of the switch, the sensitivity of the image sensor to mismatch of precharge transistors among di f ferent pixels may be reduced . Further, according to embodiments , the number of transistors may be reduced while maintaining the performance and speed . Since a reduced pixel pitch deteriorates transistor matching, the present invention may be speci fically applied to image sensors having a reduced pixel si ze . As a result , speed and power may be increased and a good image quality may be maintained .

[0068] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .

[0069] LIST OF REFERENCES pixel photosensitive element incident radiation column output image data image sensor pixel circuit floating di f fusion reset transistor trans fer transistor first transistor gate electrode source region drain region precharge transistor source region node capacitor arrangement first capacitor first sampling transistor second capacitor second sampling transistor third transistor switch first switching transistor second switching transistor node gate electrode second transistor source region drain region selection transistor source region 140 drain region

[0070] 150 row selection line driver

[0071] 151 controller

[0072] 152 column processing device 153 pixel data processing device

Claims

CLAIMS1. A pixel circuit (100) comprising: a floating diffusion (102) configured to be connected to a photosensitive element (11) , the photosensitive element (11) being configured to generate charges in response to incident radiation (15) ; a reset transistor (105) connected to the floating diffusion (102) for resetting the floating diffusion (102) to a predetermined voltage; a capacitor arrangement (120) comprising capacitors (121, 123) for storing charges; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) ; a source region (112) of the first transistor (110) being electrically connected to the capacitor arrangement (120) via a transistor (122, 125) , and a switch (130) for electrically connecting a drain region (113) of the first transistor (110) to a supply voltage .

2. The pixel circuit (100) according to claim 1, wherein the switch (130) comprises a first switching transistor (131) configured to connect the drain region (113) of the first transistor (110) to VH, a terminal of the first switching transistor (131) being connected to a node (133) that is connected to the drain region (113) of the first transistor (110) .

3. The pixel circuit (100) according to claim 2, wherein the switch (130) further comprises a second switching transistor (132) configured to connect the drain region (113)of the first transistor (110) to VL, a terminal of the second switching transistor (132) being connected to the node (133) .

4. The pixel circuit (100) according to claim 3, being configured to discharge the capacitors (121, 123) of the capacitor arrangement (120) while electrically connecting the drain region (113) of the first transistor (110) to VL .

5. The pixel circuit (100) according to any of claims 2 to 4, wherein the node (133) is further connected to a drain terminal of the reset transistor (105) .

6. The pixel circuit (100) according to any of the preceding claims, wherein an output of the capacitor arrangement (120) is connected to the gate electrode (134) of a second transistor (135) , a first terminal (136) of the second transistor (135) being connectable to a column output (16) .

7. The pixel circuit (100) according to claim 6, wherein the node (133) is connected to a second terminal (137) of the second transistor (135) .

8. The pixel circuit (100) according to claim 7, wherein a selection transistor (138) is disconnected from the first terminal (136) of the second transistor (135) .

9. The pixel circuit (100) according to any of claims 1 to 7, further comprising a selection transistor (138) connected to the first terminal (136) of the second transistor (135) .

10. The pixel circuit (100) according to any of the preceding claims, further comprising a precharge transistor(116) electrically connected to the source region (112) of the first transistor (110) .

11. The pixel circuit (100) according to any of claims 1 to 9, wherein a precharge transistor (116) is disconnected from the source region (112) of the first transistor (110) .

12. The pixel circuit (100) according to any of the preceding claims, wherein the capacitor arrangement (120) comprises a first and a second capacitor (121, 123) , connected in parallel.

13. The pixel circuit (100) according to claim 12, wherein the capacitor arrangement (120) further comprises a first sampling transistor (122) and a second sampling transistor (124) , a node connected to the first and second sampling transistors (122, 124) being connected to the first capacitor (121) , a further node connected to the second sampling transistor (124) being connected to the second capacitor (123) .

14. The pixel circuit (100) according to claim 12, wherein the capacitor arrangement (120) further comprises a first sampling transistor (122) connected in series with the first capacitor (121) , a second sampling transistor (124) connected in series with the second capacitor (123) and a third transistor (125) connected to a node connected to the first sampling transistor (122) .

15. An image sensor (20) comprising: an array of pixels (10) , each of the pixels comprising: a photosensitive element (11) , and a pixel circuit (100) , at least one of the pixel circuits (100) comprising:a floating diffusion (102) configured to be connected to the photosensitive element (11) , the photosensitive element(11) being configured to generate charges in response to incident radiation (15) ; a reset transistor (105) connected to the floating diffusion (102) for resetting the floating diffusion (102) to a predetermined voltage; a capacitor arrangement (120) comprising capacitors (121, 123) for storing charges; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) , a source region (112) of the first transistor (110) being electrically connected to the capacitor arrangement (120) via a transistor (122, 125) , and a switch (130) for electrically connecting a drain region (113) of the first transistor (110) of at least one of the pixel circuits (100) to a supply voltage.

16. The image sensor (20) according to claim 15, wherein the switch (130) is shared between pixels (10) .

17. The image sensor (20) according to claim 15, wherein the switch (130) is shared between columns of pixels (10) .

18. The image sensor (20) according to claim 15, wherein the switch (130) is shared between all pixels (10) .

19. The image sensor (20) according to claim 15, wherein the switch (130) is shared between pixels (10) in different layers .

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