Semiconductor device and electronic equipment

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a first substrate having first pixels that include light-receiving units and second pixels that include light-guiding units; and a second substrate stacked on the first substrate, the second substrate having transistor units that are disposed facing the first pixels and drive the first pixels, and light-emitting units that are disposed facing the second pixels.

Description

Semiconductor devices and electronic devices

[0001] The present disclosure relates to a semiconductor device and an electronic device that include both a light receiving element and a light emitting element.

[0002] For example, Patent Document 1 discloses a semiconductor device in which a light receiving element and a light emitting element are provided on the same substrate.

[0003] Japanese Patent Application Laid-Open No. 2018-174246

[0004] In a semiconductor device having both a light-emitting portion and a light-receiving portion, there is a demand for higher illuminance of the light-emitting portion and an enlargement of the light-receiving portion.

[0005] It is desirable to provide a semiconductor device and electronic equipment that can realize high illuminance of the light emitting portion and enlargement of the light receiving portion in a device that has both a light emitting portion and a light receiving portion.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a first substrate having a first pixel including a light receiving portion and a second pixel including a light guiding portion, and a second substrate stacked on the first substrate and having a transistor portion arranged opposite the first pixel for driving the first pixel and a light emitting portion arranged opposite the second pixel.

[0007] An electronic device according to an embodiment of the present disclosure includes a semiconductor device, and includes the semiconductor device according to the embodiment of the present disclosure as the semiconductor device.

[0008] In the semiconductor device and electronic device according to an embodiment of the present disclosure, the light-emitting section is provided on a first substrate, the light-receiving section is provided on a second substrate, and the first and second substrates are stacked together, thereby enabling the light-receiving section to be enlarged while forming a light-emitting element with higher illuminance than when the light-emitting section and the light-receiving section are arranged in parallel on the same substrate.

[0009] FIG. 1 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically illustrating an example of a planar configuration of the semiconductor device illustrated in FIG. 1. FIG. 3 is an equivalent circuit diagram of a sensor pixel illustrated in FIG. 1. FIG. 4A is a cross-sectional view schematically illustrating an example of a manufacturing process of the semiconductor device illustrated in FIG. 1. FIG. 4B is a cross-sectional view schematically illustrating a process subsequent to FIG. 4A. FIG. 4C is a cross-sectional view schematically illustrating a process subsequent to FIG. 4B. FIG. 4D is a cross-sectional view schematically illustrating a process subsequent to FIG. 4C. FIG. 4E is a cross-sectional view schematically illustrating a process subsequent to FIG. 4D. FIG. 4F is a cross-sectional view schematically illustrating a process subsequent to FIG. 4E. FIG. 4G is a cross-sectional view schematically illustrating a process subsequent to FIG. 4F. FIG. 4H is a cross-sectional view schematically illustrating a process subsequent to FIG. 4G. FIG. 4I is a cross-sectional view schematically illustrating a process subsequent to FIG. 4H. FIG. 4J is a cross-sectional view schematically illustrating a process subsequent to FIG. 4I. FIG. 4K is a cross-sectional view schematically illustrating a process subsequent to FIG. 4J. FIG. 5A is a cross-sectional view schematically illustrating a process subsequent to FIG. 4K. FIG. 5B is a schematic cross-sectional view showing a step subsequent to FIG. 5A. FIG. 5C is a schematic cross-sectional view showing a step subsequent to FIG. 5B. FIG. 5D is a schematic cross-sectional view showing a step subsequent to FIG. 5C. FIG. 5E is a schematic cross-sectional view showing a step subsequent to FIG. 5D. FIG. 5F is a schematic cross-sectional view showing a step subsequent to FIG. 5E. FIG. 5G is a schematic cross-sectional view showing a step subsequent to FIG. 5F. FIG. 5H is a schematic cross-sectional view showing a step subsequent to FIG. 5G. FIG. 6A is a schematic cross-sectional view showing a step subsequent to FIG. 5G. FIG. 6B is a schematic cross-sectional view showing a step subsequent to FIG. 6A. FIG. 6C is a schematic cross-sectional view showing a step subsequent to FIG. 6B. FIG. 6D is a schematic cross-sectional view showing a step subsequent to FIG. 6C. FIG. 6E is a schematic cross-sectional view showing a step subsequent to FIG. 6D. FIG. 6F is a schematic cross-sectional view showing a step subsequent to FIG. 6E. FIG. 6G is a schematic cross-sectional view showing a step subsequent to FIG. 6F. FIG. 6H is a schematic cross-sectional view showing a step subsequent to FIG. 6G. Fig. 6I is a schematic cross-sectional view showing a step subsequent to Fig. 6H. Fig. 6J is a schematic cross-sectional view showing a step subsequent to Fig. 6I. Fig. 6K is a schematic cross-sectional view showing a step subsequent to Fig. 6J. Fig. 6L is a schematic cross-sectional view showing a step subsequent to Fig. 4K. Fig. 6M is a schematic cross-sectional view showing a step subsequent to Fig. 6L. Fig. 6N is a schematic cross-sectional view showing a step subsequent to Fig. 6M. Fig. 6O is a schematic cross-sectional view showing a step subsequent to Fig. 6N. Fig. 6P is a schematic cross-sectional view showing a step subsequent to Fig. 6O.6Q is a schematic cross-sectional view showing a step subsequent to FIG. 6P. FIG. 6R is a schematic cross-sectional view showing a step subsequent to FIG. 6Q. FIG. 6S is a schematic cross-sectional view showing a step subsequent to FIG. 6R. FIG. 6T is a schematic cross-sectional view showing a step subsequent to FIG. 6S. FIG. 6U is a schematic cross-sectional view showing a step subsequent to FIG. 6T. FIG. 6V is a schematic cross-sectional view showing a step subsequent to FIG. 6U. FIG. 6W is a schematic cross-sectional view showing a step subsequent to FIG. 6V. FIG. 6X is a schematic cross-sectional view showing a step subsequent to FIG. 6W. FIG. 7 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to a modified example of the present disclosure. FIG. 8 is a schematic view showing an example of the planar configuration of the semiconductor device shown in FIG. 7. FIG. 9 is a block diagram showing an example of the configuration of an electronic device to which the present technology is applied. FIG. 10 is an explanatory diagram showing an example of use of the semiconductor device. FIG. 11 is a schematic view showing an example of application of the semiconductor device of the present disclosure to the mobile device shown in FIG. 10. FIG. 12 is a schematic view showing another example of application of the semiconductor device of the present disclosure to the mobile device shown in FIG. 10. Fig. 13 is a schematic diagram showing another example of application of the semiconductor device of the present disclosure to the mobile device shown in Fig. 10. Fig. 14 is a schematic diagram showing another example of application of the semiconductor device of the present disclosure to the mobile device shown in Fig. 10.

[0010] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows: 1. Embodiment (Example of a semiconductor device including both a light-emitting element and a light-receiving element, in which the light-emitting element and the light-receiving element are provided on different substrates) 1-1. Configuration of the semiconductor device 1-2. Method for manufacturing the semiconductor device 1-3. Actions and effects 2. Modified examples (other examples of the configuration of the semiconductor device) 3. Application examples 4. Usage examples of the semiconductor device

[0011] 1. Embodiment Fig. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present disclosure. Fig. 2 is a schematic diagram illustrating an example of a planar configuration of the semiconductor device 1 illustrated in Fig. 1, and Fig. 1 is a cross-sectional view corresponding to line II' illustrated in Fig. 2. The semiconductor device 1 can be suitably used for a so-called notch display mounted on an electronic device such as a mobile device (see, for example, Fig. 11) having an imaging function, which will be described later.

[0012] The semiconductor device 1 is formed by stacking a first substrate 10 including a light-receiving element 11 and a wavelength conversion layer 16 and a second substrate 20 including a light-emitting element 21 and a pixel transistor 22 that drives the light-receiving element 11. The semiconductor device 1 has a plurality of pixels arranged in a two-dimensional array, and each pixel is provided with a light-receiving element 11 and a pixel transistor 22 or a wavelength conversion layer 16 and a light-emitting element 21. In other words, in the semiconductor device 1 of this embodiment, the light-receiving element 11 and the light-emitting element 21 are provided on different substrates (the first substrate 10 or the second substrate 20), and the light-receiving element 11 and the pixel transistor 22, and the wavelength conversion layer 16 and the light-emitting element 21 are arranged facing each other, respectively.

[0013] Here, the first substrate 10 corresponds to a specific example of a "first substrate" in an embodiment of the present disclosure, and the second substrate 20 corresponds to a specific example of a "second substrate" in an embodiment of the present disclosure. The light-receiving element 11 corresponds to a specific example of a "light-receiving section" in an embodiment of the present disclosure, and the wavelength conversion layer 16 corresponds to a specific example of a "light-guiding section" in an embodiment of the present disclosure. The light-emitting element 21 corresponds to a specific example of a "light-emitting section" in an embodiment of the present disclosure, and the pixel transistor 22 corresponds to a specific example of a "transistor section" in an embodiment of the present disclosure.

[0014] (1-1. Configuration of Semiconductor Device) The semiconductor device 1 includes a first substrate 10 on which a light-receiving element 11 and a wavelength conversion layer 16 are provided, a second substrate 20 on which a light-emitting element 21 and a pixel transistor 22 are provided, and a third substrate 30 on which a drive circuit for controlling the driving of the light-receiving element 11 and the light-emitting element 21 is provided, stacked in this order from the display surface S1 side. For convenience, the display surface S1 side of the semiconductor device 1 may be referred to as the "top," "upper side," or "upper" and the opposite side from the display surface S1 side may be referred to as the "bottom," "lower side," or "below." In the semiconductor device 1, the pixel transistor 22 is provided below the light-receiving element 11, and the wavelength conversion layer 16 is provided above the light-emitting element 21. As described above, the semiconductor device 1 has a plurality of pixels arranged in a two-dimensional array. Each pixel includes a light-receiving element 11 and a pixel transistor 22, or a wavelength conversion layer 16 and a light-emitting element 21, which are arranged opposite each other, and constitutes a sensor pixel P1 and a display pixel P2, respectively. As shown in FIG. 2, the plurality of sensor pixels P1 and the plurality of display pixels P2 are arranged alternately in the row direction (for example, the Y-axis direction) and the column direction (for example, the X-axis direction).

[0015] Here, the sensor pixel P1 corresponds to a specific example of a "first pixel" in the embodiment of the present disclosure, and the display pixel P2 corresponds to a specific example of a "second pixel" in the embodiment of the present disclosure.

[0016] The first substrate 10 includes a semiconductor layer 100S having a pair of opposing surfaces (surfaces 100S1 and 100S2) and a wiring layer 100T. The semiconductor layer 100S is formed, for example, from a silicon (Si) substrate. The semiconductor layer 100S has, for example, a p-well 111 near the surface 100S1 and an n-type semiconductor region 112 in the remaining region. A p-n junction photodiode PD composed of the p-well 111 and the n-type semiconductor region 112 is embedded in the semiconductor layer 100S as the light receiving element 11 for each sensor pixel P1. The photodiode PD photoelectrically converts incident light and generates an electric charge according to the amount of light received.

[0017] A floating diffusion FD and a transfer transistor TR are further provided for each sensor pixel P1 on the surface 100S1 of the semiconductor layer 100S.

[0018] The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-to-voltage conversion means that generates a voltage according to the amount of charge. The floating diffusion FD is made of an n-type semiconductor region (not shown) provided in the p-well 111.

[0019] The transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion facing the surface 100S1 of the semiconductor layer 100S and a vertical portion provided within the semiconductor layer 100S. The vertical portion extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion contacts the horizontal portion, and the other end is provided within the n-type semiconductor region 112 that constitutes the photodiode PD. By configuring the transfer transistor TR as such a vertical transistor, transfer failures of pixel signals are less likely to occur, and the readout efficiency of pixel signals can be improved.

[0020] A fixed charge film 12 having, for example, a negative fixed charge is provided on the surface 100S2 of the semiconductor layer 100S. The fixed charge film 12 forms a pinning region in which holes are accumulated at the interface on the light-receiving surface (surface 100S2) side of the semiconductor layer 100S. This suppresses the generation of dark current due to interface states on the surface 100S1 side of the semiconductor layer 100S. The fixed charge film 12 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), and tantalum oxide (TaO).

[0021] The semiconductor layer 100S further includes a separation portion 13 that separates the adjacent sensor pixel P1 and display pixel P2 from each other. The separation portion 13 extends in the thickness direction of the semiconductor layer 100S. The separation portion 13 is provided to separate the adjacent sensor pixel P1 and display pixel P2 from each other and has, for example, a grid-like planar shape. The separation portion 13 includes, for example, an insulating film 13A and a light-shielding film 13B. The insulating film 13A is provided between the light-shielding film 13B and the p-well layer 115 and the n-type semiconductor region 114. The insulating film 13A can be formed using, for example, silicon oxide (SiO). The light-shielding film 13B can be formed using, for example, a metal material such as tungsten (W). A predetermined potential may be applied to the light-shielding film 13B. The isolation portion 13 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Note that the isolation portion 13 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, the isolation portion 13 may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S.

[0022] Here, the separating portion 13 corresponds to a specific example of a "light blocking portion" in the embodiment of the present disclosure.

[0023] The semiconductor layer 100S is provided with, for example, a pinning region 113. The pinning region 113 is provided on a side surface of the isolation portion 13, specifically, between the isolation portion 13 and the p-well 111 and between the isolation portion 13 and the n-type semiconductor region 112. The pinning region 113 is formed of, for example, a p-type semiconductor region.

[0024] The wiring layer 100T is provided on the surface 100S1 side of the semiconductor layer 100S facing the second substrate 20. The wiring layer 100T includes an interlayer insulating layer 14 and, for example, a gate (transfer gate TG) of the transfer transistor TR and a wiring (for example, wiring 15) provided in the interlayer insulating layer 14, which electrically connects the transfer transistor TR and the pixel transistor 22. The first substrate 10 and the second substrate 20 are electrically connected, for example, via this wiring 15. A horizontal portion of the transfer gate TG is provided, for example, in this wiring layer 100T. The interlayer insulating layer 14 is in contact with the semiconductor layer 100S. The interlayer insulating layer 14 can be formed using, for example, silicon oxide (SiO).

[0025] In the display pixel P2, an opening H (see FIG. 6W) is provided, and the semiconductor layer 100S and the wiring layer 100T are removed. A wavelength conversion layer 16 is provided in the opening H. A reflective film 17 is provided between the wavelength conversion layer 16 and the separation portion 13 and interlayer insulating layer 14 exposed by the opening H. A planarization layer 18 is continuously provided on the surface 100S1 of the semiconductor layer 100S and on the wavelength conversion layer 16.

[0026] The wavelength conversion layer 16 converts light emitted from the light emitting elements 21 provided on the second substrate 20 into a desired wavelength (e.g., red (R) / green (G) / blue (B)) and emits the light. Each display pixel P2 is provided with one of a red wavelength conversion layer 16R that converts light emitted from the light emitting elements 21 into light in a red wavelength band (red light), a green wavelength conversion layer 16G that converts light emitted from the light emitting elements 21 into light in a green wavelength band (green light), and a blue wavelength conversion layer 16B that converts light emitted from the light emitting elements 21 into light in a blue wavelength band (blue light).

[0027] The wavelength conversion layer 16 can be formed using quantum dots corresponding to each color. Specifically, when red light is obtained, the quantum dots can be selected from, for example, InP, GaInP, InAsP, CdSe, CdZnSe, CdTeSe, or CdTe. When green light is obtained, the quantum dots can be selected from, for example, InP, GaInP, ZnSeTe, ZnTe, CdSe, CdZnSe, CdS, or CdSeS. When blue light is obtained, the quantum dots can be selected from, for example, ZnSe, ZnTe, ZnSeTe, CdSe, CdZnSe, CdS, CdZnS, and CdSeS. Note that when blue light is emitted from the light-emitting element 21, the blue wavelength conversion layer 16B may be formed from a light-transmitting resin layer.

[0028] The reflective film 17 is intended to efficiently extract the color light emitted from the light-emitting element 21 and converted by the wavelength conversion layers 16R, 16G, and 16B from the display surface S1 side of the wavelength conversion layer 16. The reflective film 17 can be formed using a metal material having light reflectivity. Examples of the metal material for forming the reflective film 17 include metals having high reflectivity in the visible light range. Specific examples of the material include silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys thereof.

[0029] The planarization layer 18 is intended to planarize the display surface S1 side of the first substrate 10. The planarization layer 18 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0030] The second substrate 20 includes a semiconductor layer 200S. The semiconductor layer 200S has a pair of opposing surfaces (surface 200S1 and surface 200S2), with surface 200S1 facing the third substrate 30 and surface 200S2 facing the first substrate 10. The semiconductor layer 200S is configured, for example, by a compound semiconductor substrate such as a gallium nitride (GaN) substrate. The semiconductor layer 200S is separated between the sensor pixel P1 and the display pixel P2, with a pixel transistor 22 provided in the sensor pixel P1 and a light-emitting element 21 provided in the display pixel P2. An insulating layer 26 that forms a bonding surface with the third substrate 30 and a plurality of pad portions 27 embedded in the insulating layer 26 are provided on the surface 200S1 side of the semiconductor layer 200S.

[0031] 3 is an equivalent circuit diagram showing an example of the configuration of the sensor pixel P1. As described above, the sensor pixel P1 includes one light-receiving element 11 (photodiode PD), a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR, which are provided on the first substrate 10. The pixel transistor 22 is provided directly below the light-receiving element 11 (photodiode PD) and the transfer transistor TR on the second substrate 20. The pixel transistor 22 includes, for example, four transistors. Specifically, the pixel transistor 22 includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0032] The pixel transistors 22 provided on the second substrate 20 may also be called pixel circuits, pixel transistor circuits, pixel transistor groups, pixel readout circuits, or readout circuits. In this specification, the term "pixel transistors" is used.

[0033] The floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is electrically connected to the source of the reset transistor RST. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to a drive signal line. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to a vertical signal line VSL, and the gate of the select transistor SEL is connected to a drive signal line.

[0034] In the pixel transistor 22, for example, at least one of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG has a three-dimensional structure such as a fin type. This improves transistor characteristics, thereby improving, for example, image quality. In particular, by configuring the amplification transistor AMP using a transistor with a three-dimensional structure, noise can be effectively reduced and image quality can be improved. Furthermore, all of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG may be configured using transistors with a three-dimensional structure. In this case, manufacturing of the pixel transistor 22 becomes easier. The pixel transistor 22 is formed, for example, containing gallium nitride or silicon.

[0035] A three-dimensional transistor is one in which multiple flat gate electrodes are provided facing the channel, or one in which a curved gate electrode is provided around the channel. Such a three-dimensional transistor can have a larger effective gate width than a planar transistor when it has the same footprint as a planar transistor. Therefore, a larger current flows through the three-dimensional transistor, resulting in a higher transconductance gm. This allows the three-dimensional transistor to have a higher operating speed than a planar transistor. Additionally, it is also possible to reduce RN (Random Noise). Furthermore, since a three-dimensional transistor has a larger gate area than a planar transistor, RTS (Random Telegraph Signal) noise is reduced.

[0036] The sensor pixel P1 has a well region 221 on the surface 200S2 of the semiconductor layer 200S and a fin structure on the surface 200S1. The well region 221 is, for example, a p-type semiconductor region. A gate 223 is formed on the top and side surfaces of the fin structure via a gate insulating film 222. The gate insulating film 222 extends, for example, from the top and side surfaces of the fin structure to the side surfaces of the semiconductor layer 200S separated for each pixel. The periphery of the pixel transistor 22 is buried in an insulating film 224. A portion of the gate 223 protrudes from the insulating film 224, and the top and side surfaces of the protruding gate 223 are covered with insulating films 225 and 226. A sidewall SW is formed between the insulating film 225 and insulating film 226 that cover the side surfaces of the gate 223. A buried layer 227 is provided on the surface 200S2 side of the semiconductor layer 200S, specifically on the insulating film 226, so as to bury the pixel transistor 22. A via V2 that connects the gate 223 and the pad portion 27 is provided in the buried layer 227 .

[0037] The gate insulating film 222 can be formed using, for example, silicon oxide (SiO), silicon nitride (SiN), etc. Alternatively, the gate insulating film 222 can be formed using hafnium silicate (HfSiO), HfSiON, TaO, TaON, etc.

[0038] The gate 223 can be formed using, for example, polysilicon.

[0039] The insulating films 224, 225, and 226 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0040] The buried layer 227 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0041] A light-emitting element 21 is provided for each display pixel P2. An electrode layer 214 is provided on the surface 200S2 side of the semiconductor layer 200S constituting the light-emitting element 21. An electrode layer 215 and an insulating layer 216 are provided on the surface 200S1 side of the semiconductor layer 200S constituting the light-emitting element 21. The light-emitting element 21 has a mesa shape on the third substrate 30 side. The upper surface of the insulating layer 216, the side surfaces of the insulating layer 216 and the electrode layer 215, and the side surfaces of the semiconductor layer 200S processed into a mesa shape are covered with a protective layer 217. The top surface of the protective layer 217 and the side surfaces of the semiconductor layer 200S exposed from the protective layer 217 are covered with a stacked film made of an insulating film 218A and a reflective film 218B. An embedding layer 219 is provided around the light-emitting element 21 to embed the light-emitting element 21. On the surface 200S2 side of the semiconductor layer 200S, a plug 23 connected to the electrode layer 215, and an insulating layer 25 including a pad portion 24 connected to the plug 23 and a via V1 are provided in this order.

[0042] The light-emitting element 21 is a solid-state light-emitting element that emits light in a predetermined wavelength band from the surface 200S2, and is, for example, an LED (Light Emitting Diode) chip. The LED chip refers to an element cut from a wafer used for crystal growth, and is not a packaged type covered with molded resin or the like. The LED chip has a size of, for example, 5 μm to 100 μm, and is a so-called micro LED.

[0043] In the display pixel P2, the semiconductor layer 200S includes a first conductivity type layer 211, an active layer 212, and a second conductivity type layer 213. The first conductivity type layer 211, the active layer 212, and the second conductivity type layer 213 are stacked in this order from the surface 200S1 side, and the upper surface (surface 200S2) of the second conductivity type layer 213 serves as a light emitting surface.

[0044] The first conductivity type layer 211 is made of, for example, a p-type GaN-based semiconductor. The active layer 212 has, for example, a multiple quantum well structure in which InGaN and GaN are alternately stacked, and has a light-emitting region within the layer. Light in the blue band of, for example, 430 nm to 500 nm is extracted from the active layer 212. In addition, light with a wavelength corresponding to, for example, the ultraviolet region (ultraviolet light) may also be extracted from the active layer 212. The second conductivity type layer 213 is made of, for example, an n-type GaN-based semiconductor. Note that the conductivity types of the first conductivity type layer 211 and the second conductivity type layer 213 are not limited to those described above. For example, the first conductivity type layer 211 may be made of an n-type GaN-based semiconductor, and the second conductivity type layer 213 may be made of a p-type GaN-based semiconductor.

[0045] The electrode layer 214 is in ohmic contact with the second conductivity type layer 213, and can be formed using a transparent electrode material such as ITO, indium zinc oxide (IZO), tin oxide (SnO), or TiO.

[0046] The electrode layer 215 is in ohmic contact with the first conductivity type layer 211 and can be formed using, for example, a multilayer film (Ni / Au) of nickel (Ni) and gold (Au) or a transparent conductive material such as ITO.

[0047] The insulating layer 216 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0048] The protective layer 217 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0049] The insulating film 218A can be formed using an insulating material such as silicon oxide (SiO) or silicon nitride (SiN). The reflective film 218B can be formed using a metal material that has high reflectivity in the visible light range. Examples of metal materials that have high reflectivity in the visible light range include silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys thereof.

[0050] The buried layer 219 can be formed using an insulating material such as silicon oxide (SiO) or silicon nitride (SiN).

[0051] The plug 23 is for applying a voltage to the first conductivity type layer 211 of the light emitting element 21. The plug 23 can be formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or an alloy thereof.

[0052] The pad portion 24 and the vias V1 and V2 can be formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or an alloy thereof.

[0053] The insulating layer 25 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0054] In the semiconductor device 1, voltages are applied to the sensor pixel P1 and the display pixel P2 independently of each other via vias V1 and V2. That is, the sensor pixel P1 and the display pixel P2 can be driven with different voltages. Furthermore, between adjacent pixels (e.g., the sensor pixel P1 and the display pixel P2), for example, a via V3 is provided. One end of the via V3 penetrates the second substrate 20 and is connected to the light-shielding film 13B of the isolation portion 13, and the other end of the via V3 is connected to a plurality of pad portions 27 embedded in the insulating layer 26 that forms the bonding surface with the third substrate 30. In the semiconductor device 1, a predetermined potential can be applied to the light-shielding film 13B via the via V3.

[0055] As described above, the insulating layer 26 that forms the bonding surface with the third substrate 30 and the plurality of pad portions 27 that are embedded in the insulating layer 26 are provided on the embedded layer 227 provided in the sensor pixel P1 and on the insulating layer 25 provided in the display pixel P2. The insulating layer 26 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN). The pad portions 27 can be formed using, for example, copper (Cu).

[0056] The third substrate 30 is provided with a drive circuit and the like that controls the driving of a plurality of light receiving elements 11 provided for each sensor pixel P1 on the first substrate 10 and a light emitting element 21 provided for each display pixel P2 on the second substrate 20. The third substrate 30 has a support substrate 31 made of, for example, silicon (Si), a plurality of wiring layers (wiring layers M1, ..., Mn) provided on the support substrate 31, an interlayer insulating layer 32 including vias that electrically connect the wiring layers, an insulating layer 33 that forms a bonding surface with the second substrate 20, and a plurality of pad portions 34 that are embedded in the insulating layer 33.

[0057] The interlayer insulating layer 32 can be formed using, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0058] The wiring layers M1, ..., Mn and the vias electrically connecting the wiring layers can be formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. The insulating layer 33 can be formed using, for example, silicon oxide (SiO), silicon nitride (SiN), etc. The multiple pad portions 34 can be formed using, for example, copper (Cu).

[0059] The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding with a plurality of pads 27, 34 formed on the respective bonding surfaces.

[0060] Further provided on the display surface S1 side of the first substrate 10 are a separation wall 41, a color filter 42, and a lens layer 43. The separation wall 41 is provided between adjacent pixels, and the color filter 42 is provided so as to fill the space between the separation walls 41.

[0061] The separation wall 41 is intended to prevent light from leaking into adjacent pixels, and can be formed using, for example, a metal material such as tungsten (W) or a resin material having light-blocking properties.

[0062] The color filters 42 selectively transmit light of predetermined wavelengths, and include color filters 42R, 42G, and 42B that selectively transmit, for example, red light (R), green light (G), or blue light (B) of visible light. The color filters 42R, 42G, and 42B are provided, for example, for each pixel, as shown in Fig. 2. Each of the color filters 42R, 42G, and 42B is shared by, for example, four pixels (two sensor pixels P1 and two display pixels P2) arranged in two rows and two columns, as shown in Fig. 2. In the semiconductor device 1, four pixels (two sensor pixels P1 and two display pixels P2) arranged in two rows and two columns are considered as one pixel unit. Two color filters 42G that selectively transmit green light (G) are arranged diagonally across the four pixel units, and color filters 42R and 42B that selectively transmit red light (R) and blue light (B) are arranged on the perpendicular diagonal lines. In the sensor pixel P1 provided with each color filter 42R, 42G, or 42B, the corresponding color light is photoelectrically converted in the photodiode PD. The corresponding color light is extracted from the display pixel P2 provided with each color filter 42R, 42G, or 42B. That is, in the semiconductor device 1, the sensor pixel P1 that detects red light (R), green light (G), or blue light (B) and the display pixel P2 that extracts red light (R), green light (G), or blue light (B) are arranged in a Bayer pattern. The thickness of the color filter 42 may be different for each color, taking into consideration the color reproducibility and sensor sensitivity of the optical spectrum.

[0063] The lens layer 43 has a plurality of on-chip lenses 43L on its surface. The on-chip lenses 43L are provided for each pixel. Examples of materials for the lens layer 43 include resin materials with a refractive index of 1.5 to 2.0, and inorganic materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), and amorphous silicon. Alternatively, the lens layer 43 may be formed using organic materials with a high refractive index, such as episulfide resins, thietane compounds, and their resins. The shape of the on-chip lenses 43L is not particularly limited, and various lens shapes, such as a hemispherical shape or a semi-cylindrical shape, can be used.

[0064] (1-2. Manufacturing Method of Semiconductor Device) The semiconductor device 1 of the present embodiment can be manufactured, for example, as follows. Figures 4A to 4K, 5A to 5H, and 6A to 6X show an example of a manufacturing process of the semiconductor device 1.

[0065] 4A , for example, a sapphire substrate 231 is used as a growth substrate, and a semiconductor layer 200S is formed by epitaxial crystal growth using a method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Subsequently, an electrode layer 215 and an insulating layer 216 are formed on the semiconductor layer 200S by, for example, chemical vapor deposition (CVD). Next, the surface of the insulating layer 216 is planarized by, for example, chemical mechanical polishing (CMP).

[0066] Next, as shown in Fig. 4B, the insulating layer 216, the electrode layer 215, and the semiconductor layer 200S are etched and patterned using, for example, photolithography. Next, as shown in Fig. 4C, the sapphire substrate 231 is transferred to the support substrate 51 so that the insulating layer 216 faces the support substrate 51, and then the sapphire substrate 231 is cleaved and divided into individual pieces. Next, as shown in Fig. 4D, each of the divided sapphire substrates 231 is bonded to a transfer substrate 232 so that the insulating layer 216 faces the support substrate 51.

[0067] Next, as shown in Fig. 4E, the sapphire substrate 231 is thinned to a thickness of, for example, 500 nm by, for example, grinding and polishing. Subsequently, as shown in Fig. 4F, an inversion substrate 234 is bonded to the sapphire substrate 231 side and inverted, and the transfer substrate 232 is peeled off. Next, the surface of the insulating layer 216 is planarized again by, for example, CMP, and then, as shown in Fig. 4G, the insulating layer 216 is bonded to a support substrate 235, and the sapphire substrate 231 is removed by, for example, grinding and polishing.

[0068] Next, as shown in Fig. 4H, a buried layer 219 is formed on the support substrate 235 by, for example, CVD and then planarized. Next, as shown in Fig. 4I, the edge of the support substrate 235 is trimmed. Next, as shown in Fig. 4J, the buried layer 219 is bonded to the support substrate 236 by, for example, plasma bonding, and then the support substrate 235 is peeled off. Below, the inside of the frame X shown in Fig. 4K will be explained in enlarged form.

[0069] 5A, the insulating layer 216 and the electrode layer 215 are etched and patterned using, for example, photolithography. Then, as shown in FIG. 5B, a mesa structure including the first conductivity type layer 211, the active layer 212, and a portion of the second conductivity type layer 213 is formed by etching a portion of the semiconductor layer 200S using, for example, photolithography.

[0070] Next, for example, by atomic layer deposition (ALD), an AlO film is formed on the top surface of insulating layer 216 and on the side and bottom surfaces of insulating layer 216, electrode layer 215, and first conductivity type layer 211, active layer 212, and second conductivity type layer 213 that constitute the mesa structure, and then a SiN film is further formed by, for example, CVD. Thereafter, the SiN film is etched using, for example, photolithography to form protective layer 217 as sidewalls on the top surface and side surfaces of the mesa structure, as shown in FIG. 5C .

[0071] Next, as shown in FIG. 5D , the second conductivity type layer 213 exposed from the protective layer 217 is etched and divided, for example, using photolithography. This results in the formation of a plurality of light emitting elements 21 that are independent of one another. Next, as shown in FIG. 5E , an AlO film is formed, for example, by ALD, to cover the upper surface of the protective layer 217 and the exposed side surfaces of the light emitting elements 21. Then, an Al film is formed, for example, by CVD, to form the insulating film 218A and the reflective film 218B. An opening 118H is then formed in the upper surface of the mesa structure. Note that, in this example, a well region 221 is formed in the semiconductor layer 200S in which the pixel transistor 22 is formed. However, the well region 221 may also be formed after removing the sapphire substrate 231 shown in FIG. 4G .

[0072] Next, as shown in Fig. 5F, a buried layer 219 is further formed by, for example, CVD to bury the plurality of light-emitting elements. After that, the buried layer 219 is planarized, and then, as shown in Fig. 5G, an insulating layer 25 is formed for each light-emitting element 21, in which a plug 23 and a plurality of pad portions 24 are buried. Subsequently, as shown in Fig. 5H, the insulating layer 25 is thickened.

[0073] First, as shown in Fig. 6A, every other light emitting element 21 is etched using, for example, photolithography to expose the semiconductor layer 200S. Next, as shown in Fig. 6B, the semiconductor layer 200S is processed using, for example, photolithography to form a fin structure. Subsequently, as shown in Fig. 6C, a SiO film, for example, is formed on the surface of the exposed semiconductor layer 200S using, for example, ALD to form a gate insulating film 222, and further, a SiN film 241 is formed to embed the fin structure.

[0074] Next, as shown in Fig. 6D, a resist mask 242 is patterned at a predetermined position using, for example, photolithography, and then, as shown in Fig. 6E, a portion of the SiN film 241 and the semiconductor layer 200S exposed from the resist mask 242 is etched. Subsequently, as shown in Fig. 6F, the surface of the semiconductor layer 200S exposed by etching is oxidized. Next, as shown in Fig. 6G, a resist mask 244 is patterned on the SiN film 241 and the gate insulating film 222.

[0075] 6H, the semiconductor layer 200S outside the resist mask 244 is removed by dry etching. Next, as shown in Fig. 6I, the exposed surface of the semiconductor layer 200S is oxidized, and then, as shown in Fig. 6J, an insulating film 224 is formed to bury the semiconductor layer 200S. Next, as shown in Fig. 6K, the SiN film 241 covering the fin is removed.

[0076] Next, as shown in Fig. 6L, a polysilicon film that forms the gate 223 is formed by, for example, CVD, and then a resist mask 245 is patterned on the polysilicon film. Subsequently, as shown in Fig. 6M, the polysilicon film is thinned to a predetermined thickness, and then a resist film 246 is patterned above the fin. Next, as shown in Fig. 6N, the polysilicon film is patterned to form the gate 223, and then an insulating film 225 is formed by, for example, ALD, and then a sidewall SW is formed.

[0077] Next, as shown in Fig. 6O, an insulating film 226 is formed by, for example, ALD, and then a buried layer 227 is formed by, for example, CVD. Next, as shown in Fig. 6P, the SiN film 241 is removed and the buried layer 227 is planarized by, for example, CMP. Next, as shown in Fig. 6Q, the insulating layer 25 and the buried layer 227 are bonded to a support substrate 237 by, for example, plasma bonding, and then the support substrate 236 is peeled off as shown in Fig. 6R.

[0078] Next, the buried layer 219 on the surface 200S1 of the semiconductor layer 200S is removed by, for example, CMP to planarize the surface, and then the semiconductor layer 100S is bonded to the surface 200S1 of the semiconductor layer 200S with the semiconductor layer 100ST interposed therebetween, as shown in Fig. 6S. Subsequently, the support substrate 237 is peeled off, and then openings are formed in the insulating layer 25 and the buried layer 227, as shown in Fig. 6T. Then, vias V1, V2, and V3 are formed, as shown in Fig. 6U. Furthermore, as shown in Fig. 6U, a plurality of pad portions 27 are formed embedded in the insulating layer 26 that forms the bonding surface with the third substrate 30, and a separately formed third substrate 30 is bonded to the third substrate 30.

[0079] 6V, the semiconductor layer 100S is thinned from the surface 100S2 side by, for example, CMP, and then a fixed charge film 12 is formed on the surface 100S2, followed by the formation of a planarization layer 18. Subsequently, as shown in FIG. 6W, the semiconductor layer 100S on the light-emitting element 21 is etched using, for example, photolithography to form an opening H, exposing the surface 200S1 of the semiconductor layer 200S. Thereafter, an electrode layer 214 is formed on the surface 200S1 of the semiconductor layer 200S.

[0080] 6X, wavelength conversion layers 16 (16R, 16G, 16B) of each color are formed in the opening H by a coating method such as an inkjet method. After that, a planarization layer 18 is further formed by, for example, a CVD method to planarize the display surface S1 side of the first substrate 10. Then, separation walls 41 and color filters 42 (42R, 42G, 42B) are formed on the planarization layer 18, and a lens layer 43 is then attached. This completes the semiconductor device 1 shown in FIG.

[0081] (1-3. Actions and Effects) In this embodiment, in the semiconductor device 1, the first substrate 10 and the second substrate 20 are arranged in this order from the display surface S1 side, with the light receiving element 11 provided on the first substrate 10 and the light emitting element 21 provided on the second substrate 20. This will be described below.

[0082] For example, as described above, a semiconductor device has been disclosed in which a light-receiving element and a light-emitting element are provided on the same substrate, as a device equipped with both a light-emitting element and a light-receiving element that can be used as a so-called notch display. When the light-receiving element and the light-emitting element are configured on the same substrate, the light-receiving element and the light-emitting element are different elements, and therefore are laid out in separate regions. As an example, a semiconductor device has been developed in which a photodiode PD is embedded in a substrate provided with a small organic electroluminescence (EL) element.

[0083] However, in the semiconductor device described above, there is a problem that the photodiode PD cannot be made large due to the low illuminance of the small organic EL element.

[0084] In contrast, in the semiconductor device 1 of the present embodiment, the light receiving element 11 and the light emitting element 21 are provided on different substrates. Specifically, the light receiving element 11 is provided on the first substrate 10, and the light emitting element 21 is provided on the second substrate. The first substrate 10 and the second substrate 20 are stacked in this order from the display surface S1 side, with a wavelength conversion layer 16 provided on the first substrate 10 above the light emitting element 21, and a pixel transistor 22 provided on the second substrate 20 below the light receiving element 11. This makes it possible to form a light emitting element 21 with higher illuminance and to increase the area of ​​the light receiving element compared to when the light emitting element and the light receiving element are arranged in parallel on the same substrate.

[0085] As described above, the semiconductor device 1 of this embodiment can achieve high luminance of the light-emitting portion and an enlarged light-receiving portion.

[0086] Furthermore, in the semiconductor device 1 of this embodiment, since it is possible to mount the light emitting element 21 with higher illuminance as described above, it is possible to miniaturize the pixels.

[0087] Furthermore, in the semiconductor device 1 of this embodiment, the light receiving element 11 and the light emitting element 21 are provided on different substrates, which allows for improved mass production speed compared to the case where the light emitting element and the light receiving element are provided on the same substrate as described above.

[0088] Next, modified examples and application examples of the present disclosure will be described. Note that components corresponding to those of the semiconductor device 1 of the above embodiment are given the same reference numerals and descriptions thereof will be omitted.

[0089] 2. Modifications Fig. 7 is a schematic diagram showing an example of a cross-sectional configuration of a semiconductor device (semiconductor device 2) according to a modification of the present disclosure. Fig. 8 is a schematic diagram showing an example of a planar configuration of the semiconductor device 2 shown in Fig. 7, and Fig. 7 is a cross-sectional view corresponding to line II-II' shown in Fig. 8. The semiconductor device 2 can be suitably used for a so-called notch display mounted on an electronic device such as a mobile device having an imaging function, which will be described later.

[0090] In the above embodiment, an example in which the on-chip lens 43L is provided for each pixel has been described, but the present invention is not limited to this. In the semiconductor device 2 of this modified example, the on-chip lens 43L is configured to be shared by a plurality of pixels.

[0091] Specifically, four pixels (two sensor pixels P1 and two display pixels P2) arranged in two rows and two columns are considered to be one pixel unit, and one on-chip lens 43L is provided for each pixel unit.

[0092] Even with this configuration, the same effects as those of the above embodiment can be obtained.

[0093] 3. Application Examples The semiconductor device 1 described above can be applied to various electronic devices, such as display devices such as head-mounted displays and head-up displays, imaging devices such as digital still cameras and digital video cameras, portable devices with imaging functions, and audio players with imaging functions.

[0094] FIG. 9 is a block diagram showing an example configuration of an electronic device 3 to which the present technology is applied.

[0095] The electronic device 3 shown in FIG. 9 is configured with an optical system 301, a shutter device 302, a semiconductor device (e.g., semiconductor device 1), a control circuit 303, a signal processing circuit 304, a monitor 305, and a memory 306, and is capable of capturing still images and moving images.

[0096] The optical system 301 is configured to have one or more lenses, and guides light (incident light) from a subject to the semiconductor device 1 to form an image on the light-receiving surface of the semiconductor device 1 .

[0097] The shutter device 302 is disposed between the optical system 301 and the semiconductor device 1 , and controls the light irradiation period and the light blocking period for the semiconductor device 1 under the control of the control circuit 303 .

[0098] The semiconductor device 1 accumulates signal charges for a certain period of time in response to light that is imaged on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the semiconductor device 1 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 303. The semiconductor device 1 also emits light at a predetermined timing in accordance with the drive signal (timing signal) supplied from the control circuit 303. The light emitted by the semiconductor device 1 may be used for an illumination function or a display function.

[0099] The semiconductor device 1 may be configured as a single chip by itself, or may be configured as part of a camera module packaged together with an optical system 301, a shutter device 302, a control circuit 303, a signal processing circuit 304, a monitor 305 and a memory 306.

[0100] The control circuit 303 outputs a drive signal that controls the transfer operation of the semiconductor device 1 and the shutter operation of the shutter device 302 , thereby driving the semiconductor device 1 and the shutter device 302 .

[0101] The signal processing circuit 304 performs various types of signal processing on the pixel signals output from the semiconductor device 1. An image (image data) obtained by performing the signal processing by the signal processing circuit 304 is supplied to a monitor 305 to be displayed, or supplied to a memory 306 to be stored (recorded).

[0102] By using the semiconductor device 1 to which the above-described embodiments are applied, miniaturization can be achieved while realizing light-emitting and imaging functions in the electronic device 3. Therefore, even in the electronic device 3 such as a video camera, a digital still camera, or a camera module for a mobile device such as a mobile phone, it is possible to achieve high illuminance of the light-emitting portion and an enlarged light-receiving portion.

[0103] 10 shows an example of use of the semiconductor device according to the present disclosure (e.g., the semiconductor device 1). The semiconductor device 1 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0104] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as televisions, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0105] 11 to 14 are schematic diagrams showing the appearance of electronic devices (for example, mobile devices 3A to 3D) that use a semiconductor device (for example, semiconductor device 1) according to the present disclosure.

[0106] The mobile devices 3A to 3D each include, for example, a display unit 310 and a non-display unit (housing 320). The semiconductor device 1 can be arranged, for example, on the top of the display unit 310, as in the mobile device 3A shown in FIG. 11. The semiconductor device 1 can be arranged, for example, at the four corners of the display unit 310, as in the mobile device 3B shown in FIG. 12. The semiconductor device 1 can be arranged, for example, on the outer periphery of the display unit 310, as in the mobile device 3C shown in FIG. 13. The semiconductor device 1 can be arranged, for example, in the center of the display unit 310, as in the mobile device 3D shown in FIG. 14.

[0107] Furthermore, by using this technology, the sensor unit (light receiving unit) and the display unit (light emitting unit) can be shared, making it possible to achieve both a larger sensor unit and a more aesthetically pleasing design without the sensor unit being noticeable.

[0108] Although the present technology has been described above by way of embodiments, modifications, and application examples, the present technology is not limited to the above embodiments, etc., and various modifications are possible. For example, in the above embodiments, etc., examples have been shown in which the light emitted from the light-emitting element 21 is blue light or ultraviolet light, but the present technology is not limited to this. For example, the semiconductor device 1 may also use a light-emitting element that emits two or more types of light, such as blue light and green light, or ultraviolet light and green light.

[0109] In addition, in the above-described embodiment and the like, an example has been shown in which a plurality of rectangular pixels (a plurality of sensor pixels P1 and a plurality of display pixels P2) are arranged in a matrix, but this is not limiting. For example, the plurality of pixels (a plurality of sensor pixels P1 and a plurality of display pixels P2) may have a substantially regular hexagonal shape and be arranged in, for example, a honeycomb pattern.

[0110] Furthermore, in the above embodiments, each component constituting the semiconductor device 1 etc. has been specifically listed and described, but it is not necessary to include all components, and other components may also be included.

[0111] The effects described in this specification are merely examples and are not limited to those described, and other effects may also be obtained.

[0112] The present technology may also have the following configurations. According to the present technology configured as follows, (1) a semiconductor device including: a first substrate having first pixels including light receiving portions and second pixels including light guiding portions; and a second substrate stacked on the first substrate, the second substrate having a transistor portion arranged opposite the first pixel and driving the first pixel, and a light emitting portion arranged opposite the second pixel. (2) The semiconductor device according to (1), further including a first wiring connecting the light receiving portion and the transistor portion, the first substrate and the second substrate being electrically connected via the first wiring. (3) The semiconductor device according to (1) or (2), wherein the light receiving portion is a photodiode. (4) The semiconductor device according to any one of (1) to (3), wherein the light emitting portion is a light emitting diode. (5) The semiconductor device according to any one of (1) to (4), wherein the light guiding portion includes a wavelength conversion layer or a resin layer having optical transparency. (6) The semiconductor device according to any one of (1) to (5), further comprising a light-shielding portion between the first pixel and the second pixel. (7) The semiconductor device according to any one of (1) to (6), wherein the first substrate has a first surface facing the second substrate and a second surface opposite to the first surface, and the first pixel and the second pixel each further have a color filter on the second surface side. (8) The semiconductor device according to (7), wherein the color filter includes a first color filter that selectively transmits light in a first wavelength band and a second color filter that selectively transmits light in a second wavelength band different from the first wavelength band, and the first color filter and the second color filter are each shared by a plurality of pixels including the first pixel and the second pixel adjacent to each other. (9) The semiconductor device according to any one of (1) to (8), wherein the first substrate has a first surface facing the second substrate and a second surface opposite to the first surface, and further has a lens arranged on the second surface side. (10) The semiconductor device according to (9), wherein the lens is provided in each of the first pixel and the second pixel.(11) The semiconductor device according to (9), wherein the lens is shared by a plurality of pixels including the first pixel and the second pixel adjacent to each other. (12) The semiconductor device according to any one of (1) to (11), wherein the first pixel and the second pixel have different driving voltages. (13) The semiconductor device according to any one of (1) to (12), wherein the first substrate includes a first semiconductor layer, and the light receiving unit is a photodiode embedded in the first semiconductor layer. (14) The semiconductor device according to (13), wherein the first semiconductor layer is a silicon substrate. (15) The semiconductor device according to any one of (1) to (14), wherein the second substrate includes a second semiconductor layer, and the second semiconductor layer is a compound semiconductor substrate. (16) The semiconductor device according to (15), wherein the second semiconductor layer is a gallium nitride substrate. (17) The semiconductor device according to (16), wherein the transistor unit includes gallium nitride or silicon. (18) An electronic device comprising a semiconductor device, the semiconductor device comprising: a first substrate having first pixels including light receiving sections and second pixels including light guiding sections; and a second substrate stacked on the first substrate, the second substrate having a transistor section that drives the first pixels and is arranged opposite the first pixels, and a light emitting section that is arranged opposite the second pixels.

[0113] This application claims priority based on Japanese Patent Application No. 2023-196796, filed on November 20, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0114] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a first substrate having a first pixel including a light receiving portion and a second pixel including a light guiding portion; and a second substrate laminated on the first substrate, the second substrate having a transistor portion arranged opposite the first pixel for driving the first pixel, and a light emitting portion arranged opposite the second pixel.

2. The semiconductor device according to claim 1, further comprising a first wiring that connects said light receiving portion and said transistor portion, said first substrate and said second substrate being electrically connected via said first wiring.

3. The semiconductor device according to claim 1, wherein said light receiving portion is a photodiode.

4. The semiconductor device according to claim 1, wherein said light emitting portion is a light emitting diode.

5. The semiconductor device according to claim 1, wherein said light guide portion includes a wavelength conversion layer or a resin layer having optical transparency.

6. The semiconductor device according to claim 1, further comprising a light shielding portion between said first pixel and said second pixel.

7. The semiconductor device according to claim 1, wherein the first substrate has a first surface facing the second substrate and a second surface opposite the first surface, and the first pixel and the second pixel each further have a color filter on the second surface side.

8. The semiconductor device described in claim 7, wherein the color filter includes a first color filter that selectively transmits light in a first wavelength band and a second color filter that selectively transmits light in a second wavelength band different from the first wavelength band, and the first color filter and the second color filter are each shared by a plurality of pixels including adjacent first pixels and second pixels.

9. The semiconductor device according to claim 1, wherein the first substrate has a first surface facing the second substrate and a second surface opposite the first surface, and further has a lens disposed on the second surface side.

10. The semiconductor device according to claim 9, wherein the lens is provided for each of the first pixel and the second pixel.

11. The semiconductor device according to claim 9, wherein the lens is shared by a plurality of pixels including the first pixel and the second pixel that are adjacent to each other.

12. The semiconductor device according to claim 1, wherein the first pixel and the second pixel have different drive voltages.

13. The semiconductor device according to claim 1, wherein the first substrate includes a first semiconductor layer, and the light receiving portion is a photodiode embedded in the first semiconductor layer.

14. The semiconductor device according to claim 13, wherein said first semiconductor layer is a silicon substrate.

15. The semiconductor device according to claim 1, wherein the second substrate includes a second semiconductor layer, the second semiconductor layer being a compound semiconductor substrate.

16. The semiconductor device according to claim 15, wherein the second semiconductor layer is a gallium nitride substrate.

17. The semiconductor device according to claim 16, wherein the transistor portion includes gallium nitride or silicon.

18. An electronic device comprising a semiconductor device, the semiconductor device comprising: a first substrate having a first pixel including a light receiving portion and a second pixel including a light guiding portion; and a second substrate stacked on the first substrate, the second substrate having a transistor portion arranged opposite the first pixel for driving the first pixel, and a light emitting portion arranged opposite the second pixel.

Images