Semiconductor device

Abstract

A sense element (Se) has a well layer (17) of a second conductivity type formed on a drift layer (11) and includes: an emitter electrode (E) which is electrically connected to an emitter region (16) and a base layer (12); a collector electrode (C) which is electrically connected to a collector layer (19); and a sense electrode (S) which is electrically connected to the well layer (17), wherein, by a predetermined voltage being applied to a gate electrode (15), a first carrier is supplied from the emitter electrode (E) to the drift layer (11), a second carrier is supplied from the collector electrode (C) to the drift layer (11), and a part of the second carrier supplied to the drift layer (11) flows to the well layer (17).

Description

Semiconductor Devices CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2023-196771, filed on November 20, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device.

[0003] Conventionally, semiconductor devices have been proposed that have a main cell region in which a main element is formed and a sense cell region in which a sense element is formed (see, for example, Patent Document 1). Specifically, the main element and the sense element in this semiconductor device are formed by forming IGBT (Insulated Gate Bipolar Transistor) elements with the same configuration, including gate structures, emitter regions, etc. The main element and the sense element (i.e., the main cell region and the sense cell region) are formed to have a predetermined area ratio. Furthermore, this semiconductor device includes a temperature detection unit that detects the temperature of a semiconductor substrate on which the main element and the sense element are formed. In such a semiconductor device, the current flowing through the main element is detected as follows: That is, in the semiconductor device, a detection resistor is connected in series to the sense element. When detecting the current flowing through the main element, a control unit that performs predetermined processing determines the voltage across the detection resistor as a detection voltage and detects the current flowing through the main element based on this detection voltage.

[0004] More specifically, when the main element and the sense element have the same configuration, the current flowing through the main element and the current flowing through the sense element depend on the area ratio between the main element and the sense element. Therefore, the main current flowing through the main element is derived from the sense current (i.e., the detected voltage) flowing through the sense element and the area ratio between the main element and the sense element. In this case, the control unit detects the current flowing through the main element while performing correction using the temperature detected by the temperature detection unit.

[0005] Japanese Patent Application Laid-Open No. 2006-271098

[0006] However, a configuration including a temperature detection unit can be complicated, so the present inventors are studying a semiconductor device that can reduce the effects of temperature without including a temperature detection unit or performing temperature correction.

[0007] An object of the present disclosure is to provide a semiconductor device that can reduce the influence of temperature without performing temperature compensation.

[0008] According to one aspect of the present disclosure, there is provided a semiconductor device having a main cell region in which a main element is formed and a sense cell region in which a sense element is formed, a detection unit is connected to the sense element, and a main current flowing through the main element is detected based on a detection result of the detection unit, the semiconductor device having a semiconductor substrate including a drift layer of a first conductivity type, and the main element includes a base layer of a second conductivity type formed on the drift layer, an emitter region of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a gate insulating film disposed on the surface of the base layer disposed between the emitter region and the drift layer a gate electrode layer disposed on the gate insulating film, and a collector layer of a second conductivity type formed on the opposite side of the drift layer to the base layer, and the sense element has a well layer of the second conductivity type formed on the drift layer, and is provided with an emitter electrode electrically connected to the emitter region and the base layer, a collector electrode electrically connected to the collector layer, and a sense electrode electrically connected to the well layer, and when a predetermined voltage is applied to the gate electrode layer, first carriers are supplied from the emitter electrode to the drift layer and second carriers are supplied from the collector electrode to the drift layer, and some of the second carriers supplied to the drift layer flow into the well layer.

[0009] According to this, in the sense cell region, a well layer is formed on the drift layer, and when the main cell region is in the on state, some of the second carriers flow into the well layer. In this case, the detection result of the detection unit connected to the sense element is based on the second carriers and is not affected by temperature. Therefore, with this semiconductor device, when the main current is detected based on the detection result of the detection unit connected to the sense element, the main current can be detected with reduced influence of temperature without performing temperature correction.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0011] 1 is a cross-sectional view of a semiconductor device in a first embodiment; FIG. 2 is a diagram showing a hole current when the semiconductor device is in an on state; FIG. 3 is a circuit diagram when detecting a current flowing through a main element; FIG. 4 is a diagram showing a semiconductor device used in a simulation; FIG. 5 is a diagram showing a hole current density at 25°C; FIG. 6 is a diagram showing a hole current density at 90°C; FIG. 7 is a diagram showing a hole current density at 150°C; FIG. 8 is a diagram showing a relationship between a collector current and a detection voltage of a semiconductor device in a first embodiment; FIG. 9 is a diagram showing a relationship between a collector current and a detection voltage of a semiconductor device in a comparative example; FIG. 10 is a diagram showing a relationship between temperature and a temperature characteristic ratio; FIG. 11 is a diagram showing an electron current density at 25°C; FIG. 12 is a diagram showing an electron current density at 90°C; FIG. 13 is a diagram showing an electron current density at 150°C; FIG. 14 is a diagram showing a relationship between a distance ratio and a detection voltage; FIG. 15 is a cross-sectional view of a semiconductor device in a modified example of the second embodiment;

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0013] First Embodiment A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

[0014] 1, the semiconductor device of this embodiment has a main cell region Rm in which a main element Me is formed and a sense cell region Rs in which a sense element Se is formed. The main cell region Rm and the sense cell region Rs are formed to have a predetermined area ratio (for example, several thousand:1).

[0015] The semiconductor device is configured using a semiconductor substrate 10. The semiconductor substrate 10 is made of N － The semiconductor substrate 10 of this embodiment has a P-type drift layer 11. Note that the thickness of the semiconductor substrate 10 is approximately 130 μm. In the main cell region Rm, a P-type base layer 12 with a relatively low impurity concentration is disposed on the drift layer 11. In this embodiment, the base layer 12 has an outer edge base layer 12a on the sense cell region Rs side and an inner edge base layer 12b located closer to the inner edge than the outer edge base layer 12a. The outer edge base layer 12a is deeper than the inner edge base layer 12b so as to suppress electric field concentration at the end of the main cell region Rm on the outer edge side. In the following description, the surface of the semiconductor substrate 10 on the base layer 12 side is referred to as one surface 10a of the semiconductor substrate 10, and the surface opposite to the one surface 10a is referred to as the other surface 10b.

[0016] In the semiconductor substrate 10, a plurality of trenches 13 are formed in the main cell region Rm, penetrating the base layer 12 from the one surface 10a side to reach the drift layer 11. The base layer 12 in the main cell region Rm is separated into a plurality of base layers by the trenches 13. The trenches 13 are elongated in one direction (i.e., the depth direction of the paper in FIG. 1 ) of the planar directions of the one surface 10a of the semiconductor substrate 10, and are arranged so that the trenches 13 are equally spaced to form stripes. The portion of the base layer 12 located closer to the sense cell region Rs than the trenches 13 arranged at the end of the intersecting direction intersecting the one direction is defined as an outer edge base layer 12a. The intersecting direction can also be referred to as the arrangement direction of the trenches 13.

[0017] Each trench 13 is filled with a gate insulating film 14 formed to cover the wall surface of the trench 13 and a gate electrode layer 15 made of polysilicon or the like formed on the gate insulating film 14. This forms a trench gate structure. In this embodiment, the portion of the wall surface of the trench 13 that exposes the base layer 12 corresponds to the surface of the base layer 12 arranged between the emitter region 16 and the drift layer 11.

[0018] In the main cell region Rm, the surface layer of the base layer 12 is filled with N ＋ 1, a P type emitter region 16 having a higher impurity concentration than the drift layer 11 is formed in the base layer 12. Specifically, the emitter region 16 is configured to have a higher impurity concentration than the drift layer 11, and is formed along the longitudinal direction of the trench 13. Although not specifically shown in FIG. 1, a P type emitter region 16 having a higher impurity concentration than the base layer 12 is formed in a portion of the surface layer of the base layer 12 located on the opposite side of the emitter region 16 from the trench 13. ＋ A mold contact region may be formed.

[0019] In the sense cell region Rs, a P-type well layer 17 is formed on the drift layer 11. In this embodiment, the well layer 17 is formed at a distance d from the base layer 12. Therefore, in this embodiment, the drift layer 11 is arranged between the well layer 17 and the base layer 12. In other words, in the semiconductor device of this embodiment, an intermediate region Rt, in which the base layer 12 and the well layer 17 are not formed, is arranged between the main cell region Rm and the sense cell region Rs.

[0020] The well layer 17 in this embodiment has the same impurity concentration as the outer edge base layer 12 a in the main cell region Rm and is formed to the same depth as the outer edge base layer 12 a. Therefore, the well layer 17 is formed in the same process as the process for forming the outer edge base layer 12 a.

[0021] In the main cell region Rm, the base layer 12 and the emitter region 16 are connected to the emitter electrode E, and the gate electrode layer 15 is connected to the gate electrode G. In the sense cell region Rs, the well layer 17 is connected to the sense electrode S.

[0022] In the main cell region Rm and the sense cell region Rs, an N-type field stop layer (hereinafter simply referred to as an FS layer) 18 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., the other surface 10b side of the semiconductor substrate 10). This FS layer 18 is not necessarily required, but is provided to improve the breakdown voltage and steady-state loss performance by preventing the depletion layer from expanding, and to control the amount of holes injected from the other surface 10b side of the semiconductor substrate 10.

[0023] A p-type collector layer 19 is formed on the opposite side of the FS layer 18 from the drift layer 11. The collector layer 19 is connected to a collector electrode C.

[0024] The above is the configuration of the semiconductor device in this embodiment. － Type, N ＋ The P type corresponds to the first conductivity type, and the P type and P+ type correspond to the second conductivity type. In such a semiconductor device, as described above, the semiconductor substrate 10 is configured to include the collector layer 19, the FS layer 18, the drift layer 11, the base layer 12, the emitter region 16, etc. Also, although details are omitted above, the semiconductor device has a termination structure such as a guard ring formed to surround the main cell region Rm and the sense cell region Rs.

[0025] Next, the operation of such a semiconductor device and the main current (i.e., collector current IC) flowing through the main cell region Rm will be described, and the configuration will be further detailed.

[0026] In the semiconductor device of this embodiment, when a voltage lower than that of the collector electrode C is applied to the emitter electrode E and a voltage equal to or greater than the threshold voltage of the insulated gate structure is applied to the gate electrode layer 15, an N-type inversion layer (i.e., a channel) is formed in the portion of the base layer 12 that contacts the trench 13. In the main cell region Rm, electrons are supplied to the drift layer 11 from the emitter region 16 via the inversion layer, and holes are supplied to the drift layer 11 from the collector layer 19. The resistance value of the drift layer 11 decreases due to conductivity modulation, and a collector current IC flows, resulting in an ON state. In this embodiment, electrons correspond to first carriers and holes correspond to second carriers.

[0027] Here, in the energy band, the P-type has lower energy than the N-type for holes supplied to the drift layer 11, and therefore, some of the holes supplied to the drift layer 11 become hole currents that flow into the P-type layer. In this embodiment, a P-type base layer 12 is formed in the main cell region Rm, and a P-type well layer 17 is formed in the sense cell region Rs. For this reason, as shown in FIG. 2 , the hole current is separated into a main hole current MH that flows in the base layer 12 of the main cell region Rm and a sense hole current SH that flows in the well layer 17 of the sense cell region Rs. The main hole current MH and the sense hole current SH flow at a predetermined ratio depending on the impurity concentrations of the drift layer 11, the base layer 12, and the well layer 17, etc.

[0028] The main current (i.e., collector current IC) in the main cell region Rm in the semiconductor device of this embodiment is detected using a circuit configuration as shown in Fig. 3. Specifically, in this circuit configuration, a detection resistor R formed of a shunt resistor is provided as a detection unit between the sense electrode S of the sense element Se and the emitter electrode E of the main element Me.

[0029] The main current flowing through the main element Me is detected by a control unit (not shown) or the like based on a detection voltage Vs, which is the voltage across the detection resistor R. More specifically, a sense current flowing through the sense element Se is first detected from the detection voltage Vs. Note that the sense current in this embodiment is the sense hole current SH. In this embodiment, the detection voltage Vs corresponds to the detection result.

[0030] Here, the inventors conducted extensive research into the hole current density using the model shown in Fig. 4 and obtained the results shown in Fig. 5A to Fig. 5C. As shown in Fig. 5A to Fig. 5C, it was confirmed that the hole current density hardly changes even when the temperature changes. Note that the model shown in Fig. 4 has an area ratio of the main cell region Rm to the sense cell region Rs of 30:1.

[0031] The inventors obtained the results shown in Fig. 6 regarding the relationship between the collector current IC (i.e., the main current) flowing through the main cell region Rm and the detected voltage Vs of the detection resistor R when the temperature was changed. As shown in Fig. 6, it was confirmed that the detected voltage Vs is almost independent of the temperature.

[0032] In contrast, if a conventional semiconductor device in which the sense cell region Rs has the same configuration as the main cell region Rm is taken as the comparative semiconductor device, it is confirmed that in the comparative semiconductor device, as shown in Figure 7, the detection voltage Vs changes significantly depending on the temperature.

[0033] 6 and 7 show the results when the resistance value of the detection resistor R is 1 Ω. Also, Fig. 6 and 7 show the results when the distance d is 13 μm. The distance d being 13 μm means that the distance d is approximately 10% of the thickness of the semiconductor substrate 10.

[0034] If the detection voltage Vs at 25°C is taken as the reference for the temperature-dependent characteristic ratio (i.e., the temperature-dependent characteristic ratio is 1), as shown in Figure 8, it is confirmed that in the semiconductor device of this embodiment, the temperature-dependent characteristic ratio hardly changes even when the temperature changes. In contrast, in the semiconductor device of the comparative example, it is confirmed that the temperature-dependent characteristic ratio increases as the temperature increases. Note that the temperature-dependent characteristic ratio in Figure 8 is the result when the resistance value of the detection resistor R is 1 Ω and the collector current IC is 925 A. Also, Figure 8 shows the result when the distance d is 13 μm.

[0035] Furthermore, the inventors also conducted extensive research into the electron current density of the model shown in Fig. 4, and obtained the results shown in Fig. 9A to Fig. 9C. As shown in Fig. 9A to Fig. 9C, it was confirmed that the electron current density, like the hole current density, hardly changes even when the temperature changes.

[0036] The electron current and hole current flowing through the main cell region Rm flow at a predetermined ratio depending on the impurity concentrations of the drift layer 11, the base layer 12, and the emitter region 16. Therefore, in this embodiment, the ratio of the main hole current MH to the sense hole current SH is determined in advance through experiments, etc., and the ratio of the main hole current MH to the electron current in the main cell region Rm is also determined in advance. When detecting the collector current IC flowing through the main cell region Rm, the main current is detected as follows based on the determined ratio of the main hole current MH to the sense hole current SH and the ratio of the main hole current MH to the electron current in the main cell region Rm. That is, the sense hole current SH is derived from the detection voltage Vs, and the main hole current MH is derived from the sense hole current SH. The main current flowing through the main cell region Rm is then detected by deriving the electron current from the main hole current MH. In this case, since the hole current density and the electron current density are not affected by temperature as described above, there is no particular need for a circuit for performing temperature correction, etc. In other words, according to the semiconductor device of this embodiment, the main current can be detected with reduced temperature influence without performing temperature correction.

[0037] In a semiconductor device such as that of this embodiment, as described above, the sense hole current SH flows into the well layer 17 of the sense cell region Rs. In this case, if the distance d between the sense cell region Rs and the main cell region Rm is made too wide, the sense hole current SH may not easily enter the well layer 17, and the detection voltage Vs may become too small. For this reason, the inventors defined the ratio of the distance d to the thickness of the semiconductor substrate 10 as the distance ratio, and conducted extensive research into the relationship between the distance ratio and the detection voltage Vs, resulting in the results shown in FIG. 10. Note that the detection voltage Vs in FIG. 10 is a result obtained when the resistance value of the detection resistor R is 1 Ω and the collector current IC is 925 A at 25° C.

[0038] 10 , it is confirmed that the detection voltage Vs increases as the distance ratio increases when the distance ratio is 0.1 or less. Furthermore, it is confirmed that the detection voltage Vs decreases as the distance ratio increases when the distance ratio is greater than 0.1, and that when the distance ratio is 4 or greater, the detection voltage Vs becomes lower than when the distance ratio is 0. Therefore, when the main cell region Rm and the sense cell region Rs are spaced apart as in this embodiment, it is preferable that the distance d between the main cell region Rm and the sense cell region Rs be adjusted so that the distance ratio is 4 or less.

[0039] It is assumed that the reason why the detection voltage Vs becomes small when the distance ratio is 0 (i.e., when the well layer 17 and the base layer 12 are connected) is due to the following phenomenon. That is, when the detection voltage Vs is detected using the circuit configuration shown in FIG. 3 , if the well layer 17 and the base layer 12 are connected, the resistance between the well layer 17 and the base layer 12 is likely to be smaller than the detection resistor R. Then, after the sense hole current SH flows into the well layer 17, a portion of it escapes from the base layer 12 in the main cell region Rm. Therefore, when the distance ratio is 0, the sense hole current SH flowing through the detection resistor R decreases, and therefore the detection voltage Vs is assumed to become small.

[0040] Therefore, if the detection voltage Vs is lower than the desired value, it is preferable to adjust the magnitude of the detection voltage Vs appropriately by making adjustments such as increasing the resistance value of the detection resistor R. However, if the resistance value of the detection resistor R is made too high, the potential difference between the sense electrode S and the emitter electrode E becomes too large, and this potential difference may exceed the breakdown voltage between the well layer 17 and the base layer 12. For this reason, when adjusting the resistance value of the detection resistor R, it is preferable to also take into consideration the breakdown voltage between the well layer 17 and the base layer 12. Specifically, it is preferable to set the resistance value of the detection resistor R so that the potential of the sense electrode S is lower than the collector-emitter voltage of the main cell region Rm.

[0041] According to the embodiment described above, the P-type well layer 17 is formed on the drift layer 11 in the sense cell region Rs, and a portion of the hole current flows into the sense cell region Rs when the main cell region Rm is in the on state. When a detection resistor R is connected to the sense cell region Rs and the voltage across the detection resistor R is detected as a detection voltage Vs, the detection voltage Vs is not affected by temperature. Therefore, by detecting the main current flowing through the main cell region Rm based on this detection voltage Vs, the main current can be detected with the influence of temperature reduced, without performing temperature correction.

[0042] (1) In this embodiment, the well layer 17 formed in the sense cell region Rs is formed away from the base layer 12 formed in the main cell region Rm. This makes it difficult for holes that have flowed into the well layer 17 to escape from the base layer 12, making it easier to increase the detection voltage Vs.

[0043] (2) In this embodiment, by setting the distance ratio to 4 or less, the detection voltage Vs can be made larger than when the well layer 17 is connected to the base layer 12 .

[0044] Second Embodiment A second embodiment will be described. In this embodiment, the well layer 17 is connected to the base layer 12, as opposed to the first embodiment. As the other features are the same as those of the first embodiment, a description thereof will be omitted here.

[0045] In the semiconductor device of this embodiment, as shown in FIG. 11 , the base layer 12 of the main cell region Rm and the well layer 17 of the sense cell region Rs are connected. That is, the distance d between the main cell region Rm and the sense cell region Rs is set to 0, and the intermediate region Rt in the first embodiment is not disposed between the main cell region Rm and the sense cell region Rs. In this embodiment, the well layer 17 has the same depth as the outer edge base layer 12a. Note that, in such a semiconductor device, the detection voltage Vs tends to be small, as described in the first embodiment. For this reason, in this embodiment, it is preferable to appropriately adjust the resistance value of the detection resistor R.

[0046] According to the present embodiment described above, in the sense cell region Rs, the P-type well layer 17 is formed on the drift layer 11, and therefore, the same effects as those of the first embodiment can be obtained.

[0047] (1) In this embodiment, the well layer 17 is connected to the base layer 12, and no intermediate region Rt is disposed between the main cell region Rm and the sense cell region Rs. This makes it possible to reduce the size of the semiconductor device and to simplify the structure because there is no need to design a breakdown voltage for the intermediate region Rt.

[0048] (Modification of Second Embodiment) A modification of the second embodiment will be described. In the second embodiment, the well layer 17 may have the same depth as the inner edge base layer 12b, as shown in FIG. 12 . That is, the well layer 17 does not need to have a uniform depth, and the depth may be adjusted according to the pressure resistance design. For example, in FIG. 12 , a portion of the well layer 17 that is the same depth as the inner edge base layer 12b is formed between the deep portion of the well layer 17 and the base layer 12. Even with this configuration, the same effects as those of the second embodiment can be obtained.

[0049] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0050] For example, in each of the above embodiments, an example was described in which the first conductivity type was N type and the second conductivity type was P type, but the first conductivity type could also be P type and the second conductivity type could also be N type.

[0051] In each of the above embodiments, the semiconductor device may be a planar type in which the gate electrode layer 15 is disposed on one surface 10 a of the semiconductor substrate 10 , instead of a trench gate type.

[0052] Furthermore, in each of the above embodiments, the detection section connected to the sense electrode S may be a current mirror circuit or the like instead of the detection resistor R.

Claims

1. A semiconductor device comprising: a main cell region (Rm) in which a main element (Me) is formed; and a sense cell region (Rs) in which a sense element (Se) is formed; a detection unit (R) is connected to the sense element; and a main current flowing through the main element is detected based on a detection result of the detection unit; the main element and the sense element have a semiconductor substrate (10) including a drift layer (11) of a first conductivity type; the main element comprises: a base layer (12) of a second conductivity type formed on the drift layer; an emitter region (16) of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer; a gate insulating film (14) disposed on the surface of the base layer between the emitter region and the drift layer; a gate electrode layer (15) disposed on the gate insulating film; and a collector layer (19) of the second conductivity type formed on the opposite side of the drift layer to the base layer; the sense element has a well layer (17) of a second conductivity type formed on the drift layer, and comprises an emitter electrode (E) electrically connected to the emitter region and the base layer, a collector electrode (C) electrically connected to the collector layer, and a sense electrode (S) electrically connected to the well layer, wherein when a predetermined voltage is applied to the gate electrode layer, first carriers are supplied from the emitter electrode to the drift layer and second carriers are supplied from the collector electrode to the drift layer, and a portion of the second carriers supplied to the drift layer flows into the well layer.

2. The semiconductor device according to claim 1, wherein said well layer is separated from a base layer of said main cell region.

3. The semiconductor device according to claim 2, wherein the well layer has a distance ratio, which is a ratio of a distance (d) between the well layer and the base layer to a thickness of the semiconductor substrate, of 4 or less.

4. The semiconductor device according to claim 1, wherein the well layer is connected to a base layer of the main cell region.

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