Surface polarity-controlled quantum interfaces

Abstract

A device includes a substrate and a plurality of structures supported by the substrate. Each structure of the plurality of structures includes a semiconductor base, a semiconductor segment supported by the semiconductor base, and a quantum heterostructure supported by the semiconductor segment. The quantum heterostructure includes an active layer. The active layer includes a polar semiconductor material. An interface of the quantum heterostructure is disposed along a semipolar plane of the polar semiconductor material.

Description

Atty. Docket No.10110-23015A SURFACE POLARITY-CONTROLLED QUANTUM INTERFACES CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. provisional application entitled “Surface Polarity-Controlled Quantum Interfaces,” filed October 6, 2023, and assigned Serial No. 63 / 542,895, the entire disclosure of which is hereby expressly incorporated by reference. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Contract No.2118809 awarded by the National Science Foundation. The government has certain rights in the invention. BACKGROUND OF THE DISCLOSURE Field of the Disclosure

[0003] The disclosure relates generally to quantum-well heterostructures for light emitting diode (LED) and other devices. Brief Description of Related Technology

[0004] Semiconductor heterostructures, stacked by two or more dissimilar materials, have been explored in controlling band structure, polarization field, strain distribution, charge carrier confinement and mobility, and excitonic oscillator strength. Semiconductor heterostructures can provide material properties that are superior or not possible otherwise.

[0005] A significant challenge to achieving the potential of atomic-scale heterostructures is the presence of atomic substitution processes among cations with different ionicity at the heterointerface. Such substitution processes lead to interfacial composition gradients or formation of nanoclusters, preventing the realization of atomically ordered quantum heterostructures. A diffusive interface causes a reduction in electron mobility due to alloy scattering in high electron mobility transistors, as well as significantly broadened emissions and slow radiative recombination in light-emitting diodes.Atty. Docket No.10110-23015A

[0006] Extensive theoretical analysis and experimental synthesis have been devoted to improving the interface quality of semiconductor heterostructures. Despite improvements in synthesis methods and parameters, the presence of diffusive layers has remained widely observed. The presence of diffusive layers has been attributed to surface segregation, composition pulling effect, and high synthesis temperature. SUMMARY OF THE DISCLOSURE

[0007] In accordance with one aspect of the disclosure, a device includes a substrate and a plurality of structures supported by the substrate. Each structure of the plurality of structures includes a semiconductor base, a semiconductor segment supported by the semiconductor base, and a quantum heterostructure supported by the semiconductor segment. The quantum heterostructure includes an active layer. The active layer includes a polar semiconductor material. An interface of the quantum heterostructure is disposed along a semipolar plane of the polar semiconductor material.

[0008] In accordance with another aspect of the disclosure, a method of fabricating a heterostructure device includes growing semiconductor bases of an array of structures on a substrate, growing a semiconductor segment on each semiconductor base of the array of structures, and growing a quantum heterostructure on each semiconductor segment of the array of structures. Growing the semiconductor bases is configured to space apart adjacent structures of the array of structures to an extent that each semiconductor segment includes a shell portion, each semiconductor segment has a convex facet to relax strain arising from the shell portion, and the convex facet of the semiconductor segment is adjacent to the quantum heterostructure to establish an orientation of an interface of the quantum heterostructure.

[0009] In accordance with yet another aspect of the disclosure, a device includes a substrate and a plurality of structures supported by the substrate, each structure of the plurality of structures including a semiconductor base, a semiconductor segment supported by the semiconductor base, and a quantum heterostructure supported by the semiconductor segment. The semiconductor segment includes a shell portion disposed along sidewalls of the semiconductor base. The semiconductor segment has a convex facet adjacent to the quantum heterostructure. The convex facet establishes an orientation of an interface of the quantum heterostructure.

[0010] In accordance with still yet another aspect of the disclosure, a device includes a substrate and a plurality of structures supported by the substrate, each structure of theAtty. Docket No.10110-23015A plurality of structures including a Group III-nitride base, first and second Group III-nitride charge carrier injection layers supported by the Group III-nitride base, and a quantum heterostructure disposed between the first and second charge carrier injection layers. The quantum heterostructure includes a pair of Group III-nitride barrier layers, and a Group III- nitride active layer disposed between the pair of Group III-nitride barrier layers. An interface between one of the pair of Group III-nitride barrier layers and the Group III-nitride active layer is disposed along a semipolar plane of the Group III-nitride active layer.

[0011] In accordance with still yet another aspect of the disclosure, a device includes a substrate and a plurality of structures supported by the substrate, each structure of the plurality of structures including a Group III-nitride base, first and second Group III-nitride charge carrier injection layers supported by the Group III-nitride base, and a quantum heterostructure disposed between the first and second charge carrier injection layers. The first Group III-nitride charge carrier injection layer includes a shell portion disposed along sidewalls of the Group III-nitride base. The quantum heterostructure includes a pair of Group III-nitride barrier layers and a Group III-nitride active layer disposed between the pair of Group III-nitride barrier layers. The first Group III-nitride charge carrier injection layer has a convex top facet adjacent to the quantum heterostructure. The convex facet establishes an orientation of an interface between one of the pair of Group III-nitride barrier layers and the Group III-nitride active layer.

[0012] In connection with any one of the aforementioned aspects, the devices and / or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The semipolar plane corresponds with a morphology of the semiconductor segment. The semiconductor segment includes a shell portion disposed along sidewalls of the semiconductor base. The plurality of structures has a lateral density along the substrate such that the shell portion of the semiconductor segment is sufficiently significant such that strain relaxation is achieved along a top facet of the semiconductor segment. The semiconductor segment has a convex top facet adjacent to the quantum heterostructure. The convex top facet of the semiconductor segment establishes an orientation of the interface of the quantum heterostructure. The semipolar plane is the (11^03^) plane. The heterostructure includes a barrier layer in contact with the active layer at the interface of the quantum heterostructure. The active layer has a thickness for quantum confinement of charge carriers. The active layer has a countable number of monolayers of a Group III-nitride material. The active layer includes gallium nitride. The quantum heterostructure includes a pair of barrier layers between which the active layer is disposed. Each barrier layer of the pair of barrier layers includes aluminumAtty. Docket No.10110-23015A nitride. The semiconductor segment includes aluminum nitride doped to act as a charge carrier injection layer. The semiconductor base includes gallium nitride. Each structure of the plurality of structures includes a nanowire oriented perpendicularly to the substrate. Growing the quantum heterostructure includes growing a barrier layer of the quantum heterostructure, and growing an active layer of the quantum heterostructure, the active layer including a polar semiconductor material. The active layer is adjacent to the barrier layer to define the interface of the quantum heterostructure. The interface is disposed along a semipolar plane of the polar semiconductor material. Growing the semiconductor bases, growing the semiconductor segment, and growing the quantum heterostructure include implementing respective epitaxial growth procedures configured such that the quantum heterostructure grows along the ^0001^^ direction and quantum wells of the quantum heterostructure are incorporated on a plane other than the (0001^) plane to establish the interface of the quantum heterostructure. The plane on which the quantum wells are incorporated is the (11^03^) plane. Growing the semiconductor bases, growing the semiconductor segment, and growing the quantum heterostructure, are performed under nitrogen-rich conditions. Growing the quantum heterostructure includes closing, at an end of a growth period of a barrier layer of the quantum heterostructure, a shutter for a Group III material while leaving a shutter for nitrogen open for a length of time to consume extra Group III atoms at the surface of the barrier layer. The quantum heterostructure includes an active layer. The active layer includes a polar semiconductor material. The interface of the quantum heterostructure is disposed along a semipolar plane of the polar semiconductor material. BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0013] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.

[0014] Figure 1 depicts structural characterizations of example GaN / AlN quantum heterostructures on the c-plane of AlN nanowire segments, including (a) a low-magnification HAADF-STEM image of monolayer GaN incorporated on the c-plane of an AlN nanowire segment, (b) a high-resolution HAADF-STEM image of an orange-boxed region in the HAADF-STEM image, in which the monolayer GaN as well as the AlN barriers are indicated by arrows, (c) a graphical plot of ADF intensity analysis of a yellow-boxed region in the high- resolution HAADF-STEM image, in which a highlighted region indicates a cation intermixingAtty. Docket No.10110-23015A region, and (d) a HAADF-STEM image of five periods of digital alloys of two GaN monolayers and six AlN monolayers (referred to herein as "Sample A2").

[0015] Figure 2 depicts structural characterizations of GaN / AlN quantum heterostructures on a semipolar plane in accordance with one example, including (a) a low-magnification HAADF-STEM image of 10 periods of GaN / AlN digital alloys embedded in an AlN nanowire, (b) a HAADF-STEM image of an orange-boxed region in the HAADF-STEM image, (c) a high-resolution HAADF-STEM image of a green-boxed region in the HAADF-STEM image, (d) a graphical representation of the fast Fourier transform of the high-resolution HAADF- STEM image, (e) a graphical plot of ADF intensity analysis of the yellow-boxed region in the high-resolution HAADF-STEM image, and (f) a HAADF-STEM image of an active region of an example GaN / AlN quantum heterostructure having two GaN monolayers and six AlN monolayers (referred to herein as "Sample B2").

[0016] Figure 3 depicts first-principles density functional theory calculations and analysis of atomic arrangements on c-planes and on semipolar planes, including (a) a schematic representation of a GaN (0001^) surface covered with an Al adlayer, in which each Al adatom forms one broken bond with an underlying N anion, (b) a schematic representation of Al adatoms on the (11^03^) surface of GaN, in which the two-coordinated Al adatom labeled as Al2C forms two bonds with adjacent N anions while the one-coordinated Al adatom labeled as Al1C forms one bond with an adjacent N anion, and in which the three(four)-coordinated Ga cation labeled as Ga3C (or Ga4C) forms three (four) bonds with adjacent N anions, and (c-g) a number of schematic representations of cation substitution along with the corresponding calculated substitutional energies, in which dashed red circles enclose the Al adatom and the Ga cation involved in the substitution process.

[0017] Figure 4 depicts luminescence properties of example GaN / AlN quantum heterostructures on the c-plane and on the semipolar plane, including (a) a graphical plot of temperature-dependent photoluminescence (PL) spectra of a Sample B2 example measured with an excitation power of 420 mW / cm2, (b) a graphical plot of PL peak energy vs. excitation power for a Sample A2 example (green circles) and a Sample B2 example (blue squares), (c) a schematic representation of a deep UV LED device based on GaN / AlN heterostructures in accordance with one example, (d) pptical images of a deep UV LED device on a Si(111) substrate in accordance with one example, and (e) a graphical plot of current-dependent electroluminescence spectra of an example deep UV LED device with semipolar plane GaN / AlN digital alloys as the active region.Atty. Docket No.10110-23015A

[0018] Figure 5 is a schematic representation of a device having an array of nanowires with a quantum heterostructure having surface polarity-controlled quantum interfaces in accordance with one example.

[0019] Figure 6 is a flow diagram of a method of fabricating a device having an array of nanowires with a quantum heterostructure having surface polarity-controlled quantum interfaces in accordance with one example.

[0020] The embodiments of the disclosed devices and methods may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein. DETAILED DESCRIPTION OF THE DISCLOSURE

[0021] Devices having quantum heterostructure interfaces oriented in accordance with surface polarity are described. For instance, in some cases, the quantum heterostructure interfaces are disposed along a semipolar plane of a polar semiconductor material. Nanostructures of the disclosed devices may include a segment having a top facet configured to establish the orientation of the quantum heterostructure interfaces.

[0022] Methods of fabricating devices having heterostructure interfaces oriented in accordance with surface polarity are also described. The disclosed methods include epitaxial growth procedures that establish the orientation or configuration of the top facet of the nanostructure segment. As described herein, the spacing or density of the nanostructures may be used to control an extent to which a shell is formed about a nanostructure base during growth. The strain resulting from the presence of the shell is relaxed via the morphology of the top facet. For example, the top facet may have a convex shape, which, in turn, establishes the orientation of the quantum heterostructure interfaces.

[0023] As described herein, interfacial diffusion in GaN / AlN heterostructures strongly depends on the surface polarities. Examples of ultrathin GaN / AlN digital alloys with nearly diffusion-free heterointerfaces on the semipolar plane were achieved, in contrast to the severe interfacial diffusion observed on the conventional c-plane. The resulting atomically ordered quantum heterostructures exhibited superior optical properties including high internal quantum efficiency and absence of quantum-confined Stark effect. Moreover, the surface polarities can be readily controlled through varying the strain relaxation process in the core-shell nanostructure ensembles.Atty. Docket No.10110-23015A

[0024] The nanostructures of the disclosed devices are configured in view of the strong dependence of interfacial diffusion on surface polarity observed in example GaN / AlN quantum heterostructures. Example GaN / AlN quantum heterostructures with a near-perfect quantum interface are achieved on the semipolar plane. Theoretical calculations show that the atomic substitution process is significantly suppressed on the semipolar plane relative to the conventional c-plane. The resulting interdiffusion-free ultrathin GaN layers exhibit efficient luminescence and are nearly free of the quantum-confined Stark effect. Control of the incorporation sites during growth is achieved by controlling or varying the surface polarities in the nanostructures.

[0025] Described herein are examples of devices with heterostructures having atomically ordered heterointerfaces. The atomically ordered heterointerfaces are formed via interface engineering at the atomic scale implemented by the disclosed methods. The disclosed methods and devices address the strong diffusive feature of interfacial atoms in heterostructures based on the realization of a strong dependence of interfacial diffusion on the surface polarity. As described herein, near-perfect quantum interfaces are formed and attained on the semipolar plane instead of the conventional c-plane of GaN / AlN heterostructures. The chemical bonding configurations on the semipolar plane significantly suppress the cation substitution process as evidenced by, e.g., first-principles calculations. The suppression of cation substitution leads to an atomically sharp interface. Moreover, the surface polarity of GaN / AlN heterostructures is controlled by varying the strain relaxation process in connection with core-shell nanostructures.

[0026] Example LED devices are described herein that present confined, interdiffusion-free ultrathin GaN quantum wells. The example LED devices exhibit a record-high internal quantum efficiency of about 75%. Examples of deep ultraviolet light-emitting diodes are fabricated utilizing a scalable and robust fabrication method. The electroluminescence emission of the example devices is nearly free of the quantum-confined Stark effect, which is useful for ultra-stable device operation. The disclosed devices and fabrication methods demonstrate the achievement of atomically ordered quantum heterostructures for III-nitride materials as well as other polar materials.

[0027] Although described herein in connection with LED devices, the heterostructures described herein are useful in connection with a wide variety of devices. For instance, the heterostructures may be used in various non-emissive devices, such as detectors. Moreover, other types of emissive devices may also be formed, including, for instance, various types of laser devices.Atty. Docket No.10110-23015A

[0028] Although described in connection with III-nitride-based nanostructures and heterostructures (e.g., aluminum nitride (AlN) barrier layers and GaN active layers), the disclosed devices and methods may use other semiconductor materials. For example, Group III-arsenide materials, perovskite materials, and other polar materials may be used in any one or more of the nanostructure segments or heterostructure layers. Other Group III- nitride materials may also be used. For example, the active layers may be composed of, or otherwise include, indium nitride (InN). Various compound semiconductors (e.g., ternary semiconductors) may be used. The composition (e.g., cation composition) of the segments of the nanostructures (or the heterostructure layers thereof) may also vary. For instance, the composition of the barrier layers may gradually change (e.g., from AlN to GaN or vice versa) at an interface with one of the charge carrier injection layers. In some cases, the barrier layers may be composed of, or otherwise include, AlGaN or, if InN is used for the active layer, GaN or InGaAlN.

[0029] Although described herein in connection with nanowire arrays, the disclosed devices and methods may include or form a variety of nanostructures. The shape, dimensions, aspect ratio, and other aspects of the nanostructures may thus vary from the examples shown and described.

[0030] In the examples described below, 3-inch Si wafers with <111> orientations were used for the epitaxy of GaN / AlN heterostructures. The wafers were chemically and thermally cleaned. Further details regarding example cleaning processes can be found in Aiello A, et al., "Deep Ultraviolet Luminescence Due to Extreme Confinement in Monolayer GaN / Al(Ga)N Nanowire and Planar Heterostructures," Nano Lett 19(11):7852-7858 (2019), the entire disclosure of which is incorporated by reference.

[0031] The quantum heterostructures of the example devices described below were grown on a nanostructure platform. The growth may be implemented under nitrogen-rich conditions in which the strain effect is mitigated. As described below, ultrathin GaN / AlN quantum wells (QWs) in AlN nanowire ensembles were grown on Si substrate by plasma- assisted molecular beam epitaxy (PAMBE). The epitaxy includes an initial spontaneous formation of a GaN nanowire template for promoting the nanowire morphology followed by the formation of an AlN segment before the growth of the GaN / AlN quantum wells. The samples and examples addressed below include two series that differ in the crystalline planes on which the GaN quantum wells were incorporated (or along which the GaN quantum wells were oriented). The samples in Series A have quantum wells on the c-plane. The examples in Series B have quantum wells on the semipolar plane. The growth parameters for the samples and examples are set forth below in Table I.Atty. Docket No.10110-23015A Table I. Growth conditions of Samples A1, A2 and Examples B1, B2

[0032] To form the sample and example devices, Si-doped n-type GaN nanowire templates were first grown at a substrate temperature of 780 ºC. The growth durations of the GaN nanowire were 60 mins and 20 mins in Series A and B, respectively. Then, Si-doped n-type AlN nanowires of about 180 nm were grown at a substrate temperature of 910 ºC. GaN / AlN digital alloys in the active region of the samples and examples were grown using identical conditions, including a substrate temperature of 910 ºC and N-rich conditions with the nominal Ga / N ratio of about 0.3 and Al / N ratio of about 0.25, except for the number of periods and GaN ML and AlN thickness (see Table I). The growth rate was about 0.1 monolayer / s. During the growth of the deep UV nanowire LED structures, an Mg-doped p- type AlN segment and GaN contact layer were grown on top of the active region, in which the Ga / N ratio of 0.2 and Al / N ratio of 0.2 was used. Details regarding a method for achieving effective p-type doping in AlN nanostructures are set forth in the publications referenced herein, including Wu Y, et al., "Controlling Defect Formation of Nanoscale AlN: Toward Efficient Current Conduction of Ultrawide‐Bandgap Semiconductors," Advanced Electronic Materials 6(9) (2020), the entire disclosure of which is hereby incorporated by reference.

[0033] The example deep UV LED devices having the nanowire ensembles were fabricated as follows. In this case, device fabrication included atomic layer deposition (ALD) of 60 nm SiO2to passivate the sidewall of the nanowire arrays and planarize the nanowire array. Then a top-down etching process was performed using fluorine-based reactive ion etching (RIE) to reveal the top p-Al(Ga)N of the nanowire array. Another 200 nm SiO2was deposited by plasma-enhanced chemical vapor deposition (PECVD). The current injection window was configured by lithography followed by another fluorine-based RIE. A metal contact on top of the nanowire LED was fabricated based on lithography and metallization of 10 nm Ni and 10Atty. Docket No.10110-23015A nm Au. Finally, metal pads of 80 nm Au and backside coating of 20 nm Ti and 80 nm Au were fabricated.

[0034] As described herein, the density or spacing of the nanostructures of the disclosed devices may be useful in connection with establishing the crystalline plane and surface polarity of the quantum heterostructure interfaces. The lateral density or spacing of the nanostructures may be controlled or established via selective area growth (or selective area epitaxy). Use of selective area growth (or selective area epitaxy) to form nanowire arrays is described in U.S. Patent Publication No.2022 / 0367561 ("High Efficiency InGaN Light Emitting Diodes") and Liu et al., "Selective area epitaxy of AlGaN nanowire arrays across nearly the entire compositional range for deep ultraviolet photonics," Optics Express Vol.25, Issue 24, pp.30494-30502 (2017), the entire disclosures of which are hereby incorporated by reference.

[0035] Further details regarding selective area growth / epitaxy, as well as other aspects of the growth of the nanostructure platform and quantum heterostructures of the disclosed devices, are set forth in International Patent Publication WO2021133910 ("Group III-nitride excitonic heterostructures"), U.S. Patent Nos.8,563,395 ("Method of growing uniform semiconductor nanowires without foreign metal catalyst and devices thereof"), U.S. Patent No.9356091 ("Method for fabricating optical semiconductor tubes and devices thereof"), and U.S. Patent Publication No.2022 / 0165913 ("Monolithically Integrated InGaN / GaN Quantum Nanowire Devices"), the entire disclosures of which are hereby incorporated by reference.

[0036] Figure 1, part a, shows a low magnification high angle angular dark field (HAADF) scanning transmission electron microscopy (STEM) image of Sample A1 with a monolayer GaN quantum well embedded in an AlN nanowire. The ultrathin GaN quantum well is embedded on the flat c-plane of an AlN segment and intersects the entire nanowire. A high- resolution STEM image of the quantum well region (see dashed, box-shaped region) is shown in Figure 1, part b, where the GaN monolayer forms an atomically sharp interface with the underlying AlN. However, random contrast variations are present at the AlN-on-GaN interface, suggesting a strong intermixing of Al and Ga cations. Figure 1, part c, is the averaged line profiles across the interface (see dash, box-shaped ed region in Figure 1, part b), in which random intensity variations up to 6 monolayers are observed after the monolayer GaN, as indicated by a highlighted region 100. The asymmetric interfacial abruptness has been widely observed in Al(Ga)N heterostructures synthesized using MBE and metalorganic chemical vapor deposition (MOCVD). Although the quantum well remains distinct when separated by thick AlN barriers, the intermixing issue is exacerbated when the thickness of the AlN barrier is comparable to, or smaller than the cation diffusion length.Atty. Docket No.10110-23015A

[0037] Sample A2 has an active region of five periods of 2 monolayers of GaN and 6 monolayers of AlN. However, the GaN quantum wells can barely be distinguished in the high-resolution STEM image as shown of Figure 1, part d. Such interdiffusion even occurs at a much lower growth temperature, indicating a low thermal activation energy of the atomic substitution process on the c-plane.

[0038] This interdiffusion issue can be alleviated by incorporating GaN quantum wells on semipolar planes. Figure 2, part a, shows low-magnification HAADF-STEM images of Example B1, where an active region of a nanowire heterostructure has 10 periods of two monolayers of GaN and 18 monolayers of AlN. Unlike the GaN / AlN digital alloys in the samples of Series A, the quantum wells are incorporated on {11^03^} semipolar planes while the growth is along the^0001^^direction, as shown in Figures 2, parts b-d. In contrast to the smeared interface in the samples of Series A, Figure 2, part e, shows interfacial diffusion neither before nor after the GaN quantum well, which is further evidenced by the distinct contrast variation across the interface in the dashed, box-shaped region of Figure 2, part c. This characteristic remains true for closely separated GaN quantum wells as shown in Figure 2, part f, in which the active region of Example B2 has two monolayers of GaN with six monolayer AlN barriers.

[0039] Density functional theory analysis of the GaN / AlN heterostructures was conducted. The pronounced dependence of GaN / AlN interface quality on the incorporation plane was analyzed by investigating the chemical bonding configurations and atomic arrangements of the growth front. The two front facets of GaN, namely, the (0001^) plane and the (11^03^) plane, are covered by one monolayer of Al, as shown in Figure 3, parts a and b. The models were obtained from density functional theory (DFT)-based geometry optimization, which are further used in the calculation of substitutional energy. The obtained results show that the substitution of an Al adatom with a Ga atom from the first subsurface cation layer on the (0001^) plane, as indicated by the arrow and dashed circles in Figure 3, part c, provides a substitutional energy of -2.74 eV, driving the cation exchange process over an extended distance, i.e., a diffusive interface. The Al adatoms on (11^03^) plane have two distinct types of sites in the surface layer. The sites are referred to as Al1C and Al2C, as shown in Figure 3, part b. The adatoms at the Al1C sites are bonded to a single N atom in the layer below, which resembles the bonding configuration of Al adatom on the (0001^) surface. The Al adatoms at the Al2C sites bond with two adjacent N atoms, one in the underlying (0001^) plane and another in the layer above. The Al adatoms in the two sites can substitute three-coordinated and four-coordinated Ga atoms (labeled as Ga3Cand Ga4Cin Figure 3, part b). These four possible combinations of substitution are schematically illustrated in Figure 3, parts d-g,Atty. Docket No.10110-23015A along with the corresponding calculated substitutional energies. The atomic substitution with the smallest energy reduction, Al2C↔Ga3C, is -1.04 eV, which is 1.7 eV less negative than that on the c-plane. Therefore, although the GaN / AlN digital alloys in Example B2 and Sample A2 were grown using the same conditions, the less negative substitutional energy in Example B2 can stabilize the Al adatoms on the semipolar plane and eliminate the diffusion at the interface.

[0040] The substitution process of Al and Ga in the deeper subsurface was also investigated. The result reveals that all substitutional energies in the models are close to zero, which can be attributed to the highly or fully-coordinated Al or Ga in subsurface layers. Hence, the intrinsic coordination structures of the outmost surface layers, instead of subsurface layers, play a more significant role during heteroepitaxy.

[0041] The luminescence properties of an example device having the above-described quantum heterostructure are now described. Given a GaN / AlN quantum heterostructure with a near-perfect interface on the semipolar plane, enhanced quantum confinement of charge carriers within the GaN quantum well is attained. Temperature-dependent photoluminescence (PL) measurements were performed on Example B2 and Sample A2 under the same excitation conditions of 420 mW / cm2. The corresponding spectra for Example B2 are shown in Figure 4, part a. The origin of the emission peaks can be discerned through comparison with the spectra of AlN nanowires without embedded GaN quantum wells, where an emission at about 5.93 eV is related to the excitonic emission from AlN and emissions between 4.0 and 5.5 eV are related to the GaN / AlN digital alloys. The measured room-temperature peak energy of Example B2 is about 5.1 eV, larger than the peak energy of about 4 eV obtained from Sample A2.

[0042] The room-temperature internal quantum efficiency (IQE) is estimated by taking the integrated intensity ratio between room temperature and 12 K under the assumption that the IQE is unity at the lowest temperature. The measured IQE of the GaN / AlN digital alloys in Example B2 was about 75%, which is more than 3 times higher than the 23% IQE measured from Sample A2. While the intended thickness of the GaN / AlN digital alloys in both cases is the same, the Al-Ga intermixing on the c-plane (Sample A2) leads to the formation of a wide Al(Ga)N quantum well with large inhomogeneity along with an increased probability to encounter nonradiative recombination centers and therefore a less efficient radiative recombination process.

[0043] Considering example GaN quantum wells with a nominal thickness of two monolayers and AlN barriers with a thickness of 6 monolayers, the calculated internalAtty. Docket No.10110-23015A electrostatic field can be up to about 10 MV / cm for GaN / AlN quantum wells. Despite this large built-in electric field, the quantum-contained Stark effect (QCSE) is expected to be significantly suppressed in an atomically thin quantum well. The large band structure offset between GaN and AlN can provide extreme quantum-confinement of charge carriers and ensure excellent electron-hole wavefunction overlap under various carrier densities. Indeed, the PL energy of Example B2 shows negligible shift with excitation power as shown by the squares in Figure 4, part b. Meanwhile, a monotonic blue shift of the peak energy from 4.014 eV to 4.117 eV with excitation power was observed from Sample A2 (circles in Figure 4, part b) as a result of the increasing screening of the QCSE. Moreover, the complex spatial landscape for the electronic states could be formed during Al-Ga intermixing, which leads to the presence of localized states. With increasing excitation power, extra generated charge carriers tend to occupy the higher localized states, which also contribute to the blue-shift in emission energies.

[0044] Deep UV (DUV) LED structures with two monolayers GaN / 6 monolayers AlN as an active region were grown and fabricated as schematically shown in Figure 4, part c. In one of the LED structures, the active region is grown on the c-plane. In the other LED structure, the active region is grown on the semipolar plane. In this case, the fabrication method includes a SiO2 filling followed by a reactive etching process to define a current injection window, which is more scalable and robust than the tilted metal deposition method. In addition to the details provided above for the fabrication of the DUV LED devices, further information regarding example fabrication processes is set forth below in connection with Figure 6.

[0045] The current-voltage characteristics of devices based on the c-plane and semipolar plane of GaN / AlN show similar electrical properties including a rectification ratio of over 5 orders of magnitude at ±10 V. The typical current-dependent electroluminescence (EL) spectra of the devices with semipolar GaN / AlN as an active region are shown in Figure 4, part e. The peak energies show a slight red shift from 5.07 eV to 5.02 eV with increasing currents, which can be explained by heating effect-induced bandgap renormalization. In contrast, DUV LEDs with c-plane GaN / AlN as the active region show a significant blue-shift with increasing injection current for the reasons set forth above.

[0046] Further details are now provided regarding the manner in which the surface polarity of the quantum heterostructures of the disclosed devices is controlled. The control of surface polarity and incorporation sites of GaN / AlN heterostructures, i.e., c-plane versus semipolar plane, has a crystalline origin. Among the samples and examples addressed above, the orientation of the embedded GaN quantum wells is parallel to the faceted top ofAtty. Docket No.10110-23015A the nanowire ensemble, as most clearly seen in Figure 1, part a, and Figure 2, part a. The incorporation sites of the GaN quantum wells are defined or established by the morphology of the growth front of the AlN segment. While the bottom GaN nanowire ensembles always have a flat (0001^) facet, the top facet of the AlN segment on the GaN nanowire can be tuned or toggled between (11^0^)̅ and (0001^) by varying the bottom GaN nanowire density. For example, experiments demonstrated that the heteroepitaxy of AlN on GaN nanowires with a density of about 4×1010cm-2resulted in a flat facet. In contrast, the heteroepitaxy of AlN on GaN nanowires with a density of about 2×1010cm-2resulted in a convex semipolar facet. The growth front of various facets is generally attributed to the anisotropy of the growth rate along different crystalline axes and has been widely studied using Wuff’s plot. However, high-resolution annular bright field (ABF) characterizations on both samples and examples from Series A and B show that the nanowires have the same growth direction of [0001^] orientation, consistent with previous reports of III-nitride nanowires grown on a Si substrate by MBE.

[0047] The two dissimilar top facets of AlN can be attributed to different strain relaxation processes during the initial heteroepitaxy of the AlN nanowire on top of the GaN nanowire. AlN tends to be formed on both the top (c-plane) and sidewall (m-planes) of GaN nanowires due to the limited migration length of Al adatoms. The coverage of the Al adatoms on the sidewall is greatly affected by the shadowing effect of adjacent nanowires. For GaN nanowire ensembles with high density (small spacing between neighboring nanowires), a thin and short AlN shell tends to be formed. In such cases, coherent biaxial tensile strain is stored in the AlN segment initially and strain relaxation is achieved through the sidewalls as the AlN segment growth proceeds. For thick and long AlN shells formed as a result of low GaN nanowire ensemble density (larger nanowire spacing), the AlN shell at the sidewall causes a significant accumulation of strain, particularly at the periphery of the AlN segment, which leads to strain relaxation through the generation of high index facets on the top of the AlN segment.

[0048] Figure 5 depicts a device 500 having a quantum heterostructure 502 with a surface polarity controlled interface in accordance with one example. The device 500 may be configured as an LED device, such as a deep UV LED device. Only a portion of the device 500 is shown schematically for ease in illustration of the quantum heterostructure interface. One or more aspects or features of the heterostructure 502 and / or the device 500 are also depicted in a schematic fashion for ease in illustration and accordingly may not be shown to scale.Atty. Docket No.10110-23015A

[0049] The device 500 includes a substrate 504 and an array of structures 506 supported by the substrate 504. The substrate 504 may be composed of, or otherwise include, silicon. Additional or alternative materials may be included. In this example, the silicon is n-type doped. The doping profile may vary in other cases. For instance, the substrate 504 may be p-type doped, or otherwise include p-type doping, in cases in which the dopant polarities in each structure are reversed.

[0050] Each structure 506 may be configured as a nanowire or other nanostructure. Each structure 506 includes a semiconductor base 508 (e.g., a Group III-nitride base), a pair of semiconductor segments 510, 512 supported by the semiconductor base 508, and the quantum heterostructure 502 disposed between the pair of semiconductor segments 510, 512. The semiconductor segments 510, 512 may be doped and / or otherwise configured to act as charge carrier injection layers (e.g., Group III-nitride charge carrier injection layers).

[0051] The lower and upper charge carrier injection layers 510, 512 may be in contact with opposite ends of the quantum heterostructure 502. In this example, the base 508 is n-type doped, the lower charge carrier injection layer 510 is n-type doped, and the upper charge carrier injection layer is p-type doped 512. Each structure 506 may also include a contact layer 514 (e.g., a Group III-nitride contact layer) supported by, and in contact with, the upper charge carrier injection layer 512. In this example, the contact layer 514 is p-type doped. The dopant polarities of the aforementioned segments and layers may be reversed in other cases. The composition or nature of one or more metal contacts of the device 500 in such cases may vary accordingly.

[0052] The quantum heterostructure 502 of each nanostructure 506 includes one or more pairs of barrier layers 516 (e.g., Group III-nitride barrier layers), and an active layer 518 (e.g., a Group III-nitride active layer) disposed between each pair of barrier layers 516. The barrier layers 516 and the active layer 518 may be in contact with one another and disposed in a stacked arrangement as shown. In the example of Figure 5, five barrier layers 516 are provided in the stacked arrangement to establish four pairs of barrier layers 516. Disposed between each one of the four pairs is a respective one of the active layers 518. As a result, in this example, the quantum heterostructure 502 includes three active layers 518. The number of barrier layers 516 and active layers 518 may be greater or lesser in other cases. For instance, in one example, a single pair of barrier layers 516 may be provided, along with a single active layer 518.

[0053] In some cases, each active layer 518 is composed of, or otherwise includes, gallium nitride. In some cases, each barrier layer 516 is composed of, or otherwise includes,Atty. Docket No.10110-23015A aluminum nitride. The lower and upper charge carrier injection layers 510, 512 may be composed of, or otherwise include, aluminum nitride (AlN). The AlN of the lower charge carrier injection layer 510 may be doped with silicon. The AlN of the upper charge carrier injection layer 512 may be doped with magnesium. The base 508 may be composed of, or otherwise includes, gallium nitride. Alternative or additional semiconductor (e.g., Group III- nitride) materials may be used in any one or more of the above-referenced layers.

[0054] Each structure 506 may be or include a nanostructure. In the example of Figure 5, each structure 506 of the plurality of structures is configured as, or otherwise includes, a nanowire or nanorod oriented perpendicularly to the substrate. The dimensions, shape, cross-sectional shape, and other characteristics of the structures 506 may vary. For instance, each structure 506 may be or include a microstructure.

[0055] Each active layer 518 has a thickness for quantum confinement of charge carriers. In some cases, the thickness of the active layer 518 corresponds with a monolayer of the semiconductor material of which the active layer is composed. In other cases, the thickness of the active layer 518 corresponds with a bilayer (i.e., two monolayers) of a semiconductor (e.g., Group III-nitride) material of which the active layer 518 is composed. Other thicknesses may be used. For instance, the active layer 518 may have any countable number of monolayers of a semiconductor material of which the active layer 518 is composed.

[0056] In some cases (e.g., Group III-nitride cases), at least one of the pair of barrier layers 516 has a nitride surface adjacent to one of the active layers 518. For instance, the nitride surface of the barrier layer 516 on which the active layer 518 is grown is free of a Group III element of which the pair of barrier layers 516 are composed.

[0057] Each barrier layer 516 of each pair of barrier layers may have a thickness that corresponds with a countable number of monolayers of a semiconductor (e.g., Group III- nitride) material of which the barrier layers 516 are composed. A variety of thicknesses may be used, as described below.

[0058] In one example, the quantum heterostructure 502 of each structure 506 is grown on an n-type Si wafer using a Veeco GEN II MBE system equipped with a radio frequency plasma-assisted nitrogen source. Prior to loading into the MBE system, the Si wafer may be cleaned in buffered hydrofluoric acid solution. Si-doped GaN nanowires are first grown directly on the Si substrate.

[0059] As described herein, the active layer(s) 518 may be composed of, or otherwise include, a polar semiconductor material, and the interfaces of the quantum heterostructureAtty. Docket No.10110-23015A 502 are disposed along a semipolar plane of the polar semiconductor material. In the schematic depiction of Figure 5, the interfaces are disposed along a convex-shaped surface of the active layer 518.

[0060] The semipolar plane corresponds with a morphology of the lower semiconductor segment acting as one of the charge carrier injection layers 510. As described herein, the semiconductor segment 510 includes a shell portion 520 disposed along sidewalls of the semiconductor base 508. A portion of the base 508 thus defines a core 522 about which the shell 520 is disposed as shown in Figure 5.

[0061] As described herein, the array of structures 506 has a lateral density along the substrate 504 such that the shell portion 520 of the semiconductor segment 510 reaches a sufficiently significant size such that strain relaxation is achieved along a top facet of the semiconductor segment 510. As schematically shown in Figure 5, the semiconductor segment 510 in this example accordingly has a convex top facet adjacent to the quantum heterostructure 502 to relieve the stress. The convex facet establishes an orientation of each interface of the quantum heterostructure 502 (e.g., each interface between one of the pair of Group III-nitride barrier layers 516 and the Group III-nitride active layer 518). As described herein, in some cases, the semipolar plane is the (11^03^) plane. Alternative oradditional semipolar planes include, without limitation, the ^21^1^ 0^ and ^01^ 11^ planes.

[0062] Figure 6 depicts a method 600 of fabricating a heterostructure device in accordance with one example. The method 600 may be used to manufacture any type of heterostructure device described herein or another type of heterostructure device. The method 600 may include additional, fewer, or alternative acts. For instance, the method 600 may or may not include one or more acts directed to preparing a substrate (act 602).

[0063] The method 600 may begin with an act 602 in which a substrate is prepared. The substrate may be or be formed from a n-type silicon (Si) wafer. Other semiconductors and substrates may be used. Preparation of the substrate may include one or more thermal diffusion or other doping procedures. In some cases, the act 602 may include one or more doping procedures to establish one or more n-type layers or regions.

[0064] In an act 604, one or more n-metal contacts are deposited on a backside of the substrate. In some cases, the act 604 includes deposition of an adhesion metal layer (act 606) and a contact metal later (act 608).

[0065] The method 600 includes an act 610 in which bases (e.g., Group III-nitride bases) of an array of structures are grown on the substrate. The structures may be nanowires or otherAtty. Docket No.10110-23015A nanostructures. The act 610 may include implementation of a plasma-assisted molecular beam epitaxy procedure. The procedure may be implemented under nitrogen-rich conditions. In one example, the growth conditions are as follows: a growth temperature of 790oC for 1.5 h, a Ga beam equivalent pressure of ~6×10-8Torr, a nitrogen flow rate of 1 standard cubic centimeter per minute (sccm), and a plasma power of 350 W. The nanowires provide platforms or other structures for the heterostructures formed in the following steps. Other platforms or structures may be formed. For instance, the structures may be microstructures.

[0066] The act 610 may include an act 611 in which a selective area epitaxy (SAE) or selective area growth (SAG) procedure is implemented. The SAE procedure may be configured to establish a lateral density or spacing of the array of structures.

[0067] A lower charge carrier injection layer (e.g., a Group III-nitride charge carrier injection layer) or other semiconductor segment is then grown on each Group III-nitride base of the array of nanostructures in an act 612. The injection layer may be doped (e.g., Si-doped) for injection of electrons.

[0068] In an act 614, a quantum heterostructure is grown on each lower charge carrier injection layer of the array of nanostructures. The quantum heterostructures may be grown under Nitrogen-rich conditions (act 616). The act 614 may include growing a barrier layer (e.g., a Group III-nitride barrier layer) with a nitride surface (act 618), and growing an active layer (e.g., a Group III-nitride active layer) on the nitride surface (620). Additional active layers, and surrounding barrier layers, may be grown. The active layer has a thickness for quantum confinement of charge carriers as described herein.

[0069] In some cases (e.g., Group III-nitride cases), growing the barrier layer with the nitride surface may include closing, at an end of a growth period, a shutter for a Group III material (e.g., Al) while leaving a shutter for nitrogen open for a length of time to consume extra Group III atoms at the surface of the barrier layer. In some cases, the Al shutter may be closed for about 10 minutes. The time period length may vary. For instance, the length of time may be on the order of minutes, or longer.

[0070] In an act 622, an upper charge carrier injection layer (e.g., a Group III-nitride charge carrier injection layer) is grown on each quantum heterostructure of the array of the nanostructures. The upper charge carrier injection layer may be doped (e.g., Mg-doped) to act as a hole injection layer. The act 622 may also include growing a p-contact layer on each charge carrier injection layer.Atty. Docket No.10110-23015A

[0071] The method 600 may further include depositing one or more metal contacts on the nanostructures in an act 624. In some cases, the act 624 includes acts 626 and 628 in which adhesion and contact metal layers are deposited using a tilting angle deposition procedure. Alternatively or additionally, a metal grid contact is deposited in an act 630.

[0072] As described herein, the act 610 in which the semiconductor bases are grown is configured to space apart adjacent structures of the array of structures to an extent that each lower charge carrier injection layer (or other semiconductor segment) includes a shell portion. In some cases, each semiconductor segment has a convex facet to relax strain arising from the shell portion. The convex facet of the semiconductor segment is adjacent to the quantum heterostructure to establish an orientation of an interface of the quantum heterostructure. Thus, even though the growth procedures of the acts 610, 612, 614, 622 are configured such that the quantum heterostructure grows along the ^0001^^ direction, the quantum wells of the quantum heterostructure are incorporated on a plane other than the (0001^) plane. Instead, the plane on which the quantum wells are incorporated may be a semipolar plane of the polar semiconductor of the active layer, such as the (11^03^) plane.

[0073] One or more of the growth procedures of the method 600 may be performed under nitrogen-rich conditions. Such nitrogen-rich conditions may include consumption of cations at the surface of the underlying layer. For instance, growing the quantum heterostructure may include closing, at an end of a growth period of an underlying layer (e.g., a barrier layer of the quantum heterostructure), a shutter for a Group III material while leaving a shutter for nitrogen open for a length of time to consume extra Group III atoms at the surface of the underlying layer.

[0074] Described above are examples of devices having atomically ordered GaN / AlN quantum heterostructures. Atomically ordered quantum interfaces are attained by incorporating GaN on the semipolar plane of the AlN nanostructure. First-principles DFT calculations show that the atomic substitutional energy on the semipolar plane is less negative than that on the c-plane, which effectively prevents interdiffusion between cations with different ionicity. The near-perfect interface between GaN and AlN ensures extreme quantum confinement and superior optical properties, including an IQE of 75% and negligible QCSE in both optically and electrically pumped devices. The origin of the varying incorporation planes is also studied and attributed to the different strain relaxation mechanisms in nanostructured GaN / AlN. Methods of fabricating devices having such a high-quality digital alloy / superlattice are also described. The disclosed devices and methods are not limited to III-nitride materials, but also useful in connection with other materialAtty. Docket No.10110-23015A systems such as III-arsenides, ABO3 perovskites, group IV heterostructures, and other polar semiconductors.

[0075] The term "about" is used herein in a manner to include deviations from a specified value that would be understood by one of ordinary skill in the art to effectively be the same as the specified value due to, for instance, the absence of appreciable, detectable, or otherwise effective difference in operation, outcome, characteristic, or other aspect of the disclosed methods and devices.

[0076] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and / or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

[0077] The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

Atty. Docket No.10110-23015A What is Claimed is:

1. A device comprising: a substrate; and a plurality of structures supported by the substrate, each structure of the plurality of structures comprising a semiconductor base, a semiconductor segment supported by the semiconductor base, and a quantum heterostructure supported by the semiconductor segment; wherein: the quantum heterostructure comprises an active layer; the active layer comprises a polar semiconductor material; and an interface of the quantum heterostructure is disposed along a semipolar plane of the polar semiconductor material.

2. The device of claim 1, wherein the semipolar plane corresponds with a morphology of the semiconductor segment.

3. The device of claim 1, wherein the semiconductor segment comprises a shell portion disposed along sidewalls of the semiconductor base.

4. The device of claim 3, wherein the plurality of structures has a lateral density along the substrate such that the shell portion of the semiconductor segment is sufficiently significant such that strain relaxation is achieved along a top facet of the semiconductor segment.

5. The device of claim 1, wherein the semiconductor segment has a convex top facet adjacent to the quantum heterostructure.

6. The device of claim 5, wherein the convex top facet of the semiconductor segment establishes an orientation of the interface of the quantum heterostructure.

7. The device of claim 1, wherein the semipolar plane is the (11^03^) plane.

8. The device of claim 1, wherein the heterostructure comprises a barrier layer in contact with the active layer at the interface of the quantum heterostructure.

9. The device of claim 1, wherein the active layer has a thickness for quantum confinement of charge carriers.Atty. Docket No.10110-23015A 10. The device of claim 1, wherein the active layer has a countable number of monolayers of a Group III-nitride material.

11. The device of claim 1, wherein: the active layer comprises gallium nitride; the quantum heterostructure comprises a pair of barrier layers between which the active layer is disposed; and each barrier layer of the pair of barrier layers comprises aluminum nitride.

12. The device of claim 1, wherein: the semiconductor segment comprises aluminum nitride doped to act as a charge carrier injection layer; the semiconductor base comprises gallium nitride.

13. The device of claim 1, wherein each structure of the plurality of structures comprises a nanowire oriented perpendicularly to the substrate.

14. A method of fabricating a heterostructure device, the method comprising: growing semiconductor bases of an array of structures on a substrate; growing a semiconductor segment on each semiconductor base of the array of structures; and growing a quantum heterostructure on each semiconductor segment of the array of structures; wherein growing the semiconductor bases is configured to space apart adjacent structures of the array of structures to an extent that -- each semiconductor segment comprises a shell portion; each semiconductor segment has a convex facet to relax strain arising from the shell portion; and the convex facet of the semiconductor segment is adjacent to the quantum heterostructure to establish an orientation of an interface of the quantum heterostructure.

15. The method of claim 14, wherein growing the quantum heterostructure comprises: growing a barrier layer of the quantum heterostructure; and growing an active layer of the quantum heterostructure, the active layer comprising a polar semiconductor material; wherein: the active layer is adjacent to the barrier layer to define the interface of theAtty. Docket No.10110-23015A quantum heterostructure; and the interface is disposed along a semipolar plane of the polar semiconductor material.

16. The method of claim 14, wherein growing the semiconductor bases, growing the semiconductor segment, and growing the quantum heterostructure comprise implementing respective epitaxial growth procedures configured such that -- the quantum heterostructure grows along the ^0001^^ direction; and quantum wells of the quantum heterostructure are incorporated on a plane other than the (0001^) plane to establish the interface of the quantum heterostructure.

17. The method of claim 14, wherein the plane on which the quantum wells are incorporated is the (11^03^) plane.

18. The method of claim 14, wherein growing the semiconductor bases, growing the semiconductor segment, and growing the quantum heterostructure, are performed under nitrogen-rich conditions.

19. The method of claim 14, wherein growing the quantum heterostructure comprises closing, at an end of a growth period of a barrier layer of the quantum heterostructure, a shutter for a Group III material while leaving a shutter for nitrogen open for a length of time to consume extra Group III atoms at the surface of the barrier layer.

20. A device comprising: a substrate; and a plurality of structures supported by the substrate, each structure of the plurality of structures comprising a semiconductor base, a semiconductor segment supported by the semiconductor base, and a quantum heterostructure supported by the semiconductor segment; wherein: the semiconductor segment comprises a shell portion disposed along sidewalls of the semiconductor base; the semiconductor segment has a convex facet adjacent to the quantum heterostructure; and the convex facet establishes an orientation of an interface of the quantum heterostructure.Atty. Docket No.10110-23015A 21. The device of claim 20, wherein: the quantum heterostructure comprises an active layer; the active layer comprises a polar semiconductor material; and the interface of the quantum heterostructure is disposed along a semipolar plane of the polar semiconductor material.

22. A device comprising: a substrate; and a plurality of structures supported by the substrate, each structure of the plurality of structures comprising a Group III-nitride base, first and second Group III-nitride charge carrier injection layers supported by the Group III-nitride base, and a quantum heterostructure disposed between the first and second charge carrier injection layers; wherein: the quantum heterostructure comprises a pair of Group III-nitride barrier layers, and a Group III-nitride active layer disposed between the pair of Group III-nitride barrier layers; and an interface between one of the pair of Group III-nitride barrier layers and the Group III-nitride active layer is disposed along a semipolar plane of the Group III-nitride active layer.

23. A device comprising: a substrate; and a plurality of structures supported by the substrate, each structure of the plurality of structures comprising a Group III-nitride base, first and second Group III-nitride charge carrier injection layers supported by the Group III-nitride base, and a quantum heterostructure disposed between the first and second charge carrier injection layers; wherein: the first Group III-nitride charge carrier injection layer comprises a shell portion disposed along sidewalls of the Group III-nitride base; the quantum heterostructure comprises a pair of Group III-nitride barrier layers and a Group III-nitride active layer disposed between the pair of Group III-nitride barrier layers; the first Group III-nitride charge carrier injection layer has a convex top facet adjacent to the quantum heterostructure; and the convex facet establishes an orientation of an interface between one of the pair of Group III-nitride barrier layers and the Group III-nitride active layer.

Images