Memory and operation method therefor, memory system, and word line voltage control circuit

Abstract

Provided are a memory and an operation method therefor, a memory system, and a word line voltage control circuit. The memory (20) comprises a memory cell array (220) and a peripheral circuit (210) coupled to the memory cell array (220). The memory cell array (220) comprises multiple word lines. The peripheral circuit (210) is configured to: at a first moment, start providing a precharge voltage for a selected word line among multiple word lines; at a second moment before the first moment, change the voltage provided to a non-selected word line adjacent to the selected word line from a first voltage to a second voltage; at a third moment after the first moment, start floating the selected word line; and at a fourth moment before the third moment and after the first moment, change the voltage provided to the adjacent non-selected word line from the second voltage to a third voltage, wherein the second voltage is lower than the first voltage, and the second voltage is lower than the third voltage.

Description

Memory and operation method thereof, memory system, and word line voltage control circuit Technical Field

[0001] The present application relates to, but is not limited to, a memory and an operating method thereof, a memory system, and a word line voltage control circuit. Background Art

[0002] As memory density continues to increase, memory cells are physically shrinking, bringing the wordlines within a memory cell closer together and increasing the capacitive coupling between adjacent wordlines. When the number of accesses to a row of memory cells exceeds a threshold, data in nearby rows may become abnormal. This phenomenon is commonly known as row hammering.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory, comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of word lines; the peripheral circuit is configured to: start providing a precharge voltage to a selected word line among the plurality of word lines at a first moment; at a second moment before the first moment, change the voltage provided on a non-selected word line adjacent to the selected word line from the first voltage to the second voltage; and at a third moment after the first moment, start floating the selected word line; at a fourth moment before the third moment and after the first moment, change the voltage provided on the adjacent non-selected word line from the second voltage to a third voltage; wherein the second voltage is less than the first voltage, and the second voltage is less than the third voltage.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising a memory as in the above-mentioned solution; and a controller coupled to the memory and configured to control the memory.

[0006] In a third aspect, an embodiment of the present application provides a word line voltage control circuit, comprising: a first voltage transmission circuit, configured to provide a first transmission voltage in response to a first enable signal before a pre-charge voltage is started to be provided to a selected word line; a second voltage transmission circuit, configured to provide a second transmission voltage in response to a second enable signal before the selected word line starts to float and after the pre-charge voltage is started to be provided to the selected word line; a local word line drive circuit, connected to both the first voltage transmission circuit and the second voltage transmission circuit, configured to connect a non-selected word line adjacent to the selected word line to the first voltage transmission circuit before the pre-charge voltage is started to be provided to the selected word line, and to connect the adjacent non-selected word line to the second voltage transmission circuit before the selected word line starts to float and after the pre-charge voltage is started to be provided to the selected word line.

[0007] In a fourth aspect, an embodiment of the present application provides a method for operating a memory, the operating method comprising: starting to provide a precharge voltage to a selected word line among multiple word lines of the memory at a first moment; at a second moment before the first moment, changing the voltage provided on a non-selected word line adjacent to the selected word line from a first voltage to a second voltage; and at a third moment after the first moment, starting to float the selected word line; at a fourth moment before the third moment and after the first moment, changing the voltage provided on an adjacent non-selected word line from the second voltage to a third voltage; wherein the second voltage is less than the first voltage, and the second voltage is less than the third voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0009] FIG1 shows a schematic structural diagram of an exemplary electronic device 1 having a memory according to an embodiment of the present application;

[0010] FIG2 is a schematic diagram of an exemplary dynamic random access memory according to an embodiment of the present application;

[0011] 3 is a schematic diagram illustrating connections among word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to an embodiment of the present application;

[0012] 4 is a schematic diagram of the voltage timing of related signals, word lines, and voltage transmission lines when accessing and selecting a word line according to an embodiment of the present application;

[0013] FIG5 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0014] 6 is a schematic diagram showing a timing sequence of voltages of related signals, word lines, and voltage transmission lines when accessing and selecting a word line according to another embodiment of the present application;

[0015] FIG7 is a schematic diagram of a partial structure of a peripheral circuit provided in an embodiment of the present application;

[0016] FIG8 a is a schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to an embodiment of the present application;

[0017] FIG8 b is a top view schematically showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to an embodiment of the present application;

[0018] FIG9 a is a schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application;

[0019] FIG9 b is a top view schematically showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application;

[0020] FIG10 is a schematic diagram of an implementation flow of a memory operation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0022] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0023] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0024] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] FIG1 shows a schematic diagram of the composition structure of an exemplary electronic device 1 having a memory according to an embodiment of the present application. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. As shown in FIG1 , the electronic device 1 may include a host HOST and a memory system 30, the memory system 30 including a memory controller 10 and one or more memories 20. The host HOST may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphic processing unit (GPU)). The host HOST may be configured to send data to the memory 20 or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host HOST and is configured to control the memory 20. The memory controller 10 may manage the data stored in the memory 20 and communicate with the host HOST.

[0027] The memory controller 10 may be configured to control operations of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 may also be configured to process error correction codes (ECC) on data read from or written to the memory 20. The memory controller 10 may also perform any other suitable functions, such as formatting the memory 20.

[0028] In some specific embodiments, the memory controller 10 and one or more memories 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and the multiple memories 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into various types of terminal electronic products.

[0029] The memory controller 10 can send and receive data to and from the host HOST and can send commands CMD and addresses ADDR to the memory 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 receives commands CMD and addresses ADDR from the host HOST. The command generator 110 can decode the commands CMD received from the host HOST to generate access commands, row hammer refresh commands, and the like, and can provide the access commands and row hammer refresh commands to the memory 20 via the device interface 130. An access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. A row hammer refresh command may be a signal instructing the memory 20 to perform additional refresh operations on word lines adjacent to word lines that have been frequently accessed in a short period of time. In other words, additional refresh operations may be performed on word lines adjacent to word lines that have been accessed multiple times in a short period of time. A high number of accesses may result from repeated requests to access the same word line.

[0030] The address generator 120 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory 20 can generate an address of a memory bank to be accessed when the memory cell array 220 includes a plurality of memory banks.

[0031] Furthermore, the memory controller 10 can control memory operations such as writes and reads by providing various signals to the memory 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20. In some embodiments, the memory 20 includes a memory cell array 220 and a peripheral circuit 210. The memory cell array 220 includes multiple memory banks, each memory bank includes multiple memory blocks, each memory block includes multiple memory cell rows and multiple memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 210 can write data to or read data from the memory cell array 220 based on the command CMD and address ADDR received from the memory controller 10, or can provide a control signal CTRL for refreshing the memory cells included in the memory cell array 220 to the row decoder and column decoder. In other words, the peripheral circuit 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: a control circuit corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD), a control circuit corresponding to each memory bank, such as a row decoder and a column decoder, and a control circuit corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0032] The memory 20 may be a random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description only uses DRAM as an example.

[0033] FIG2 is a schematic diagram of an exemplary dynamic random access memory according to an embodiment of the present application; FIG3 is a schematic diagram of the connections among word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to an embodiment of the present application.

[0034] The right side of Figure 2 shows the circuit of the memory cell in the DRAM. DRAM includes at least one DRAM chip (die). Each DRAM chip includes a memory cell array. The memory cell array includes multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T (Tran sistor) and a capacitor C (Capacitor). The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array and can be regarded as a typical mesh structure. The mesh structure can be specifically referred to in Figure 3. The memory cell array uses rows (Row) and columns (Column) to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and read, write, or refresh the data stored therein.

[0035] A DRAM memory cell is essentially a capacitor that stores charge. This capacitor can leak during reads, writes, and refreshes, and the read process itself is destructive. Therefore, a refresh is required after a read operation or when the memory cell has not been accessed for an extended period.

[0036] The data stored in a memory cell is determined by the charge in the capacitor, and this charge is easily affected between refresh cycles. Drifting electrons can migrate into or out of a memory cell, changing the charge in the cell. If a row address is accessed too many times in a short period of time, the memory cells in the adjacent rows of that address may accumulate enough charge changes to change the perceived state of the stored value. This is the row hammer phenomenon. As the size decreases, the rows whose perceived state of the stored value changes may not only be adjacent rows, but even nearby rows (two or more rows away) may be affected.

[0037] FIG4 is a schematic diagram of the voltage timing of the related signals, word lines and voltage transmission lines when accessing the selected word line according to an embodiment of the present application. <n>It can be understood as the word line connected to the memory cell to be accessed. The selected word line is similar to the selected word line, and both are used to determine the target memory cell to be read, written or perform other operations. Therefore, the two terms can be used interchangeably to express similar meanings; the adjacent non-selected word line wl<n+1 or n-1> It can be understood as the word line adjacent to the physical address of the selected word line; Vneg_local <n>It can be understood as a voltage transfer line with one end coupled to the selected word line and providing voltage to the selected word line, Vneg_local <n>The other end is coupled to the power supply terminal; Vneg_local<n+1 or n-1> It can be understood that one end is connected to the adjacent non-selected word line wl<n+1 or n-1> A voltage transfer line coupled to and providing voltage to adjacent non-selected word lines. Similarly, Vneg_local<n+1 or n-1> The other end is coupled to the power supply terminal. In addition, since the word line wl is selected <n>The length is long, the resistance cannot be ignored, and the Vneg_local <n>When coupling, place the select word line close to Vneg_local <n>One end is called the near end of the selected word line wl_near <n>, move the selected word line away from Vneg_local <n>One end is called the far end of the selected word line wl_far <n>Similarly, move the adjacent non-selected word lines close to Vneg_local<n+1 or n-1> One end of the adjacent non-selected word line is called the near end wl_near<n+1 or n-1> , move the adjacent non-selected word lines away from Vneg_local<n+1 or n-1> One end is called the far end wl_far of the adjacent non-selected word line<n+1 or n-1> .

[0038] For ease of understanding, the embodiment of the present application uses the remote end wl_far of the adjacent non-selected word line as an example.<n+1 or n-1> This is used as an example for illustration, but is not intended to limit the scope of protection of this application. The explanations in the embodiments of this application are also applicable to the near end wl_near of the adjacent non-selected word line.<n+1 or n-1> .

[0039] As shown in FIG4 , the bank selection signal Bank_enble and the main word line selection signal mwl_n <k>, word line selection signal wld <n>Under the condition of enabling state, the precharge control signal xpp <n>When switching from the disabled state to the enabled state, at the first time node Q1, the memory starts to perform a precharge operation on the selected word line, and selects the near end wl_near of the word line. <n>(The portion shown by the dotted parabola after Q1 in FIG. 4 ) and the far end wl_far of the selected word line <n>(The solid line portion below the dotted line after Q1 in FIG4 ) The time required to charge from the initial voltage vneg to the voltage Vpp at the first time node Q1 is different. It can be understood that the near end wl_near of the selected word line <n>Due to being closer to Vneg_loc cal <n>That is, it is closer to the power supply terminal, so it can be charged to the voltage Vpp faster. Select the far end of the word line wl_far <n>Vneg_local <n>The distance between the adjacent non-selected word lines wl is longer, so the time required to charge to the voltage Vpp is longer. This is shown in FIG4 as the slope of the dotted parabola portion is greater than the slope of the solid parabola portion.<n+1 or n-1> , with the remote end wl_far of the adjacent non-selected word line<n+1 or n-1> For example, select the far end of the word line wl_far <n>The voltage on the node Q1 starts to charge from the initial voltage vneg to the voltage Vpp at the first time, and at the far end wl_far of the selected word line <n>During the voltage rise, due to the word line coupling effect, the far end wl_far of the adjacent non-selected word line<n+1 or n-1> The voltage on the far end of the selected word line wl_far <n>After stabilizing at the voltage Vpp, the far end wl_far of the adjacent non-selected word line<n+1 or n-1> The voltage on the MOSFET gradually decreases and returns to a value equal to or slightly greater than the initial voltage vneg.

[0040] Select the far end of the word line wl_far <n>After stabilizing at voltage Vpp, and pre-charge control signal xpp <n>At the second time node Q2 when the enabled state is switched to the disabled state, the memory starts to float the selected word line.

[0041] Next, after the second time node Q2, after a certain buffer time at the third time node Q3, the word line is selected to start discharging. Here, the buffer discharge can be achieved by the falling edge delay circuit. <n>(The portion shown by the dotted parabola after Q3 in FIG. 4 ) is farther away from the selected word line than wl_far <n>(The portion shown by the solid parabola above the dotted parabola after Q3 in FIG4 ) The time required to discharge from the voltage Vpp to the initial voltage vneg at the third time node Q3 is shorter. <n>During the voltage rise on the word line, due to the word line coupling effect, the far end wl_far of the adjacent non-selected word line<n+1 or n-1> The voltage on the word line gradually drops to below the initial voltage vneg. <n>After the voltage on the adjacent non-selected word line stabilizes at the initial voltage vneg, the far end wl_far<n+1 or n-1> The voltage on the selected word line gradually rises and returns to near the initial voltage vneg. Thus, during the precharge operation and subsequent discharge of the selected word line, a large voltage difference will appear on the adjacent non-selected word lines due to coupling when the voltage of the selected word line rises or falls. This voltage difference is shown as ΔV1 in Figure 4. This voltage change ΔV1 may, on the one hand, change the perceived state of the storage value of the memory cell coupled to the adjacent non-selected word line, thereby threatening data security and exacerbating the row hammer problem. On the other hand, it may also cause the risk of gate-induced drain leakage (GIDL), which will cause hole accumulation and increase the floating body potential. The high floating body potential can turn on the parasitic transistor between the floating body and the drain junction, causing a series of problems.

[0042] Increasing the refresh frequency can mitigate the effects of row hammering to some extent, ensuring that each row is refreshed before row hammering causes sufficient damage to cell charge to cause errors. However, this approach consumes unnecessary time or power, increasing system power consumption and reducing performance. Furthermore, GIDL leakage remains an unresolved concern.

[0043] In this regard, the present application proposes the following implementation methods to reduce the large voltage difference caused by coupling to adjacent non-selected word lines, thereby alleviating the row hammer problem and GIDL leakage problem.

[0044] An embodiment of the present application provides a memory, as shown in Figure 5, the memory 20 includes a memory cell array 220 and a peripheral circuit 210 coupled to the memory cell array 220; the memory cell array 220 includes multiple word lines; the peripheral circuit 210 is configured to: start providing a precharge voltage to a selected word line among the multiple word lines at a first moment; at a second moment before the first moment, the voltage provided on the non-selected word line adjacent to the selected word line changes from the first voltage to the second voltage; and at a third moment after the first moment, start floating the selected word line; at a fourth moment before the third moment and after the first moment, the voltage provided on the adjacent non-selected word line changes from the second voltage to a third voltage; wherein the second voltage is less than the first voltage, and the second voltage is less than the third voltage.

[0045] FIG6 is a schematic diagram of the voltage timing of related signals, word lines, and voltage transmission lines when accessing a selected word line according to another embodiment of the present application. In some embodiments, in conjunction with FIG5 and FIG6, the peripheral circuit 210 is configured to: at a first time T1, begin providing a precharge voltage Vpp to a selected word line among a plurality of word lines; at a second time T2 before the first time T1, the voltage provided to the non-selected word lines adjacent to the selected word line changes from the first voltage V1 to the second voltage V2; and

[0046] At the third moment T3 after the first moment T1, the floating selection word line begins; at the fourth moment T4 before the third moment T3 and after the first moment T1, the voltage provided on the adjacent non-selected word line changes from the second voltage V2 to the third voltage V3; wherein the second voltage V2 is less than the first voltage V1, and the second voltage V2 is less than the third voltage V3.

[0047] For example, as shown in FIG6 , the bank selection signal Bank_enble and the main word line selection signal mwl_n <k>, word line selection signal wld <n>Under the condition of enabling state, the precharge control signal xp p <n>When switching from the disabled state to the enabled state, a precharge operation is performed on the selected word line at the first moment T1, and the near end wl_near of the selected word line is selected. <n>(The portion shown by the dotted parabola after T1 in FIG. 6 ) and the far end wl_far of the selected word line <n>The time required to charge the battery from the first voltage V1 to the pre-charge voltage Vpp starting from the first time T1 (the portion indicated by the solid line below the dotted line after T1 in FIG6 ) is different.

[0048] It should be noted that the bank selection signal Bank_enble and the main word line selection signal mwl_n <k>And word line selection signal wld <n>The enabled state is a low level voltage such as Vss, and the disabled state is a high level voltage such as Vpp or Vdd. <n>The enabled state is a high level voltage such as Vpp or Vdd, and the disabled state is a low level voltage such as Vss.

[0049] The wld shown in Figure 6 <n>It represents the word line selection signal of the selected word line. The word line selection signals corresponding to the adjacent non-selected word lines are always in the non-enabled state, that is, the high level voltage, and are not shown in FIG. 6 .

[0050] For the adjacent non-selected word line wl<n+1 or n-1> , with the far end of the adjacent non-selected word line w l_far<n+1 or n-1> For example, at the second moment T2 before the first moment T1, Vneg_local<n+1 or n-1> The voltage on the Vneg_local is changed from the first voltage V1 to the second voltage V2. It can be understood that the Vneg_local<n+1 or n-1> Provided at the far end wl_far of the non-selected word line adjacent to the selected word line<n+1 or n-1> The voltage on the selected word line changes from the first voltage V1 to the second voltage V2, and the second voltage V2 is less than the first voltage V1. In this way, before the selected word line starts precharging at the first time T1, the voltage provided to the adjacent non-selected word line is reduced in advance to reduce the starting voltage of the adjacent non-selected word line due to coupling. Under the condition that the rising voltage difference of the adjacent non-selected word line caused by the coupling effect remains basically unchanged, the absolute voltage of the adjacent non-selected word line after being coupled and pulled up is effectively reduced.

[0051] In the embodiment of the present application, at the third moment T3, the pre-charge control signal xpp <n>When the memory is switched from the enabled state to the disabled state, the memory stops the precharge operation on the selected word line and starts to float the selected word line.

[0052] In some embodiments, as shown in FIG6 , the memory starts to float the selected word line at a third time T3 , and the selected word line starts to discharge at a seventh time T7 after a certain buffer time after the third time T3 .

[0053] For the adjacent non-selected word line wl<n+1 or n-1> , still with the remote end wl_far of the adjacent non-selected word line<n+1 or n-1> For example, at the fourth moment T4 before the third moment T3 and after the first moment T1, Vneg_local<n+1 or n-1> The voltage on the Vneg_local is changed from the second voltage V2 to the third voltage V3. It can be understood that the Vneg_local<n+1 or n-1> Provided at the far end wl_far of the non-selected word line adjacent to the selected word line<n+1 or n-1> The voltage on the CMOS circuit changes from the second voltage V2 to the third voltage V3, and the second voltage V2 is less than the third voltage V3. Thus, before the selected word line begins to float, the voltage provided to the adjacent non-selected word line is raised in advance to increase the starting voltage of the adjacent non-selected word line due to coupling. While the voltage drop difference of the adjacent non-selected word line caused by the coupling effect remains essentially unchanged, the absolute voltage of the adjacent non-selected word line after being coupled and pulled down is effectively increased.

[0054] As shown in Figure 6, by lowering the voltage supplied to adjacent non-selected word lines before precharging the selected word line, the final voltage at which the voltage on the adjacent non-selected word lines is coupled up is controlled, which becomes the highest voltage in the subsequent voltage variation. Simultaneously, by raising the voltage supplied to the adjacent non-selected word lines before discharging the selected word line, the final voltage at which the voltage on the adjacent non-selected word lines is coupled down is controlled, which becomes the lowest voltage in the subsequent voltage variation. Because the highest voltage in the voltage variation is reduced and the lowest voltage is increased, the voltage variation ΔV2 on the adjacent non-selected word lines during the charge-discharge process of the selected word line can be effectively reduced, thereby alleviating row hammer and GIDL leakage issues.

[0055] In the embodiment of the present application, as shown in FIG6 , at the fifth time T5, the voltage on the adjacent non-selected word line reaches the second voltage V2, and the time length between the second time T2 and the fifth time T5 is the first time length ΔT1; at the sixth time T6, the voltage on the adjacent non-selected word line reaches the third voltage V3; the time length between the fourth time T4 and the sixth time T6 is the second time length ΔT2;

[0056] The time difference between the first moment T1 and the second moment T2 is greater than or equal to the first time duration ΔT1;

[0057] The time difference between the third time point T3 and the fourth time point T4 is greater than or equal to the second time period ΔT2.

[0058] It is understandable that through Vneg_local<n+1 or n-1> For adjacent non-selected word lines wl_<n+1 or n-1> When passing voltage, Vneg_local<n+1 or n-1> The voltage on the word line wl_ changes from the first voltage V1 to the second voltage V2 at time T2, and the adjacent non-selected word line wl_<n+1 or n-1> The time required for the first voltage V1 to decrease and become the stable second voltage V2 is the first time length ΔT1. Based on this, the time difference between the first moment T1 and the second moment T2 is greater than or equal to the first time length ΔT1, which can be understood as the time difference between the adjacent non-selected word line wl_<n+1 or n-1> When the voltage on the selected word line drops to the second voltage V2 or later, the precharge operation of the selected word line is started, and when the adjacent non-selected word line wl_<n+1 or n-1> When the voltage on the adjacent non-selected word line wl_<n+1 or n-1> The starting voltage that is coupled and pulled up is not controlled to the lowest level.

[0059] Similarly, the time difference between the third time T3 and the fourth time T4 is greater than or equal to the second time length ΔT2, which can be understood as the time difference between the adjacent non-selected word lines wl_<n+1 or n-1> When the voltage on the selected word line rises to the third voltage V3 or later, the discharge operation of the selected word line is started, and when the adjacent non-selected word line wl_<n+1 or n-1> When the voltage on the adjacent non-selected word line wl_ has not risen to the third voltage V3 and is between the second voltage V2 and the third voltage V3, the adjacent non-selected word line wl_<n+1 or n-1> The starting voltage that is lowered by coupling is not controlled to the maximum. Thus, by setting the first time duration, it is ensured that the voltage on the adjacent non-selected word line has reached the second voltage V2 before the selected word line is precharged, and by setting the second time duration, it is ensured that the voltage on the adjacent non-selected word line has reached the third voltage V3 before the selected word line is discharged, thereby further improving the control effect of the voltage variation amplitude on the adjacent non-selected word line during the charge-discharge process of the selected word line.

[0060] In other embodiments, after the second time T2, the timing of starting the precharge operation of the selected word line can be selected according to actual needs. For example, the precharge operation of the selected word line can be started at any time between the second time T2 and the fifth time T5. It can be understood that the precharge operation of the selected word line is started at any time between the second time T2 and the fifth time T5.<n+1 or n-1> Before the voltage on the selected word line drops to the second voltage V2, the precharge operation of the selected word line is started.<n+1 or n-1> While coupling and raising the starting voltage, the waiting time of the pre-charge operation can also be controlled.

[0061] Similarly, after the fourth moment T4, the timing of starting the discharge operation of the selected word line can be selected according to actual needs. For example, the discharge operation of the selected word line can be started at any time between the fourth moment T4 and the sixth moment T6. It can be understood that the discharge operation of the selected word line is started at any time between the fourth moment T4 and the sixth moment T6.<n+1 or n-1> Before the voltage on the selected word line rises to the third voltage V3, the discharge operation of the selected word line is started.<n+1 or n-1> While the starting voltage is lowered by coupling, the waiting time of the discharge operation can also be controlled. In some embodiments, the first voltage V1 is the same as the third voltage V3.

[0062] In some embodiments, the relationship between the second voltage, the first voltage, and the pre-charge voltage is as follows: |V2|=r(Vpp-V1) Formula (1)

[0063] Wherein, V1 is the first voltage, V2 is the second voltage, Vpp is the pre-charge voltage, and r is the coupling coefficient.

[0064] Exemplarily, the coupling coefficient r=C1 / C2, where C1 represents the capacitance between a selected word line and an adjacent non-selected word line, and C2 represents the capacitance of the selected word line.

[0065] It should be noted that the word line is connected to the memory cell through the gate of the transistor (refer to Figure 2), and the capacitance of the word line refers to the sum of the write capacitance and the load capacitance. Among them, the write capacitance refers to the amount of charge that needs to be charged or discharged on the word line when writing data to the memory cell. When performing a write operation, it involves transferring charge between the word line and the memory cell to change the charge state of the memory cell. The size of the write capacitance is related to the required amount of charge, the size of the memory cell, etc. The load capacitance refers to the capacitance caused by other circuit elements connected to the word line (such as a read circuit, a decoding circuit buffer, etc.). In some embodiments, the coupling coefficient r is related to the physical distance between the selected word line and the adjacent non-selected word line. The smaller the physical distance between the selected word line and the adjacent non-selected word line, the greater the capacitance between the selected word line and the adjacent non-selected word line, and the greater the coupling coefficient r.

[0066] It can be understood that, when the first voltage V1 and the third voltage V3 are different, the relationship between the second voltage, the third voltage and the pre-charge voltage is as follows: |V2|=r(Vpp-V3) Formula (2)

[0067] Wherein, V3 is the third voltage, V2 is the second voltage, Vpp is the pre-charge voltage, and r is the coupling coefficient.

[0068] In the embodiment of the present application, the first voltage V1 and the third voltage V3 are the same as an example. As shown in FIG5 , the peripheral circuit 210 includes: a first voltage generator 214, a second voltage generator 215, a first voltage transfer circuit 211, and a second voltage transfer circuit 212. The first voltage generator 214 is connected to the first voltage transfer circuit 211 and configured to provide the first voltage V1. The second voltage generator 215 is connected to the second voltage transfer circuit 212 and configured to provide the second voltage V2. The first voltage transfer circuit 211 is configured to transmit the first voltage V1 to an adjacent non-selected word line in response to the first control signal wlup_enb at a fourth time T4. The second voltage transfer circuit 212 is configured to transmit the second voltage V2 to an adjacent non-selected word line in response to the second control signal wlup_vneg2 at a second time T2.

[0069] In some embodiments, the first voltage generator 214 and the second voltage generator 215 may be included in a voltage generator of a peripheral circuit. In some specific embodiments, the first voltage generator 214 and the second voltage generator 215 may each include a charge pump. The first voltage generator 214 and the second voltage generator 215 may be integrated into a charge pump with multiple outputs, or may be included in different charge pumps.

[0070] In some embodiments, as shown in Figures 5 and 6, the peripheral circuit 210 also includes a control signal generating circuit 216; the control signal generating circuit 216 is configured to receive the enable control signal wlup_en and provide a first control signal wlup_enb to the first voltage transmission circuit 211 and provide a second control signal wlup_vneg2 to the second voltage transmission circuit 212.

[0071] In some embodiments, as shown in FIG5 , the peripheral circuit further includes a plurality of local word line driver circuits 213 corresponding one-to-one to the word lines;

[0072] The local word line driving circuit 213 is configured to respond to the main word line selection signal mwl_n <k>, word line selection signal wld <n>And precharge control signal xpp <n>, at a first moment T1, the adjacent non-selected word lines are connected to the first voltage transfer circuit 211 , and at a second moment T2, the adjacent non-selected word lines are connected to the second voltage transfer circuit 212 ;

[0073] Among them, the main word line selection signal mwl_n <k>Used to indicate the selection of one of the multiple main word lines of the peripheral circuit, each main word line corresponds to multiple word lines; word line selection signal wld <n>, used to indicate the selection of one of the multiple word lines corresponding to the main word line; precharge control signal xpp <n>Used to indicate that the precharge voltage Vpp is provided to the selected word line.

[0074] In some embodiments, as shown in FIG5 , the control signal generating circuit 216 is connected to the first voltage transfer circuit 211 via the first node N1; the control signal generating circuit 216 is connected to the second voltage transfer circuit 212 via the second node N2;

[0075] The first voltage transfer circuit 211 and the second voltage transfer circuit 212 are both connected to the local word line driving circuit 213 via the third node N3;

[0076] The first voltage generator 214 and the second voltage generator 215 are both connected to the control signal generating circuit 216 .

[0077] In some embodiments, the plurality of local word line driving circuits are divided into a plurality of groups; each group of local word line driving circuits corresponds to a first voltage generator, a second voltage generator, a first voltage transmission circuit, and a second voltage transmission circuit.

[0078] It can be understood that the main word line selection signal mwl_n <k>And word line selection signal wld <n>The word line can be selected by working together. Each word line corresponds to a local word line driver circuit. The multiple local word line driver circuits corresponding to multiple word lines are based on the word line selection signal wld. <n>The word lines in the same group are divided into multiple groups, and the word line selection signals wld corresponding to all word lines in the same group are <n>All are in the same level state, and the main word line selection signal mwl_n corresponding to the selected word line or the unselected word line in the same group <k>Different level states.

[0079] Exemplarily, a memory block shares a control signal generating circuit, and the 16 local word line driver circuits in a memory block are divided into four groups, each of which shares the same first voltage generator, the same second voltage generator, the same first voltage transmission circuit, and the same second voltage transmission circuit. That is, the 16 word lines corresponding to the local word line driver circuits are divided into four groups, which are respectively connected to four first voltage transmission circuits and four second voltage transmission circuits. Every four word lines are connected to the same first voltage transmission circuit and the same second voltage transmission circuit. The four word lines connected to the same first voltage transmission circuit and the same second voltage transmission circuit will be selected or not selected at the same time, and the corresponding word line selection signal wld <n>same.

[0080] In this way, the circuit area can be greatly reduced by having multiple local word line driving circuits in each group of local word line driving circuits share the first voltage generator, a second voltage generator, a first voltage transmission circuit, and a second voltage transmission circuit.

[0081] FIG7 is a partial structural diagram of a peripheral circuit provided in an embodiment of the present application. In some embodiments, as shown in FIG7 , the first voltage transmission circuit 211 includes a first transistor M1, and the second voltage transmission circuit 212 includes a second transistor M2 and a third transistor M3;

[0082] The first terminal of the first transistor M1 is used to receive the first control signal wlup_enb, the second terminal is connected to the output terminal of the first voltage generator (not shown in FIG7 ), and the third terminal is connected to the third terminal of the second transistor M2. The output terminal of the first voltage generator outputs the first voltage V1, which can be the voltage VNEG.

[0083] A first end of the second transistor M2 is used to receive the second control signal wlup_vneg2 , and a second end of the second transistor M2 is connected to the third end of the third transistor M3 .

[0084] A first terminal of the third transistor M3 is used to receive a word line selection signal wld <n>The second end is connected to the output end of the second voltage generator (not shown in FIG7 ). The output end of the second voltage generator outputs a second voltage V2, which may be a voltage VNEG2.

[0085] It can be understood that the third end of the first transistor M1 is connected to the third end of the second transistor M2 via the third node N3.

[0086] In some embodiments, as shown in FIG. 7 , the control signal generating circuit 216 includes a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , and a seventh transistor M7 ; wherein:

[0087] The fourth transistor M4 has a first terminal for receiving an enable control signal wlup_en, a second terminal for receiving a high-level voltage such as Vpp or Vdd, and a third terminal connected to the third terminal of the fifth transistor M5 for outputting the first control signal wlup_enb. It will be appreciated that the third terminal of the fourth transistor M4 is connected to the third terminal of the fifth transistor M5 via the first node N1.

[0088] A first end of the fifth transistor M5 is connected to the first end of the fourth transistor M4 , and a second end of the fifth transistor M5 is used to receive the voltage VNEG.

[0089] The sixth transistor M6 has a first terminal for receiving the first control signal wlup_enb, a second terminal for receiving a high-level voltage such as Vpp or Vdd, and a third terminal connected to the third terminal of the seventh transistor M7 for outputting the second control signal wlup_vneg2. It will be appreciated that the third terminal of the sixth transistor M6 is connected to the third terminal of the seventh transistor M7 via the second node N2.

[0090] A first end of the seventh transistor M7 is connected to the first end of the sixth transistor M6 , and a second end of the seventh transistor M7 is used to receive the voltage VNEG2 .

[0091] In some embodiments, as shown in FIG. 4 , the local word line driver circuit 213 includes an eighth transistor M8 , a ninth transistor M9 , and a tenth transistor M10 ; wherein:

[0092] The first terminal of the eighth transistor M8 is used to receive the main word line selection signal mwl_n. <k>The second end is used to receive the pre-charge control signal xpp <n>, the third end is connected to the selected word line WL <n>Coupling.

[0093] The first terminal of the ninth transistor M9 is used to receive the main word line selection signal mwl_n. <k>The second end is connected to the second end of the tenth transistor M10, and the third end is connected to the word line WL <n>Coupling.

[0094] The first terminal of the tenth transistor M10 is used to receive the word line selection signal wld <n>The second end is connected to the N3 node, that is, the third end of the first transistor M1 and the third end of the second transistor M2, and the third end is connected to the word line WL <n>Coupling.

[0095] In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are field-effect MOS transistors; wherein the first end of the field-effect MOS transistor is a gate, the second end of the field-effect MOS transistor is a source, and the third end of the field-effect MOS transistor is a drain.

[0096] In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9 and the tenth transistor M10 are N-type channel field effect MOS transistors; the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are P-type channel field effect MOS transistors.

[0097] It should be noted that FIG7 only shows the local word line driving circuit 213 corresponding to one word line, but in practice each word line is provided with its corresponding local word line driving circuit 213 .

[0098] In the embodiment of the present application, the pre-charge voltage is a high-level voltage; the first voltage, the second voltage, and the third voltage are all negative voltages. For example, the pre-charge voltage is Vpp, with a voltage range of 2.2V to 2.8V, the first voltage and the third voltage are VNEG, with a voltage range of -0.2V to -0.1V, and the second voltage is VNEG2, with a voltage range of -0.8V to -0.4V.

[0099] 6 and 7 , a detailed description is given below of how various specific circuits in the peripheral circuits are used to implement voltage supply on non-selected word lines during the process from pre-charging operation to discharging operation of the selected word line, thereby reducing the large voltage difference caused by coupling to the adjacent word lines.

[0100] 6 and 7, before the second time T2, the enable control signal wlup_en (not shown in FIG6) is a low-level voltage, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off. Therefore, the first control signal wlup_enb provided by the control signal generating circuit 216 to the first voltage transfer circuit 211 is a high-level voltage Vpp, and the first transistor M1 is turned on. Therefore, the voltage VNEG is transmitted to the local word line driving circuit 213 corresponding to the word line via the first transistor M1 in the first voltage transfer circuit 211. For all word lines, the main word line selection signal mwl_n <k>and word line select signal wld <n>Before time T2, the voltage VPP is high, the ninth transistor M9 is turned on, and the tenth transistor M10 is turned on. Based on this, the voltage provided by the first voltage transfer circuit 211 on all word lines through M9 and M10 is the voltage VNEG. Here, the voltage VNEG is equivalent to the first voltage V1 shown in FIG6.

[0101] At the same time, before time T2, the voltage on the first node N1 is the high-level voltage Vpp, the sixth transistor M6 is turned off, and the seventh transistor M7 is turned on. Therefore, the second control signal wlup_vneg2 provided by the control signal generating circuit 216 to the second voltage transfer circuit 212 is the voltage VNEG2, and the second transistor M2 is turned off. Therefore, the second voltage transfer circuit 211 is not connected to the local word line driver circuit, that is, the second voltage transfer circuit 211 does not provide voltage to the local word line driver circuit.

[0102] Next, at the second moment T2, the enable control signal wlup_en changes from a low level voltage to a high level voltage, the fourth transistor M4 is turned off, and the fifth transistor M5 is turned on, so the first control signal wlup_enb provided by the control signal generating circuit 216 to the first voltage transfer circuit 211 is switched from the high level voltage Vpp to the voltage VNEG.

[0103] At time T2, the voltage at the first node N1 also switches from the high-level voltage Vpp to the voltage VNEG, the sixth transistor M6 is turned on, and the seventh transistor M7 is turned off. Therefore, the second control signal wlup_vneg2 provided by the control signal generating circuit 216 to the second voltage transfer circuit 212 switches from the voltage VNEG2 to the high-level voltage Vpp. Here, the voltage VNEG2 is equivalent to the second voltage V2 shown in FIG6 .

[0104] At the same time, at the second moment T2, for the adjacent non-selected word line, the first control signal wlup_enb is at the voltage VNEG, and the first transistor M1 is turned off. The second control signal wlup_vneg2 is at the high level Vpp, and the second transistor M2 is turned on. <n>= is a high level voltage, and the third transistor M3 is turned on. Therefore, the voltage VNEG2 is transmitted to the local word line driving circuit 213 corresponding to the adjacent non-selected word line via the second transistor M2 and the third transistor M3 in the second voltage transfer circuit 212. For the adjacent non-selected word line, the word line selection signal wld <n>The tenth transistor M10 is turned on, and thus the voltage VNEG2 is transmitted to the corresponding adjacent non-selected word line via the local word line driver circuit 213. Based on this, at the second time T2, the voltage provided on the adjacent non-selected word line decreases from the voltage VNEG to the voltage VNEG2.

[0105] It should be noted that at the second moment T2, for selecting a word line, the word line selection signal wld <n>= is a low level voltage, the third transistor M3 is turned off, the tenth transistor M10 is turned off, and the main word line selection signal mwl_n is selected. <k>, at time T2, they all change from high level to low level, and the precharge control signal xpp <n>At time T2, the voltage is low. At this time, the eighth transistor M8 and the ninth transistor M9 are both turned off, and the selected word line is floating. However, due to the coupling effect with the adjacent non-selected word line, the voltage on the selected word line gradually decreases from the voltage VNEG.

[0106] Next, at the first time T1, for the selected word line, the precharge control signal xpp <n>From the low level voltage to the high level voltage, the main word line selection signal mwl_n <k>is a low level voltage, the word line selection signal wld <n>is a low level voltage, at this time the eighth transistor M8 is turned on, the ninth transistor M9 and the tenth transistor M10 are turned off, and the local word line driving circuit 213 corresponding to the selected word line starts to provide the precharge voltage Vpp to the selected word line via the eighth transistor M8.

[0107] Meanwhile, at the first time T1, the voltage VNEG2 is still transmitted to the corresponding adjacent non-selected word lines via the local word line driver circuit 213. However, due to the coupling with the selected word line, the voltage on the adjacent non-selected word lines gradually increases from the voltage VNEG2.

[0108] Next, at the fourth time T4, the local word line driving circuit 213 corresponding to the selected word line still provides the precharge voltage Vpp to the selected word line via the eighth transistor M8.

[0109] At the same time, at the fourth moment T4, for the adjacent non-selected word line, the first control signal wlup_enb switches from the voltage VNEG to the high level voltage Vpp, and the first transistor M1 is turned on. The second control signal wlup_vneg2 switches from the high level voltage Vpp to the voltage VNEG2, and the second transistor M2 is turned off. <n>= is a high level voltage, and the third transistor M3 is turned on. At this time, the voltage VNEG is transmitted to the local word line driving circuit 213 corresponding to the adjacent non-selected word line via the first transistor M1 in the first voltage transfer circuit 211. For the adjacent non-selected word line, the word line selection signal wld <n>is a high-level voltage, the tenth transistor M10 is turned on, and thus the voltage VNEG is transmitted to the corresponding adjacent non-selected word line via the local word line driving circuit 213 .

[0110] It can be understood that at the fourth time T4, the voltage provided to the adjacent non-selected word line changes from the voltage VNEG2 to the voltage VNEG. Here, the voltage VNEG is equivalent to the third voltage V3 shown in FIG6.

[0111] Next, at the third time T3, for the selected word line, the precharge control signal xpp <n>The voltage changes from a high level to a low level, the eighth transistor M8 is turned off, the local word line driving circuit 213 corresponding to the selected word line stops providing the precharge voltage Vpp to the selected word line, and the memory starts to float the selected word line.

[0112] Next, at the seventh time T7, after a certain buffer time after the third time T3, the selected word line begins to discharge. Here, this buffer discharge can be achieved by a falling edge delay circuit (not shown in FIG7 ). At this time, the voltage provided to the adjacent non-selected word line by the local word line driver circuit 213 corresponding to the adjacent non-selected word line is still VNEG, but due to the coupling effect between the adjacent non-selected word line and the selected word line, the voltage on the adjacent non-selected word line gradually decreases from the voltage VNEG.

[0113] As mentioned above, as the memory size decreases, the physical distance between word lines will further decrease. Row hammer may affect not only the word lines of adjacent rows, but even the word lines of nearby rows (two or even more adjacent rows) may be affected.

[0114] Based on this, in some embodiments, when the selected word line is the Nth word line, the adjacent non-selected word lines include at least the N-1th word line and the N+1th word line.

[0115] In some specific embodiments, the adjacent non-selected word lines further include word lines spaced apart from the selected word line by a number M; wherein M is a natural number, 1≤M≤4.

[0116] Here, M can be determined based on the range of surrounding rows affected by the row hammer in actual applications.

[0117] For example, when the selected word line is word line 6, the adjacent non-selected word lines include word line 5 and word line 7. The adjacent non-selected word lines may also include word line 4 and word line 8, word line 3 and word line 9, and word line 2 and word line 10.

[0118] It should be noted that when the adjacent non-selected word lines include multiple word lines, each word line needs to be applied with a corresponding voltage according to the timing required by the embodiment of the present application.

[0119] In some embodiments, for each adjacent non-selected word line among a plurality of adjacent non-selected word lines, each adjacent non-selected word line can be lowered from a first voltage V1 to a same second voltage V2 in advance when rising coupling begins, and each adjacent non-selected word line can be raised from the second voltage V2 to a same third voltage V3 in advance when falling coupling begins.

[0120] In other embodiments, for each adjacent non-selected word line among a plurality of adjacent non-selected word lines, each adjacent non-selected word line can be dropped from a first voltage V1 to a different second voltage V2 in advance at the start of the rising coupling, and each adjacent non-selected word line can be raised from the second voltage V2 to a different third voltage V3 in advance at the start of the falling coupling. Here, the adjustment values ​​between the different second voltages V2 and the adjustment values ​​between the different third voltages V3 can be determined based on the distance between each adjacent non-selected word line and the selected word line. For example, a smaller distance results in a greater coupling effect, a greater absolute value of the difference between the first voltage V1 and the second voltage V2, and a greater absolute value of the difference between the second voltage V2 and the third voltage V3. A larger distance results in a smaller coupling effect, a smaller absolute value of the difference between the first voltage V1 and the second voltage V2, and a smaller absolute value of the difference between the second voltage V2 and the third voltage V3.

[0121] It is understandable that the absolute value of the voltage difference between the second voltage and the first voltage decreases as the distance between the adjacent non-selected word line and the selected word line increases. For example, as the distance between the selected word line and the adjacent non-selected word line increases, the capacitance between the selected word line and the adjacent non-selected word line decreases, the coupling coefficient r decreases, and the influence of the selected word line on the adjacent non-selected word line decreases. Therefore, when the absolute value of the voltage difference between the second voltage and the first voltage is small, interference of the selected word line on the adjacent non-selected word line can be avoided.

[0122] Due to the improvement of the row hammer problem, the refresh frequency of the memory caused by the row hammer problem can be reduced to a certain extent, so that the power of the memory can be reduced to a certain extent, and then the complexity of the peripheral circuit of the memory can also be reduced as the power is reduced.

[0123] 8a is a schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to an embodiment of the present application; and FIG. 8b is a top-down schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to an embodiment of the present application.

[0124] As shown in FIG8a , the memory cell array 220 and the peripheral circuit 210 are arranged in parallel. More specifically, the memory cell array includes M memory banks, each memory bank includes N memory blocks, and at least one side of each memory block is provided with a control circuit corresponding to the memory block. At least one side of each memory bank is provided with a control circuit corresponding to the memory bank. Every K memory banks in the M memory banks form a memory bank row, and the M memory banks form M / K memory bank rows. Peripheral circuits corresponding to all memory banks are provided between the middle two memory bank rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0125] For example, as shown in FIG8b , the memory cell array 220 includes 16 memory banks Bank0-Bank15, each of which includes multiple memory blocks Block. Each memory block Block is surrounded by corresponding memory blocks SA and WLD. Each memory bank is flanked by column decoders and row decoders corresponding to the memory bank. Every four memory banks form a memory bank row, and 16 memory banks form four memory bank rows. Control circuits corresponding to all memory banks are provided between the two middle memory bank rows. It should be noted that the number of memory banks in FIG8b is for illustrative purposes only and is not intended to limit the number of memory banks in the memory of this application.

[0126] As mentioned above, in order to suppress the coupling effect in the embodiments of the present application, a first voltage generator 214, a second voltage generator 215, a control signal generating circuit 216, a first voltage transmission circuit 211, and a second voltage transmission circuit 212 are added. However, in the distribution of the memory cell array and the peripheral circuit shown in Figures 8a and 8b, there may be no free space to place these newly added circuits. Considering that the memory cell array in the DRAM occupies a larger area than the peripheral circuit, in some embodiments, the memory cell array in the DRAM and the peripheral circuit are stacked and electrically connected by bonding. There will still be some free space in the semiconductor layer where the peripheral circuit is located. This free space can be used to place the aforementioned newly added circuits.

[0127] 9a is a schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application; FIG. 9b is a top-down schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application.

[0128] As shown in FIG9 a , the first semiconductor structure 100 is located above the second semiconductor structure 200 . The first semiconductor structure 100 includes a memory cell array 220 , and the second semiconductor structure 200 includes a peripheral circuit 210 .

[0129] It should be noted that the first semiconductor structure corresponding to FIG. 9a in FIG. 9b is located above the second semiconductor structure, and the structure corresponding to the solid line in FIG. 9b is located within the first semiconductor structure, while the structure corresponding to the dashed line is located within the second semiconductor structure. For ease of understanding, the structure within the second semiconductor structure is shown in perspective. That is, in the enlarged view corresponding to each memory block in FIG. 9b , the solid line represents the enlarged portion of the memory block, while the dashed line represents the structure within the second semiconductor structure directly below the memory block.

[0130] For example, as shown in FIG9b , the memory cell array 220 includes 16 memory banks Bank0-Bank15, each memory bank includes multiple memory blocks Block, and a first voltage generator 214, a second voltage generator 215, a control signal generating circuit 216, a first voltage transmission circuit 211, and a second voltage transmission circuit 212 are arranged directly below each memory block Block. In addition, according to actual needs, a control signal generating circuit 216 shared by a memory block, as well as multiple first voltage generators 214, multiple second voltage generators 215, multiple first voltage transmission circuits 211, and multiple second voltage transmission circuits 212 corresponding to the memory block can be arranged directly below a memory block.

[0131] It should be noted that the number of the control signal generating circuit 216, the first voltage generator 214, the multiple second voltage generators 215, the first voltage transmission circuit 211 and the second voltage transmission circuit 212 in Figure 9b is only for example and is not used to limit the number and position of the corresponding circuits in the memory in this application.

[0132] It should be noted that, in addition to the aforementioned newly added circuits, if space permits, each memory block may have its corresponding SA and WLD disposed directly below the memory block, ie, in the dotted box shown in FIG. 9 b .

[0133] In some specific embodiments, the bonding methods of the memory cell array 220 and the peripheral circuit 210 include but are not limited to hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0134] When the memory is stacked in a bonding manner, the newly added circuits and SA, WLD and other related circuits in the embodiment of the present application can be placed under the array. Due to the stacking configuration, there is no additional area cost for the newly added circuits.

[0135] With the development of memory, such as DRAM, process means are used to improve or eliminate leakage induced by row hammer, but the scale of this process is getting larger and larger, and the effect is limited. The embodiment of the present application improves the neighborhood Wl coupling effect from the perspective of design control without increasing the memory cost.

[0136] FIG10 is a schematic diagram of an implementation flow of a memory operation method provided in an embodiment of the present application. The present application provides a memory operation method, which specifically includes the following steps:

[0137] Step S10: at a first moment, a precharge voltage is provided to a selected word line among a plurality of word lines of the memory; at a second moment before the first moment, a voltage provided to a non-selected word line adjacent to the selected word line is changed from a first voltage to a second voltage;

[0138] Step S20: at a third moment after the first moment, starting to float the selected word line; at a fourth moment before the third moment and after the first moment, changing the voltage provided to the adjacent non-selected word line from the second voltage to a third voltage;

[0139] The second voltage is lower than the first voltage, and the second voltage is lower than the third voltage.

[0140] The operation method will be described below in conjunction with Figures 6 and 10. The structure of the memory can be referred to the relevant description in the above embodiment and will not be repeated here.

[0141] In some embodiments, at a first moment T1, a precharge voltage Vpp is started to be provided to a selected word line among multiple word lines; at a second moment T2 before the first moment T1, the voltage provided on a non-selected word line adjacent to the selected word line changes from the first voltage V1 to the second voltage V2; at a third moment T3 after the first moment T1, the selected word line starts to float; at a fourth moment T4 before the third moment T3 and after the first moment T1, the voltage provided on the adjacent non-selected word line changes from the second voltage V2 to the third voltage V3; wherein, the second voltage V2 is less than the first voltage V1, and the second voltage V2 is less than the third voltage V3.

[0142] By lowering the voltage supplied to adjacent non-selected word lines before precharging the selected word line, the final voltage at which the voltage on the adjacent non-selected word lines is coupled up is controlled, which becomes the highest voltage in the subsequent voltage variation. Simultaneously, by raising the voltage supplied to the adjacent non-selected word lines before discharging the selected word line, the final voltage at which the voltage on the adjacent non-selected word lines is coupled down is controlled, which becomes the lowest voltage in the subsequent voltage variation. This effectively reduces voltage variations on adjacent non-selected word lines during the charge-discharge process of the selected word line, preventing changes to the contents of adjacent memory cells and bit flips, thereby protecting data security.

[0143] In some embodiments, at a fifth time T5, the voltage on the adjacent non-selected word line reaches a second voltage V2, and the duration between the second time T2 and the fifth time T5 is a first duration ΔT1; at a sixth time T6, the voltage on the adjacent non-selected word line reaches a third voltage V3; and the duration between the fourth time T4 and the sixth time T6 is a second duration ΔT2;

[0144] The time difference between the first moment T1 and the second moment T2 is greater than or equal to the first time length ΔT1; the time difference between the third moment T3 and the fourth moment T4 is greater than or equal to the second time length ΔT2.

[0145] In this way, by setting the first time length, it is ensured that the voltage on the adjacent non-selected word line has reached the second voltage before the selected word line is pre-charged, and by setting the second time length, it is ensured that the voltage on the adjacent non-selected word line has reached the third voltage before the selected word line is discharged, so as to further improve the control effect of the voltage change amplitude on the adjacent non-selected word line during the charging and discharging process of the selected word line.

[0146] In some embodiments, the first voltage V1 is the same as the third voltage V3 .

[0147] An embodiment of the present application further provides a memory system, comprising: at least one memory as disclosed in the embodiment of the present application; and a controller coupled to the memory and configured to control the memory.

[0148] Here, the memory can be understood with reference to the memory in the aforementioned embodiments of the present application. The internal composition of the memory system can be understood with reference to the aforementioned memory system.

[0149] An embodiment of the present application also provides a word line voltage control circuit, including: a first voltage transmission circuit, configured to provide a first transmission voltage in response to a first enable signal before starting to provide a pre-charge voltage to a selected word line; a second voltage transmission circuit, configured to provide a second transmission voltage in response to a second enable signal before starting to float the selected word line and after starting to provide a pre-charge voltage to the selected word line; a local word line drive circuit, connected to both the first voltage transmission circuit and the second voltage transmission circuit, configured to connect a non-selected word line adjacent to the selected word line to the first voltage transmission circuit before starting to provide a pre-charge voltage to the selected word line, and to connect the adjacent non-selected word line to the second voltage transmission circuit before starting to float the selected word line and after starting to provide a pre-charge voltage to the selected word line.

[0150] Here, the structure of the first voltage transmission circuit can be understood with reference to the second voltage transmission circuit in FIG. 7 , and the second voltage transmission circuit can be understood with the first voltage transmission circuit shown in FIG. 7 .

[0151] The first enable signal can be understood with reference to the second control signal wlup_vneg2 shown in FIG7 , and the first transmission voltage can be understood with reference to the second voltage V2 shown in FIG6 . The second enable signal can be understood with reference to the first control signal wlup_enb shown in FIG7 , and the second transmission voltage can be understood with reference to the first voltage V1 shown in FIG6 .

[0152] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0153] The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0154] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application. Industrial Applicability

[0155] The embodiments of the present application provide a memory and an operation method thereof, a memory system, and a word line voltage control circuit. The memory controls the final voltage at which the voltage on the adjacent non-selected word lines is coupled and pulled up by lowering the voltage supplied to the adjacent non-selected word lines before precharging the selected word lines, which is the highest voltage in the subsequent voltage change. At the same time, the memory controls the final voltage at which the voltage on the adjacent non-selected word lines is coupled and lowered by raising the voltage supplied to the adjacent non-selected word lines before discharging the selected word lines, which is the lowest voltage in the subsequent voltage change. Since the highest voltage forming the voltage change becomes smaller and the lowest voltage becomes larger, the voltage change on the adjacent non-selected word lines can be effectively reduced during the charge-discharge process of the selected word lines, thereby alleviating the row hammer problem and GIDL leakage problem.< / n> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory, the memory comprising a memory cell array and peripheral circuits coupled to the memory cell array; The memory cell array includes a plurality of word lines; The peripheral circuits are configured to: Start providing a precharge voltage to a selected word line among the plurality of word lines at a first moment; at a second moment before the first moment, provide that the voltage on a non-selected word line adjacent to the selected word line changes from a first voltage to a second voltage; and Start floating the selected word line at a third moment after the first moment; at a fourth moment before the third moment and after the first moment, provide that the voltage on the adjacent non-selected word line changes from the second voltage to a third voltage; Wherein, The second voltage is less than the first voltage and the second voltage is less than the third voltage.

2. The memory according to claim 1, Wherein, The voltage on the adjacent non-selected word line reaches the second voltage at a fifth moment, and the duration between the second moment and the fifth moment is a first duration; At a sixth moment, the voltage on the adjacent non-selected word line reaches the third voltage; the duration between the fourth moment and the sixth moment is a second duration; The time difference between the first moment and the second moment is greater than or equal to the first duration; The time difference between the third moment and the fourth moment is greater than or equal to the second duration.

3. The memory according to claim 1 or 2, Wherein, The first voltage is the same as the third voltage.

4. The memory according to claim 3, Wherein, The relationship between the second voltage and the first voltage and the precharge voltage is as follows: |V2| = r(Vpp - V1) Wherein, V1 is the first voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is the coupling coefficient.

5. The memory according to claim 3, Wherein, The peripheral circuits include: a first voltage generator, a second voltage generator, a first voltage transfer circuit, and a second voltage transfer circuit; The first voltage generator, connected to the first voltage transfer circuit, is configured to provide the first voltage; The second voltage generator, connected to the second voltage transfer circuit, is configured to provide the second voltage; The first voltage transfer circuit is configured to transfer the first voltage to the adjacent non-selected word line in response to a first control signal at the fourth moment; The second voltage transfer circuit is configured to transfer the second voltage to the adjacent non-selected word line in response to a second control signal at the second moment.

6. The memory according to claim 5, Wherein, The peripheral circuits further include a control signal generation circuit; the control signal generation circuit is configured to receive an enable control signal and provide the first control signal to the first voltage transfer circuit and provide the second control signal to the second voltage transfer circuit.

7. The memory according to claim 6, Wherein, The peripheral circuits further include a plurality of local word line drive circuits corresponding to the word lines one by one; The local word line driving circuit is configured to connect the adjacent unselected word lines to the first voltage transmission circuit at the first moment and connect the adjacent unselected word lines to the second voltage transmission circuit at the second moment in response to a main word line selection signal, a word line selection signal, and a precharge control signal; Wherein, the main word line selection signal is used to indicate selecting one of multiple main word lines of the peripheral circuit, and each of the main word lines corresponds to multiple word lines; the word line selection signal is used to indicate selecting one of the multiple word lines corresponding to the main word line; the precharge control signal is used to indicate providing the precharge voltage to the selected word line.

8. The memory according to claim 7, Wherein, The control signal generating circuit is connected to the first voltage transmission circuit through a first node; the control signal generating circuit is connected to the second voltage transmission circuit through a second node; Both the first voltage transmission circuit and the second voltage transmission circuit are connected to the local word line driving circuit through a third node; Both the first voltage generator and the second voltage generator are connected to the control signal generating circuit.

9. The memory according to claim 7, Wherein, The multiple local word line driving circuits are divided into multiple groups; each group of local word line driving circuits corresponds to one of the first voltage generator, one of the second voltage generator, one of the first voltage transmission circuit, and one of the second voltage transmission circuit.

10. The memory according to claim 8, Wherein, The first voltage transmission circuit includes a first transistor, and the second voltage transmission circuit includes a second transistor and a third transistor; The first end of the first transistor is used to receive the first control signal, the second end is connected to the first voltage generator, and the third end is connected to the third end of the second transistor; The first end of the second transistor is used to receive the second control signal, and the second end is connected to the third end of the third transistor; The first end of the third transistor is used to receive the word line selection signal, and the second end is connected to the second voltage generator.

11. The memory according to claim 10, Wherein, The first transistor, the second transistor, and the third transistor are of the field effect MOS transistor type; The first end of the field effect MOS transistor is the gate, the second end is the source, and the third end is the drain.

12. The memory according to claim 11, Wherein, The first transistor, the second transistor, and the third transistor are of the N-type channel field effect MOS transistor type.

13. The memory according to claim 1, Wherein, The precharge voltage is a high-level voltage; the first voltage, the second voltage, and the third voltage are all negative voltages.

14. The memory according to claim 1, Wherein, The memory includes a dynamic random access memory.

15. The memory according to claim 14, Wherein, The memory cell array and the peripheral circuit are coupled by a bonding method.

16. The memory according to claim 1, wherein, when the selected word line is the Nth word line, the adjacent non - selected word lines include the (N - 1)th word line and the (N + 1)th word line.

17. The memory according to claim 16, wherein, the adjacent non - selected word lines further include word lines with a number M of word lines spaced from the selected word line; where M is a natural number and 1 ≤ M ≤ 4.

18. The memory according to claim 16, wherein, the absolute value of the voltage difference between the second voltage and the first voltage decreases as the distance between the adjacent non - selected word lines and the selected word line increases.

19. A memory system, comprising: at least one memory according to any one of claims 1 to 18; and a controller coupled to the memory and configured to control the memory.

20. A word line voltage control circuit, comprising: a first voltage transmission circuit configured to provide a first transmission voltage in response to a first enable signal before starting to provide a pre - charge voltage to a selected word line; a second voltage transmission circuit configured to provide a second transmission voltage in response to a second enable signal after starting to float the selected word line and before starting to provide a pre - charge voltage to the selected word line; a local word line driving circuit connected to both the first voltage transmission circuit and the second voltage transmission circuit, configured to connect the non - selected word lines adjacent to the selected word line to the first voltage transmission circuit before starting to provide a pre - charge voltage to the selected word line, and to connect the adjacent non - selected word lines to the second voltage transmission circuit after starting to float the selected word line and before starting to provide a pre - charge voltage to the selected word line.

21. An operation method of a memory, the method comprising: starting to provide a pre - charge voltage to a selected word line among multiple word lines of the memory at a first moment; providing that the voltage on the non - selected word lines adjacent to the selected word line changes from a first voltage to a second voltage at a second moment before the first moment; and starting to float the selected word line at a third moment after the first moment; providing that the voltage on the adjacent non - selected word lines changes from the second voltage to a third voltage at a fourth moment before the third moment and after the first moment; wherein, the second voltage is less than the first voltage and the second voltage is less than the third voltage.

22. The operation method according to claim 21, wherein, the voltage on the adjacent non - selected word lines reaches the second voltage at a fifth moment, and the duration between the second moment and the fifth moment is a first duration; the voltage on the adjacent non - selected word lines reaches the third voltage at a sixth moment; the duration between the fourth moment and the sixth moment is a second duration; the time difference between the first moment and the second moment is greater than or equal to the first duration; the time difference between the third moment and the fourth moment is greater than or equal to the second duration.

23. The operation method according to claim 21 or 22, wherein, the first voltage is the same as the third voltage.

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