Encoder structure for high reliability in short block-length regimes

Abstract

Various aspects of the present disclosure relate to an enhanced encoder design (and associated signaling), such as an enhanced encoder structure for a quasi-cyclic low-density parity-check (QC-LDPC) encoder. The new encoder may enable a larger girth (e.g., a length of the shortest cycle of a Tanner graph) without adding complexity to a hardware implementation of the encoder, by using permutation matrices. Thus, the enhanced encoder may facilitate the use of short or finite-length codes with wireless communications data channels, among other benefits.

Description

ENCODER STRUCTURE FOR HIGH RELIABILITY IN SHORT BLOCK- LENGTH REGIMES CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 620,332, filed on January 12, 2024, entitled ENCODER STRUCTURE FOR HIGH RELIABILITY IN SHORT BLOCK-LENGTH REGIMES, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to wireless communications, and more specifically to encoding information for wireless communications. BACKGROUND

[0003] A wireless communications system may include one or multiple network communication devices, such as base stations, which may support wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE), or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers, or the like). Additionally, the wireless communications system may support wireless communications across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G)).

[0004] Some use cases supported by a wireless communications system, such as enhanced ultra-reliable low-latency communications (eURLLC), are predicted to rely on significantly lower end-to-end latency (less than 1ms) compared to the latencies within 5G Attorney Docket No.793MS0117PCNR wireless communication systems, as well as realize high levels of transmission reliability (e.g., where a block error rate (BLER) is less than 10−7).

[0005] eURLLC, and similar communications use cases, can enable certain emerging applications, such as factory applications, tactile internet services, distributed utility grid, metaverse applications, and mission-critical applications (e.g., telesurgery, autonomous driving, factory automation, and so on). Thus, a wireless communications system, such as a 5G NR or 6G radio access technology system, may seek to implement standardized processes to enable the enhanced end-to-end latency and reliability parameters. SUMMARY

[0006] An article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on. Further, as used herein, including in the claims, a “set” may include one or more elements.

[0007] The present disclosure relates to methods, apparatuses, and systems that facilitate the design and implementation of an enhanced encoder design, such as a quasi- cyclic low-density parity-check (QC-LDPC) encoder.

[0008] Some implementations of the method and apparatuses described herein may further include an encoder, comprising at least one memory and at least one processor coupled with the at least one memory and configured to cause the encoder to apply a permutation matrix to a parity-check matrix of a quasi-cyclic low-density parity-check Attorney Docket No.793MS0117PC(QC-LDCP) code or to an information bits vector to which the parity-check matrix is applied, generate a codeword based on the application of the permutation matrix to the parity-check matrix of the QC-LDCP code, and transmit the generated codeword to a decoder over a data channel.

[0009] In some implementations of the method and apparatuses described herein, the at least one processor is further configured to cause the encoder to generate a set of permutation matrices associated with maximizing a girth of a Tanner graph for the QC- LDPC code and select the permutation matrix from the generated set of permutation matrices.

[0010] In some implementations of the method and apparatuses described herein, each permutation matrix of the set of permutation matrices is associated with a code rate, an information bits size, a Tanner graph’s girth, and a target block error rate (BLER) performance.

[0011] In some implementations of the method and apparatuses described herein, the BLER performance is determined based on Monte Carlo simulations performed over an Additive White Gaussian Noise (AWGN) channel.

[0012] In some implementations of the method and apparatuses described herein, each permutation matrix of the set of permutation matrices is designed based on a modified progressive edge growth (PEG) algorithm.

[0013] In some implementations of the method and apparatuses described herein, the application of the permutation matrix to the parity-check matrix of the QC-LDCP code preserves quasi-cyclicity properties of the parity-check matrix.

[0014] In some implementations of the method and apparatuses described herein, the QC-LDCP code is a 5G new radio (NR) LCDP code.

[0015] In some implementations of the method and apparatuses described herein, the encoder is part of a network entity of a 5G communications network.

[0016] Some implementations of the method and apparatuses described herein may further include a processor for wireless communication, comprising at least one controller Attorney Docket No.793MS0117PCcoupled with at least one memory and configured to cause the processor to apply a permutation matrix to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied, generate a codeword based on the application of the permutation matrix to the parity-check matrix of the QC-LDCP code, and transmit the generated codeword to a receiver over a data channel.

[0017] In some implementations of the method and apparatuses described herein, the at least one controller is further configured to cause the processor to generate a set of permutation matrices associated with maximizing a girth of a Tanner graph for the QC- LDPC code and select the permutation matrix from the generated set of permutation matrices.

[0018] In some implementations of the method and apparatuses described herein, each permutation matrix of the set of permutation matrices is associated with a code rate, an information bits size, a Tanner graph girth, and a target block error rate (BLER) performance.

[0019] Some implementations of the method and apparatuses described herein may further include a decoder, comprising at least one memory and at least one processor coupled with the at least one memory and configured to cause the decoder to receive reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied and decode a received codeword using the permutation matrix referenced by the received reference bits signaled within downlink control information (DCI).

[0020] In some implementations of the method and apparatuses described herein, the reference bits are referenced by a modulation and coding scheme (MCS) field within the DCI.

[0021] In some implementations of the method and apparatuses described herein, the MCS field of the DCI can include the reference bits that point to the permutation matrix a modulation, and a code rate tabulated in an associated MCS table.

[0022] In some implementations of the method and apparatuses described herein, the reference bits are signaled within a new DCI field of the DCI. Attorney Docket No.793MS0117PC

[0023] In some implementations of the method and apparatuses described herein, a size of the new DCI field is based on a number of tabulated permutation matrices from which the permutation matrix is selected.

[0024] In some implementations of the method and apparatuses described herein, the reference bits are signaled within a dedicated field of a new DCI format.

[0025] Some implementations of the method and apparatuses described herein may further include a processor for wireless communication, comprising at least one controller coupled with at least one memory and configured to cause the processor to receive reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied and decode a received codeword using the permutation matrix represented by the received reference bits.

[0026] In some implementations of the method and apparatuses described herein, the reference bits are received within DCI.

[0027] In some implementations of the method and apparatuses described herein, the reference bits are referenced by the MCS field within the DCI. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 illustrates an example of a wireless communications system in accordance with aspects of the present disclosure.

[0029] Figure 2 illustrates an example encoder structure in accordance with aspects of the present disclosure.

[0030] Figures 3A-3B illustrate example graphs that depict LDPC code performance at different block sizes in accordance with aspects of the present disclosure.

[0031] Figure 4 illustrates another example encoder structure in accordance with aspects of the present disclosure.

[0032] Figure 5 illustrates an example of a user equipment (UE) in accordance with aspects of the present disclosure. Attorney Docket No.793MS0117PC

[0033] Figure 6 illustrates an example of a processor in accordance with aspects of the present disclosure.

[0034] Figure 7 illustrates an example of a network equipment (NE) in accordance with aspects of the present disclosure.

[0035] Figure 8 illustrates a flowchart of a method performed by an encoder in accordance with aspects of the present disclosure.

[0036] Figure 9 illustrates a flowchart of a method performed by a decoder in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0037] As described herein, eURLLC, which includes communications having short packet sizes and short block lengths, can enable services with stringent requirements for various key performance indicators (KPIs), such as low end-to-end transmission latency, ultra-reliability (10-7), packet size flexibility, and / or availability. Such communications provide connectivity for enhanced services, such as emerging applications and services from vertical domains. plays an essential role in providing connectivity for the new services and applications from vertical domains, such as factory automation, tactile internet, autonomous driving and so on.

[0038] To satisfy these KPIs, legacy channel codes (e.g., LDPC and polar codes), may be updated and / or enhanced. For example, with large block lengths, systems can estimate the performance of LDPC codes using asymptotic techniques (e.g., density evolution techniques). Data channels (e.g., 5G NR data channels) utilize QC-LDPC codes due to their low complexity implementation and near Shannon limit performance, based on iterative decoding that is very close to the Shannon limit over Additive White Gaussian Noise (AWGN) channels.

[0039] However, with finite (e.g., short) block lengths, such techniques may not be effective in estimating performance. Iteratively decoded finite-length codes can demonstrate an abrupt change in their error rate curves, referred to as error floor, within high signal to noise ratio (SNR) and low bit-error-rate (BER) regimes. Attorney Docket No.793MS0117PC

[0040] For example, short cycles may cause trapping and absorbing sets within an LDPC Tanner graph. A Tanner graph, or a bipartite graph, include two sets of nodes, variable nodes and check nodes. The variable nodes correspond to the number of codeword symbols, and the check nodes correspond to the number of parity symbols. Edges connect variable nodes constrained by check nodes. With the Tanner graph, a cycle, having a length ^^^^, is a path within the graph having ^^^^ edges that closes back to itself. A girth, ^^^^, of a code is a length of the shortest cycle within the Tanner graph associated with the code. Cycles can degrade the performance of iterative decoding algorithms used for LDPC codes.

[0041] Also, because belief-propagation (BP) or sum-product algorithm (SPA) over cycle-free Tanner graphs can provide optimum decoding, minimizing the influence of cycles during an iterative decoding process can realize enhanced performance when decoding finite-length codes. For example, when the cycles are made long enough, the decoding algorithm may run several iterations without being affected by the lengths of the cycles, while the error rate decreases exponentially with the number of independent iterations. For example, a progressive edge growth (PEG) construction may design Tanner graphs having a large shortest cycle length (girth) in a best-effort sense by progressively establishing edges between symbol and check nodes in an edge-by-edge manner.

[0042] Thus, the systems and method described herein provide an enhanced error floor performance of QC-LDPC codes within small to moderate block length regimes by maximizing the girth of the QC-LDPC Tanner graph using permutation matrices. For example, the systems and methods provide a new or enhanced QC-LDPC encoder design (and associated signaling), which enables a larger girth (e.g., a length of the shortest cycle of the Tanner graph) without adding complexity to the hardware implementation of the QC- LDPC encoder. Thus, the enhanced encoder may facilitate the use of finite-length LDPC codes with wireless communications data channels, among other benefits.

[0043] Figure 1 illustrates an example of a wireless communications system 100 in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more NE 102, one or more UE 104, and a core network (CN) 106. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, Attorney Docket No.793MS0117PCsuch as an LTE network or an LTE-Advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a NR network, such as a 5G network, a 5G-Advanced (5G-A) network, or a 5G ultrawideband (5G-UWB) network. In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G, for example, 6G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA), frequency division multiple access (FDMA), or code division multiple access (CDMA), etc.

[0044] The one or more NE 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the NE 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a network function, a network entity, a radio access network (RAN), a NodeB, an eNodeB (eNB), a next-generation NodeB (gNB), or other suitable terminology. An NE 102 and a UE 104 may communicate via a communication link, which may be a wireless or wired connection. For example, an NE 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

[0045] An NE 102 may provide a geographic coverage area for which the NE 102 may support services for one or more UEs 104 within the geographic coverage area. For example, an NE 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc.) according to one or multiple radio access technologies. In some implementations, an NE 102 may be moveable, for example, a satellite associated with a non-terrestrial network (NTN). In some implementations, different geographic coverage areas associated with the same or different radio access technologies may overlap, but the different geographic coverage areas may be associated with different NE 102.

[0046] The one or more UE 104 may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a Attorney Docket No.793MS0117PCremote unit, a mobile device, a wireless device, a remote device, a subscriber device, a transmitter device, a receiver device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an Internet-of-Things (IoT) device, an Internet-of-Everything (IoE) device, or machine-type communication (MTC) device, among other examples.

[0047] A UE 104 may be able to support wireless communication directly with other UEs 104 over a communication link. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

[0048] An NE 102 may support communications with the CN 106, or with another NE 102, or both. For example, an NE 102 may interface with other NE 102 or the CN 106 through one or more backhaul links (e.g., S1, N2, N2, or network interface). In some implementations, the NE 102 may communicate with each other directly. In some other implementations, the NE 102 may communicate with each other or indirectly (e.g., via the CN 106. In some implementations, one or more NE 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC). An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmission-reception points (TRPs).

[0049] The CN 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The CN 106 may be an evolved packet core (EPC), or a 5G core (5GC), which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME), an access and mobility management functions (AMF)) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW), a Packet Data Network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the Attorney Docket No.793MS0117PCcontrol plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc.) for the one or more UEs 104 served by the one or more NE 102 associated with the CN 106.

[0050] The CN 106 may communicate with a packet data network over one or more backhaul links (e.g., via an S1, N2, N2, or another network interface). The packet data network may include an application server. In some implementations, one or more UEs 104 may communicate with the application server. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the CN 106 via an NE 102. The CN 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server using the established session (e.g., the established PDU session). The PDU session may be an example of a logical connection between the UE 104 and the CN 106 (e.g., one or more network functions of the CN 106).

[0051] In the wireless communications system 100, the NEs 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communications). In some implementations, the NEs 102 and the UEs 104 may support different resource structures. For example, the NEs 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the NEs 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the NEs 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures). The NEs 102 and the UEs 104 may support various frame structures based on one or more numerologies.

[0052] One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., ^^^^=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., ^^^^=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., ^^^^=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., ^^^^=2) may be associated with Attorney Docket No.793MS0117PCa third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., ^^^^=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., ^^^^=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

[0053] A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames). Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

[0054] Additionally, or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., ^^^^=0, ^^^^=1, ^^^^=2, ^^^^=3, ^^^^=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing), a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., ^^^^=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

[0055] In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, Attorney Docket No.793MS0117PCfrequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz – 7.125 GHz), FR2 (24.25 GHz – 52.6 GHz), FR3 (7.125 GHz – 24.25 GHz), FR4 (52.6 GHz – 114.25 GHz), FR4a or FR4-1 (52.6 GHz – 71 GHz), and FR5 (114.25 GHz – 300 GHz). In some implementations, the NEs 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the NEs 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., control information, data). In some implementations, FR2 may be used by the NEs 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

[0056] FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies). For example, FR1 may be associated with a first numerology (e.g., ^^^^=0), which includes 15 kHz subcarrier spacing; a second numerology (e.g., ^^^^=1), which includes 30 kHz subcarrier spacing; and a third numerology (e.g., ^^^^=2), which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies). For example, FR2 may be associated with a third numerology (e.g., ^^^^=2), which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., ^^^^=3), which includes 120 kHz subcarrier spacing.

[0057] As described herein, the technology provides a new or enhanced encoder design, such as a QC-LDPC encoder, for encoding QC-LDPC codes utilized by eURLLC and other data communications having short packet sizes and short block lengths. The QC-LDPC encoder described herein can enable a larger Tanner graph girth while maintaining a low complexity encoding scheme and simple hardware implementation. As described herein, QC-LDPC encoder provides a better error floor performance for short length regimes.

[0058] For example, a QC-LDPC parity-check matrix can be constructed using a base graph (e.g., one of the two base graphs defined in the 3GPP specification) and selected lifting sizes and circulant matrices. The selection of the base graph and / or lifting size depends on the code rate and information bits length. Thus, a resulting parity-check matrix ^^^^ has a girth ^^^^. The technology described herein designs and / or implements one or more permutation matrices ^^^^^^^^that enable higher Tanner graph girth of ^^^^ by selectively Attorney Docket No.793MS0117PCpermuting well-chosen columns and / or rows of ^^^^ to facilitate a higher shortest cycle length of the graph while maintaining quasi-cyclicity properties of the parity-check matrix.

[0059] In some cases, the design or configuration of the permutation matrices is based on a modified progressive edge growth (PEG) algorithm. Such a technique can provide a better error floor performance for short to moderate QC-LDPC code block lengths by eliminating absorbing sets within the LDPC Tanner graph.

[0060] Further, for a decoder or receiver of a codeword to decode the received codeword, the technology (e.g., from the encoder) can signal parameters of the permutation matrix to the decoder. The decoder, receiving the codeword and the parameters, can perform LDPC iterative decoding of the codeword. In some cases, using the techniques described herein, iterative decoding convergence at the decoder can be realized in fewer iterations, due to the elimination or minimization of trapping sets, among other benefits.

[0061] Figure 2 illustrates an example encoder 200 structure in accordance with aspects of the present disclosure. As described herein, the design or structure of the encoder 200 (e.g., QC-LDPC encoder), includes a permutation matrix 250, or interleaver, that permutes a QC-LDPC parity-check matrix. The permutation matrix 250 is designed or configured to enable larger Tanner graph girth, allowing for better error floor performance at short to moderate block lengths.

[0062] In some cases, the permutation matrix design is based on a modified version of the progressive edge growth (PEG) algorithm, aiming to maximize the Tanner graph girth or maximize the connectivity of the shortest cycle nodes with the rest of the graph nodes (e.g., maximize ACE metric) when the girth cannot be maximized beyond a certain value. Further, the encoder 200 may determine several permutation matrices for different code rates and information block sizes, The encoder 200 may tabulate the permutation matrices along with achieved girth and BLER performance. Thus, encoder complexity is not impacted when the quasi-cyclic property of the parity-check matrix is preserved after performing the permutation.

[0063] In some embodiments, the permutation matrix 250, or ^^^^^^^^, can be designed based on a modified progressive edge growth (PEG) algorithm, and can be applied to a parity- Attorney Docket No.793MS0117PCcheck matrix 230, or ^^^^, of an NR QC-LDPC code constructed with a certain Tanner graph girth ^^^^. The permutation matrix enables the maximization of the Tanner graph girth of H, which enables better error floor performance of the LDPC codes in the medium and short block length regimes.

[0064] In some cases, a girth optimization procedure may be performed offline or before information bits are encoded. The encoder 200 can tabulate or select, via a selection module 260, permutation matrices corresponding to different code rates, girth values, BLER performance, and / or information bits sizes. Thus, the selected permutation matrix 250, or ^^^^^^^^, permutes columns and / or rows of the parity-check matrix (PCM) 230, or ^^^^, to maximize the shortest cycle length without impacting the encoder complexity and hardware implementation. Such a design can enhance a short block length regime where 5G NR LDPC codes exhibit an error floor around 10−4for certain block lengths and certain code rates.

[0065] Maximization of the Tanner graph girth can allow for better QC-LDPC performance in the waterfall region as well as better performance in the error floor region. Figures 3A-3B illustrate example graphs that depict QC-LDPC code performance at different block sizes in accordance with aspects of the present disclosure. For example, graph 300, shown in Figure 3A, depicts the performance of LDPC codes at different short block sizes with a code rate of 0.66667. As another example, graph 350, shown in Figure 3B, depicts the performance of LDPC codes at different short block sizes with a code rate of 0.5.

[0066] In some embodiments, the structure of the encoder 200 may include legacy base graph selection 210, lifting size and circulant matrices selection 220, and a determined LDPC parity check matrix 230, or ^^^^. The structure can also include the permutation matrix 250, as well as a permutation matrix selection module 240. The selected permutation matrix 250 is applied to the selected parity-check matrix 230, and the encoder 200 performs permutations over the columns and / or rows of the parity-check matrix ^^^^ to generate orform a new LDPC parity check matrix 260, or ^^^^′ = ^^^^^^^^^^^^.

[0067] The new matrix 260 encodes the information bits ^^^^^^^^ , 1 ≤ ^^^^ ≤ ^^^^, such that:Attorney Docket No.793MS0117PC

[0068] ^^^^^^^^^^^^^^^^^^^^ = ^^^^^^^^^^^^′ = 0.

[0069] When the girth cannot be maximized beyond a certain value, the algorithm may maximize a cycle node connectivity measured by the ACE (approximated cycle EMD), which is a parameter that measures the connectivity of the cycle with the rest of the graph and may be determined as a function of the node’s degree. Thus, the algorithm may enable the design of a permutation matrix that preserves a relatively small girth but maximizes the ACE of the variable nodes within the shortest cycle. This design may realize a better error floor performance and the convergence of the iterative decoder in less iterations.

[0070] In some cases, the permutation matrix may be designed such that the quasi- cyclicity properties of ^^^^ are preserved. For example, row or column permutations may not be performed within the same circulant matrix (e.g., a column ^^^^^^^^, which belongs to the circulant matrix ^^^^^^^^,^^^^, would be permuted with another column ^^^^ℎ, which belongs to another circulant matrix ^^^^^′^^^,^^^^). This design may further constrain the optimization problem.

[0071] In some cases, ^^^^′may be designed to be non-quasi-cyclic, where the parity check matrix is not structured and may be considered a pseudo-random matrix. However, in both cases, the parity check matrix may be sparse, and an associated iterative decoder can successfully decode a codeword generated by the encoder 200, possibly introducing additional complexity at the encoder 200.

[0072] In some embodiments, given the associativity of matrix multiplication, the encoding process of information bits vector ^^^^ may be expressed as follows:

[0073] c=^^^^ (^^^^^^^^^^^^),

[0074] where ^^^^ is the LDPC code generator matrix, and ^^^^ is the codeword. Using this encoding process, QC LDPC code properties are preserved, and the permutation matrix is applied to the information bits vector ^^^^.

[0075] Further, in some cases, the permutation matrix ^^^^^^^^may be a deterministic interleaver applied to the information sequence prior to the LDPC encoding process, as described herein. In these cases, the LDPC encoding structure my preserve its low complexity based on an interleaver and simple linear shift registers. The permutation Attorney Docket No.793MS0117PCmatrices may be tabulated based on the desired girth value and targeted BLER performance. Table 1 presents a permutation matrix and associated properties: Permutation Information Code Rate Achieved BLER Matrix Bits length Girth performance ^^^^^^^^

[0076] In some embodiments, different permutation matrices associated with different code rates and information bits block lengths may be determined offline by solving the corresponding optimization problem. In such cases, the different permutation matrices may be tabulated. As described above, Table 1 maps the permutation matrix to associated properties, such as the maximum girth that may be achieved, the code rate, block length, and the block error rate (BLER) performance. In some cases, the BLER performance may be determined by running a monte Carlo simulation over a BI-AWGN channel.

[0077] In some embodiments, resolution of the convex optimization problem described herein enables the design of a permutation matrix used to maximize the girth of the LDPC Tanner graph. For example, the permutation matrix design algorithm may be based on a combination of a modified PEG algorithm and ACE-constrained algorithm. The main difference is that PEG is used for the construction of LDPC codes with large girth given the variable nodes’ degree distributions. However, in some cases, the input to the modified PEG algorithm is the QC-LDPC parity-check matrix ^^^^ with a certain girth value ^^^^ and the algorithm allows the design of permutations that outputs a parity-check matrix ^^^^′having agirth ^^^^′ such that ^^^^′ > ^^^^.

[0078] Given a (^^^^, ^^^^)- QC-LDPC parity-check matrix ^^^^, as follows:^^^^(0) ^^^^(^^^^1,^^^^) ⋯ ^^^^(0)�Attorney Docket No.793MS0117PC

[0079] where 1 ≤ ^^^^ ≤ ^^^^ and 1 ≤ ^^^^ ≤ ^^^^, ^^^^�^^^^^^^^,^^^^� represent the circulant permutationmatrix with a 1 at column- (^^^^ + ^^^^^^^^,^^^^) ^^^^^^^^^^^^ (^^^^ + 1) and 0 ≤ ^^^^ ≤ ^^^^ − 1 (where ^^^^ is thelifting size according to TR.38.211), and zeros elsewhere. It follows that ^^^^(0) represents the ^^^^ × ^^^^ zeros matrix. In addition, since the ^^^^ rows of each of the ^^^^ submatrices�^^^^(0) ^^^^�^^^^^^^^,1�… ^^^^�^^^^^^^^,^^^^, 0 ≤ ^^^^ ≤ ^^^^ sum of the all-1 vector, the rank of H is at most[^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^ ≤ [^^^^^^^^ − ^^^^ + 1]

[0080] Since a cycle of length ^^^^ = 2^^^^ in ^^^^ = [ℎ^^^^,^^^^] is defined by 2^^^^ positions ℎ^^^^,^^^^ = 1such that: (1) two consecutive positions are changing alternatively of row orcolumn only and (2) all positions are distinct and last ones. It follows that two consecutive positions in any cycle belong to distinct circulant permutation matrices which are either in the same row, or in the same column. Hence, a cycle of length 2^^^^ can be associated with an ordered series of circulant permutation matrices. ^^^^�^^^^^^^^0,^^^^0�, ^^^^�^^^^^^^^1,^^^^0�, ^^^^�^^^^^^^^1,^^^^1�… . ^^^^�^^^^^^^^^^^^−1,^^^^^^^^−1�… … .. ^^^^(^^^^^^^^0,^^^^0)

[0081] withof going from^^^^(^^^^^^^^^^^^−1,^^^^^^^^−1) to ^^^^(^^^^^^^^^^^^,^^^^^^^^) via ^^^^(^^^^^^^^^^^^,^^^^^^^^−1). Any cycle of length 2^^^^ in H can be represented by(^^^^0, ^^^^0); (^^^^1, ^^^^1), … … . (^^^^^^^^−1, ^^^^^^^^−1); (^^^^0, ^^^^0)

[0082] with 1 ≤ ^^^^△^^^^^^^^,^^^^^^^^ (^^^^) = ^^^^^^^^^^^^,^^^^ − ^^^^^^^^^^^^,^^^^

[0083] The matrix Hand only if: ∑^^^^−1 ^^^^=0△^^^^^^^^,^^^^^^^^+1 (^^^^^^^^) =0 ^^^^^^^^^^^^ ^^^^.

[0084] with ^^^^0 = ^^^^^^^^ , ^^^^^^^^ ≠ ^^^^^^^^+1 and ^^^^^^^^ ≠ ^^^^^^^^+1. This simple graph representation of Hdefined in (1) to have a girth at least 2(^^^^ + 1) is:^^^^−1 ^^^^Attorney Docket No.793MS0117PC

[0085] For all m; 2 ≤ ^^^^ ≤ ^^^^ ; all ^^^^^^^^, 0 ≤ ^^^^^^^^ ≤ ^^^^ − 1, all ^^^^^^^^+1, 0 ≤ ^^^^^^^^+1 ≤ ^^^^ − 1 andall 0 ≤ ^^^^^^^^ ≤ ^^^^ − 1 with ^^^^0 = ^^^^^^^^, ^^^^^^^^ ≠ ^^^^^^^^+1 and ^^^^^^^^ ≠ ^^^^^^^^+1.

[0086] Thus, an example girth-maximization algorithm for QC-LDPC coded may include some or all of the following steps:

[0087] Identify the shortest length (g-length) cycle ^^^^ edges of ^^^^: ^^^^1 ∪ ^^^^2 … .∪ ^^^^^^^^

[0088] Identify the degree distribution ^^^^^^^^^^^^of each variable node ^^^^^^^^involved in the cycle.

[0089] Evaluate each paths’ ACE: cycle connectivity.

[0090] Group edges having less ACE and variable nodes having higher degree distribution within the cycle.

[0091] Permute the columns or row containing the edge having smallest ACE and corresponding to variable node having highest degree distribution with another column or row belonging to another circulant matrix such that (1) No new cycle is being created bythe permutation and (2) The new girth of the cycle ^^^^ is ^^^^ > ^^^^.

[0092] ^^^^ = ^^^^ ; ^^^^ = ^^^^′ and ℙ = [^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^ ; ℙ], where ^^^^^^^^^^^^^^^^ , ^^^^^^^^^^^^^^^^ are the columns’indices of the permuted columns in ^^^^.

[0093] Repeat steps 1), 2), 3), 4) and 5) until: (1) ^^^^^^^^^^^^^^^^is achieved, or (2) connectivity is maximized.

[0094] Return ^^^^; ^^^^ and ℙ, and end.

[0095] In some embodiments, the permutation matrix may directly permute an information bits vector. Figure 4 illustrates another example encoder 400 structure in accordance with aspects of the present disclosure. The encoder 400 includes an interleaver 410, as described herein, which receives a permutation matrix 420 and transmits the permutation matrix 420 and information bits to an encoding module 430, which applies the permutations to the information bits to generate a codeword (e.g., ^^^^′(^^^^^^^^^^^^)). Further, similarAttorney Docket No.793MS0117PCto the structure of the encoder 200, the complexity of the encoder 400 is minimized when the interleaver 410 is applied to the information bits vector before LDPC encoding.

[0096] In some embodiments, the girth-maximization of QC-LDPC codes described herein may include LDPC decoder-based optimization, such as a sum-product algorithm (SPA). For example, a decoder-based algorithm compares the performance of the code under the current graph setting for each of the candidate check nodes, and the permutation that produces the best performance according to the SPA is selected.

[0097] While complexity and processing at the encoder may be increased, such selection may realize a better performance, such as in the error-floor region (e.g., a region of high SNR or low BER). In such cases, a ^^^^^′^^^^^^^^^^^^^^^is constructed using the algorithm described herein and associated with a permutation matrix ^^^^^^^^. For each (^^^^) candidate codes generated using this test, PCM are subjected to an AWGN channel and over a range of values of signal-to-noise ratio (SNR), and the candidate PCM is used to decode through iterative decoding (e.g., SPA decoding). The performance of each candidate code is evaluated in terms of error floor performance and iterative decoding convergence. Finally, the code providing the best performance indicates the candidate permutation to choose for girth-maximization. Thus, the decoder-optimized girth-maximization algorithm may allow for better performance with acceptable complexity increases at the encoder.

[0098] In some embodiments, the encoders 200 or 400 may employ different signaling procedures to signal an applied permutation matrix to a decoder. For example, the encoders 200 or 400 may include different downlink control information (DCI) formats, which may include additional fields that incorporate a reference to a corresponding or applied permutation matrix. In some cases, the DCI fields may impact the DCI size of legacy DCI formats. Further, in some cases, permutation matrices may be tabulated within the same modulation and coding scheme (MCS) tables and the field “Modulation and Coding scheme” within the DCI may indicate both the MCS scheme and the permutation matrix being used for generating codewords.

[0099] In some embodiments, the channel coding signaling of the LDPC parameters to a decoder may include information about the permutation matrix being used, to allow for Attorney Docket No.793MS0117PCproper decoding of a received codeword. In some cases, a permutation matrix reference may be indicted within a DCI mechanism field “Modulation and coding Scheme.”

[0100] In some cases, some bits, depending on the number of permutation matrices being tabulated, may be added to DCI where the bits convey or refer to a permutation matrix. The added bits may impact the DCI sizes of existing DCI formats, and DCI formats may include a field of N bits dedicated to signaling the permutation matrix reference. Forexample, when the number of tabulated permutation matrices ^^^^ is ^^^^ = 64 matrices, then 6bits may be added to a legacy DCI format or assigned within a new DCI format to signal the permutation matrix reference to the receiver (e.g., the decoder).

[0101] Table 2 presents a permutation matrix reference with DCI formats 0_0, as follows: Field Number of Description bits n f e

[0102] In some cases, different permutation matrices may be tabulated within the same MCS table and one or several permutation matrices may be added according to the code rate, modulation order, and / or spectral efficiency. In such cases, the same reference in DCI Attorney Docket No.793MS0117PCindicating the modulation and coding scheme could also indicate the permutation matrix being used at the encoder, as shown in Table 3: MCS Modulation Ta Spectral Permutation Index Order rget code Rate R x

[1024] efficiency matrix

[0103] In some cases, the decoder may perform a blind identification of the permutation matrix used at the encoder. For example, the reference to the matrix may not be signaled to the receiver, but the receiver may use the knowledge of LDPC parity-check matrix ^^^^ and extract the permuted parity check matrix ^^^^′from the received codeword.

[0104] As described herein, the encoder and / or decoder can be part of the UE 104, the network entity 102, or other functions, devices, or entities of the wireless communications system 100.

[0105] Figure 5 illustrates an example of a UE 500 in accordance with aspects of the present disclosure. The UE 500 may include a processor 502, a memory 504, a controller 506, and a transceiver 508. The processor 502, the memory 504, the controller 506, or the transceiver 508, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

[0106] The processor 502, the memory 504, the controller 506, or the transceiver 508, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. Attorney Docket No.793MS0117PC

[0107] The processor 502 may include an intelligent hardware device (e.g., a general- purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof). In some implementations, the processor 502 may be configured to operate the memory 504. In some other implementations, the memory 504 may be integrated into the processor 502. The processor 502 may be configured to execute computer-readable instructions stored in the memory 504 to cause the UE 500 to perform various functions of the present disclosure.

[0108] The memory 504 may include volatile or non-volatile memory. The memory 504 may store computer-readable, computer-executable code including instructions when executed by the processor 502 cause the UE 500 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 504 or another type of memory. Computer-readable media includes both non- transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0109] In some implementations, the processor 502 and the memory 504 coupled with the processor 502 may be configured to cause the UE 500 to perform one or more of the functions described herein (e.g., executing, by the processor 502, instructions stored in the memory 504). For example, the processor 502 may support wireless communication at the UE 500 in accordance with examples as disclosed herein. The UE 500 may be configured to support a means for applying a permutation matrix to a parity-check matrix of a QC- LDCP code or to an information bits vector to which the parity-check matrix is applied, generating a codeword based on the application of the permutation matrix to the parity- check matrix of the QC-LDCP code, and transmitting the generated codeword to a receiver over a data channel.

[0110] As another example, the processor 502 may support wireless communication at the UE 500 in accordance with examples as disclosed herein. The UE 500 may be configured to support a means for receiving reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits Attorney Docket No.793MS0117PCvector to which the parity-check matrix is applied and decoding a received codeword using the permutation matrix represented by the received reference bits.

[0111] The controller 506 may manage input and output signals for the UE 500. The controller 506 may also manage peripherals not integrated into the UE 500. In some implementations, the controller 506 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 506 may be implemented as part of the processor 502.

[0112] In some implementations, the UE 500 may include at least one transceiver 508. In some other implementations, the UE 500 may have more than one transceiver 508. The transceiver 508 may represent a wireless transceiver. The transceiver 508 may include one or more receiver chains 510, one or more transmitter chains 512, or a combination thereof.

[0113] A receiver chain 510 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 510 may include one or more antennas for receive the signal over the air or wireless medium. The receiver chain 510 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 510 may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 510 may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

[0114] A transmitter chain 512 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 512 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 512 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 512 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium. Attorney Docket No.793MS0117PC

[0115] Figure 6 illustrates an example of a processor 600 in accordance with aspects of the present disclosure. The processor 600 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 600 may include a controller 602 configured to perform various operations in accordance with examples as described herein. The processor 600 may optionally include at least one memory 604, which may be, for example, an L1 / L2 / L3 cache. Additionally, or alternatively, the processor 600 may optionally include one or more arithmetic-logic units (ALUs) 606. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses).

[0116] The processor 600 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 600) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others).

[0117] The controller 602 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 600 to cause the processor 600 to support various operations in accordance with examples as described herein. For example, the controller 602 may operate as a control unit of the processor 600, generating control signals that manage the operation of various components of the processor 600. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

[0118] The controller 602 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 604 and determine subsequent instruction(s) to be executed Attorney Docket No.793MS0117PCto cause the processor 600 to support various operations in accordance with examples as described herein. The controller 602 may be configured to track memory address of instructions associated with the memory 604. The controller 602 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 602 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 600 to cause the processor 600 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 602 may be configured to manage flow of data within the processor 600. The controller 602 may be configured to control transfer of data between registers, arithmetic logic units (ALUs), and other functional units of the processor 600.

[0119] The memory 604 may include one or more caches (e.g., memory local to or included in the processor 600 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementations, the memory 604 may reside within or on a processor chipset (e.g., local to the processor 600). In some other implementations, the memory 604 may reside external to the processor chipset (e.g., remote to the processor 600).

[0120] The memory 604 may store computer-readable, computer-executable code including instructions that, when executed by the processor 600, cause the processor 600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 602 and / or the processor 600 may be configured to execute computer-readable instructions stored in the memory 604 to cause the processor 600 to perform various functions. For example, the processor 600 and / or the controller 602 may be coupled with or to the memory 604, the processor 600, the controller 602, and the memory 604 may be configured to perform various functions described herein. In some examples, the processor 600 may include multiple processors and the memory 604 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein. Attorney Docket No.793MS0117PC

[0121] The one or more ALUs 606 may be configured to support various operations in accordance with examples as described herein. In some implementations, the one or more ALUs 606 may reside within or on a processor chipset (e.g., the processor 600). In some other implementations, the one or more ALUs 606 may reside external to the processor chipset (e.g., the processor 600). One or more ALUs 606 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 606 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 606 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 606 may support logical operations such as AND, OR, exclusive-OR (XOR), not-OR (NOR), and not-AND (NAND), enabling the one or more ALUs 606 to handle conditional operations, comparisons, and bitwise operations.

[0122] The processor 600 may support wireless communication in accordance with examples as disclosed herein. For example, the processor 600 may be configured to or operable to support a means for applying a permutation matrix to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied, generating a codeword based on the application of the permutation matrix to the parity- check matrix of the QC-LDCP code, and transmitting the generated codeword to a receiver over a data channel.

[0123] As another example, the processor 600 may be configured to or operable to support a means for receiving reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied and decoding a received codeword using the permutation matrix represented by the received reference bits.

[0124] Figure 7 illustrates an example of a NE 700 in accordance with aspects of the present disclosure. The NE 700 may include a processor 702, a memory 704, a controller 706, and a transceiver 708. The processor 702, the memory 704, the controller 706, or the transceiver 708, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described Attorney Docket No.793MS0117PCherein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

[0125] The processor 702, the memory 704, the controller 706, or the transceiver 708, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

[0126] The processor 702 may include an intelligent hardware device (e.g., a general- purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof). In some implementations, the processor 702 may be configured to operate the memory 704. In some other implementations, the memory 704 may be integrated into the processor 702. The processor 702 may be configured to execute computer-readable instructions stored in the memory 704 to cause the NE 700 to perform various functions of the present disclosure.

[0127] The memory 704 may include volatile or non-volatile memory. The memory 704 may store computer-readable, computer-executable code including instructions when executed by the processor 702 cause the NE 700 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 704 or another type of memory. Computer-readable media includes both non- transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0128] In some implementations, the processor 702 and the memory 704 coupled with the processor 702 may be configured to cause the NE 700 to perform one or more of the functions described herein (e.g., executing, by the processor 702, instructions stored in the memory 704). For example, the processor 702 may support wireless communication at the NE 700 in accordance with examples as disclosed herein. The NE 700 may be configured to support a means for applying a permutation matrix to a parity-check matrix of a QC- LDCP code or to an information bits vector to which the parity-check matrix is applied, Attorney Docket No.793MS0117PCgenerating a codeword based on the application of the permutation matrix to the parity- check matrix of the QC-LDCP code, and transmitting the generated codeword to a receiver over a data channel.

[0129] As another example, the processor 702 may support wireless communication at the NE 700 in accordance with examples as disclosed herein. The NE 700 may be configured to support a means for receiving reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied and decoding a received codeword using the permutation matrix represented by the received reference bits.

[0130] The controller 706 may manage input and output signals for the NE 700. The controller 706 may also manage peripherals not integrated into the NE 700. In some implementations, the controller 706 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 706 may be implemented as part of the processor 702.

[0131] In some implementations, the NE 700 may include at least one transceiver 708. In some other implementations, the NE 700 may have more than one transceiver 708. The transceiver 708 may represent a wireless transceiver. The transceiver 708 may include one or more receiver chains 710, one or more transmitter chains 712, or a combination thereof.

[0132] A receiver chain 710 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 710 may include one or more antennas for receive the signal over the air or wireless medium. The receiver chain 710 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 710 may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 710 may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

[0133] A transmitter chain 712 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 712 may include at least one Attorney Docket No.793MS0117PCmodulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 712 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 712 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

[0134] Figure 8 illustrates a flowchart of a method 800 in accordance with aspects of the present disclosure. The operations of the method may be implemented by an encoder, such as an encoder supported by a UE or NE as described herein. In some implementations, the UE or NE may execute a set of instructions to control the function elements of the UE or NE to perform the described functions.

[0135] At 802, the method may include applying a permutation matrix to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied. The operations of 802 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 802 may be performed by a UE as described with reference to Figure 5 or by an NE as described with reference to Figure 7.

[0136] At 804, the method may include generating a codeword based on the application of the permutation matrix to the parity-check matrix of the QC-LDCP code. The operations of 804 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 804 may be performed by a UE as described with reference to Figure 5 or by an NE as described with reference to Figure 7.

[0137] At 806, the method may include transmitting the generated codeword to a decoder over a data channel. The operations of 806 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 806 may be performed by a UE as described with reference to Figure 5 or by an NE as described with reference to Figure 7. Attorney Docket No.793MS0117PC

[0138] It should be noted that the method described herein describes a possible implementation, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible.

[0139] Figure 9 illustrates a flowchart of a method 900 in accordance with aspects of the present disclosure. The operations of the method may be implemented by a decoder, such as a decoder supported by a UE or NE as described herein. In some implementations, the UE or NE may execute a set of instructions to control the function elements of the UE or NE to perform the described functions.

[0140] At 902, the method may include receiving reference bits that represent a permutation matrix to be applied to a parity-check matrix of a QC-LDCP code or to an information bits vector to which the parity-check matrix is applied. The operations of 902 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 902 may be performed by a UE as described with reference to Figure 5 or by an NE as described with reference to Figure 7.

[0141] At 904, the method may include decoding a received codeword using the permutation matrix referenced by the received reference bits signaled within DCI. The operations of 904 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 904 may be performed by a UE as described with reference to Figure 5 or by an NE as described with reference to Figure 7.

[0142] It should be noted that the method described herein describes a possible implementation, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible.

[0143] The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein. Attorney Docket No.793MS0117PC

Claims

CLAIMS What is claimed is:

1. An encoder, comprising: at least one memory; and at least one processor coupled with the at least one memory and configured to cause the encoder to: apply a permutation matrix to a parity-check matrix of a quasi-cyclic low-density parity-check (QC-LDCP) code or to an information bits vector to which the parity-check matrix is applied; generate a codeword based on the application of the permutation matrix to the parity-check matrix of the QC-LDCP code; and transmit the generated codeword to a decoder over a data channel.

2. The encoder of claim 1, wherein the at least one processor is further configured to cause the encoder to: generate a set of permutation matrices associated with maximizing a girth of a Tanner graph for the QC-LDPC code; and select the permutation matrix from the generated set of permutation matrices.

3. The encoder of claim 1, wherein each permutation matrix of the set of permutation matrices is associated with a code rate, an information bits size, a Tanner graph’s girth, and a target block error rate (BLER) performance.

4. The encoder of claim 3, wherein the BLER performance is determined based on Monte Carlo simulations performed over an Additive White Gaussian Noise (AWGN) channel.

5. The encoder of claim 1, wherein each permutation matrix of the set of permutation matrices is designed based on a modified progressive edge growth (PEG) algorithm.

6. The encoder of claim 1, wherein the application of the permutation matrix to the parity-check matrix of the QC-LDCP code preserves quasi-cyclicity properties of the parity-check matrix.

7. The encoder of claim 1, wherein the QC-LDCP code is a 5G new radio (NR) LCDP code.

8. The encoder of claim 1, wherein the encoder is part of a network entity of a 5G communications network.

9. A processor for wireless communication, comprising: at least one controller coupled with at least one memory and configured to cause the processor to: apply a permutation matrix to a parity-check matrix of a quasi-cyclic low-density parity-check (QC-LDCP) code or to an information bits vector to which the parity-check matrix is applied; generate a codeword based on the application of the permutation matrix to the parity-check matrix of the QC-LDCP code; and transmit the generated codeword to a receiver over a data channel.

10. The processor of claim 9, wherein the at least one controller is further configured to cause the processor to: generate a set of permutation matrices associated with maximizing a girth of a Tanner graph for the QC-LDPC code; and select the permutation matrix from the generated set of permutation matrices.

11. The processor of claim 9, wherein each permutation matrix of the set of permutation matrices is associated with a code rate, an information bits size, a Tanner graph girth, and a target block error rate (BLER) performance.

12. A decoder, comprising: at least one memory; and at least one processor coupled with the at least one memory and configured to cause the decoder to: receive reference bits that represent a permutation matrix to be applied to a parity-check matrix of a quasi-cyclic low-density parity-check (QC-LDCP) code or to an information bits vector to which the parity-check matrix is applied; decode a received codeword using the permutation matrix referenced by the received reference bits signaled within downlink control information (DCI).

13. The decoder of claim 12, wherein the reference bits are referenced by a modulation and coding scheme (MCS) field within the DCI.

14. The decoder of claim 13, wherein the MCS field of the DCI can include the reference bits that point to the permutation matrix a modulation, and a code rate tabulated in an associated MCS table.

15. The decoder of claim 12, wherein the reference bits are signaled within a new DCI field of the DCI.

16. The decoder of claim 15, wherein a size of the new DCI field is based on a number of tabulated permutation matrices from which the permutation matrix is selected.

17. The decoder of claim 12, wherein the reference bits are signaled within a dedicated field of a new DCI format.

18. A processor for wireless communication, comprising: at least one controller coupled with at least one memory and configured to cause the processor to: receive reference bits that represent a permutation matrix to be applied to a parity-check matrix of a quasi-cyclic low-density parity-check (QC-LDCP) code or to an information bits vector to which the parity-check matrix is applied; decode a received codeword using the permutation matrix represented by the received reference bits.

19. The processor of claim 18, wherein the reference bits are received within downlink control information (DCI).

20. The processor of claim 19, wherein the reference bits are referenced by the modulation and coding scheme (MCS) field within the DCI.

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