Spiking neural network operation device capable of zero spike prediction and method therefor

Abstract

The present invention relates to a spiking neural network operation device capable of zero spike prediction and a method therefor. A spiking neural network accelerator included in the spiking neural network operation device according to the present invention: updates a membrane potential of a post-neuron on the basis of a spike generation time of a fan-in neuron and a weight between the fan-in neuron and the post-neuron; predicts whether there will be no spike generation of a target post-neuron on the basis of the membrane potential of the post-neuron; if it is not predicted that there is no spike generation of the target post-neuron, performs a softmax function operation on the basis of the membrane potential of the post-neuron; if it is predicted that there is no spike generation of the target post-neuron, does not generate a spike of the target post neuron; and if it is not predicted that there is no spike generation of the target post-neuron and a result of the softmax function operation exceeds a set threshold value, generates a spike of the target post-neuron.

Description

A spiking neural network computational device capable of zero-spike prediction and its method

[0001] The present invention relates to a spiking neural network computing device and method thereof.

[0002] As AI processing becomes increasingly necessary in environments with limited hardware power consumption, such as IoT and mobile devices, research on AI accelerators utilizing spiking neural networks (SNNs), which mimic biological phenomena, rather than convolutional neural networks (CNNs) based on backpropagation learning, is gaining traction. Spiking neural networks utilize the concept of spikes, represented as binary digits of 0 and 1, to transmit signals between neurons. Each post-neuron in the network calculates its membrane potential and generates a new spike based on the sum of the product of the signal transmitted from fan-in pre-neurons and the weight representing the connection strength with that neuron. Spiking neural network accelerators enable lower-power AI processing by only performing neuronal operations when spikes occur. Therefore, if spike occurrences can be made rare, higher energy efficiency can be expected in spiking neural network accelerators. The unsupervised learning-based RL-STDP (Representation Learning using Spike-Timing-Dependent-Platicity) algorithm can increase spike sparsity. However, this algorithm requires a softmax activation function to determine whether a neuron will spike. Calculating this softmax activation function requires exponential functions with natural constants as bases and division operations, which results in significant hardware energy consumption.

[0003] The present invention aims to provide a spiking neural network operation device and method that performs zero-spike prediction after membrane potential calculation and does not perform subsequent softmax activation function operation if it is predicted that no spike will occur for the current neuron, in order to improve energy efficiency by utilizing the spike sparsity characteristic of a spiking neural network.

[0004] The purpose of the present invention is not limited to the purposes mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] A spiking neural network accelerator according to one embodiment of the present invention determines whether a post neuron generates a spike based on spike generation information of a fan-in neuron.

[0006] The spiking neural network accelerator comprises: a membrane potential update unit that updates the membrane potential of one or more post neurons based on a spike occurrence time of the fan-in neuron and a weight between the fan-in neuron and the post neuron; a zero-spike prediction unit that predicts whether a spike of a target post neuron does not occur based on the updated membrane potential of the one or more post neurons including the target post neuron; a softmax function operation unit that performs an operation of a softmax activation function based on the updated membrane potential when the spike occurrence of the target post neuron is not predicted to occur; a comparator that determines whether an operation result of the softmax activation function exceeds a set threshold; and a spike generation unit that does not generate a spike of the target post neuron when the spike occurrence of the target post neuron is predicted to not occur, and generates a spike of the target post neuron when the spike occurrence of the target post neuron is not predicted to not occur and the operation result of the softmax activation function exceeds the set threshold.

[0007] In one embodiment of the present invention, the zero-spike prediction unit predicts whether there will be no spike generation of the target post neuron using the sum of the updated membrane potentials of the one or more post neurons.

[0008] In one embodiment of the present invention, the zero spike prediction unit predicts that there is no spike occurrence of the target post neuron when the following mathematical equation holds true.

[0009] [Mathematical formula]

[0010]

[0011] (However, in the above mathematical formula, D is the channel size of the feature map composed of one or more post neurons,

[0012] U j(t) is the updated membrane potential of the target post neuron at the current time point,

[0013] U1(t)+U2(t)+...+U D (t) is the sum of the updated membrane potentials of one or more post neurons at the current time point,

[0014] θ is the threshold value set above.)

[0015] In one embodiment of the present invention, the spiking neural network accelerator is implemented in the form of either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

[0016] In one embodiment of the present invention, the spiking neural network accelerator is implemented in the form of a computer system.

[0017]

[0018] A spiking neural network computing device according to one embodiment of the present invention includes a memory; and the spiking neural network accelerator. The memory stores the spike occurrence time of a fan-in neuron and the weight between the fan-in neuron and a post neuron, and the spiking neural network accelerator further includes a memory interface that reads the spike occurrence time of the fan-in neuron and the weight from the memory and transmits them to the membrane potential update unit of the first claim.

[0019]

[0020] A spiking neural network operation method according to one embodiment of the present invention is a method for determining whether a spike occurs in a post neuron based on spike occurrence information of a fan-in neuron.

[0021] The above spiking neural network operation method includes: a step of updating a membrane potential of one or more post neurons based on a spike occurrence time of a fan-in neuron and a weight between a fan-in neuron and a post neuron; a step of predicting whether a spike of a target post neuron does not occur based on the updated membrane potential of the one or more post neurons including the target post neuron; a step of performing an operation of a softmax activation function based on the updated membrane potential when the spike of the target post neuron is not predicted to occur; a step of not generating a spike of the target post neuron when the spike of the target post neuron is predicted to not occur; and a step of generating a spike of the target post neuron when the spike of the target post neuron is not predicted to not occur and the operation result of the softmax activation function exceeds a set threshold.

[0022] In one embodiment of the present invention, the zero-spike prediction step predicts whether there will be no spike occurrence of the target post neuron using the sum of the updated membrane potentials of the one or more post neurons.

[0023] In one embodiment of the present invention, the zero spike prediction step is a step of predicting that there is no spike occurrence of the target post neuron when the following mathematical equation is satisfied.

[0024] [Mathematical formula]

[0025]

[0026] (However, in the above mathematical formula, D is the channel size of the feature map composed of one or more post neurons,

[0027] U j (t) is the updated membrane potential of the target post neuron at the current time point,

[0028] U1(t)+U2(t)+...+UD (t) is the sum of the updated membrane potentials of one or more post neurons at the current time point,

[0029] θ is the threshold value set above.)

[0030] In one embodiment of the present invention, the step of generating a spike of the target post neuron further includes not generating a spike of the target post neuron when it is not predicted that there will be no spike generation of the target post neuron and the result of the operation of the softmax activation function is less than or equal to the set threshold value.

[0031] According to one embodiment of the present invention, energy efficiency can be increased without degrading the accuracy performance of the algorithm.

[0032] According to one embodiment of the present invention, unlike the RL-STDP operation in which the presence or absence of a spike is confirmed for each neuron through a softmax activation function, an increase in energy efficiency can be expected by omitting the softmax activation operation process according to spike sparsity through a spike prediction device with low computational complexity.

[0033] In addition, according to one embodiment of the present invention, there is an effect of improving energy efficiency while maintaining the accuracy of the SNN operation result by predicting zero spikes using the arithmetic geometric mean formula without approximating the formula of the algorithm.

[0034]

[0035] The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary skill in the art to which the present invention belongs from the description below.

[0036] Figure 1 is a block diagram showing the configuration of a conventional spiking neural network computing device.

[0037] FIG. 2 is a block diagram showing the configuration of a spiking neural network computation device capable of zero-spike prediction according to one embodiment of the present invention.

[0038] FIG. 3 is a reference diagram showing operations performed in each part of a spiking neural network operation device according to one embodiment of the present invention.

[0039] FIG. 4 is a flowchart for explaining an operation method of a spiking neural network operation device capable of zero-spike prediction according to one embodiment of the present invention.

[0040] FIG. 5 is a block diagram illustrating a computer system for implementing a spiking neural network operation processing method according to an embodiment of the present invention.

[0041] The present invention relates to a spiking neural network (SNN) computational device and method capable of predicting unnecessary computations in advance to improve energy efficiency. More specifically, the present invention proposes a spiking neural network computational device and method capable of improving the overall energy efficiency of spiking neural network inference computation by predicting the probability of spike occurrence based on the rarity of spike occurrence in the spiking neural network and omitting the computational process of a neuron when a spike is predicted not to occur.

[0042] The features of the present invention that differentiate it from the prior art are as follows.

[0043] (1) While the spiking neural network accelerator for RL-STDP operation performs a softmax activation function operation after calculating the membrane potential, the spiking neural network operation device according to one embodiment of the present invention additionally performs zero-spike prediction immediately after calculating the membrane potential.

[0044] (2) If it is predicted that no spike will occur for the current neuron through the zero-spike prediction process, energy efficiency is improved by not performing the subsequent softmax activation function operation.

[0045]

[0046] The advantages and features of the present invention, and the methods for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Meanwhile, the terminology used in this specification is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated in the phrase. The terms "comprises" and / or "comprising" as used in the specification do not exclude the presence or addition of one or more other components, steps, operations, and / or elements mentioned.

[0047] In describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In order to facilitate an overall understanding in describing the present invention, the same reference numbers will be used for the same means regardless of the drawing numbers.

[0049]

[0050] Figure 1 is a block diagram showing the configuration of a conventional spiking neural network computing device.

[0051] A conventional spiking neural network computation device consists of a memory that stores spike occurrence information and weights of pre-neurons, a part that performs membrane potential updates and softmax activation, and a comparator.

[0052] Each post-neuron in the network calculates the membrane potential based on the sum of the product of the signal transmitted from the pre-neuron connected to it through fan-in and the weight, which is the connection strength with the neuron. The post-neuron's membrane potential is input into the softmax activation function, and whether or not the post-neuron generates a spike is determined based on the result of the softmax activation function. However, the calculation of the softmax activation function requires the calculation of an exponential function with a base as a natural constant and a division operation, which causes a problem in that it consumes considerable hardware energy.

[0053]

[0054] Figure 2 is a block diagram illustrating the configuration of a spiking neural network computation device capable of zero-spike prediction according to one embodiment of the present invention. The spiking neural network computation device (10) according to one embodiment of the present invention is configured to include a memory (100) and a spiking neural network accelerator (200).

[0055] The memory (100) stores spike generation information of a fan-in neuron and the weight of a link connecting a fan-in neuron and a post neuron. The spike generation information includes information on the point of time when the fan-in neuron generates a spike.

[0056] The spiking neural network accelerator (200) reads spike occurrence information and weights between fan-in neurons and post neurons from the memory (100), and determines whether a spike occurs in each post neuron. In particular, the spiking neural network accelerator (200) determines whether to omit the softmax activation function operation during the RL-STDP (Representation Learning using Spike-Timing-Dependent-Platicity) operation through the zero-spike prediction unit (220). The spiking neural network accelerator (200) according to one embodiment of the present invention determines whether a spike occurs in each post neuron of the network based on the membrane potential of all post neurons.

[0057] The spiking neural network accelerator (200) may be implemented in the form of, for example, an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or a personal computer. The spiking neural network accelerator (200) may be implemented as a computer, and the term "computer" in this specification should be broadly interpreted to encompass any kind of electronic device having data processing capabilities, including, but not limited to, an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a personal computer, a server, an embedded core, a computer system, a communication device, a processor (a digital signal processor; DSP), a microcontroller, and other electronic computing devices. Any reference to a computer, a controller, or a processor is intended to include one or more hardware devices, such as chips, which may be co-located or remote from one another. Any controller or processor may include, for example, at least one ASIC, FPGA, CPU or DSP suitably configured according to the logic and functionality described herein.

[0058] The spiking neural network accelerator (200) is configured to include a membrane potential update unit (210), a zero spike prediction unit (220), a softmax function operation unit (230), a comparator (240), and a spike generation unit (250). The spiking neural network accelerator (200) illustrated in FIG. 2 is according to one embodiment, and the components of the spiking neural network accelerator (200) according to the present invention are not limited to the embodiment illustrated in FIG. 2, and may be added, changed, or deleted as needed.

[0059] The membrane potential update unit (210) updates the membrane potential of one or more post neurons based on the spike occurrence time of the fan-in neuron and the weight between the fan-in neuron and the post neuron.

[0060] The zero-spike prediction unit (220) predicts whether a spike will not occur in a target post neuron based on the updated membrane potentials of one or more post neurons, including the target post neuron. The zero-spike prediction unit (220) can predict whether a spike will occur in a target post neuron using the sum of the updated membrane potentials of the one or more post neurons (see Equation 9).

[0061] The softmax function operation unit (230) performs a softmax activation function operation based on the updated membrane potential of one or more post neurons when it is not predicted that there will be no spike occurrence of the target post neuron.

[0062] The comparator (240) determines whether the result of the softmax activation function operation exceeds a set threshold value.

[0063] The spike generating unit (250) does not generate a spike of the target post neuron when the zero spike prediction unit (220) predicts that there will be no spike generation of the target post neuron.

[0064] In addition, the spike generating unit (250) generates a spike of the target post neuron when the target post neuron is not predicted to not generate a spike and the result of the softmax activation function operation exceeds the set threshold. The spike generating unit (250) does not generate a spike of the target post neuron when the result of the softmax activation function operation is less than or equal to the set threshold, even when the target post neuron is not predicted to not generate a spike.

[0065] Although not shown in the drawing, the spiking neural network accelerator (200) may further include a memory interface. The memory interface reads spike generation information of a fan-in neuron and weight information between a fan-in neuron and a post-neuron from the memory (100) and transmits them to the membrane potential update unit (210).

[0066]

[0067] Hereinafter, the functions of each component of the spiking neural network accelerator (200) will be described in detail with reference to FIG. 2.

[0068] Based on the spike occurrence time of the fan-in neuron and the weights between the fan-in neuron and the post neuron, the membrane potential of all post neurons is updated for the current time. The membrane potential update unit (210) calculates the membrane potential of each post neuron using mathematical expression 1.

[0069]

[0070]

[0071]

[0072] U in mathematical formula 1 j (t) represents the membrane potential of the jth post neuron updated at the current time point (t). i is the index of the fan-in neuron, i.e., the pre-neuron connected to the fan-in t f represents the spike generation point of the fan neuron. τ is a preset time constant. w ij is the weight of the link connecting the i-th fan neuron and the j-th post neuron. That is, w ij is the weight between the i-th fan neuron and the j-th post neuron.

[0073] Referring to Equation 1, the membrane potential U of the jth post neuron measured in the time domain t is the spike occurrence time t of the fan neuron f and the weight w between the fan-in neuron and the post-neuron ijis determined. At this time, the area multiplied by the weight includes all spike occurrence times of the fan-in neuron that occurred within a time period prior to the time constant τ from the current time point t. After the membrane potential update, the zero-spike prediction unit (220) predicts whether a spike occurs in the target post neuron. If the zero-spike prediction unit (220) predicts a zero spike, in other words, if it predicts that the target post neuron does not generate a spike, the spike of the target post neuron has a value of 0.

[0074]

[0075] The formula used by the zero spike prediction unit (220) to predict a zero spike can be derived from mathematical formula 2, which was used in the existing algorithm to determine whether a spike occurred using a softmax activation function and a comparator.

[0076]

[0077]

[0078] The left side of Equation 2 is the softmax activation function. In Equation 2, D represents the channel size of the feature map composed of post-neurons. Furthermore, θ is the threshold value used to determine whether a spike occurs.

[0079] The softmax activation function on the left side of Equation 2 can be calculated based on the membrane potential of the post neuron obtained in advance. If the softmax activation function value is greater than the threshold θ, the spike of the corresponding post neuron has a value of 1.

[0080]

[0081] Below, the process of deriving the zero spike prediction formula used by the zero spike prediction unit (220) based on mathematical formula 2 is described.

[0082] First, the numerator and denominator of the softmax activation function are divided by the feature channel value (D) of the postneuron. Therefore, the softmax activation function takes the form shown in Equation 3.

[0083]

[0084]

[0085] The denominator term in mathematical equation 3 corresponds to the arithmetic mean. According to the theorem of the arithmetic and geometric mean, the arithmetic mean is greater than or equal to the geometric mean, and can be expressed as in mathematical equation 4.

[0086]

[0087]

[0088] According to mathematical expression 4, the minimum value of the denominator term of mathematical expression 3 corresponding to the arithmetic mean is equal to the geometric mean.

[0089] And, the right side of mathematical expression 4 (left side of mathematical expression 5) can be expressed as the right side of mathematical expression 5.

[0090]

[0091]

[0092] The maximum value of the existing softmax activation function can be obtained by replacing the arithmetic mean, which is the denominator term in mathematical expression 3, with the geometric mean.

[0093] The denominator term can have a minimum value for the geometric mean, and the existing softmax activation function value can have a maximum value by replacing the arithmetic mean with the geometric mean (see Equation 6).

[0094]

[0095]

[0096] Therefore, if the maximum value of the softmax activation function (right-hand side of Equation 6) does not exceed the threshold (θ), it is possible to predict that no spike will occur (zero spike) in the target post-neuron. Through the process of Equations 7 to 9, the final zero-spike prediction equation can be obtained.

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104] The effect of designing a spiking neural network operation device according to the present invention by applying the zero-spike prediction formula of mathematical formula 9 is described.

[0105] Since spike neural networks generally use a power of 2 as the value of the parameter D, the division by D on the left side of Equation 9 can be replaced with a shift operation. In addition, the threshold value (θ) on the right side of Equation 9 and the log term for D can be used as fixed values. Therefore, when applying the prediction formula of Equation 9, there is an effect of requiring low hardware cost. As a result, the zero-spike prediction unit (220) has low complexity in terms of computation time and implementation.

[0106] The zero spike prediction unit (220) predicts whether there is no spike occurrence in the target post neuron using the zero spike prediction formula (Mathematical Formula 9) based on the updated membrane potential of all post neurons.

[0107]

[0108] The zero-spike prediction unit (220) determines whether to omit the operations performed by the softmax function operation unit (230) and the comparator (240) when it predicts that no spike will occur in the target post neuron (zero-spike prediction = 1). Specifically, the zero-spike prediction unit (220) may not operate the softmax function operation unit (230) and the comparator (240). As another example, the zero-spike prediction unit (220) may prevent the softmax function operation unit (230) from operating by not providing the membrane potential information of the post neuron to the softmax function operation unit (230). In addition, the zero-spike prediction unit (220) transmits to the spike generation unit (250) that no spike occurrence in the target post neuron is predicted (zero-spike prediction = 1), and the spike generation unit (250) does not generate a spike in the target post neuron when it receives a zero-spike prediction signal from the zero-spike prediction unit (220).

[0109]

[0110] The zero spike prediction unit (220) transmits the updated membrane potential information of the post neuron to the softmax function operation unit (230) when a zero spike is not predicted, and operates the softmax function operation unit (230). In addition, the zero spike prediction unit (220) transmits a signal (zero spike prediction = 0) indicating that a zero spike is not predicted to the spike generation unit (250). The softmax function operation unit (230) performs a softmax activation function operation based on the updated membrane potential of the post neuron, and the comparator (240) determines whether the softmax activation function operation result exceeds a set threshold. The spike generation unit (250) generates a spike of the target post neuron when it is not predicted that there will be no spike occurrence of the target post neuron (zero spike prediction = 0) and the softmax activation function operation result exceeds the set threshold. The spike generating unit (250) does not generate a spike of the target post neuron if the result of the softmax activation function operation is below the set threshold value, even if it is not predicted that the target post neuron will not generate a spike.

[0111]

[0112] FIG. 3 is a reference diagram showing operations performed in each unit of a spiking neural network operation device according to an embodiment of the present invention. As illustrated in FIG. 3, the membrane potential update unit (210) updates the membrane potential of a post neuron using Equation 1, and the zero spike prediction unit (220) predicts whether there is a zero spike using Equation 9 (zero spike prediction equation). In addition, the softmax function operation unit (230) performs an operation on the softmax activation function on the left side of Equation 2 when the zero spike prediction unit (220) does not predict a zero spike, and the comparator (240) compares the softmax activation function operation result (function value) with a set threshold value as in Equation 2, and transmits the comparison result to the spike generation unit (250).

[0113]

[0114] Figure 4 is a flowchart illustrating a computational method of a spiking neural network computational device capable of zero-spike prediction according to one embodiment of the present invention. The spiking neural network computational method according to one embodiment of the present invention is a method for determining whether a post neuron generates a spike based on spike generation information of a fan-in neuron.

[0115] For convenience of explanation, it is assumed that the spiking neural network operation method according to one embodiment of the present invention is performed by a spiking neural network accelerator (200). However, it is of course possible that the spiking neural network operation method according to one embodiment of the present invention may be performed by a device other than the spiking neural network accelerator (200).

[0116]

[0117] Referring to FIG. 4, a spiking neural network computation method according to one embodiment of the present invention comprises steps S310 to S370. The spiking neural network computation method illustrated in FIG. 4 is according to one embodiment, and the steps of the spiking neural network computation method according to the present invention are not limited to the embodiment illustrated in FIG. 4, and may be added, changed, or deleted as needed.

[0118]

[0119] Step S310 is a membrane potential update step. The membrane potential update unit (210) updates the membrane potential of one or more post neurons based on the spike occurrence time of the fan-in neuron and the weight between the fan-in neuron and the post neuron.

[0120]

[0121] Step S320 is a zero-spike prediction step. The zero-spike prediction unit (220) predicts whether a target post neuron does not generate spikes (whether a zero-spike occurs) based on the updated membrane potential of one or more post neurons, including the target post neuron. The zero-spike prediction unit (220) can predict whether a target post neuron generates zero spikes using Equation 9.

[0122]

[0123] Step S330 is a step for determining whether a zero spike is predicted. If a zero spike is predicted, the spiking neural network accelerator (200) performs step S340, and if a zero spike is not predicted, it performs step S350.

[0124]

[0125] The S340 stage is a stage that does not generate spikes.

[0126] The spike generating unit (250) does not generate a spike if a zero spike is predicted or if the operation result of the softmax activation function does not exceed the threshold even if a zero spike is not predicted.

[0127]

[0128] Step S350 is the softmax activation function operation step.

[0129] If the zero spike of the target post neuron is not predicted, the softmax function operation unit (230) performs a softmax activation function operation using mathematical expression 2 (left side) based on the updated membrane potential of the entire post neuron.

[0130]

[0131] Step S360 is a step for determining whether the result of the operation of the softmax activation function exceeds the threshold value. The comparator (240) determines whether the result of the operation of the softmax activation function exceeds the threshold value (see mathematical equation 2). If the result of the operation of the softmax activation function exceeds the set threshold value, the spike generating unit (250) generates a spike of the target post neuron (S370), and if not, does not generate a spike of the target post neuron (S340).

[0132]

[0133] The spiking neural network computation method described above has been described with reference to the flowchart presented in the drawings. For simplicity, the method has been depicted and described as a series of blocks. However, the present invention is not limited to the order of the blocks. Some blocks may occur in a different order or simultaneously with other blocks than depicted and described herein, and various other branches, flow paths, and block orders that achieve the same or similar results may be implemented. Furthermore, not all of the depicted blocks may be required to implement the method described herein.

[0134]

[0135] Meanwhile, in the description referring to FIG. 4, each step may be further divided into additional steps or combined into fewer steps, depending on the implementation of the present invention. Furthermore, some steps may be omitted as needed, and the order of the steps may be changed. Furthermore, even if other omitted content is included, the content of FIGS. 2 and 3 may be applied to the content of FIG. 4. In other words, even content not specifically described in FIG. 4 can be understood based on the description of FIGS. 2 and 3. Furthermore, the content of FIG. 4 may be applied to the content of FIGS. 2 and 3.

[0136]

[0137] FIG. 5 is a block diagram illustrating a computer system for implementing a method according to an embodiment of the present invention. A spiking neural network computation device (10) according to one embodiment of the present invention can be implemented in the form of the computer system of FIG. 5.

[0138] Referring to FIG. 5, a computer system (1000) may include at least one processor (1010), a memory (1030), an input interface device (1050), an output interface device (1060), and a storage device (1040) that communicate via a bus (1070). The computer system (1000) may further include a communication device (1020) coupled to a network. The processor (1010) may be a central processing unit (CPU), or a semiconductor device that executes instructions stored in the memory (1030) or the storage device (1040). The memory (1030) and the storage device (1040) may include various forms of volatile or non-volatile storage media. For example, the memory may include a read-only memory (ROM) and a random access memory (RAM). In embodiments of the present disclosure, the memory may be located internally or externally to the processor, and the memory may be connected to the processor via various known means. Memory is a variety of volatile or non-volatile storage media, and may include, for example, read-only memory (ROM) or random access memory (RAM).

[0139]

[0140] Accordingly, embodiments of the present invention may be implemented as a computer-implemented method or as a non-transitory computer-readable medium storing computer-executable instructions. In one embodiment, when executed by a processor, the computer-readable instructions may perform a method according to at least one aspect of the present disclosure.

[0141] The memory (1030) can perform the function of the memory (100), and the at least one processor (1010) can perform operations of each unit (210 to 250) of the spiking neural network accelerator (200).

[0142] The communication device (1020) can transmit or receive wired or wireless signals.

[0143] In addition, the method according to the embodiment of the present invention may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium.

[0144]

[0145] The computer-readable medium may include program commands, data files, data structures, etc., either singly or in combination. The program commands recorded on the computer-readable medium may be specially designed and configured for embodiments of the present invention, or may be known and usable by those skilled in the art of computer software. The computer-readable recording medium may include a hardware device configured to store and execute the program commands. For example, the computer-readable recording medium may be a magnetic medium such as a hard disk, a floppy disk, and a magnetic tape, an optical medium such as a CD-ROM or a DVD, a magneto-optical medium such as a floptical disk, a ROM, a RAM, a flash memory, etc. The program commands may include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer through an interpreter, etc.

[0146] The contents of FIGS. 2 to 4 can be applied to the contents of FIG. 5. In addition, the contents of FIG. 5 can be applied to the contents of FIGS. 2 to 4.

[0147]

[0148] For reference, components according to embodiments of the present invention may be implemented in the form of software or hardware such as a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), and may perform certain roles.

[0149] However, 'components' are not limited to software or hardware, and each component may be configured to reside on an addressable storage medium or configured to trigger one or more processors.

[0150] Thus, as an example, components include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.

[0151] Components and the functionality provided within those components may be combined into a smaller number of components or further separated into additional components.

[0152]

[0153] At this time, it will be understood that each block of the processing flowchart drawings and combinations of the flowchart drawings can be performed by computer program instructions. These computer program instructions can be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions executed by the processor of the computer or other programmable data processing equipment create a means for performing the functions described in the flowchart block(s). These computer program instructions can also be stored in a computer-readable memory or a computer-readable memory that can direct a computer or other programmable data processing equipment to perform a function in a specific manner, so that the instructions using the computer or stored in the computer-readable memory can also produce a manufactured item that includes an instruction means for performing the functions described in the flowchart block(s). Since the computer program instructions may be installed on a computer or other programmable data processing device, a series of operational steps may be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform the steps for performing the functions described in the flowchart block(s) may also provide steps for performing the functions described in the flowchart block(s).

[0154]

[0155] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0156] Here, the term '~ part' used in this embodiment means a part of software or a hardware component such as an FPGA or ASIC, and the '~ part' performs certain roles. However, the '~ part' is not limited to software or hardware. The '~ part' may be configured to be on an addressable storage medium and may be configured to play one or more processors. Therefore, as an example, the '~ part' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ parts' may be combined into a smaller number of components and '~ parts' or further separated into additional components and '~ parts'. Additionally, components and '~parts' may be implemented to regenerate one or more CPUs within a device or secure multimedia card.

[0157]

[0158] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. In a spiking neural network accelerator that determines whether a post neuron generates a spike based on spike generation information of a fan-in neuron, A membrane potential update unit that updates the membrane potential of one or more post neurons based on the spike occurrence time of the fan-in neuron and the weights between the fan-in neuron and the post neuron; A zero-spike prediction unit that predicts whether there is no spike occurrence of the target post neuron based on the updated membrane potential of one or more post neurons including the target post neuron; A softmax function operation unit that performs operation of a softmax activation function based on the updated membrane potential when the spike occurrence of the target post neuron is not predicted to be absent; A comparator that determines whether the operation result of the above softmax activation function exceeds a set threshold; and If it is predicted that there will be no spike generation of the target post neuron, the target post neuron will not generate a spike, A spike generating unit that generates a spike of the target post neuron when the spike occurrence of the target post neuron is not predicted to be absent and the operation result of the softmax activation function exceeds the set threshold value; A spiking neural network accelerator including:

2. In the first paragraph, the zero spike prediction unit, Predicting whether a spike will not be generated by the target post neuron by using the sum of the updated membrane potentials of the one or more post neurons. A spiking neural network accelerator.

3. In the second paragraph, the zero spike prediction unit, If the following mathematical equation holds true, it is predicted that there will be no spike occurrence from the target post neuron. A spiking neural network accelerator. [Mathematical formula] (However, in the above mathematical formula, D is the channel size of the feature map composed of one or more post neurons. U j (t) is the updated membrane potential of the target post neuron at the current time point, U 1 (t)+U 2 (t)+...+U D (t) is the sum of the updated membrane potentials of one or more post neurons at the current time point, θ is the threshold value set above.) 4. In the first paragraph, the spiking neural network accelerator, Implemented in either the form of an ASIC (Application-Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array) A spiking neural network accelerator.

5. In the first paragraph, the spiking neural network accelerator, implemented in the form of a computer system A spiking neural network accelerator.

6. Memory; and Containing the spiking neural network accelerator of the first clause, The above memory is, Store the spike occurrence time of the fan-in neuron and the weight between the fan-in neuron and the post neuron, The above spiking neural network accelerator, Further comprising a memory interface for reading the spike occurrence time of the fan neuron and the weight from the memory and transmitting them to the membrane potential update unit of the first clause. A spiking neural network computational unit.

7. A spiking neural network operation method for determining whether a post neuron generates a spike based on spike generation information of a fan-in neuron. A step of updating the membrane potential of one or more post neurons based on the spike occurrence time of the fan-in neuron and the weights between the fan-in neuron and the post neuron; A zero-spike prediction step for predicting whether there will be no spike occurrence of the target post neuron based on the updated membrane potential of one or more post neurons including the target post neuron; If the spike occurrence of the target post neuron is not predicted to be absent, a step of performing an operation of a softmax activation function based on the updated membrane potential; a step of not generating a spike of the target post neuron when it is predicted that there will be no spike generation of the target post neuron; and A step of generating a spike of the target post neuron when the spike occurrence of the target post neuron is not predicted to be absent and the operation result of the softmax activation function exceeds a set threshold value; A spiking neural network computational method including:

8. In the 7th paragraph, the zero spike prediction step, Predicting whether a spike will not be generated by the target post neuron by using the sum of the updated membrane potentials of the one or more post neurons. A method for computing spiking neural networks.

9. In the 7th paragraph, the zero spike prediction step, If the following mathematical equation holds true, it is predicted that there will be no spike occurrence from the target post neuron. A method for computing spiking neural networks. [Mathematical formula] (However, in the above mathematical formula, D is the channel size of the feature map composed of one or more post neurons. U j (t) is the updated membrane potential of the target post neuron at the current time point, U 1 (t)+U 2 (t)+...+U D (t) is the sum of the updated membrane potentials of one or more post neurons at the current time point, θ is the threshold value set above.) 10. In the 7th paragraph, the step of generating a spike of the target post neuron is: Further including not generating a spike of the target post neuron if it is not predicted that there will be no spike generation of the target post neuron and the result of the operation of the softmax activation function is less than or equal to the set threshold value. A method for computing spiking neural networks.

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