Pixel driving circuit, display panel and light-emission control method

Abstract

The present application relates to the technical field of display. Disclosed are a pixel driving circuit, a display panel and a light-emission control method. The pixel driving circuit comprises: a turn-on control sub-circuit, which turns on a gate of a driving transistor and a first node in response to a signal from a first light-emission control signal end; a data writing sub-circuit, which writes a driving signal into the first node in response to a signal from a scanning signal end; a coupling sub-circuit, which stores the driving signal and a threshold value voltage of the driving transistor; a first light-emission control sub-circuit, which provides a signal from a first power source end to a first electrode of the driving transistor in response to a signal from a second light-emission control signal end; and a second light-emission control sub-circuit, which turns on a second electrode of the driving transistor and a light-emission device in response to a signal from the first light-emission control signal end. By means of the provision of a turn-on control sub-circuit, the effect of the capacitance value of a light-emission device on a pixel circuit is effectively blocked, thereby making the display brightness of the pixel circuit in a low-grayscale picture more uniform.

Description

Pixel driving circuit, display panel and light emitting control method Technical Field

[0001] The present application relates to the field of display technology and provides a pixel driving circuit, a display panel and a light emitting control method. Background Art

[0002] In related technologies, the capacitance values ​​of the light-emitting devices in different pixel units corresponding to the pixel driving circuit are different. Different capacitance values ​​will have different degrees of impact on the driving signal of the pixel driving circuit, etc., especially when the display panel wants to display a low grayscale image, the displayed image will have a large brightness difference.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a pixel driving circuit, a display panel, and a light-emitting control method for shielding the influence of the capacitance value of the light-emitting device on the pixel circuit, so that the display brightness of the pixel circuit in low grayscale images is more uniform.

[0005] The specific technical solutions provided in this application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a pixel driving circuit, comprising: a driving transistor, a light-emitting device, a data writing subcircuit, a conduction control subcircuit, a coupling subcircuit, a first light-emitting control subcircuit, and a second light-emitting control subcircuit;

[0007] a driving transistor configured to generate a driving current according to a driving signal;

[0008] The conduction control subcircuit is coupled to the gate of the driving transistor and the first node, and is configured to conduct the gate of the driving transistor and the first node in response to a signal of the first light emitting control signal terminal;

[0009] The data writing sub-circuit is coupled to the first node and is configured to write a driving signal into the first node in response to a signal at the scanning signal terminal;

[0010] The coupling subcircuit is coupled to the first node and the second electrode of the driving transistor and is configured to store the driving signal and the threshold voltage of the driving transistor;

[0011] The first light emitting control subcircuit is coupled to the first electrode of the driving transistor and is configured to provide a signal from the first power supply terminal to the first electrode of the driving transistor in response to a signal from the second light emitting control signal terminal;

[0012] The second light emitting control subcircuit is coupled between the second electrode of the driving transistor and the light emitting device, and is configured to connect the second electrode of the driving transistor and the light emitting device in response to a signal at the first light emitting control signal terminal.

[0013] Optionally, the second light emitting control subcircuit includes: a first transistor;

[0014] The control terminal of the first transistor is coupled to the first light emitting control signal terminal, the first terminal of the first transistor is coupled to the second electrode of the driving transistor, and the second terminal of the first transistor is coupled to the light emitting device.

[0015] Optionally, the driving transistor is a single-gate transistor or a double-gate transistor;

[0016] When the driving transistor is a dual-gate transistor, the first gate of the driving transistor is coupled to the conduction control sub-circuit, and the second gate of the driving transistor is coupled to the second electrode of the driving transistor.

[0017] Optionally, it further includes a first capacitor;

[0018] A first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to the second electrode of the driving transistor.

[0019] Optionally, the data writing sub-circuit includes: a second transistor;

[0020] The control end of the second transistor is coupled to the scan signal end, the first end of the second transistor is coupled to the data signal end, and the second end of the second transistor is coupled to the first node.

[0021] Optionally, the conduction control subcircuit includes: a third transistor;

[0022] The control terminal of the third transistor is coupled to the first light emitting control signal terminal, the first terminal of the third transistor is coupled to the gate of the driving transistor, and the second terminal of the third transistor is coupled to the first node.

[0023] Optionally, the first light emitting control subcircuit includes: a fourth transistor;

[0024] The control terminal of the fourth transistor is coupled to the second light emitting control signal terminal, the first terminal of the fourth transistor is coupled to the first power terminal, and the second terminal of the fourth transistor is coupled to the first electrode of the driving transistor.

[0025] Optionally, the coupling subcircuit includes: a second capacitor and a third capacitor;

[0026] A first end of the second capacitor is coupled to a second end of the third capacitor, and a second end of the second capacitor is coupled to a second electrode of the driving transistor;

[0027] The first terminal of the third capacitor is coupled to the first node.

[0028] Optionally, it further includes a first reset subcircuit;

[0029] The first reset sub-circuit is coupled to the gate of the driving transistor and is configured to provide a signal from the first initialization signal terminal to the gate of the driving transistor in response to a signal from the first reset signal terminal.

[0030] Optionally, the first reset sub-circuit includes: a fifth transistor;

[0031] The control terminal of the fifth transistor is coupled to the first reset signal terminal, the first terminal of the fifth transistor is coupled to the first initialization signal terminal, and the second terminal of the fifth transistor is coupled to the gate of the driving transistor.

[0032] Optionally, it further includes a second reset sub-circuit;

[0033] The second reset sub-circuit is coupled to the coupling sub-circuit and is configured to provide a signal from the second initialization signal terminal to the second electrode of the driving transistor in response to a signal from the second reset signal terminal.

[0034] Optionally, the second reset sub-circuit includes: a sixth transistor;

[0035] The control terminal of the sixth transistor is coupled to the second reset signal terminal, the first terminal of the sixth transistor is coupled to the anode of the light emitting device, and the second terminal of the sixth transistor is coupled to the second initialization signal terminal.

[0036] Optionally, the second reset sub-circuit includes: an eighth transistor;

[0037] The control terminal of the eighth transistor is coupled to the second reset signal terminal, the first terminal of the eighth transistor is coupled to the second electrode of the driving transistor, and the second terminal of the eighth transistor is coupled to the second initialization signal terminal.

[0038] Optionally, a third reset sub-circuit is further included;

[0039] The third reset sub-circuit is coupled to the first end of the second capacitor and is configured to provide the signal of the first initialization signal end to the first end of the second capacitor in response to the signal of the first reset signal end.

[0040] Optionally, the third reset sub-circuit includes: a seventh transistor;

[0041] The control terminal of the seventh transistor is coupled to the first reset signal terminal, the first terminal of the seventh transistor is coupled to the first terminal of the second capacitor, and the second terminal of the seventh transistor is coupled to the first initialization signal terminal.

[0042] In a second aspect, an embodiment of the present application further provides a display panel, comprising:

[0043] A base substrate, comprising a plurality of sub-pixels, wherein the sub-pixels include any one of the above-mentioned pixel driving circuits;

[0044] The pixel driving circuit includes: a first transistor and a third transistor, wherein the control terminal of the first transistor is coupled to the control terminal of the third transistor;

[0045] An orthographic projection of the active layer of the first transistor on the substrate and an orthographic projection of the first signal line on the substrate have a first overlapping region, wherein the first signal line in the first overlapping region is a gate of the first transistor;

[0046] An orthographic projection of the active layer of the third transistor on the substrate and an orthographic projection of the first signal line on the substrate have a second overlapping region, wherein the first signal line in the second overlapping region is the gate of the third transistor.

[0047] Optionally, the display panel includes: a first conductive layer, a second conductive layer, a first semi-conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0048] A first conductive layer is located on the base substrate, and the first conductive layer includes a plate of the second capacitor and a plate of the third capacitor;

[0049] A second conductive layer is located on a side of the substrate away from the first conductive layer, and the second conductive layer includes the other plate of the second capacitor, the other plate of the third capacitor, and the first gate of the driving transistor;

[0050] A first semiconductive layer is located on a side of the substrate facing away from the second conductive layer, and the first semiconductive layer includes an active layer of the driving transistor;

[0051] a third conductive layer, located on a side of the substrate away from the first semiconductive layer, and comprising a second gate of the driving transistor;

[0052] a fourth conductive layer, located on a side of the substrate away from the third conductive layer, and comprising a plate of the first capacitor;

[0053] The fifth conductive layer is located on a side of the substrate away from the fourth conductive layer, and the fifth conductive layer includes another electrode plate of the first capacitor.

[0054] Optionally, the second conductive layer includes a second control signal line;

[0055] The third conductive layer includes a second auxiliary signal line and a third signal line, wherein the signal in the second control signal line and the second auxiliary signal line is the signal in the second reset signal terminal;

[0056] The fourth conductive layer includes a first signal line, a fourth signal line, a fifth signal line, a sixth control signal line, a seventh control signal line and a first power signal line;

[0057] The fifth conductive layer includes a data signal line, a second power signal line, a sixth auxiliary signal line, and a seventh auxiliary signal line, wherein the signals in the sixth control signal line and the sixth auxiliary signal line are the signals in the first reset signal terminal, and the signals in the seventh control signal line and the seventh auxiliary signal line are the signals in the first initialization signal terminal.

[0058] Optionally, the second conductive layer includes a first gate of the first transistor, a first gate of the second transistor, a first gate of the third transistor, a first gate of the fourth transistor, a first gate of the fifth transistor, and a first gate of the seventh transistor;

[0059] The third conductive layer includes the second gate of the first transistor, the second gate of the second transistor, the second gate of the third transistor, the second gate of the fourth transistor, the second gate of the fifth transistor, and the second gate of the seventh transistor.

[0060] In a third aspect, an embodiment of the present application further provides a light emission control method of any of the above pixel driving circuits, comprising:

[0061] Phase 1: The first reset sub-circuit provides the signal of the first initialization signal terminal to the gate electrode of the driving transistor in response to the signal of the first reset signal terminal, the second reset sub-circuit provides the signal of the second initialization signal terminal to the second electrode of the driving transistor in response to the signal of the second reset signal terminal, and the third reset sub-circuit provides the signal of the first initialization signal terminal to the first terminal of the first capacitor in response to the signal of the first reset signal terminal;

[0062] Phase 2: When the voltage of the second electrode of the driving transistor changes to the difference between the signal at the first initialization signal terminal and the threshold voltage, the driving transistor is turned off, the gate-source voltage of the driving transistor is reset, and the threshold voltage of the driving transistor is stored in the second capacitor;

[0063] Phase 3: The data writing sub-circuit stores the driving signal into the third capacitor in response to the signal at the scanning signal terminal;

[0064] Phase 4: The conduction control subcircuit responds to the signal of the first light-emitting control signal terminal and provides the threshold voltage stored in the second capacitor and the drive signal stored in the third capacitor to the gate of the driving transistor, so that the driving transistor generates a drive current. The first light-emitting control subcircuit responds to the signal of the second light-emitting control signal terminal and provides the drive current generated by the driving transistor to the second light-emitting control subcircuit. In addition, the second light-emitting control subcircuit responds to the signal of the first light-emitting control signal terminal and provides the drive current to the light-emitting device.

[0065] The beneficial effects of this application are as follows:

[0066] In summary, the embodiments of the present application provide a pixel driving circuit, a display panel, and a light emitting control method. The pixel driving circuit includes: a driving transistor, a light emitting device, a data writing sub-circuit, The conduction control subcircuit, the coupling subcircuit, the first light-emitting control subcircuit, the second light-emitting control subcircuit, and the driving transistor are configured to generate a driving current according to a driving signal. The conduction control subcircuit is coupled to the gate of the driving transistor and the first node and is configured to conduct the gate of the driving transistor and the first node in response to a signal at the first light-emitting control signal terminal. The data writing subcircuit is coupled to the first node and is configured to write the driving signal to the first node in response to a signal at the scan signal terminal. The coupling subcircuit is coupled to the first node and the second electrode of the driving transistor and is configured to store the driving signal and the threshold voltage of the driving transistor. The first light-emitting control subcircuit is coupled to the first electrode of the driving transistor and is configured to provide a signal from the first power supply terminal to the first electrode of the driving transistor in response to a signal at the second light-emitting control signal terminal. The second light-emitting control subcircuit is coupled between the second electrode of the driving transistor and the light-emitting device and is configured to conduct the second electrode of the driving transistor and the light-emitting device in response to a signal at the first light-emitting control signal terminal. The configuration of the conduction control subcircuit effectively shields the influence of the capacitance value of the light-emitting device on the pixel circuit, thereby making the display brightness of the pixel circuit more uniform on low grayscale images.

[0067] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0069] FIG1 is a schematic diagram of a pixel driving circuit in the related art;

[0070] FIG2 is a connection diagram of a pixel driving circuit according to an embodiment of the present application;

[0071] FIG3 is a circuit connection diagram of a first pixel driving circuit in an embodiment of the present application;

[0072] FIG4 is a circuit connection diagram of a second pixel driving circuit in an embodiment of the present application;

[0073] FIG5 is a circuit connection diagram of a third pixel driving circuit in an embodiment of the present application;

[0074] FIG6 is a circuit connection diagram of a fourth pixel driving circuit in an embodiment of the present application;

[0075] FIG7 is a timing diagram of a pixel driving circuit according to an embodiment of the present application;

[0076] FIG8 is a schematic diagram of the layout structure of a first conductive layer in a display panel according to an embodiment of the present disclosure;

[0077] FIG9 is a schematic diagram of the layout structure of a second conductive layer in a display panel according to an embodiment of the present disclosure;

[0078] FIG10 is a schematic diagram of the layout structure of a first semiconductive layer in a display panel according to an embodiment of the present disclosure;

[0079] FIG11 is a schematic diagram of the layout structure of a third conductive layer in a display panel according to an embodiment of the present disclosure;

[0080] FIG12 is a schematic diagram of a first layout structure of a display panel in an embodiment of the present disclosure;

[0081] FIG13 is a schematic diagram of the layout structure of a fourth conductive layer in a display panel according to an embodiment of the present disclosure;

[0082] FIG14 is a schematic diagram of a second layout structure of a display panel in an embodiment of the present disclosure;

[0083] FIG15 is a schematic diagram of the layout structure of a fifth conductive layer in a display panel according to an embodiment of the present disclosure;

[0084] FIG16 is a schematic diagram of a third layout structure of a display panel in an embodiment of the present disclosure;

[0085] FIG17 is a flow chart of a light emitting control method of a pixel driving circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0086] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of the technical solutions of this application, but not all of them. Based on the embodiments described in this application document, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the technical solutions of this application.

[0087] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0088] In related art, as shown in Figure 1, during the operation of a pixel driver circuit, the light-emitting device itself generates parasitic capacitance, the capacitance of which affects the drive signal of the pixel driver circuit. When a display panel is required to display low-grayscale images, the capacitance values ​​of the light-emitting devices in different pixel driver circuits vary, resulting in significant differences in the brightness of the displayed image.

[0089] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0090] Referring to FIG. 2 , a pixel driving circuit proposed in an embodiment of the present application includes: a driving transistor DTFT, a light-emitting device LED, a data writing subcircuit 100, a conduction control subcircuit 200, a coupling subcircuit 300, a first light-emitting control subcircuit 400, and a second light-emitting control subcircuit 500. It should be noted that the light-emitting device can also be an OLED, micro LED, mini LED, or an inorganic light-emitting device. The present embodiment uses an OLED as an example for further explanation.

[0091] The driving transistor DTFT is configured to generate a driving current according to a driving signal.

[0092] The conduction control subcircuit 200 is coupled to the gate of the driving transistor DTFT and the first node N1 and is configured to conduct the gate of the driving transistor DTFT and the first node N1 in response to a signal of the first light emitting control signal terminal EM1 .

[0093] The data writing sub-circuit 100 is coupled to the first node N1 and is configured to write a driving signal into the first node N1 in response to a signal at the scan signal terminal Gate.

[0094] The coupling sub-circuit 300 is coupled to the first node N1 and the second electrode of the driving transistor DTFT, and is configured to store the driving signal and the threshold voltage of the driving transistor DTFT.

[0095] The first light emitting control sub-circuit 400 is coupled to the first electrode of the driving transistor DTFT and is configured to provide a signal from the first power supply terminal VDD to the first electrode of the driving transistor DTFT in response to a signal from the second light emitting control signal terminal EM2 .

[0096] The second light emitting control subcircuit 500 is coupled between the second electrode of the driving transistor DTFT and the light emitting device LED, and is configured to connect the second electrode of the driving transistor DTFT and the light emitting device LED in response to the signal of the first light emitting control signal terminal EM1.

[0097] The following is a detailed introduction to each of the above sub-circuits:

[0098] 3 , the second light emitting control sub-circuit 500 includes a first transistor T1 .

[0099] The connection relationship between the first transistor T1 and other devices in Figure 3 is: the control end of the first transistor T1 is coupled to the first light-emitting control signal end EM1, the first end of the first transistor T1 is coupled to the second electrode of the driving transistor DTFT, and the second end of the first transistor T1 is coupled to the light-emitting device LED.

[0100] During implementation, when the signal at the first light emitting control signal terminal EM1 is at a high level, the first transistor T1 is turned on, and the driving current generated by the driving transistor DTFT is provided to the anode of the light emitting device LED through the turned-on first transistor T1, causing the light emitting device LED to emit light.

[0101] Referring to FIG. 5 , the driving transistor DTFT is a single-gate transistor or a double-gate transistor.

[0102] When the driving transistor DTFT is a dual-gate transistor, the first gate of the driving transistor DTFT is coupled to the conduction control sub-circuit 200 , and the second gate of the driving transistor DTFT is coupled to the second electrode of the driving transistor DTFT.

[0103] Compared with single-gate transistors, dual-gate transistors increase the grayscale control capability of the driving transistor DTFT, thereby reducing the influence of the parasitic capacitance of the light-emitting device LED on the driving current generated by the driving transistor DTFT, thereby making the display brightness of the display panel more uniform.

[0104] In addition, referring to FIG6 , the pixel driving circuit further includes a first capacitor C1 .

[0105] The connection relationship between the first transistor T1 and other devices in FIG6 is as follows: a first end of the first capacitor C1 is coupled to the first power supply terminal VDD, and a second end of the first capacitor C1 is coupled to the second electrode of the driving transistor DTFT.

[0106] Before adding the first capacitor C1, the driving current is calculated as follows: (1) Ids = 1 / 2k (Vgs - Vth) 2 =1 / 2*k*((Data-vinit))^ 2 Formula (1)

[0107] After adding the first capacitor C1, the driving current is calculated as follows:

[0108] Ids=C1 / (Cst+C1)*1 / 2k(Vgs-Vth) 2 =C1 / (Cst+C1)*1 / 2*k*((Data-vinit))^ 2 Formula (2) Wherein, Cst=(C1*C2) / (C1+C2).

[0109] It can be seen that the calculation formula of the driving current is more refined by adding the first capacitor C1, so that the driving current is further regulated, thereby adjusting the display brightness of the picture.

[0110] 3 , the data writing sub-circuit 100 includes a second transistor T2 .

[0111] 3 , the connection relationship between the first transistor T1 and other devices is as follows: the control terminal of the second transistor T2 is coupled to the scan signal terminal Gate, the first terminal of the second transistor T2 is coupled to the data signal terminal Data, and the second terminal of the second transistor T2 is coupled to the first node N1.

[0112] During implementation, when the signal at the scan signal terminal Gate is at a high level, the second transistor T2 is turned on, and the signal at the data signal terminal Data is provided to the first node N1 via the turned-on second transistor T2.

[0113] 3 , the conduction control sub-circuit 200 includes a third transistor T3 .

[0114] The connection relationship between the first transistor T1 and other devices in Figure 3 is: the control end of the third transistor T3 is coupled to the first light-emitting control signal end EM1, the first end of the third transistor T3 is coupled to the gate of the driving transistor DTFT, and the second end of the third transistor T3 is coupled to the first node N1.

[0115] During implementation, when the signal at the first light emitting control signal terminal EM1 is at a high level, the third transistor T3 is turned on, and the signal at the data signal terminal Data in the first node N1 is provided to the gate of the driving transistor DTFT via the turned-on third transistor T3.

[0116] 3 , the first light emitting control sub-circuit 400 includes a fourth transistor T4 .

[0117] The connection relationship between the first transistor T1 and other devices in Figure 3 is as follows: the control end of the fourth transistor T4 is coupled to the second light-emitting control signal end EM2, the first end of the fourth transistor T4 is coupled to the first power supply end VDD, and the second end of the fourth transistor T4 is coupled to the first electrode of the driving transistor DTFT.

[0118] During implementation, when the signal at the second light emitting control signal terminal EM2 is at a high level, the fourth transistor T4 is turned on, and the signal at the first power supply terminal VDD is provided to the first electrode of the driving transistor DTFT via the turned-on fourth transistor T4.

[0119] 3 , the coupling sub-circuit 300 includes a second capacitor C2 and a third capacitor C3 .

[0120] The connection relationship between the first transistor T1 and other devices in FIG3 is as follows: the first end of the second capacitor C2 is coupled to the second end of the third capacitor C3 , and the second end of the second capacitor C2 is coupled to the second electrode of the driving transistor DTFT.

[0121] A first terminal of the third capacitor C3 is coupled to the first node N1 .

[0122] During implementation, when the gate-source voltage of the driving transistor DTFT is reset, the threshold voltage of the driving transistor DTFT can be obtained, and then the threshold voltage is stored in the second capacitor C2. After the third transistor T3 is turned on, the threshold voltage stored in the second capacitor C2 can be provided to the gate of the driving transistor DTFT via the turned-on third transistor T3. After the driving signal is written to the first node N1, the driving signal is further stored in the third capacitor C3. Thus, when the third transistor T3 is turned on, the driving signal stored in the third capacitor C3 can be provided to the gate of the driving transistor DTFT via the turned-on third transistor T3.

[0123] In addition, referring to FIG. 3 , the pixel driving circuit further includes a first reset sub-circuit 600 .

[0124] The first reset sub-circuit 600 is coupled to the gate of the driving transistor DTFT and is configured to provide a signal from the first initialization signal terminal Vint1 to the gate of the driving transistor DTFT in response to a signal from the first reset signal terminal Reset1 .

[0125] 3 , the first reset sub-circuit 600 includes a fifth transistor T5 .

[0126] The connection relationship between the first transistor T1 and other devices in Figure 3 is: the control end of the fifth transistor T5 is coupled to the first reset signal end Reset1, the first end of the fifth transistor T5 is coupled to the first initialization signal end Vint1, and the second end of the fifth transistor T5 is coupled to the gate of the driving transistor DTFT.

[0127] During implementation, when the signal of the first reset signal terminal Reset1 is at a high level, the fifth transistor T5 is turned on, and the signal of the first initialization signal terminal Vint1 is provided to the gate of the driving transistor DTFT via the turned-on fifth transistor T5, thereby resetting the gate of the driving transistor DTFT.

[0128] In addition, referring to FIG. 3 , the pixel driving circuit further includes a second reset sub-circuit 700 .

[0129] The second reset sub-circuit 700 is coupled to the coupling sub-circuit, and is configured to provide a signal from the second initialization signal terminal Vint2 to the second electrode of the driving transistor DTFT in response to a signal from the second reset signal terminal Reset2.

[0130] Referring to FIG. 3 , in one embodiment, the second reset sub-circuit 700 includes a sixth transistor T6 .

[0131] The connection relationship between the sixth transistor T6 and other devices in Figure 3 is: the control end of the sixth transistor T6 is coupled to the second reset signal end Reset2, the first end of the sixth transistor T6 is coupled to the anode of the second electrode light-emitting device of the driving transistor DTFT, and the second end of the sixth transistor T6 is coupled to the second initialization signal end Vint2.

[0132] During implementation, when the signal of the second reset signal terminal Reset2 is at a high level, the sixth transistor T6 is turned on, and the signal of the second initialization signal terminal Vint2 is provided to the anode of the light-emitting device via the turned-on sixth transistor T6, thereby resetting the anode of the light-emitting device.

[0133] Referring to FIG. 4 , in another embodiment, the second reset sub-circuit 700 includes an eighth transistor T8 .

[0134] The connection relationship between the eighth transistor T8 and other devices in Figure 3 is: the control end of the eighth transistor T8 is coupled to the second reset signal end Reset2, the first end of the eighth transistor T8 is coupled to the second electrode of the driving transistor DTFT, and the second end of the eighth transistor T8 is coupled to the second initialization signal end Vint2.

[0135] During implementation, when the signal of the second reset signal terminal Reset2 is at a high level, the eighth transistor T8 is turned on, and the signal of the second initialization signal terminal Vint2 is provided to the second electrode of the driving transistor DTFT via the turned-on eighth transistor T8, thereby resetting the second electrode of the driving transistor DTFT.

[0136] In the following description, the second reset sub-circuit 700 including the sixth transistor T6 is described in detail.

[0137] In addition, referring to FIG. 3 , the pixel driving circuit further includes a third reset sub-circuit 800 .

[0138] 3 , the third reset sub-circuit 800 is coupled to the first terminal of the second capacitor C2 and is configured to provide the signal of the first initialization signal terminal Vint1 to the first terminal of the second capacitor C2 in response to the signal of the first reset signal terminal Reset1 .

[0139] 3 , the third reset sub-circuit 800 includes a seventh transistor T7 .

[0140] The connection relationship between the first transistor T1 and other devices in Figure 3 is: the control end of the seventh transistor T7 is coupled to the first reset signal end Reset1, the first end of the seventh transistor T7 is coupled to the first end of the second capacitor C2, and the second end of the seventh transistor T7 is coupled to the first initialization signal end Vint1.

[0141] During the implementation process, when the signal of the first reset signal terminal Reset1 is at a high level, the seventh transistor T7 is turned on, and the signal of the first initialization signal terminal Vint1 is provided to the first end of the second capacitor C2 through the turned-on seventh transistor T7, thereby resetting the second capacitor C2 and the third capacitor C3 connected to the second capacitor C2.

[0142] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below with reference to the timing diagram 7.

[0143] Timing T1 stage: EM1 = 0, EM2 = 0, Reset1 = 1, Reset2 = 1, Gate = 0

[0144] When the signal at the first reset signal terminal Reset1 is at a high level, the fifth transistor T5 is turned on, and the signal at the first initialization signal terminal Vint1 resets the gate of the driving transistor DTFT via the turned-on fifth transistor T5. When the signal at the second reset signal terminal Reset2 is at a high level, the sixth transistor T6 is turned on, and the signal at the second initialization signal terminal Vint2 resets the second electrode of the driving transistor DTFT via the turned-on sixth transistor T6. When the signal at the first reset signal terminal Reset1 is at a high level, the seventh transistor T7 is turned on, and the signal at the first initialization signal terminal Vint1 resets the second end of the third capacitor C3 and the first end of the second capacitor C2 via the turned-on seventh transistor T7.

[0145] Timing T2 stage: EM1 = 0, EM2 = 1, Reset1 = 1, Reset2 = 0, Gate = 1

[0146] When the signal at the first reset signal terminal Reset1 is at a high level, the fifth transistor T5 is turned on, and the signal at the first initialization signal terminal Vint1 resets the gate of the driving transistor DTFT via the turned-on fifth transistor T5. When the signal at the second light-emitting control signal terminal EM2 is at a high level, the fourth transistor T4 is turned on, and the signal at the first power supply terminal VDD is provided to the first electrode of the driving transistor DTFT via the turned-on fourth transistor T4. In this way, the gate-source voltage of the driving transistor DTFT is reset to obtain the threshold voltage of the driving transistor DTFT, and the threshold voltage of the driving transistor DTFT is stored in the second capacitor C2. When the signal at the scan signal terminal Gate is at a high level, the second transistor T2 is turned on, and the driving signal at the data signal terminal Data is provided to the first node N1 via the turned-on second transistor T2, and the driving signal is then stored in the third capacitor C3.

[0147] Timing T3 stage: EM1 from 0 to 1, EM2 = 1, Reset1 = 0, Reset2 = 0, Gate = 0

[0148] When the second light-emission control signal terminal EM2 is at a high level, the fourth transistor T4 is turned on. The signal from the first power supply terminal VDD is provided to the driving transistor DTFT via the turned-on fourth transistor T4. When the first light-emission control signal terminal EM1 changes from a low level to a high level, both the first transistor T1 and the third transistor T3 are turned on. The threshold voltage stored in the second capacitor C2 and the driving signal stored in the third capacitor C3 are provided to the gate of the driving transistor DTFT via the turned-on third transistor T3. The driving transistor DTFT generates a driving current based on the driving signal and the threshold voltage. This driving current is provided to the light-emitting device LED via the turned-on first transistor T1, thereby causing the light-emitting device LED to emit light.

[0149] Based on the same inventive concept, an embodiment of the present application provides a display panel, comprising:

[0150] A base substrate, comprising a plurality of sub-pixels, wherein the sub-pixels include any one of the above pixel driving circuits;

[0151] The pixel driving circuit includes: a first transistor T1 and a third transistor T3, wherein the control terminal of the first transistor T1 is coupled to the control terminal of the third transistor T3;

[0152] An orthographic projection of the active layer of the first transistor T1 on the substrate and an orthographic projection of the first signal line on the substrate have a first overlapping region, wherein the first signal line in the first overlapping region is the gate of the first transistor T1;

[0153] The orthographic projection of the active layer of the third transistor T3 on the substrate and the orthographic projection of the first signal line on the substrate have a second overlapping area, wherein the first signal line in the second overlapping area is the gate of the third transistor T3.

[0154] Figures 8 to 13 are schematic diagrams of various layers of the pixel driving circuit provided in some embodiments of the present disclosure. The examples shown in Figures 8 to 13 take the pixel driving circuit of a sub-pixel as an example. Figures 8 to 13 also show the first signal line, the second control signal line, the second auxiliary signal line, the third signal line, the fourth signal line, the fifth signal line, the sixth control signal line, the seventh control signal line, the first power signal line, the data signal line, the second power signal line, the sixth auxiliary signal line, the seventh auxiliary signal line, etc. electrically connected to the pixel driving circuit. The first power signal line is arranged in a mesh shape, the sixth control signal line and the seventh control signal line are arranged along the first direction F1 in the fourth conductive layer, and the sixth auxiliary signal line and the seventh auxiliary signal line are arranged along the second direction F2 in the fifth conductive layer. The above-mentioned setting method can be designed and determined according to the needs of the actual application and is not limited here.

[0155] 8 to 13 , the display panel includes a first conductive layer, a second conductive layer, a first semi-conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0156] 8 , the first conductive layer is located on the base substrate, and the first conductive layer includes a plate of the second capacitor C2 and a plate of the third capacitor C3 .

[0157] Exemplarily, the first conductive layer is disposed on the substrate. The first conductive layer may include: a plate of the second capacitor C2, a plate of the third capacitor C3. In addition, an insulating layer is formed on the first conductive layer to protect the first conductive layer.

[0158] 9 , the second conductive layer is located on a side of the substrate away from the first conductive layer, and includes the other plate of the second capacitor C2 , the other plate of the third capacitor C3 , and the first gate of the driving transistor DTFT.

[0159] Exemplarily, the second conductive layer is disposed on a side of the substrate facing away from the first conductive layer, thereby being insulated from the first conductive layer. The second conductive layer may include: another plate of the second capacitor C2, and another plate of the third capacitor C3. The other plate of the second capacitor C2 and one plate of the second capacitor C2 constitute the second capacitor C2, and the other plate of the third capacitor C3 and one plate of the third capacitor C3 constitute the third capacitor C3. In addition, it should be noted that when the driving transistor DTFT is a dual-gate transistor, the first gate of the driving transistor DTFT is also disposed in the first conductive layer.

[0160] In addition, the second conductive layer includes a second control signal line. The signal transmitted in the second control signal line is the signal at the second reset signal terminal Reset2. It should be noted that the signal at the second reset signal terminal Reset2 is not only transmitted in the second control signal line in the second conductive layer, but also in the second auxiliary signal line provided in the third conductive layer.

[0161] It should also be noted that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 in the embodiment of the present application can also be set as dual-gate transistors. Exemplarily, the above-mentioned second conductive layer includes the first gate of the first transistor T1, the first gate of the second transistor T2, the first gate of the third transistor T3, the first gate of the fourth transistor T4, the first gate of the fifth transistor T5 and the first gate of the seventh transistor T7.

[0162] In Figure 9, the area corresponding to T1 is the area where the first gate of the first transistor T1 is located, the area corresponding to T2 is the area where the first gate of the second transistor T2 is located, the area corresponding to T3 is the area where the first gate of the third transistor T3 is located, the area corresponding to T4 is the area where the first gate of the fourth transistor T4 is located, the area corresponding to T5 is the area where the first gate of the fifth transistor T5 is located, and the area corresponding to T7 is the area where the first gate of the seventh transistor T7 is located.

[0163] Referring to FIG. 10 , the first semiconductive layer is located on a side of the substrate away from the second conductive layer, and the first semiconductive layer includes an active layer of a driving transistor DTFT.

[0164] Exemplarily, the first semiconductive layer can be patterned using indium gallium zinc oxide (IGZO) material. The first semiconductive layer can be used to make the active layer of the above-mentioned driving transistor DTFT and the active layers of other transistors, and each active layer may include a first region, a second region, and a first channel region located between the first region and the second region. It should be noted that the above-mentioned first region and second region can be regions doped with n-type impurities or p-type impurities in the first semiconductive layer to form conductive regions, so that the first region and the second region can serve as the source region and the drain region of the active layer for electrical connection. In addition, an insulating layer is formed on the above-mentioned first semiconductive layer to protect the above-mentioned first semiconductive layer.

[0165] It should be noted that, since the gate of the first transistor T1 and the gate of the third transistor T3 are both connected to the first signal line, the orthographic projection of the active layer of the first transistor T1 on the substrate and the orthographic projection of the first signal line on the substrate have a first overlapping region. Exemplarily, the first signal line in the first overlapping region is the gate of the first transistor T1. The orthographic projection of the active layer of the third transistor T3 on the substrate and the orthographic projection of the first signal line on the substrate have a second overlapping region. Exemplarily, the first signal line in the second overlapping region is the gate of the third transistor T3.

[0166] In Figure 10, the area corresponding to T1 is the area where the active layer of the first transistor T1 is located, the area corresponding to T4 is the area where the active layer of the fourth transistor T4 is located, the area corresponding to T5 is the area where the active layer of the fifth transistor T5 is located, and the area corresponding to T6 is the area where the active layer of the sixth transistor T6 is located.

[0167] 11 , the third conductive layer is located on a side of the substrate away from the first semiconductive layer, and the third conductive layer includes a second gate of the driving transistor DTFT.

[0168] For example, to ensure the proper functioning of each conductive layer, an insulating layer is also provided between the third conductive layer and the second conductive layer. Furthermore, the third conductive layer is provided on a side of the substrate facing away from the first semiconductive layer, thereby being insulated from the first semiconductive layer. When the driving transistor DTFT is a dual-gate transistor, the second gate of the driving transistor DTFT is provided in the third conductive layer. It should be noted that when the driving transistor DTFT is a single-gate transistor, the second gate is typically used as the gate of the driving transistor DTFT.

[0169] Correspondingly, when the other transistors are also dual-gate transistors, the third conductive layer includes the second gate of the first transistor T1, the second gate of the second transistor T2, the second gate of the third transistor T3, the second gate of the fourth transistor T4, the second gate of the fifth transistor T5, and the second gate of the seventh transistor T7. It should be noted that when the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are configured as single-gate transistors, the second gate is generally used as the gate of each transistor.

[0170] In addition, the third conductive layer includes a second auxiliary signal line and a third signal line. The signals in the second control signal line and the second auxiliary signal line are the signals in the second reset signal terminal Reset2. The signal transmitted in the third signal line is the signal in the second light emitting control terminal.

[0171] In Figure 12, the area corresponding to T1 is the area where the second gate of the first transistor T1 is located, the area corresponding to T2 is the area where the second gate of the second transistor T2 is located, the area corresponding to T3 is the area where the second gate of the third transistor T3 is located, the area corresponding to DTFT is the area where the second gate of the driving transistor is located, the area corresponding to T5 is the area where the second gate of the fifth transistor T5 is located, and the area corresponding to T7 is the area where the second gate of the seventh transistor T7 is located.

[0172] Please refer to FIG. 12 , which is a schematic diagram of the layout structure of the display panel provided by some embodiments of the present application after the second conductive layer, the first semi-conductive layer and the third conductive layer are combined.

[0173] Referring to FIG. 13 , the fourth conductive layer is located on a side of the substrate away from the third conductive layer, and the fourth conductive layer includes a plate of the first capacitor C1 .

[0174] Exemplarily, the fourth conductive layer is disposed on a side of the substrate away from the third conductive layer and is insulated from the third conductive layer. The fourth conductive layer may include: a plate of the first capacitor C1.

[0175] In addition, the fourth conductive layer further includes a first signal line, a fourth signal line, a fifth signal line, a sixth control signal line, a seventh control signal line and a first power signal line.

[0176] 13 , the first signal line, the fourth signal line, the fifth signal line, the sixth control signal line, the seventh control signal line and the first power signal line are substantially parallel in the fourth conductive layer, and can be parallel within an allowable error range.

[0177] Referring to FIG. 14 , FIG. 14 is a schematic diagram illustrating a layout structure of a display panel provided in some embodiments of the present application, wherein the first conductive layer, the second conductive layer, the first semiconductive layer, the third conductive layer, and the fourth conductive layer are combined.

[0178] Referring to FIG. 15 , the fifth conductive layer is located on a side of the substrate away from the fourth conductive layer, and the fifth conductive layer includes another electrode plate of the first capacitor C1 .

[0179] Exemplarily, the fifth conductive layer is disposed on a side of the substrate facing away from the fourth conductive layer and is insulated from the fourth conductive layer. The fifth conductive layer may include: another plate of the first capacitor C1, where the other plate of the first capacitor C1 and one plate of the first capacitor C1 in the fourth conductive layer constitute the first capacitor C1.

[0180] In addition, the fifth conductive layer includes a data signal line, a second power signal line, a sixth auxiliary signal line, and a seventh auxiliary signal line. It should be noted that the signals in the sixth control signal line and the sixth auxiliary signal line are the signals in the first reset signal terminal Reset1, and the signals in the seventh control signal line and the seventh auxiliary signal line are the signals in the first initialization signal terminal Vint1.

[0181] In addition, referring to FIG15 , the anode of the light emitting device is electrically connected to the source region - T1s (marked in FIG10 ) of the first transistor T1 located in the first semiconductor layer through the fifth conductive layer and the transition portion of the fourth conductive layer.

[0182] Referring to FIG. 16 , FIG. 16 is a schematic diagram of the layout structure of the display panel provided in some embodiments of the present application after the first conductive layer, the second conductive layer, the first semi-conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer are combined.

[0183] Based on the same inventive concept, an embodiment of the present application provides a light emitting control method for a pixel driving circuit, as shown in FIG17 , including:

[0184] Step 201: First stage: The first reset sub-circuit 600 responds to the signal of the first reset signal terminal Reset1 and provides the signal of the first initialization signal terminal Vint1 to the gate of the driving transistor DTFT, the second reset sub-circuit 700 responds to the signal of the second reset signal terminal Reset2 and provides the signal of the second initialization signal terminal Vint2 to the second electrode of the driving transistor DTFT, and the third reset sub-circuit 800 responds to the signal of the first reset signal terminal Reset1 and provides the signal of the first initialization signal terminal Vint1 to the first terminal of the first capacitor C1.

[0185] During the implementation, the driving transistor DTFT and the like in the pixel driving circuit are reset through the first reset subcircuit 600 , the second reset subcircuit 700 and the third reset subcircuit 800 so that the light emitting device LED is not affected by the display effect of the previous frame.

[0186] Step 202: Second stage: When the voltage of the second electrode of the driving transistor DTFT changes to the difference between the signal of the first initialization signal terminal Vint1 and the threshold voltage, the driving transistor DTFT is turned off, the gate-source voltage of the driving transistor DTFT is reset, and the threshold voltage of the driving transistor DTFT is stored in the second capacitor C2.

[0187] During the implementation process, in order to make the driving current more accurate, under the action of the first power supply terminal VDD, the voltage of the second electrode of the driving transistor DTFT changes to the difference between the signal of the first initialization signal terminal Vint1 and the threshold voltage, and the gate-source voltage of the driving transistor DTFT is reset, thereby obtaining the threshold voltage of the driving transistor DTFT and storing the threshold voltage in the second capacitor C2.

[0188] Step 203: The third stage: the data writing sub-circuit 100 stores the driving signal into the third capacitor C3 in response to the signal of the scan signal terminal Gate.

[0189] During implementation, when the signal at the scan signal terminal Gate is valid, the driving signal is written into the first node N1 via the turned-on data writing sub-circuit 100 and then stored in the third capacitor C3.

[0190] Step 204: Fourth stage: The conduction control subcircuit 200 responds to the signal of the first light-emitting control signal terminal EM1, and provides the threshold voltage stored in the second capacitor C2 and the drive signal stored in the third capacitor C3 to the gate of the driving transistor DTFT, so that the driving transistor DTFT generates a drive current, the first light-emitting control subcircuit 400 responds to the signal of the second light-emitting control signal terminal EM2, and provides the drive current generated by the driving transistor DTFT to the second light-emitting control subcircuit 500, and the second light-emitting control subcircuit 500 responds to the signal of the first light-emitting control signal terminal EM1, and provides the drive current to the light-emitting device LED.

[0191] During implementation, during the light-emitting phase of the light-emitting device LED, when the signal at the first light-emitting control signal terminal EM1 is valid, the conduction control subcircuit 200 is turned on, and the threshold voltage stored in the second capacitor C2 and the drive signal stored in the third capacitor C3 are provided to the gate of the drive transistor DTFT via the turned-on conduction control subcircuit 200. Simultaneously, when the signal at the second light-emitting control signal terminal EM2 is valid, the first light-emitting control subcircuit 400 is turned on, and the first voltage source causes the drive transistor DTFT to generate a drive current. When the signal at the first light-emitting control signal terminal EM1 is valid, the second light-emitting control subcircuit 500 is turned on, and the drive current generated by the drive transistor DTFT is provided to the light-emitting device LED via the second light-emitting control subcircuit 500, causing the light-emitting device LED to emit light.

[0192] In summary, in an embodiment of the present application, a pixel driving circuit, a display panel, and a light emitting control method are provided. The pixel driving circuit includes: a driving transistor, a light emitting device, a data writing subcircuit, a conduction control subcircuit, a coupling subcircuit, a first light emitting control subcircuit, and a second light emitting control subcircuit. The driving transistor is configured to generate a driving current according to a driving signal. The conduction control subcircuit is coupled to the gate of the driving transistor and the first node and is configured to conduct the gate of the driving transistor and the first node in response to a signal at the first light emitting control signal terminal. The data writing subcircuit is coupled to the first node and is configured to write the driving signal to the first node in response to a signal at the scanning signal terminal. The coupling subcircuit The subcircuit is coupled to the first node and the second electrode of the driving transistor, and is configured to store the driving signal and the threshold voltage of the driving transistor. The first light-emitting control subcircuit is coupled to the first electrode of the driving transistor, and is configured to provide the signal of the first power supply terminal to the first electrode of the driving transistor in response to the signal of the second light-emitting control signal terminal. The second light-emitting control subcircuit is coupled between the second electrode of the driving transistor and the light-emitting device, and is configured to conduct the second electrode of the driving transistor and the light-emitting device in response to the signal of the first light-emitting control signal terminal. By setting the conduction control subcircuit, the influence of the capacitance value of the light-emitting device on the pixel circuit is effectively shielded, so that the display brightness of the pixel circuit in low grayscale images is more uniform.

[0193] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program product systems. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0194] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0195] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0196] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0197] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein, comprising: a driving transistor, a light-emitting device, a data writing sub-circuit, a conduction control sub-circuit, a coupling sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit; the driving transistor is configured to generate a driving current according to a driving signal; the conduction control sub-circuit is coupled to the gate and a first node of the driving transistor, and is configured to conduct the gate and the first node of the driving transistor in response to a signal at a first light-emitting control signal terminal; the data writing sub-circuit is coupled to the first node, and is configured to write the driving signal into the first node in response to a signal at a scan signal terminal; the coupling sub-circuit is coupled to the first node and a second pole of the driving transistor, and is configured to store the driving signal and the threshold voltage of the driving transistor; the first light-emitting control sub-circuit is coupled to a first pole of the driving transistor, and is configured to provide a signal at a first power supply terminal to the first pole of the driving transistor in response to a signal at a second light-emitting control signal terminal; the second light-emitting control sub-circuit is coupled between the second pole of the driving transistor and the light-emitting device, and is configured to conduct the second pole of the driving transistor and the light-emitting device in response to a signal at the first light-emitting control signal terminal.

2. The pixel driving circuit according to claim 1, wherein, the second light-emitting control sub-circuit includes: a first transistor; a control end of the first transistor is coupled to the first light-emitting control signal terminal, a first end of the first transistor is coupled to the second pole of the driving transistor, and a second end of the first transistor is coupled to the light-emitting device.

3. The pixel driving circuit according to claim 1, wherein, the driving transistor is a single-gate transistor or a double-gate transistor; when the driving transistor is a double-gate transistor, a first gate of the driving transistor is coupled to the conduction control sub-circuit, and a second gate of the driving transistor is coupled to the second pole of the driving transistor.

4. The pixel driving circuit according to claim 1, wherein, further comprising a first capacitor; a first end of the first capacitor is coupled to a first power supply terminal, and a second end of the first capacitor is coupled to the second pole of the driving transistor.

5. The pixel driving circuit according to claim 1, wherein, the data writing sub-circuit includes: a second transistor; a control end of the second transistor is coupled to the scan signal terminal, a first end of the second transistor is coupled to a data signal terminal, and a second end of the second transistor is coupled to the first node.

6. The pixel driving circuit according to claim 1, wherein, the conduction control sub-circuit includes: a third transistor; a control end of the third transistor is coupled to the first light-emitting control signal terminal, a first end of the third transistor is coupled to the gate of the driving transistor, and a second end of the third transistor is coupled to the first node.

7. The pixel driving circuit according to claim 1, wherein, the first light-emitting control sub-circuit includes: a fourth transistor; The control terminal of the fourth transistor is coupled to the second light emission control signal terminal, the first terminal of the fourth transistor is coupled to the first power supply terminal, and the second terminal of the fourth transistor is coupled to the first pole of the driving transistor.

8. The pixel driving circuit according to claim 1, wherein, the coupling sub-circuit includes: a second capacitor and a third capacitor; the first terminal of the second capacitor is coupled to the second terminal of the third capacitor, and the second terminal of the second capacitor is coupled to the second pole of the driving transistor; the first terminal of the third capacitor is coupled to the first node.

9. The pixel driving circuit according to any one of claims 1 to 8, wherein, it further includes a first reset sub-circuit; the first reset sub-circuit is coupled to the gate of the driving transistor and is configured to provide the signal of the first initialization signal terminal to the gate of the driving transistor in response to the signal of the first reset signal terminal.

10. The pixel driving circuit according to claim 9, wherein, the first reset sub-circuit includes: a fifth transistor; the control terminal of the fifth transistor is coupled to the first reset signal terminal, the first terminal of the fifth transistor is coupled to the first initialization signal terminal, and the second terminal of the fifth transistor is coupled to the gate of the driving transistor.

11. The pixel driving circuit according to any one of claims 1 to 10, wherein, it further includes a second reset sub-circuit; the second reset sub-circuit is connected to the coupling sub-circuit and is configured to provide the signal of the second initialization signal terminal to the second pole of the driving transistor in response to the signal of the second reset signal terminal.

12. The pixel driving circuit according to claim 11, wherein, the second reset sub-circuit includes: a sixth transistor; the control terminal of the sixth transistor is coupled to the second reset signal terminal, the first terminal of the sixth transistor is coupled to the anode of the light emitting device, and the second terminal of the sixth transistor is coupled to the second initialization signal terminal.

13. The pixel driving circuit according to claim 11, wherein, the second reset sub-circuit includes: an eighth transistor; the control terminal of the eighth transistor is coupled to the second reset signal terminal, the first terminal of the eighth transistor is coupled to the second pole of the driving transistor, and the second terminal of the eighth transistor is coupled to the second initialization signal terminal.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein, it further includes a third reset sub-circuit; the third reset sub-circuit is coupled to the first terminal of the second capacitor and is configured to provide the signal of the first initialization signal terminal to the first terminal of the second capacitor in response to the signal of the first reset signal terminal.

15. The pixel driving circuit according to claim 14, wherein, the third reset sub-circuit includes: a seventh transistor; the control terminal of the seventh transistor is coupled to the first reset signal terminal, the first terminal of the seventh transistor is coupled to the first terminal of the second capacitor, and the second terminal of the seventh transistor is coupled to the first initialization signal terminal.

16. A display panel, wherein, it includes: ​ A substrate, comprising a plurality of sub-pixels, wherein the sub-pixels comprise a pixel driving circuit as described in any one of claims 1 to 14; The pixel driving circuit comprises: a first transistor and a third transistor, and a control end of the first transistor is coupled to a control end of the third transistor; A positive projection of an active layer of the first transistor on the substrate has a first overlapping region with a positive projection of the first signal line on the substrate, wherein the first signal line in the first overlapping region is a gate of the first transistor; A positive projection of an active layer of the third transistor on the substrate has a second overlapping region with a positive projection of the first signal line on the substrate, wherein the first signal line in the second overlapping region is a gate of the third transistor.

17. The display panel as claimed in claim 16, wherein, The display panel comprises: a first conductive layer, a second conductive layer, a first semi-conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The first conductive layer is located on the substrate, and the first conductive layer comprises one electrode plate of a second capacitor and one electrode plate of a third capacitor; The second conductive layer is located on a side of the substrate away from the first conductive layer, and the second conductive layer comprises the other electrode plate of the second capacitor, the other electrode plate of the third capacitor, and a first gate of a driving transistor; The first semi-conductive layer is located on a side of the substrate away from the second conductive layer, and the first semi-conductive layer comprises an active layer of the driving transistor; The third conductive layer is located on a side of the substrate away from the first semi-conductive layer, and the third conductive layer comprises a second gate of the driving transistor; The fourth conductive layer is located on a side of the substrate away from the third conductive layer, and the fourth conductive layer comprises one electrode plate of a first capacitor; The fifth conductive layer is located on a side of the substrate away from the fourth conductive layer, and the fifth conductive layer comprises the other electrode plate of the first capacitor.

18. The display panel as claimed in claim 17, wherein, The second conductive layer comprises a second control signal line; The third conductive layer comprises a second auxiliary signal line and a third signal line, wherein signals in the second control signal line and the second auxiliary signal line are signals in a second reset signal terminal; The fourth conductive layer comprises a first signal line, a fourth signal line, a fifth signal line, a sixth control signal line, a seventh control signal line and a first power supply signal line; The fifth conductive layer comprises a data signal line, a second power supply signal line, a sixth auxiliary signal line, a seventh auxiliary signal line, wherein signals in the sixth control signal line and the sixth auxiliary signal line are signals in a first reset signal terminal, and signals in the seventh control signal line and the seventh auxiliary signal line are signals in a first initialization signal terminal.

19. The display panel as claimed in claim 17, wherein, The second conductive layer includes the first gate of the first transistor, the first gate of the second transistor, the first gate of the third transistor, the first gate of the fourth transistor, the first gate of the fifth transistor, and the first gate of the seventh transistor; The third conductive layer includes the second gate of the first transistor, the second gate of the second transistor, the second gate of the third transistor, the second gate of the fourth transistor, the second gate of the fifth transistor, and the second gate of the seventh transistor.

20. A method for controlling the light emission of a pixel driving circuit according to any one of claims 1 to 15, wherein, comprising: The first stage: the first reset sub-circuit responds to the signal of the first reset signal terminal and provides the signal of the first initialization signal terminal to the gate of the driving transistor; the second reset sub-circuit responds to the signal of the second reset signal terminal and provides the signal of the second initialization signal terminal to the second pole of the driving transistor; and the third reset sub-circuit responds to the signal of the first reset signal terminal and provides the signal of the first initialization signal terminal to the first end of the first capacitor; The second stage: when the voltage of the second pole of the driving transistor changes to the difference between the signal of the first initialization signal terminal and the threshold voltage, the driving transistor is cut off, the gate-source voltage of the driving transistor is reset, and the threshold voltage of the driving transistor is stored in the second capacitor; The third stage: the data writing sub-circuit responds to the signal of the scanning signal terminal and stores the driving signal in the third capacitor; The fourth stage: the conduction control sub-circuit responds to the signal of the first light emission control signal terminal and provides the threshold voltage stored in the second capacitor and the driving signal stored in the third capacitor to the gate of the driving transistor, so that the driving transistor generates a driving current; the first light emission control sub-circuit responds to the signal of the second light emission control signal terminal and provides the driving current generated by the driving transistor to the second light emission control sub-circuit; and the second light emission control sub-circuit responds to the signal of the first light emission control signal terminal and provides the driving current to the light emitting device.

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