Interface system and remote i2c slave device data write method

Abstract

An interface system, comprising a master controller (100), an interface module (200), a functional module (300), and a remote I2C slave device (400). The master controller (100) is connected to the interface module (200); the interface module (200) is connected to the functional module (300), and the functional module (300) is connected to the remote I2C slave device (400). The system is suitable for long-distance data transmission and achieves a high data transmission speed.

Description

An interface system and a method for writing data from a remote I2C slave device Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an interface system and a method for writing data into a remote I2C slave device. Background Art

[0002] The I2C bus is a simple, bidirectional serial bus developed by Philips. Devices interconnected via the I2C bus are called I2C devices, and the interface connecting an I2C device to the I2C bus is called an I2C interface. The I2C bus has become a de facto international standard. The design specifications for the I2C bus and its protocol (referred to as the Standard I2C Specification) are generally based on the description in the document "THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000."

[0003] The I2C interface includes an I2C clock line (usually named SCL) and an I2C data line (usually named SDA). The I2C master controller connects to one or more I2C slave devices through the I2C clock line and the I2C data line. The I2C master controller drives the I2C clock line, initiates I2C write or read operations, and determines whether the data is sent successfully through the acknowledge bit. Bit errors on the bus due to signal interference and other reasons cannot be recognized by the I2C slave device.

[0004] The electrical characteristics of the I2C interface require that devices participating in I2C communication share a common ground; otherwise, data transmission will fail. Therefore, I2C communication is not suitable for applications with long transmission distances or high signal interference. To address this issue, devices used to forward I2C data are usually added to the I2C bus. However, the introduction of forwarding devices presents new problems:

[0005] The I2C communication mechanism requires that each time the I2C master controller sends a byte, the I2C slave device must reply with an acknowledge bit. When the acknowledge bit level is low, it is I2C ACK, and when the acknowledge bit level is high, it is I2C CNAK. In the prior art, each byte sent by the I2C master controller is passed to the module that ultimately receives the data (referred to as the functional module in this invention), and the functional module generates an acknowledge bit and transmits it back to the I2C master controller. The response speed of the transmission system is slow, resulting in slow transmission speed.

[0006] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that only occupies four pins on the chip, saving chip pins and space on PCB layout. SPI typically has four signal lines: SPI_CSN, SPI_CK, SPI_MOSI, and SPI_MISO. The SPI master controller connects to the SPI interface module via these four signal lines. The SPI master controller is the SPI master device, and the SPI interface module is the SPI slave device. The SPI master controller drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the SPI interface module receives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines. The SPI interface module drives the SPI_MISO signal line, while the SPI master controller receives the SPI_MISO signal line. The SPI interface module receives and samples data on the SPI_MOSI line driven by the SPI master controller on the rising or falling edges of the SPI_CK line. The SPI master controller receives and samples data on the SPI_MISO line driven by the SPI interface module on the rising or falling edges of the SPI_CK line. In the SPI protocol, the SPI master controller drives the SPI_CK line and generates clock edges on the SPI_CK line. The SPI master controller and the SPI interface module sample data on the SPI_MISO and SPI_MOSI lines on the rising or falling edges of the SPI_CK line, enabling bidirectional data transmission between the SPI master controller and the SPI interface module. The SPI_CSN line is a select signal. In the SPI protocol, data transmission occurs only when the SPI_CSN line is low. An SPI master controller can connect to multiple SPI interface modules, meaning that an SPI master device can connect to multiple SPI slave devices. The SPI master controller and multiple SPI interface modules share the SPI_CK, SPI_MOSI, and SPI_MISO signal lines, but each SPI interface module has an independent SPI_CSN signal line input. When the SPI_CSN signal line of an SPI interface module is high, this SPI interface module does not drive the SPI_MISO signal line (the driver connected to the SPI_MISO signal line of this SPI interface module outputs a Hi-Z state). An SPI interface module only drives the SPI_MISO signal line when its SPI_CSN signal line is low. When an SPI master controller connects to multiple SPI interface modules, at any given time, only one SPI interface module's SPI_CSN signal line is low, thus preventing conflicts caused by multiple SPI interface modules driving the SPI_MISO signal line simultaneously.

[0007] When an SPI master controller is connected to only one SPI interface module, this SPI interface module can drive the SPI_MISO signal line at any time without causing conflict. In this case, there can be no SPI_CSN signal line between the SPI master controller and the SPI interface module. That is, when an SPI master controller is connected to only one SPI interface module, the SPI master controller and the SPI interface module can be connected only through the SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line.

[0008] Long-distance data transmission typically involves sending a command packet and receiving a response packet. The response packet contains information about the command execution status and, in the case of a read command, may also contain the read data. The existing SPI protocol implements bidirectional data transmission between the SPI master controller and the SPI interface module by sampling the SPI_MISO and SPI_MOSI signal lines at the rising or falling edges of the SPI_CK signal line. However, this data transmission method can be considered a data stream and is not suitable for long-distance data transmission.

[0009] Summary of the Invention

[0010] In order to solve the problem that the I2C bus and SPI bus in the prior art are not suitable for long-distance data transmission, an object of the present invention is to provide an interface system, the interface system including a main controller, an interface module, a functional module, and a remote I2C slave device;

[0011] The main controller is connected to the interface module; the interface module is connected to the functional module, and the functional module is connected to a remote I2C slave device.

[0012] Another object of the present invention is to provide a method for writing data to a remote I2C slave device using an interface system, comprising:

[0013] The main controller sends a write command packet to the interface module, and when the interface module receives the write command packet, the interface module sends the write command packet to the functional module;

[0014] The write command packet includes multiple write commands, and the functional module receives the write command packet and executes the multiple write commands included in the write command packet. The method for executing each write command is:

[0015] The function module sends an I2C START to the remote I2C slave device, then the function module sends the remote I2C address byte to the remote I2C slave device, and then the function module sends a write command to the remote I2C slave device;

[0016] For each byte sent by the function module to the remote I2C slave device, the function module receives the I2C response bit sent by the remote I2C slave device and determines the execution result of the write command.

[0017] The function module returns the write status packet to the interface module, including:

[0018] When the execution result of each write command included in the write command packet is successful, the functional module returns a write status packet with success status information to the interface module;

[0019] When the execution result of at least one write command included in the write command packet is failure, the functional module returns a write status packet containing failure status information to the interface module;

[0020] The interface module returns the status information of the write status packet to the main controller.

[0021] Preferably, the functional module receives the write command packet and executes the write command contained in the write command packet. When the execution result of a write command is failure, the functional module stops executing subsequent write commands, and the functional module returns a write status packet with failure status information to the interface module.

[0022] Preferably, the main controller is an I2C main controller, and the interface module is an I2C interface module;

[0023] The I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line. The I2C master controller initiates an I2C write operation and sends a write command packet to the I2C interface module. After receiving the write command packet, the I2C interface module pulls down the I2C clock line level and sends the write command packet to the functional module.

[0024] The function module returns the write status packet to the I2C interface module, and the I2C interface module returns status information of the write status packet to the I2C master controller, including:

[0025] When the I2C interface module receives the write status packet and the status information of the write status packet is success, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller;

[0026] When the I2C interface module receives the write status packet and the status information of the write status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

[0027] Preferably, the main controller is an I2C main controller, and the interface module is an I2C interface module;

[0028] The I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line, the I2C master controller initiates an I2C write operation and sends the write command packet to the I2C interface module, and the I2C interface module sends the write command packet to the functional module after receiving the write command packet;

[0029] The function module returns the write status packet to the I2C interface module, and the I2C interface module returns status information of the write status packet to the I2C master controller, including:

[0030] After the I2C interface module receives the write command packet,

[0031] If the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module and the status information of the write status packet is success, then the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller;

[0032] If the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module and the status information of the write status packet is failure, the I2C interface module returns an I2C NAK to the I2C master controller;

[0033] If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module, the I2C interface module returns status information of the write status packet to the I2C master controller.

[0034] Preferably, the main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line;

[0035] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier, and the SPI interface module sends the write command packet to the functional module after receiving the write command packet from SPI_MOSI;

[0036] The function module returns the write status packet to the SPI interface module, and the SPI interface module returns status information of the write status packet to the SPI master controller, including:

[0037] After the SPI interface module receives the write status packet, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a write feedback packet to the SPI master controller through the SPI_MISO signal line, where the write feedback packet starts with a second identifier and includes the status information included in the write status packet.

[0038] Preferably, the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0039] When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

[0040] Preferably, the SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module via the SPI_MOSI signal line.

[0041] Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets.

[0042] Preferably, the write feedback packet is divided into a write success feedback packet and a write failure feedback packet;

[0043] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0044] When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier;

[0045] When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, where the write failure feedback packet starts with a fourth identifier.

[0046] Preferably, the functional module comprises a remote I2C address register, and the I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is the remote I2C address stored in the remote I2C address register.

[0047] Preferably, the write command packet includes a remote I2C address, and the I2C address included in the remote I2C address byte sent by the functional module to the remote I2C slave device is the remote I2C address included in the write command packet.

[0048] Preferably, the functional module includes a remote I2C address register, and the functional module further includes a remote I2C address selection module. The I2C address included in the remote I2C address byte sent by the functional module to the remote I2C slave device is derived from the remote I2C address stored in the remote I2C address register or from the remote I2C address included in the write command packet according to the instruction of the remote I2C address selection module.

[0049] Preferably, each of the multiple write commands in the write command packet includes a remote I2C address, and the remote I2C address included in the remote I2C address byte sent by the functional module to the remote I2C slave device is derived from the remote I2C address included in each write command.

[0050] The present invention provides an interface system and a remote I2C slave device data writing method, which are suitable for long-distance data transmission and have a fast data transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] FIG1 schematically shows a structural block diagram of an interface system of the present invention.

[0053] FIG2 shows a schematic diagram of the data structure of a write command packet of the present invention.

[0054] FIG3 shows a structural block diagram of an interface system according to the present invention, in which the main controller is an I2C main controller and the interface module is an I2C interface module.

[0055] FIG4 shows a timing diagram of an I2C write operation according to the present invention.

[0056] FIG5 shows a timing diagram of an I2C read operation according to the present invention.

[0057] FIG6 shows a timing diagram of the I2C continuous read and write operations of the present invention.

[0058] FIG. 7 shows a timing diagram of initiating an I2C write operation and sending a write command packet (or a read command packet) according to the present invention.

[0059] FIG8 shows a timing diagram of initiating an I2C write operation, sending a write command packet, and the status information of the write status packet indicating success, in one embodiment of the present invention.

[0060] FIG9 shows a timing diagram of initiating an I2C write operation, sending a write command packet, and the status information of the write status packet indicating failure in one embodiment of the present invention.

[0061] FIG10 shows a timing diagram of another embodiment of the present invention in which an I2C write operation is initiated, a write command packet is sent, and the status information of the write status packet is successful.

[0062] FIG. 11 shows a timing diagram of another embodiment of the present invention in which an I2C write operation is initiated, a write command packet is sent, and the status information of the write status packet is failure.

[0063] FIG. 12 shows a timing diagram of initiating an I2C write operation and sending a write command packet, and the subsequent I2C operation is an I2C read operation in another embodiment of the present invention.

[0064] FIG13 shows a structural block diagram of an interface system according to the present invention, in which the main controller is an SPI main controller and the interface module is an SPI interface module.

[0065] FIG14 shows a schematic diagram of the data structure of a write command packet when the main controller of the present invention is an SPI main controller and the interface module is an SPI interface module.

[0066] FIG. 15 shows a timing diagram of a first embodiment of SPI data writing according to the present invention.

[0067] FIG. 16 shows a timing diagram of a second embodiment of SPI data writing according to the present invention.

[0068] FIG. 17 shows a timing diagram of a third embodiment of SPI data writing of the present invention.

[0069] FIG. 18 shows a timing diagram of a fourth embodiment of SPI data writing according to the present invention.

[0070] FIG. 19 shows a timing diagram of the fifth embodiment of SPI data writing according to the present invention.

[0071] FIG. 20 is a schematic diagram showing a write status packet in which the function module of the present invention returns status information indicating success to the interface module.

[0072] FIG. 21 shows a write status packet in which the function module returns a status message indicating failure to the interface module in one embodiment of the present invention.

[0073] FIG. 22 shows a write status packet in which the function module returns a status message indicating failure to the interface module in another embodiment of the present invention.

[0074] The meanings of the text labels in the above figures are as follows: 100: main controller; 100a: I2C master controller; 100b: SPI master controller; 200: interface module; 200a: I2C interface module; 200b: SPI interface module; SDA: I2C data line; SCL: I2C clock line; S: represents the I2C START signal, and the corresponding I2C bus state is that when SCL is high, SDA jumps from high to low; P: represents the I2C STOP signal, and the corresponding I2C bus state is that when SCL is high, SDA jumps from low to high; Sr: The corresponding I2C bus state is the same as S; Sr / P: The corresponding I2C bus state is Sr or P; ADDR: I2C address; R / W: represents the read and write operation indicator bit. When this bit is R, it indicates that the current I2C read operation is performed, and when this bit is W, it indicates that the current I2C write operation is performed; R: Indicates a read operation indicator. The corresponding I2C bus state is when SDA is high while SCL is high. W: Indicates a write operation indicator. The corresponding I2C bus state is when SDA is low while SCL is high. BYTE: Write operation data or read operation data, usually a multi-byte sequence. The content in brackets after it indicates the sequence number of the byte in the sequence. Write operation data sends a write command packet or read command packet, and read operation data reads read data or status information. The byte with the smaller sequence number is sent first. A: Indicates I2C ACK. The corresponding I2C bus state is when SDA is always low while SCL is high. N: Indicates I2C NAK. The corresponding I2C bus state is when SDA is always high while SCL is high. STATUS: A byte containing status information and a sequence of I2C ACK / I2C NAK between bytes. A / N: The corresponding I2C bus state is when SDA is always high or always low while SCL is high. HOLD: SCL is continuously at a low level; IDLE: The corresponding I2C bus status includes the following two possibilities:

[0075] (1) Both SCL and SDA are high;

[0076] (2) SCL and SDA may have other level states, but no legal I2C operation occurs in the combination of these level states. When IDLE is about to end, SCL and SDA are both high.

[0077] SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0078] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0079] As shown in Figure 1, according to an embodiment of the present invention, an interface system is provided, characterized in that the interface system includes a main controller 100, an interface module 200, a functional module 300, and a remote I2C slave device 400. The main controller 100 is connected to the interface module 200; the interface module 200 is connected to the functional module 300, and the functional module 300 is connected to the remote I2C slave device 400.

[0080] In the present invention, the interface module 200 can be connected to one or more functional modules 300, and the functional module 300 can also be connected to one or more remote I2C slave devices 400. The present invention is described below using the interface module 200 connected to one functional module 300 and the functional module 300 connected to one remote I2C slave device 400.

[0081] According to an embodiment of the present invention, a method for writing data to a remote I2C slave device is provided. The method uses an interface system provided by the present invention to write data to a remote I2C slave device 400, including:

[0082] The main controller 100 sends a write command packet to the interface module 200. After receiving the write command packet, the interface module 200 sends the write command packet to the function module 300.

[0083] As shown in FIG2 , the write command packet of the present invention includes multiple write commands. An exemplary write command packet includes write command 1, write command 2, . . . , write command N.

[0084] The functional module 300 receives a write command packet and executes multiple write commands contained in the write command packet. The method for executing each write command is as follows:

[0085] The functional module 300 sends an I2C START to the remote I2C slave device 400 , then the functional module 300 sends a remote I2C address byte to the remote I2C slave device 400 , and then the functional module 300 sends a write command to the remote I2C slave device 400 .

[0086] For each byte sent by the functional module 300 to the remote I2C slave device 400 , the functional module 300 receives an I2C acknowledge bit sent by the remote I2C slave device 400 and determines the execution result of the write command.

[0087] The function module 300 returns the write status packet to the interface module 200, including:

[0088] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet containing success status information to the interface module 200 .

[0089] When the execution result of at least one write command in the write command packet is failure, the function module 300 returns a write status packet containing failure status information to the interface module 200 .

[0090] The interface module 200 returns status information of the write status packet to the main controller 100 .

[0091] In one embodiment, the functional module 300 receives a write command packet and executes the write command contained in the write command packet. When the execution result of a write command is failure, the functional module 300 stops executing subsequent write commands, and the functional module 300 returns a write status packet with failure status information to the interface module 200.

[0092] As shown in FIG. 3 , in one embodiment, the main controller 100 is an I2C main controller 100 a , and the interface module 200 is an I2C interface module 200 a .

[0093] The I2C master controller 100a is connected to the I2C interface module 200a via the I2C clock line (SCL) and the I2C data line (SDA). The I2C master controller 100a initiates an I2C write operation and sends a write command packet to the I2C interface module 200a. After receiving the write command packet, the I2C interface module 200a pulls down the I2C clock line (SCL) level and sends the write command packet to the functional module 300.

[0094] The functional module 300 returns the write status packet to the I2C interface module 200a, and the I2C interface module 200a returns the status information of the write status packet to the I2C main controller 100a, including:

[0095] When the I2C interface module 200a receives the write status packet and the status information of the write status packet is success, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns an I2C ACK to the I2C master controller 100a.

[0096] When the I2C interface module 200a receives the write status packet and the status information of the write status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns an I2C NAK to the I2C master controller 100a.

[0097] As shown in Figure 4, the I2C write operation includes a write address byte and a write operation data byte (BYTE(1), ..., BYTE(N), shaded). The write address byte is the first byte sent. The write address byte includes the I2C address (ADDR) and a write operation indicator bit (W). According to the standard I2C specification, the write operation indicator bit (W) is a low level.

[0098] In this embodiment, the write address byte and the write operation data byte are both 8 bits, wherein the write address byte includes a 7-bit I2C address (ADDR) and a 1-bit write operation indicator bit (W). The present invention does not limit the number of bits of the write address byte and the write operation data byte. In other embodiments, the write address byte and the write operation data byte can have other bit numbers.

[0099] When the I2C master controller 100a initiates an I2C write operation, it first drives the I2C clock line (SCL) and the I2C data line (SDA) according to the standard I2C specification, generating an I2C START signal (S). It then sends a write address byte. After receiving the write address byte, the I2C interface module 200a drives the I2C data line (SDA) and generates an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be either an I2C ACK (I2C data line level is low) or an I2C NAK (I2C data line level is high).

[0100] When the response bit of the write address byte is I2C ACK, the I2C master controller 100a can send the write operation data byte. The I2C interface module 200a drives the I2C data line (SDA) to generate an acknowledge bit after receiving each write operation data byte. The acknowledge bit of the write operation data byte can be I2C ACK (I2C data line level is low) or I2C NAK (I2C data line level is high).

[0101] According to the standard I2C specification, when sending a write address byte and a write operation data byte, the I2C master controller 100a drives the I2C data line (SDA) to send the number of bits contained in the write address byte and the write operation data byte, and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100a drives the I2C clock line (SCL) to generate a clock pulse.

[0102] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line (SCL) to generate a clock pulse corresponding to the acknowledge bit of the write address byte and the acknowledge bit of the write operation data byte. The I2C master controller 100a ends the current write operation by sending the I2C STOP signal (P) or I2C START signal (S) as defined in the standard I2C specification.

[0103] As shown in FIG5 , the I2C read operation includes a read address byte and a read operation data byte (BYTE (1), …, BYTE (N), unshaded). The read address byte is the first byte sent by the I2C master controller 100 a, and the read operation data byte is sent by the I2C interface module 200 a. The read address byte includes the I2C address (ADDR) and a read operation indicator bit (R). According to the standard I2C specification, the read operation indicator bit (R) is a high level.

[0104] In this embodiment, the read address byte and the read operation data byte are both 8 bits, wherein the read address byte includes a 7-bit I2C address (ADDR) and a 1-bit read operation indicator bit (R). The present invention is not limited to the number of bits in the read address byte and the read operation data byte. In other embodiments, the read address byte and the read operation data byte can have other bit numbers.

[0105] When the I2C master controller 100a initiates an I2C read operation, the I2C master controller 100a first drives the I2C clock line and the I2C data line according to the standard I2C specification to generate an I2C START signal (S), and then sends a read address byte. After receiving the read address byte, the I2C interface module 200a drives the I2C data line and generates an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2C ACK (I2C data line level is low) or I2C NAK (I2C data line level is high).

[0106] When the response bit of the read address byte is I2C ACK, the I2C interface module 200a can return the read operation data byte by driving the I2C data line. The I2C master controller 100a drives the I2C data line to generate an response bit after receiving each read operation data byte. The response bit of the read operation data byte can be I2CACK (I2C data line level is low) or I2C NAK (I2C data line level is high).

[0107] According to the standard I2C specification, when the I2C master controller 100a sends a read address byte and the I2C interface module 200a returns a read operation data byte, the I2C master controller 100a drives the I2C data line to send the number of bits contained in the read address byte, and the I2C interface module 200a drives the I2C data line to return the bits contained in the read operation data byte. In addition, for each bit contained in the read address byte and the read operation data byte, the I2C master controller 100a drives the I2C clock line to generate a clock pulse.

[0108] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line to generate a clock pulse corresponding to the acknowledge bit of the read address byte and the acknowledge bit of the read operation data byte. The I2C master controller 100a ends the current read operation by sending an I2C STOP signal (P) or an I2C START signal (S) as defined in the standard I2C specification.

[0109] An I2C write or read cycle is initiated by the I2C START signal (S) but can be terminated in two ways. The first is with the I2C STOP signal (P). The timing sequences are shown in Figures 4 and 5, respectively.

[0110] The second method generates a new I2C START signal (S), which initiates the next I2C write or read operation. The timing sequence is shown in Figure 6. The dashed line between the acknowledge bit (A / N) and the I2C START signal (Sr) in Figure 6 (similar lines appear in other figures) is because the timing diagram is too long to be described on a single line, so it is split across multiple lines to indicate the connection between the two timing diagrams.

[0111] Using any of the above ending methods will not affect the data writing method of the present invention. For the convenience of description, this embodiment describes the end of an I2C operation (I2C write operation or I2C read operation) in a manner with an I2C STOP signal (P).

[0112] The write command packet of the present invention is sent through the write operation data bytes (BYTE (1), ..., BYTE (N), which are shaded). As shown in FIG2 , four embodiments of the write command packet are given:

[0113] The write command packet may only include write command 1, write command 2, ..., write command N.

[0114] The write command packet may also include a write command packet length field and write command 1, write command 2, ..., write command N.

[0115] The write command packet may also include a remote I2C address and write command 1, write command 2, ..., write command N.

[0116] The write command packet may also include a write command packet length field, a remote I2C address, and write command 1, write command 2, ..., write command N.

[0117] It should be noted that the present invention does not limit the format of the write command packet, that is, the write command packet format in the present invention is not limited to the four write command packet embodiments shown in Figure 2. The I2C master controller 100a and the I2C interface module 200a can agree on other write command packet formats.

[0118] The write command packet of the present invention is used to distinguish the read command packet. The write command packet is used to implement data writing of the remote I2C slave device 400, and the read command packet is used to read data from the remote I2C slave device 400. The present invention does not limit the method of reading data from the remote I2C slave device 400 through the read command packet.

[0119] For example, when the I2C master controller 100a initiates a write command packet, the I2C master controller 100a initiates an I2C write operation and sends the write address byte and the write operation data bytes (BYTE (1), ..., BYTE (N), shaded) containing the write command packet to the I2C interface module 200a.

[0120] The I2C interface module 200a has an I2C interface logic circuit. The I2C interface module 200a receives and responds to data from the I2C master controller 100a. The I2C interface module 200a and the I2C master controller 100a are interconnected via the I2C bus (I2C clock line and I2C data line). One I2C master controller 100a is connected to one or more I2C interface modules 200a. Each I2C interface module 200a has a unique I2C address (ADDR) on the I2C bus (I2C clock line and I2C data line) where it is located. According to the standard I2C specification, each I2C write operation or I2C read operation other than the I2C write broadcast is only for one of the I2C addresses (ADDR). The I2C interface modules 200a using other I2C addresses do not participate in the I2C write operation or I2C read operation.

[0121] As shown in FIG7 , in a specific embodiment, the I2C interface module 200a has a 7-bit I2C address 0x50 (corresponding to a write address byte of 0xA0 or a binary value of 1010000). The I2C master controller 100a initiates an I2C write operation and writes a total of 7 bytes of write operation data, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, to the I2C interface module 200a. These 7 bytes of write operation data comprise a write command packet. The 0xA0 byte corresponds to the write address byte, the upper 7 bits of which correspond to the I2C address (ADDR) of the I2C interface module 200a, and the lower 1 bit is the write operation indicator bit (W). A value of 0 in the write operation indicator bit (W) indicates that the current operation is a write operation. The value of this byte is the binary number 10100000, i.e., the hexadecimal number 0xA0.

[0122] In this example, the write command packet format may be the four write command packet embodiments shown in FIG. 2 , or may be other write command packet formats agreed upon between the I2C master controller 100 a and the I2C interface module 200 a .

[0123] In the present invention, the I2C interface module 200a receiving the write command packet means that the write operation data received by the I2C interface module 200a includes a complete write command packet. In the embodiment shown in Figure 7, the write operation data of 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, a total of 7 bytes in length, includes a complete write command packet. Therefore, the I2C interface module 200a receives the last bit of the 0x61 byte, and the I2C interface module 200a receives the write command packet.

[0124] As shown in Figure 2, the write command packet may include a write command packet length field. The I2C interface module 200a may determine whether the received write operation data includes a complete write command packet based on the write command packet length field (or partially based on the write command packet length field) according to the agreement between the I2C main controller 100a. As shown in Figure 2, the write command packet may not include the write command packet length field. In this case, the I2C interface module 200a may determine whether the received write operation data includes a complete write command packet based on the agreement between the I2C main controller 100a (this agreement is not based on the write command packet length field).

[0125] In the embodiment shown in FIG7 , the I2C interface module 200a receives the last bit of the 0x61 byte and receives a write command packet. The I2C interface module 200a then pulls down the I2C clock line level, placing the I2C bus in a HOLD state (a continuous low level state). The I2C interface module 200a then sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the multiple write commands contained in the write command packet, namely, write command 1, write command 2, ..., write command N. It then returns a write status packet to the I2C interface module 200a, including:

[0126] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet with status information indicating success to the I2C interface module 200a;

[0127] When the execution result of at least one write command included in the write command packet is failure, the functional module 300 returns a write status packet containing failure status information to the I2C interface module 200a.

[0128] In the present invention, when the I2C interface module 200a sends the write command packet to the functional module 300, the content in the write command packet may be modified, added or deleted, and the present invention does not impose any limitation or stipulation on this.

[0129] According to an embodiment of the present invention, when the I2C interface module 200a receives a write status packet and the status information of the write status packet is success, the I2C interface module 200a stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller 100a.

[0130] When the I2C interface module 200a receives the write status packet and the status information of the write status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller 100a.

[0131] The subsequent I2C operation referred to in the present invention is relative to the previous I2C operation, and the I2C operation may be an I2C write operation or an I2C read operation.

[0132] As shown in Figure 8, an example is given to describe the situation when the I2C interface module 200a receives a write status packet and the status information of the write status packet is successful. The I2C master controller 100a initiates an I2C operation (I2C write operation) with a sequence number of m (m is a natural number), and the I2C operation with a sequence number of m+1 initiated by the I2C master controller 100a is a subsequent I2C operation (relative to the I2C operation with a sequence number of m).

[0133] In the embodiment shown in FIG8 , a write command packet is sent through an I2C write operation with a sequence number of m. After receiving the write command packet (after receiving BYTE(N)), the I2C interface module 200a pulls down the I2C clock line level.

[0134] At time ①, the I2C interface module 200a receives a write status packet and the status information of the write status packet is success. The I2C interface module 200a stops pulling down the I2C clock line level and terminates the HOLD state (terminates the continuous low level state).

[0135] At moment ②, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a. The I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and initiates the I2C operation with sequence number m+1 (subsequent I2C operation). The subsequent I2C operation is an I2C write operation or an I2C read operation.

[0136] After the I2C interface module 200a returns an I2C ACK in the I2C operation with sequence number m, it continues to receive subsequent I2C operations initiated by the I2C master controller 100a (that is, after receiving the read address byte or the write address byte in the I2C operation with sequence number m+1, it returns an I2C ACK and continues the I2C operation with sequence number m+1). The above process is repeated, and the I2C master controller 100a continuously initiates I2C operations.

[0137] As shown in Figure 9, an example is used to describe the situation when the I2C interface module 200a receives a write status packet and the status information of the write status packet is failure. The I2C master controller 100a initiates an I2C operation (I2C write operation) with a sequence number of m (m is a natural number). The I2C master controller 100a sends a write command packet through the I2C write operation with a sequence number of m. After receiving the write command packet (after receiving BYTE (N)), the I2C interface module 200a pulls down the I2C clock line level.

[0138] At time ①, the I2C interface module 200a receives a write status packet and the status information of the write status packet is failure. The I2C interface module 200a stops pulling down the I2C clock line level and terminates the HOLD state (terminates the continuous low level state).

[0139] At time ②, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (I2C write operation) with sequence number m.

[0140] After the I2C interface module 200a returns an I2C NAK in the I2C operation with sequence number m, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C write operation, after the I2C interface module 200a receives the write address byte, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a, thereby terminating the subsequent I2C operation (I2C write operation).

[0141] After the I2C interface module 200a returns an I2C NAK in the I2C operation with sequence number m, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, after the I2C interface module 200a receives the read address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a and continues to return the status information (STATUS) of the write status packet, so that the I2C master controller 100a continues to perform the subsequent I2C operation (I2C read operation). While the I2C master controller 100a continues to perform the subsequent I2C operation (I2C read operation), the I2C interface module 200a reads the status information (STATUS) of the write status packet. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a continues to receive subsequent I2C operations initiated by the I2C master controller 100a, and the above process is repeated. The I2C master controller 100a continuously initiates I2C operations. In the present invention, the status information (STATUS) may be success or failure information contained in the write status packet, or may include other information contained in the write status packet. According to an embodiment of the present invention, the I2C master controller 100a is connected to the I2C interface module 200a via the I2C clock line and the I2C data line. The I2C master controller 100a initiates an I2C write operation and sends a write command packet to the I2C interface module 200a. After receiving the write command packet, the I2C interface module 200a sends the write command packet to the functional module 300.

[0142] The functional module interface 300 receives the write command packet and executes the multiple write commands contained in the write command packet, namely, write command 1, write command 2, ..., write command N, and then returns a write status packet to the I2C interface module 200a, including:

[0143] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet with status information indicating success to the I2C interface module 200a;

[0144] When the execution result of at least one write command included in the write command packet is failure, the functional module 300 returns a write status packet containing failure status information to the I2C interface module 200a.

[0145] In the present invention, when the I2C interface module 200a sends the write command packet to the functional module 300, the content in the write command packet may be modified, added or deleted, and the present invention does not impose any limitation or stipulation on this.

[0146] The functional module 300 returns the write status packet to the I2C interface module 200a, and the I2C interface module 200a returns the status information of the write status packet to the I2C main controller 100a, including:

[0147] After the I2C interface module 200a receives the write command packet,

[0148] If the subsequent I2C operation initiated by the I2C master controller 100a is an I2C write operation, and the I2C interface module 200a receives the write status packet returned by the functional module 300 to the I2C interface module 200a, and the status information of the write status packet is success, the I2C interface module 200a receives the subsequent I2C write operation initiated by the I2C master controller 100a;

[0149] If the subsequent I2C operation initiated by the I2C master controller 100a is an I2C write operation, and the I2C interface module 200a receives the write status packet returned by the functional module 300 to the I2C interface module 200a and the status information of the write status packet is failure, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a.

[0150] If the subsequent I2C operation initiated by the I2C master controller 100a is an I2C read operation, and the I2C interface module 200a receives the write status packet returned by the functional module 300 to the I2C interface module 200a, the I2C interface module 200a returns status information of the write status packet to the I2C master controller 100a.

[0151] As shown in Figures 10 and 11, the I2C operation with sequence number m initiated by the I2C master controller 100a is an I2C write operation, and the write command packet is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a.

[0152] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)) (i.e., after the I2C interface module 200a receives the complete write command packet), the I2C interface module 200a may return an I2C ACK or an I2C NAK to the I2C master controller 100a. The specific selection is made by the agreement between the I2C master controller 100a and the I2C interface module 200a. The I2C master controller 100a and the I2C interface module 200a may agree that after the Nth write operation data byte (BYTE(N)), whether I2C ACK or I2C NAK indicates the successful reception of the Nth write operation data byte (i.e., the complete write command packet). It may also be agreed that the I2C NAK indicates that the Nth write operation data byte (BYTE(N)) was not successfully received (i.e., the complete write command packet was not successfully received). In the following description of the present invention, whether the I2C interface module 200a returns I2CACK or I2C NAK to the I2C master controller 100a after the Nth write operation data byte (BYTE(N)), it indicates that the Nth write operation data byte (i.e., the complete write command packet) was successfully received.

[0153] After the I2C master controller 100a completes sending the Nth write operation data byte (BYTE(N)), regardless of whether the I2C interface module 200a returns an I2C ACK or an I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and may optionally initiate an I2C operation with sequence number m+1 (subsequent I2C operation).

[0154] When the I2C operation with sequence number m+1 (the subsequent I2C operation) is an I2C write operation, if the I2C interface module 200a receives the write status packet (the write status packet corresponding to the I2C operation with sequence number m) returned by the functional module 300 to the I2C interface module 200a and the status information of the write status packet is success, then after the I2C master controller 100a sends the write address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a, and the I2C interface module 200a receives the write operation data byte sent by the I2C operation with sequence number m+1 (the subsequent I2C operation / I2C write operation) initiated by the I2C master controller 100a, as shown in FIG. 10 .

[0155] If the I2C interface module 200a receives a write status packet (the write status packet corresponding to the I2C operation process with sequence number m) returned by the functional module 300 to the I2C interface module 200a and the status information of the write status packet is failure, then after the I2C master controller 100a sends the write address byte, the I2C interface module 200a returns an I2C NAK to the I2C master controller 100a, and the master controller 100a terminates the initiation of the I2C operation m+1 (subsequent I2C operation / I2C write operation), as shown in Figure 11.

[0156] As shown in FIG12 , the I2C operation with sequence number m initiated by the I2C master controller 100a is an I2C write operation, and a write command packet is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), …, BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a.

[0157] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)) (ie, after the I2C interface module 200a receives the complete write command packet), the I2C interface module 200a may return an I2C ACK or an I2C NAK to the I2C master controller 100a.

[0158] After the I2C master controller 100a completes sending the Nth write operation data byte (BYTE(N)), regardless of whether the I2C interface module 200a returns an I2C ACK or an I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation with sequence number m (I2C write operation) and may optionally initiate an I2C operation with sequence number m+1 (subsequent I2C operation).

[0159] When the I2C operation with sequence number m+1 (the subsequent I2C operation) is an I2C read operation, if the I2C interface module 200a receives the write status packet (the status packet corresponding to the I2C operation with sequence number m) returned by the functional module 300 to the I2C interface module 200a, then after the I2C master controller 100a sends the read address byte, the I2C interface module 200a returns an I2C ACK to the I2C master controller 100a and returns status information (STATUS) of the write status packet (the status packet corresponding to the I2C operation with sequence number m). In the present invention, the status information (STATUS) can be the success or failure information contained in the write status packet, or can include other information contained in the write status packet.

[0160] As shown in FIG13 , in one embodiment, the main controller 100 is an SPI main controller 100 b , and the interface module 200 is an SPI interface module 200 b . The SPI main controller 100 b is connected to the SPI interface module 200 b via the SPI_CK signal line, the SPI_MOSI signal line, and the SPI_MISO signal line.

[0161] The SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b via the SPI_MOSI signal line. The write command packet starts with a first identifier. After receiving the write command packet from SPI_MOSI, the SPI interface module 200b sends the write command packet to the functional module 300.

[0162] The functional module interface 300 receives the write command packet and executes the multiple write commands contained in the write command packet, namely, write command 1, write command 2, ..., write command N, and then returns a write status packet to the SPI interface module 200b, including:

[0163] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet with status information indicating success to the SPI interface module 200b;

[0164] When the execution result of at least one write command included in the write command packet is failure, the function module 300 returns a write status packet containing failure status information to the SPI interface module 200 b.

[0165] In the present invention, when the SPI interface module 200b sends the write command packet to the functional module 300, the content in the write command packet may be modified, added or deleted, and the present invention does not impose any limitation or stipulation on this.

[0166] The functional module 300 returns the write status packet to the SPI interface module 200b, and the SPI interface module 200b returns the status information of the write status packet to the SPI master controller 100b, including:

[0167] After the SPI interface module 200b receives the write status packet, when the SPI master controller 100b generates a clock edge on SPI_CK, the SPI interface module 200b sends a write feedback packet to the SPI master controller 100b through the SPI_MISO signal line. The write feedback packet starts with the second identifier and includes the status information included in the write status packet.

[0168] As shown in FIG14 , when the main controller 100 is an SPI main controller 100b and the interface module 200 is an SPI interface module 20b, the data structure of the write command packet is shown. In the embodiment, four examples of write command packets are given as examples:

[0169] The write command packet may include a first identifier and write command 1, write command 2, . . . , write command N, and start with the first identifier.

[0170] The write command packet may also include a first identifier, a write command packet length field, and write command 1, write command 2, ..., write command N, and start with the first identifier.

[0171] The write command packet may also include a first identifier, a remote I2C address, a write command 1, a write command 2, ..., a write command N, and start with the first identifier.

[0172] The write command packet may also include a first identifier, a write command packet length field, a remote I2C address, a write command 1, a write command 2, ..., a write command N, and start with the first identifier.

[0173] The first identifier, write command packet length field (if any), remote I2C address (if any), write command 1, write command 2, ..., write command N contained in the write command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the first identifier, write command packet length field (if any), remote I2C address (if any), write command 1, write command 2, ..., write command N.

[0174] It should be noted that the present invention does not limit the format of the write command packet, that is, the write command packet format in the present invention is not limited to the four write command packet embodiments shown in Figure 14. The SPI master controller 100b and the SPI interface module 200b can agree on other write command packet formats.

[0175] In the present invention, the SPI interface module 200b receiving a write command packet means that the data received by the SPI interface module 200b from the SPI_MOSI signal line contains a complete write command packet. As shown in FIG14 , the write command packet may include a write command packet length field. The SPI interface module 200b may determine whether the received data contains a complete write command packet based on the write command packet length field (or partially based on the write command packet length field) according to an agreement between the SPI interface module 200b and the SPI master controller 100b. As shown in FIG14 , the write command packet may not include the write command packet length field. In this case, the SPI interface module 200b determines whether the received data contains a complete write command packet based on the agreement between the SPI interface module 200b and the SPI master controller 100b (this agreement is not based on the write command packet length field).

[0176] The SPI master controller 100b drives the SPI_CK signal line, generates a clock edge on the SPI_CK signal line, and samples the data on the SPI_MISO signal line at the rising or falling edge of the clock on the SPI_CK signal line. The SPI interface module 200b samples the data on the SPI_MOSI signal line at the rising or falling edge of the clock on the SPI_CK signal line, thereby realizing bidirectional data transmission between the SPI master controller 100b and the SPI interface module 200b.

[0177] The present invention is not limited to sampling data on the SPI_MISO and SPI_MOSI signal lines at the rising or falling edge of the SPI_CK signal line. In the embodiments described below, data on the SPI_MISO and SPI_MOSI signal lines are sampled at the rising edge of the SPI_CK signal line. That is, in the embodiments described below, the rising edge of the SPI_CK signal line serves as the sampling clock edge. In other embodiments, data on the SPI_MISO and SPI_MOSI signal lines may also be sampled at the falling edge of the SPI_CK signal line. That is, in these embodiments, the falling edge of the SPI_CK signal line serves as the sampling clock edge.

[0178] As shown in FIG15 , the SPI master controller 100b generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a write command packet to the SPI interface module 200b through the SPI_MOSI signal line. The write command packet contains N bytes, each byte is 8-bit binary data, the first byte is the first identifier, and the 8-bit binary data of the first byte is C 10 、C 11 …C 17 Indicates that the Nth byte of the write command packet is the last byte of the write command packet, and the 8-bit binary data of the Nth byte of the write command packet is in C N0 、C N1 …C N7 express.

[0179] The SPI interface module 200b samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line and receives the write command packet from the SPI_MOSI signal line. N7 After the SPI_MOSI signal line receives the complete write command packet, the SPI interface module 200b receives the write command packet.

[0180] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the write command packet to the functional module 300. In the present invention, when the SPI interface module 200b sends the write command packet to the functional module 300, the content of the write command packet may be modified, added, or deleted, and the present invention does not impose any restrictions or regulations on this.

[0181] The functional module interface 300 receives the write command packet and executes the multiple write commands contained in the write command packet, namely, write command 1, write command 2, ..., write command N, and then returns a write status packet to the SPI interface module 200b, including:

[0182] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet with status information indicating success to the SPI interface module 200b;

[0183] When the execution result of at least one write command included in the write command packet is failure, the function module 300 returns a write status packet containing failure status information to the SPI interface module 200 b.

[0184] At moment ①, the SPI interface module 200b receives the write status packet, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b drives the SPI_MISO signal line, and sends a write feedback packet through the SPI_MISO signal line. The SPI master controller 100b samples the data on the SPI_MISO signal line at the rising clock edge on the SPI_CK signal line and reads the write feedback packet. The write feedback packet starts with the second identifier and contains the status information contained in the write status packet. The status information contained in the write status packet can be write success, write failure, or other status information.

[0185] The write feedback packet contains M bytes, each byte is 8-bit binary data, the first byte is the second identifier, and the 8-bit binary data of the first byte is A 10 、A 11 …A 17 Indicates that the Mth byte of the write feedback packet is the last byte of the write feedback packet, and the 8-bit binary data of the Mth byte of the write feedback packet is in A M0 、A M1 …A M7 express.

[0186] For ease of understanding, in the embodiment shown in FIG. 15 and in the following description of the present invention, each byte is described as 8-bit binary data, but the present invention does not limit the number of bits of each byte, and each byte may also have other numbers of bits.

[0187] In the embodiment shown in Figure 15, the length of the first identifier and the second identifier is one byte, and the length of the write command packet and the write feedback packet is an integer multiple of bytes. For ease of understanding, in the following description of the present invention, the length of the first to fourth identifiers is one byte, and the length of the write command packet and the write feedback packet (including the write success feedback packet and the write failure feedback packet) is an integer multiple of bytes. However, the present invention does not limit the length of the first to fourth identifiers to one byte, nor does it limit the length of the first to fourth identifiers to an integer multiple of bytes. The present invention also does not limit the length of the write command packet and the write feedback packet (including the write success feedback packet and the write failure feedback packet) to an integer multiple of bytes.

[0188] In the interval marked as "no clock edge", the SPI master controller 100b does not generate a sampling clock edge on the SPI_CK signal line. In FIG. 15 and the subsequent embodiments of the present invention, the levels of the SPI_MOSI and SPI_MISO signal lines remain unchanged in the "no clock edge" interval. The present invention is not limited to the levels of the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval. The levels of the SPI_MOSI and SPI_MISO signal lines may also change in the "no clock edge" interval. However, because data on the SPI_MOSI and SPI_MISO signal lines is sampled only on the sampling clock edge of the SPI_CK signal line (the sub-sampling clock edge in the embodiment shown in FIG. 15 is the rising clock edge), level changes on the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval will not be sampled and received.

[0189] In the embodiment shown in FIG15 , the SPI master controller 100b generates a clock edge on the SPI_CK signal line and simultaneously drives the SPI_MOSI signal line. When sending a write command packet via the SPI_MOSI signal line, the SPI interface module 200b does not have a write feedback packet to send. At this time, the SPI interface module 200b drives the SPI_MISO signal line high. During this period, the SPI interface module 200b of the present invention may also drive the SPI_MISO signal line low or a varying level. However, the SPI interface module 200b must ensure that the level value or varying level value driven on the SPI_MISO signal line is not recognized as a second identifier if sampled by the SPI master controller 100b on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG15 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG15 as an example, since the SPI interface module 200b drives the SPI_MISO signal line high (sampling continuous binary bits 1) during this period, in order to avoid being recognized as a second identifier, the value of the second identifier should not be 0xFF.

[0190] In the embodiment shown in FIG15 , the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and the SPI interface module 200b drives the SPI_MISO signal line. When sending a write feedback packet via the SPI_MISO signal line, the SPI master controller 100b does not have a write command packet to send. During this period, the SPI master controller 100b of the present invention may also drive the SPI_MOSI signal line to a low level or a varying level. However, the SPI master controller 100b must ensure that the level value or varying level value driven on the SPI_MOSI signal line is not recognized as a first identifier if sampled by the SPI interface module 200b on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG15 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG15 as an example, since the SPI master controller 100b drives the SPI_MOSI signal line to a high level (sampling continuous binary bits 1) during this period, in order to avoid being recognized as a first identifier, the value of the first identifier should not be 0xFF.

[0191] In addition to the SPI_CK, SPI_MOSI, and SPI_MISO signal lines, the SPI interface module 200b can also connect to the SPI master controller 100b via the SPI_CSN signal line. The SPI master controller 100b drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the SPI interface module 200b receives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines. The SPI interface module 200b drives the SPI_MISO signal line, while the SPI master controller 100b receives the SPI_MISO signal line. The SPI_CSN signal line is a select signal. In the SPI protocol, data transmission occurs only when the SPI_CSN signal line is low. An SPI master controller 100b can be connected to multiple SPI interface modules 200b. The SPI master controller 100b and multiple SPI interface modules 200b share the SPI_CK, SPI_MOSI, and SPI_MISO signal lines. However, each SPI interface module 200b has an independent SPI_CSN signal line input. When the SPI_CSN signal line of a SPI interface module 200b is high, this SPI interface module 200b does not drive the SPI_MISO signal line (the driver connected to the SPI_MISO signal line of this SPI interface module 200b outputs a Hi-Z state). An SPI interface module 200b only drives the SPI_MISO signal line when its SPI_CSN signal line is low. When a SPI master controller 100b is connected to multiple SPI interface modules 200b, at any given time, only one SPI interface module 200b has its SPI_CSN signal line low. This prevents conflicts caused by multiple SPI interface modules 200b driving the SPI_MISO signal line simultaneously.

[0192] When an SPI master controller 100b is connected to only one SPI interface module 200b, the SPI interface module 200b can drive the SPI_MISO signal line at any time without causing any conflict. In this case, there may be no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b. That is, when an SPI master controller 100b is connected to only one SPI interface module 200b, the SPI master controller 100b and the SPI interface module 200b may be connected only through the SPI_CK signal line, the SPI_MOSI signal line, and the SPI_MISO signal line. This is the case in the above description of the embodiment shown in FIG. 15 .

[0193] The present invention only describes the case where there is no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b. However, based on the present invention, this description can be easily extended to the case where an SPI_CSN signal line is present between the SPI master controller 100b and the SPI interface module 200b. Therefore, the present invention does not further describe the case where an SPI_CSN signal line is present between the SPI master controller 100b and the SPI interface module 200b. Regardless of whether an SPI_CSN signal line exists between the SPI master controller 100b and the SPI interface module 200b, the present invention is within the scope of protection of the present invention.

[0194] According to an embodiment of the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0195] When the SPI interface module 200 b does not receive the write status packet, the SPI interface module 200 b sends data that cannot be identified as a write feedback packet to the SPI master controller 100 b through the SPI_MISO signal line.

[0196] Taking FIG16 as an example, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes multiple write commands contained in the write command packet, and then returns a write status packet to the SPI interface module 200b. At time ③, the SPI interface module 200b receives the write status packet. Before the SPI interface module 200b receives the write status packet at time ③, between time ① and time ②, the SPI master controller 100b generates a clock edge on the SPI_CK signal line. In the embodiment shown in FIG16, the SPI interface module 200b b drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200b may also drive the SPI_MISO signal line to a low level or a varying level. However, the SPI interface module 200b should ensure that the level value or the varying level value driven on the SPI_MISO signal line is not recognized as a second identifier if it is sampled by the SPI master controller 100b on the sampling clock edge of the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG16 ). That is, when the SPI interface module 200b does not receive the write status packet, if the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b sends data that cannot be recognized as a write feedback packet to the SPI master controller 100b via the SPI_MISO signal line. At time ③, after the SPI interface module 200b receives the write status packet, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback packet from the SPI interface module 200b via the SPI_MISO signal line.

[0197] In the embodiment shown in FIG17 , the SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the multiple write commands contained in the write command packet, and then returns a write status packet to the SPI interface module 200b. At time ①, the SPI interface module 200b receives the write status packet, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads a write feedback packet from the SPI interface module 200b via the SPI_MISO signal line. At moment ②, the SPI master controller 100b completes reading the write feedback packet, and the SPI interface module 200b completes sending the write feedback packet. The SPI master controller 100b continues to generate clock edges on the SPI_CK signal line. At this time, the SPI interface module 200b drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200b may also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200b should ensure that the level value driven or the changing level value on the SPI_MISO signal line is not recognized as the second identifier if it is sampled by the SPI master controller 100b on the sampling clock edge of the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG. 17 ).

[0198] According to an embodiment of the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b through the SPI_MOSI signal line.

[0199] Then the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. After the SPI interface module 200b sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets (subsequent command packets include write command packets and read command packets).

[0200] In the present invention, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module 200b through the SPI_MOSI signal line. After the SPI interface module 200b receives the write command packet from the SPI_MOSI signal line, it sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes multiple write commands contained in the write command packet, and then returns a write status packet to the SPI interface module 200b. Then, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module 200b through the SPI_MOSI signal line. A clock edge is generated on the signal line, and a write feedback packet is read through the SPI_MISO signal line. Before the SPI master controller 100b reads the write feedback packet, if the SPI master controller 100b drives the SPI_MOSI signal line to send a command packet (including a write command packet and a read command packet), the SPI interface module 200b does not receive the command packet sent before the SPI master controller 100b reads the write feedback packet. After the SPI master controller 100b reads the write feedback packet, that is, after the SPI interface module 200b sends the write feedback packet through the SPI_MISO signal line, the SPI interface module 200b can continue to receive subsequent command packets (subsequent command packets include write command packets and read command packets).

[0201] According to an embodiment of the present invention, the write feedback packet is divided into a write success feedback packet and a write failure feedback packet;

[0202] The SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0203] When the SPI interface module 200b receives the write status packet and the status information contained in the write status packet is success, the SPI interface module 200b sends a write success feedback packet through the SPI_MISO signal line. The write success feedback packet starts with the third identifier.

[0204] When the SPI interface module 200b receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module 200b sends a write failure feedback packet through the SPI_MISO signal line. The write failure feedback packet starts with the fourth identifier.

[0205] As shown in Figure 18, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes multiple write commands contained in the write command packet. It then returns a write status packet to the SPI interface module 200b. At time ①, the SPI interface module 200b receives the write status packet containing success status information. When the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200b via the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a write success feedback packet to the SPI master controller 100b via the SPI_MISO signal line. The write success feedback packet begins with the third identifier.

[0206] As shown in Figure 19, the SPI master controller 100b generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200b via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200b sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes multiple write commands contained in the write command packet. It then returns a write status packet to the SPI interface module 200b. At time ①, the SPI interface module 200b receives the write status packet containing failure status information. When the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200b via the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line and sends a write failure feedback packet to the SPI master controller 100b via the SPI_MISO signal line. The write failure feedback packet begins with the fourth identifier.

[0207] In the present invention, the third identifier is different from the fourth identifier. When the SPI master controller 100b reads a write feedback packet, it can determine whether the read write success feedback packet or the write failure feedback packet is a write success feedback packet or a write failure feedback packet based on whether the write feedback packet starts with the third identifier or the fourth identifier. Therefore, the write success feedback packet can only include the third identifier, and the write failure feedback packet can only include the fourth identifier. This allows the SPI master controller 100b to distinguish whether the read write feedback packet is a write success feedback packet or a write failure feedback packet.

[0208] In addition to being an I2C master controller 100a and an SPI master controller 100b, the main controller 100 in the present invention can also be a master controller that complies with other interface protocols (for example, a master controller that complies with serial UART protocol, CAN protocol, LIN protocol, etc.). In addition to being an I2C interface module 200a and an SPI interface module 200b, the interface module 200 in the present invention can also be an interface module that complies with other interface protocols (for example, an interface module that complies with serial UART protocol, CAN protocol, LIN protocol, etc.). The use of a main controller that complies with other interface protocols and an interface module that complies with other interface protocols also fall within the scope of protection of the present invention.

[0209] According to an embodiment of the present invention, the master controller 100 (I2C master controller 100a or SPI master controller 100b or a master controller that complies with other interface protocols) sends a write command packet to the interface module 200 (I2C interface module 200a or SPI interface module 200b or an interface module that complies with other interface protocols). After receiving the write command packet, the interface module 200 sends the write command packet to the functional module 300. The write command packet includes multiple write commands, as shown in Figures 2 and 14.

[0210] The functional module 300 receives a write command packet and executes multiple write commands contained in the write command packet. The method for executing each write command is as follows:

[0211] The functional module 300 sends an I2C START to the remote I2C slave device 400 , then the functional module 300 sends a remote I2C address byte to the remote I2C slave device 400 , and then the functional module 300 sends a write command to the remote I2C slave device 400 .

[0212] For each byte sent by the functional module 300 to the remote I2C slave device 400 , the functional module 300 receives an I2C acknowledge bit sent by the remote I2C slave device 400 and determines the execution result of the write command.

[0213] The function module 300 returns the write status packet to the interface module 200, including:

[0214] When the execution result of each write command included in the write command packet is successful, the function module 300 returns a write status packet containing success status information to the interface module 200 , and the interface module 200 returns the status information of the write status packet to the main controller 100 .

[0215] As shown in FIG20 , for each write command (write command 1, write command 2, ..., write command N) included in the write command packet, the functional module 300 first sends an I2C START to the remote I2C slave device 400. Then, the functional module 300 sends a remote I2C address byte to the remote I2C slave device 400. Then, the functional module 400 sends a write command to the remote I2C slave device 400. The remote I2C address byte consists of an I2C address (ADDR) and a write operation indicator bit (W).

[0216] For a write command, if the I2C response bit received after the functional module 300 sends the remote I2C address byte is I2C ACK, and the I2C response bit received after the functional module 300 sends each byte of the write command is I2C ACK, the result of the functional module 300 executing the write command is success.

[0217] As shown in FIG. 20 , when the execution result of each write command is successful, the function module 300 returns a write status packet with success status information to the interface module 200 , and the interface module 200 returns the status information of the write status packet to the main controller 100 .

[0218] In other embodiments (not shown in FIG. 20 ), the functional module 300 may also agree with the remote I2C slave device 400 that, for a write command, if the I2C response bit received after the functional module 300 sends the remote I2C address byte is I2C ACK, and the I2C response bit received after the functional module 300 sends each byte of the write command except the last byte is I2C ACK, and if the I2C response bit received after the functional module 300 sends the last byte of the write command is I2C NAK, the functional module 300 also considers the result of executing the write command to be successful.

[0219] When the execution result of a write command is failure, the function module 300 stops executing subsequent write commands and returns a write status packet with failure status information to the interface module 200 . The interface module 200 returns the status information of the write status packet to the main controller 100 .

[0220] As shown in FIG21 , after the functional module 300 sends the remote I2C address byte (the write command 1 address byte) to the remote I2C slave device 400, the functional module 300 receives an I2C acknowledge bit, I2CNAK, from the remote I2C slave device 400, indicating a failure in executing the write command 1. The functional module 300 stops executing subsequent write commands and returns a write status packet containing a failure status message to the interface module 200. The interface module 200 then returns the status information of the write status packet to the main controller 100.

[0221] As shown in FIG22 , another embodiment of a write command execution failure is given. After the function module 300 sends the remote I2C address byte, the I2C response bit received is I2C ACK, and the I2C response bit received after the function module 300 sends each byte of write command 1 is I2C ACK. The result of the function module 300 executing write command 1 is success. Then, for write command 2, the I2C response bit received after the function module 300 sends the remote I2C address byte is I2C ACK. However, after the function module 300 sends write command 2 byte 1, the I2C response bit received by the function module 300 from the remote I2C slave device 400 is NAK, and the execution result of write command 2 is failure (in this embodiment, write command 2 byte 1 is not the last byte of write command 2, or write command 2 byte 1 is the last byte of write command 2, but the function module 300 and the remote I2C slave device 400 agree that the I2C response bit after sending each byte of a write command is I2C ACK. ACK is considered that the write command is executed successfully), so the execution result of at least one write command in the write command packet is failure, the functional module 300 returns a write status packet with failure status information to the interface module 200, and the interface module 200 returns the status information of the write status packet to the main controller 100.

[0222] When at least one of the write commands included in the write command packet fails, the function module 300 returns a write status packet containing failure status information to the interface module 200 , and the interface module 200 returns the status information of the write status packet to the main controller 100 .

[0223] In the embodiments shown in Figures 21 and 22, when the execution result of a write command is failure, the functional module 300 stops executing subsequent write commands and returns a write status packet containing failure status information to the interface module 200, which then returns the status information of the write status packet to the main controller 100. In other embodiments, when the execution result of a write command is failure, the functional module 300 may choose to continue executing subsequent write commands included in the write command packet. However, when the execution result of at least one write command included in the write command packet is failure, the functional module 300 returns a write status packet containing failure status information to the interface module 200, which then returns the status information of the write status packet to the main controller 100.

[0224] In a preferred embodiment, the functional module 300 includes a remote I2C address register, and the I2C address (such as ADDR shown in Figures 20, 21, and 22) contained in the remote I2C address byte sent by the functional module 300 to the remote I2C slave device 400 is the remote I2C address stored in the remote I2C address register.

[0225] In a preferred embodiment, the write command packet includes a remote I2C address (as shown in FIG. 2 and FIG. 14 , which include a write command packet with a remote I2C address), and the I2C address included in the remote I2C address byte sent by the functional module 300 to the remote I2C slave device 400 is the remote I2C address included in the write command packet.

[0226] Furthermore, the functional module 300 includes a remote I2C address register, and the functional module 300 also includes a remote I2C address selection module. The I2C address contained in the remote I2C address byte sent by the functional module 300 to the remote I2C slave device 400 is derived from the remote I2C address stored in the remote I2C address register or from the remote I2C address contained in the write command packet according to the instruction of the remote I2C address selection module.

[0227] In a preferred embodiment, the write command packet includes multiple write commands, each of which includes a remote I2C address. The remote I2C address included in the remote I2C address byte sent by the functional module 300 to the remote I2C slave device is derived from the remote I2C address included in each write command.

[0228] It should be noted that the present invention does not limit the format of write command 1, write command 2, ..., write command N, nor does it limit the method for determining the length of write command 1, write command 2, ..., write command N. Regardless of the format of write command 1, write command 2, ..., write command N used, it is within the scope of protection of the present invention.

[0229] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments made by a person skilled in the art within the scope of the present invention shall fall within the scope of protection of the present invention.

Claims

1. An interface system, characterized in that: The interface system includes a main controller, an interface module, a functional module, and a remote I2C slave device; The main controller is connected to the interface module; the interface module is connected to the functional module, and the functional module is connected to a remote I2C slave device.

2. A method for writing data from a remote I2C slave device, characterized in that: Using the interface system of claim 1 to write data to a remote I2C slave device comprises: The main controller sends a write command packet to the interface module, and when the interface module receives the write command packet, the interface module sends the write command packet to the functional module; The write command packet includes multiple write commands, the function module receives the write command packet and executes the multiple write commands included in the write command packet, and the method for executing each write command is: The function module sends I2C START to the remote I2C slave device, then the function module sends the remote I2C address byte to the remote I2C slave device, and then the function module sends a write command to the remote I2C slave device; For each byte sent by the function module to the remote I2C slave device, the function module receives the I2C response bit sent by the remote I2C slave device and determines the execution result of the write command. The function module returns the write status packet to the interface module, including: When the execution result of each write command included in the write command packet is successful, the functional module returns a write status packet with status information indicating success to the interface module; When the execution result of at least one write command included in the write command packet is failure, the function module returns a write status packet with failure status information to the interface module; The interface module returns the status information of the write status packet to the main controller.

3. The remote I2C slave device data writing method according to claim 2, characterized in that: The functional module receives the write command packet and executes the write command contained in the write command packet. When the execution result of a write command is failure, the functional module stops executing subsequent write commands, and the functional module returns a write status packet with failure status information to the interface module.

4. The remote I2C slave device data writing method according to claim 2, characterized in that: The main controller is an I2C main controller, and the interface module is an I2C interface module; The I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line. The I2C master controller initiates an I2C write operation to send a write command packet to the I2C interface module. After receiving the write command packet, the I2C interface module pulls down the I2C clock line level and sends the write command packet to the functional module. The function module returns the write status packet to the I2C interface module, and the I2C interface module returns the status information of the write status packet to the I2C main controller, including: When the I2C interface module receives the write status packet and the status information of the write status packet is success, the I2C interface module stops pulling down the I2C clock line level and returns an I2C ACK to the I2C master controller; When the I2C interface module receives the write status packet and the status information of the write status packet is failure, the I2C interface module stops pulling down the I2C clock line level and returns an I2C NAK to the I2C master controller.

5. The remote I2C slave device data writing method according to claim 2, characterized in that: The main controller is an I2C main controller, and the interface module is an I2C interface module; The I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line, the I2C master controller initiates an I2C write operation to send the write command packet to the I2C interface module, and the I2C interface module sends the write command packet to the functional module after receiving the write command packet; The function module returns the write status packet to the I2C interface module, and the I2C interface module returns the status information of the write status packet to the I2C main controller, including: After the I2C interface module receives the write command packet, If the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C The interface module receives the write status packet returned by the functional module to the I2C interface module and the status information of the write status packet is success, and the I2C interface module receives a subsequent I2C write operation initiated by the I2C master controller; If the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module and the status information of the write status packet is failure, the I2C interface module returns an I2C NAK to the I2C master controller; If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module, the I2C interface module returns status information of the write status packet to the I2C master controller.

6. The remote I2C slave device data writing method according to claim 2, characterized in that: The main controller is an SPI main controller, the interface module is an SPI interface module, and the SPI main controller is connected to the SPI interface module via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line; The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier, and the SPI interface module sends the write command packet to the functional module after receiving the write command packet from SPI_MOSI; The function module returns the write status packet to the SPI interface module, and the SPI interface module returns the status information of the write status packet to the SPI master controller, including: After the SPI interface module receives the write status packet, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sends a write feedback packet to the SPI master controller through the SPI_MISO signal line, wherein the write feedback packet starts with a second identifier and includes the status information included in the write status packet.

7. The remote I2C slave device data writing method according to claim 6, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

8. The remote I2C slave device data writing method according to claim 6, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module via the SPI_MOSI signal line. Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets.

9. The remote I2C slave device data writing method according to claim 6, characterized in that: The write feedback packet is divided into a write success feedback packet and a write failure feedback packet; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier; When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

10. The method for writing data from a remote I2C slave device according to claim 2, characterized in that: The functional module comprises a remote I2C address register, and the I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is the remote I2C address stored in the remote I2C address register.

11. The remote I2C slave device data writing method according to claim 2, characterized in that: The write command packet includes a remote I2C address, and the I2C address included in the remote I2C address byte sent by the functional module to the remote I2C slave device is the remote I2C address included in the write command packet.

12. The remote I2C slave device data writing method according to claim 11, characterized in that: The functional module includes a remote I2C address register, and the functional module also includes a remote I2C address selection module. The I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is derived from the remote I2C address stored in the remote I2C address register or from the remote I2C address contained in the write command packet according to the instruction of the remote I2C address selection module.

13. The remote I2C slave device data writing method according to claim 2, characterized in that: The write command packet has multiple write commands, each of which includes a remote I2C address. The remote I2C address included in the remote I2C address byte sent by the functional module to the remote I2C slave device is derived from the remote I2C address included in each write command.

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