Semiconductor arrangement comprising a semiconductor element with at least one connection element

Abstract

A buffer layer on a connection element of a semiconductor element is produced by atmospheric thermal metal spraying and subsequently provided with recesses by structuring and subsequently reducing the oxide portion in large parts of the layer by reduction.

Description

[0001] 202321228 1 Description Semiconductor arrangement comprising a semiconductor element with at least one connection element The invention relates to a semiconductor arrangement comprising a semiconductor element with at least one connection element, wherein at least one metallic contacting element is connected in a planar manner to the at least one connection element of the semiconductor element. Furthermore, the invention relates to a power converter with at least one such semiconductor arrangement. Furthermore, the invention relates to a method for producing a semiconductor arrangement comprising a semiconductor element with at least one connection element, wherein at least one metallic contacting element is connected in a planar manner to the at least one connection element of the power semiconductor. Such semiconductor arrangements are used, for example, in a power converter. A power converter is, for example, a rectifier, an inverter,a converter or a DC-DC converter. A semiconductor element of such a semiconductor arrangement can be designed, among other things, as a transistor, in particular as an insulated-gate bipolar transistor (IGBT), field-effect transistor or bipolar transistor, triac, thyristor, or diode. Aluminum wire bonding technology is typically used to contact connection elements of such semiconductor elements. Particularly in modern packaging and connection technologies, such bonding agents are often the service life-limiting factor. A significantly longer service life, for example, is promised by copper wire bonding technology, particularly due to a higher modulus of elasticity (E-modulus) and higher electrical conductivity. However, this requires higher compressive forces during contacting.which poses the risk of damage to semiconductor elements. The published patent application DE 102009 008 926 A1 relates to a method for creating a high-temperature and thermally shock-resistant connection between a semiconductor assembly and a semiconductor component using a temperature-sensitive process, in which a metal powder suspension is applied to the areas of the individual semiconductor components to be subsequently connected, the suspension layer is dried while outgassing the volatile components and creating a porous layer, the porous layer is pre-compacted without complete sintering penetrating the suspension layer, and for achieving a solid, electrically and thermally highly conductive connection of a semiconductor component to a connection partner from the group: substrate, further semiconductor, or circuit carrier,The connection is a sintered connection produced without pressure by increasing the temperature, consisting of a dried metal powder suspension that has undergone a first transport-resistant contact with the connection partner in a pre-compaction step, and has been solidified under pressure by temperature sintering. The published patent application DE 102015 205 704 A1 describes a contact arrangement of at least one semiconductor component, in particular a power semiconductor component. An electrical connection of the semiconductor component has a metallization made of Al or an Al alloy. Furthermore, the electrical connection is connected to at least one wire or ribbon bond made of Cu or a Cu alloy. A contact element is arranged between the at least one electrical connection and the wire or ribbon bond.which is connected to the electrical connection with a bottom side and to the wire or ribbon bond with a top side. The contact element also has at least two adjacent layers, wherein the bottom side is formed from a layer of Al or an Al alloy, and the contact element comprises at least one further layer of Cu or a Cu alloy, of Ag or an Ag alloy, and / or of Ni or a Ni alloy. Published patent application US 2005 / 230820 A1 describes a power semiconductor device comprising an electrically insulating and thermally conductive substrate provided with a structured metallization on at least one side, a cooling device in thermal contact with the other side of the substrate, and at least one semiconductor component arranged on the substrate and electrically connected to the structured metallization.a fully or partially electrically insulating film with conductive structures, which is arranged at least on the side of the substrate carrying the at least one semiconductor component and which is laminated without cavities onto the substrate, including or exclusively the at least one semiconductor component, and a pressing device that exerts a force on the substrate locally and via the at least one semiconductor component, so that the substrate is pressed against the cooling device. Published patent application EP 2521 166 A1 describes a method for producing a semiconductor component, comprising creating a wafer, applying component structures to the wafer to form a wafer composite, applying a metal layer to the wafer, removing the metal layer in non-contact regions of the components, and applying passivation edges to the edge regions of the components.Applying the wafer to a foil held by a clamping ring, separating the components carried by the foil from one another from the wafer composite, applying a covering mask to the areas of the isolated components carried by the foil that are not to be coated, applying a metal layer to the isolated components masked by the mask, removing the mask and removing the components from the foil, and further processing the isolated components, in which the application of a metal layer to the isolated components masked by the mask is carried out by thermal spraying. The use of such sintered layers has the disadvantage that the different expansion coefficients of the materials, especially during thermal cycles,represent a high load. The result is rapid failure at the interface. The published patent application EP 3926 670 A1 describes a power semiconductor module with at least one power semiconductor element. In order to reduce the required installation space of the power semiconductor module and increase its service life, it is proposed that the at least one power semiconductor element be connected to a cooling element via a dielectric material layer in an electrically insulating and thermally conductive manner, wherein the dielectric material layer lies flatly on a surface of the cooling element and is non-positively connected to the cooling element by means of a first force acting orthogonally to the surface of the cooling element. Against this background, it is an object of the present inventionto increase the service life of a semiconductor device. This object is achieved by a method according to claim 1. A further solution consists in the semiconductor device according to claim 8. atmospheric which corresponds to the thickness of the contacting element reduced by a maximum of 200 µm, in particular reduced by a maximum of 100 µm. The semiconductor device according to the invention comprises a semiconductor element with at least one connection element, wherein a 202321228 5 metallic contacting element is connected flatly to the connection element of the semiconductor element. The metallic contacting element is produced by spraying it onto the semiconductor element using an atmospheric thermal spraying process. The metallic contacting element has punctiform, linear, or flat recesses that extend from the side of the contacting element facing away from the connection element to a depthwhich corresponds to the thickness of the contacting element reduced by a maximum of 200 µm, in particular reduced by a maximum of 100 µm. In other words, the recesses extend so far into the contacting element that a maximum of 200 µm, in particular a maximum of 100 µm, of the thickness remains without recesses. The thickness of the contacting element can therefore also be less, for example only 50 µm. For example, with a 120 µm thick contacting element, the recesses can extend 20 µm deep, or 60 µm deep, or through the entire contacting element. With a 250 µm thick contacting element, the recesses extend at least 50 µm deep into the contacting element, in which case 200 µm of the thickness remains. Preferably, the recesses extend at least 150 µm deep into the contacting element,leaving a maximum of 100 µm of thickness. With this contacting element, too, the recesses can extend further into the contacting element, for example, 200 µm deep (50 µm remaining) or through the entire contacting element. The method and semiconductor arrangement can be advantageously used for the construction of a power converter. The advantages and preferred embodiments listed below with regard to the semiconductor arrangement can be applied analogously to the power converter and the method. 202321228 6 The invention is based on the idea of ​​increasing the service life of a semiconductor arrangement with a semiconductor element by producing a contacting element, for example a metallic layer, by spraying it onto the semiconductor element using a thermal spraying process. A thermal spraying process is a process in which spray additives, for example particles,are projected onto a surface. The spray additives can be in the form of rods, wires, suspensions, or powders, among others. These can be heated to a plastic or molten state. Such thermal spraying processes include atmospheric plasma spraying (APS), flame spraying (FS), high-velocity oxyfuel (HVOF / HVAF), arc wire spraying (LDS), and cold gas spraying (CS). In this way, the metallic contacting element is connected to the at least one connection element of the semiconductor element. Such a connection element can be a contact pad with a chip metallization. Such a contact pad can be provided, among other things, for contacting the semiconductor element, e.g., via bonding agents. The sprayed-on metallic contacting element can form a metallic layer, which, for example, during contacting, in particular during bonding,e.g., by means of ultrasonic bonding or laser welding, occurring compressive forces are distributed, thus preventing cracks in the semiconductor. By reducing crack formation, the service life of the semiconductor device is increased. Due to the thermal spraying process and the resulting structure, the metallic contact element has a higher porosity and a slight spring effect, especially compared to a melt-metallurgically produced or sintered metal plate. The increased porosity compensates for tolerances during pressure bonding. Especially during later operation of the semiconductor element, for example, when switching a power semiconductor on and off, the different expansion coefficients of the semiconductor and the metals used in the metallic contact element can be compensated for by the slight spring effect. The metallic contact element can thus function as a buffer layer.This has a positive effect on the lifetime of the semiconductor device. When using atmospheric thermal metal spraying, the resulting layers are usually very oxide-rich, because the sprayed particles, for example, copper particles, bind a lot of oxygen from the surrounding atmosphere. To improve the quality, it is known to reduce the layers. The reduction can be carried out, for example, using hydrogen (H2) or forming gas at temperatures of at least 200°C. However, if the layer thickness increases above approximately 100 µm, the efficiency of the reduction decreases, since, for example, during reduction with hydrogen, the resulting water molecules can only slowly diffuse out of the contacting element. Thick and simultaneously well-reduced layers are therefore difficult to produce in this way. For the invention, it was recognized thatthat the introduction of a structuring into the contacting element advantageously facilitates diffusion and thus also allows the creation of contacting elements with a thickness of significantly more than 100 µm. The structuring also advantageously brings about thermomechanical relief. The structuring is expediently designed in such a way that it supports the inward and outward diffusion of the reducing gases and the products. For example, punctual recesses can be provided for this purpose, i.e. recesses in the manner of a bore with a diameter of, for example, 10 µm or 50 µm. Linear recesses, i.e., trenches, or flat recesses can also be provided. The recesses can, for example, be present in a grid, i.e., evenly distributed over the contacting element, whereby only a part of the contacting element,expediently, at least 25% of this must be affected. 202321228 8 The contacting element preferably has a thickness of at least 100 µm, in particular a thickness of at least 250 µm. The metallic contacting element preferably comprises particles that form a textured layer. The particles contain, for example, copper and / or molybdenum. Such a textured layer is composed of particles that are at least partially flattened by deformation, thereby balancing compressive forces acting on the layer. If pressure is exerted on the textured layer arranged on the semiconductor element, for example during contacting, in particular during bonding, the resulting compressive forces are leveled and passed on homogeneously to the semiconductor element, which has a positive effect on the service life of the semiconductor arrangement. Also during later operation of the semiconductor arrangement,For example, when switching a power semiconductor on and off, the different expansion coefficients are compensated by the textured layer. A further embodiment provides that a bonding means, in particular a copper bonding means, or a press contact is contacted with the connection element of the semiconductor element via a surface of the metallic contacting element. Such bonding means can be, among other things, bond wires or bonding strips. A press contact can be designed, among other things, as a busbar, which is also called a busbar. Due to the structure of the metallic contacting element produced by the thermal spraying process, forces arising from the pressure connection of the press contact or wire bond are leveled out, so that crack formation is reduced and thus the service life is increased. A further embodiment provides that the press contact is connected via a,in particular, a force acting orthogonally to the surface of the metallic contacting element is in contact with the connecting element. In particular, pressure contacting by means of a busbar is more robust against cyclic stress, for example, compared to a bond connection, which further increases the service life of the semiconductor device. A further embodiment provides that the textured layer comprises, in particular in a flat-shaped manner, deformed first particles and molten second particles, wherein the first particles are at least five times, in particular ten times, larger than the second particles. Due to their volume, the larger first particles assume a large part of the electrical property. The smaller molten second particles, which are also referred to as condensed metal vapor,define the mechanical properties. In particular, the molten second particles can form an intermediate matrix after solidification. Such a textured metallic layer compensates for CTE mismatches, and improved force distribution can be achieved. Furthermore, cracks occurring in such textured metallic layers are not conducted directly into the semiconductor, as is generally known with rigid systems, but remain in the textured metallic layer. Stresses that occur are reduced and / or cracks are eliminated. The latter is achieved by significantly reducing the Young's modulus and the yield strength compared to bulk copper (ETP-Cu). A further embodiment provides for the deformed first particles, particularly in a flat-like configuration, to be bonded to one another via the molten second particles. The smaller molten second particles thus function as an adhesion agent.whereby they define the mechanical properties, in particular a modulus of elasticity, a yield strength, etc. Thus, a spring system is formed in which the smaller molten second particles connect the larger, flat-shaped deformed first particles. As a result, 202321228 10 CTE mismatches can be compensated even better and a further improved force distribution can be achieved. Another embodiment provides that the particles have a size in the range of 1 µm to 100 µm, in particular 5 µm to 25 µm, and / or are sprayed on at a speed of 50 to 800 m / s. These parameters achieve good adhesion without damaging the semiconductor element. Another embodiment provides that the metallic contacting element has a porosity in the range of 1% to 70%, in particular 2% to 50%.Such porosity of the metallic contacting element compensates for tolerances in pressure connections without the layer becoming mechanically unstable. This leads to a reduction in the load on the semiconductor element, which has a positive effect on the service life of the semiconductor device. A further embodiment provides that the metallic contacting element additionally contains particles of a non-metallic inorganic material. Such a non-metallic inorganic material is, for example, a metal oxide such as aluminum oxide, a metal nitride such as aluminum nitride, a semiconductor such as silicon, or a semiconductor oxide such as silicon oxide. By filling the metallic contacting element in this way, the expansion coefficient of the contacting element can be varied, so that the load on the semiconductor element is reduced.which has a positive effect on the service life of the semiconductor device. Compared to an increase in porosity, improved thermal conductivity is achieved. A further embodiment provides that the contacting element has a material gradient. Such a material gradient is an uneven distribution of at least two different materials and / or material or process parameters. For example, the contacting element contains molybdenum and copper, with a molybdenum content increasing toward the semiconductor element, while a copper content increasing away from the semiconductor element, which leads to a, in particular continuous, reduction in the coefficient of expansion of the contacting element toward the semiconductor element. Furthermore, a material gradient can be produced by varying material parameters. The material parameters are determined via process parameters of the thermal spraying process,For example, the particle velocity, the particle size, the temperature, the atmosphere, etc., can be influenced. This leads to different properties depending on the location. For example, the porosity, the degree of melting, the type of particle deformation, particularly depending on the distance from the semiconductor element, can be varied by changing process parameters. Increasing the porosity towards the semiconductor element can relieve the stress on it. A further embodiment provides that the semiconductor element is designed as a vertical semiconductor element, with at least two metallic contact elements arranged on opposite sides of the vertical semiconductor element. A vertical semiconductor element can be, among other things, an IGBT. Such an arrangement can achieve leveling on both sides.which additionally positively influences the service life. In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures. They show: Figure 1 shows a schematic representation of a semiconductor arrangement with a semiconductor element, Figure 2 shows a schematic representation of a thermal spraying process, Figure 3 shows a schematic representation of a typical deformation of a metallic particle upon impact with a surface of a semiconductor element, Figure 4 shows a SEM image of deformed metallic particles in a top view, Figure 5 shows a schematic representation of a meandering spray path geometry, Figure 6 shows an enlarged schematic representation of a semiconductor arrangement with a textured layer, Figure 7 shows a SEM image of a textured layer in a side view,Figure 8 is a schematic representation of a force introduction into a semiconductor element via a standard copper layer, Figure 9 is a schematic representation of a force introduction into a semiconductor element via a textured layer, Figure 10 is a schematic representation of a semiconductor arrangement with a bonding agent, Figure 11 is a schematic representation of a semiconductor arrangement with a press contact, Figure 12 is a schematic representation of a semiconductor arrangement with contact elements arranged on both sides of the semiconductor element, Figure 13 is a schematic representation of a power converter, 202321228 13 Figure 14 is a side view of a structured contacting element, Figure 15 is a top view of a structured contacting element with point-shaped cutouts, Figure 16 is a top view of a structured contacting element with linear cutouts,Figure 17 shows a section of the contacting element in side view. The exemplary embodiments explained below are preferred embodiments of the invention. In the exemplary embodiments, the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another.which each further develop the invention independently of one another and are thus to be regarded as part of the invention, either individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by further features of the invention already described. The same reference numerals have the same meaning in the various figures. Figure 1 shows a schematic representation of a semiconductor arrangement 2 with a semiconductor element 4. The semiconductor element 4 is embodied, for example, as an insulated-gate bipolar transistor (IGBT). Further examples of such semiconductor elements 4 are other transistor types such as field-effect transistors and bipolar transistors as well as triacs, thyristors, and diodes. The semiconductor element 4 can be formed using silicon or a semiconductor with a wide band gap, e.g., silicon carbide (SiC) or gallium nitride (GaN).be formed as a semiconductor substrate. The IGBT comprises connection elements 6, which are designed as a gate connection G, a collector connection C, and an emitter connection E. The connection elements 6 each comprise a contact pad with a chip metallization, which contains, for example, AlSiCu. The contact pads are provided for contacting the semiconductor element 4, inter alia, via bonding means. By way of example, the gate connection G and the emitter connection E are contacted on a substrate 8, which can be designed, inter alia, as a DCB substrate. For example, the gate connection G and the emitter connection E are connected, in particular, via a solder connection and / or a sintered connection.materially connected to a structured metallization of the substrate 8. Alternatively, the connection to the structured metallization of the substrate 8 is made on the collector side. On a side facing away from the substrate 8, a metallic contacting element 10 is connected flat to the collector terminal C of the semiconductor element 4. The metallic contacting element 10 is produced by a thermal spraying process, wherein particles P1, P2, which contain, for example, copper and / or molybdenum, are sprayed onto the semiconductor element 4. The particles P1, P2 form a textured metallic layer 12 which, for example, has a thickness in the range of 1 µm to 250 µm, in particular 5 µm to 100 µm. A section of the textured metallic layer 12 is shown in Figure 1 as an SEM image at various magnifications. The SEM image was pulled apart,to better illustrate their properties. As an example, Figure 1 shows a textured copper or molybdenum layer. Such a textured layer 12 is composed of particles P1, P2, which are at least partially deformed in a flat shape. For example, the textured layer 12 comprises flat-shaped deformed first particles P1 and molten second particles P2, wherein the first particles P1 are at least five times, in particular ten times, larger than the second particles P2. Due to their volume, the larger first particles P1 assume a large part of the electrical properties. The smaller molten second particles P2, which are also referred to as condensed metal vapor, act as an adhesion agent and thus define the mechanical properties, in particular an E-modulus, a yield strength, etc. Thus, a spring system is formed.in which the smaller molten second particles P2 connect the larger, flat-shaped deformed first particles P1. Such a textured metallic layer 12 compensates for CTE mismatches and achieves improved force distribution. Furthermore, cracks occurring due to such textured metallic layers 12 are not conducted directly into the semiconductor, as is generally known in rigid systems, but remain in the textured metallic layer 12. Occurring stresses are reduced and / or cracks are allowed to disappear. The latter can be achieved by significantly reducing the Young's modulus and the yield strength compared to bulk copper (ETP-Cu). This can be achieved with a higher O2 content, particularly in a textured copper or molybdenum layer. Compressive forces are compensated by such textured layers 12. If, for example, during contacting, especially during bonding,If pressure is exerted, any compressive forces that occur are leveled by the textured layers 12 and passed on homogeneously to the semiconductor element 4. Even during later operation of the semiconductor element 4, for example when switching a power semiconductor on and off, the different expansion coefficients of the semiconductor (Si, GaN, SiC 3-7 ppm) and the metals (copper 17-18 ppm, aluminum 24 ppm) are largely compensated by their spring effect. The metallic contact element 10 thus functions as a buffer layer. As is generally known from the literature, copper only tends to diffusion and grain boundary growth at higher temperatures (>250°C), whereby the described spring effect persists for a longer time and the property of the textured layer 12 can be utilized for a long time during the product's life. 202321228 16 Figure 2 shows a schematic representation of a thermal spraying process, whereby by spraying particles P1,P2, a textured layer 12 of a metallic contacting element 10 is formed on a semiconductor element 4. A thermal spraying process is a process in which spray additives, for example particles, are projected onto a surface. The spray additives can be heated to a plastic or molten state. Such thermal spraying processes include atmospheric plasma spraying (APS), flame spraying (FS), high-velocity oxyfuel (HVOF / HVAF), arc wire spraying (LDS), and cold gas spraying (CS). As shown in Figure 2, the impacting particles P1, P2, for example copper particles and / or molybdenum particles, form a layer on the surface of the semiconductor element 4, which, as described in Figure 1, comprises so-called "splats," i.e., first particles P1 that are flattened upon impact, in particular in a patty-like shape. To apply the particles P1,P2 uses a thermal and / or kinetic energy source 14, which can be a plasma, a combustion flame, an arc, a laser, an explosion, or a heated gas. The spray additives can be in the form of a rod, wire, suspension, or powder, among other things. Figure 3 shows a schematic representation of a typical deformation of a metallic particle P1 upon impact with a surface 16 of a semiconductor element 4. The particle P1 is severely deformed by its speed, which is, for example, in the range of 50 m / s to 800 m / s, and its softened state, whereby a flat-cake shape is achieved. This effect is called the splattering effect and, by wetting a large surface, leads to high adhesion. Figure 4 shows an SEM image of deformed metallic particles P1 in a top view. A textured layer 12 is formed by the flat-shaped metallic particles P1,which has the properties described in Figure 1. Figure 5 shows a schematic representation of a meandering spray path geometry 18 during the application of the particles P1, P2 to the semiconductor element 4. The sample, e.g., the semiconductor device 2, is typically moved by robotics beneath a plasma jet. During the meandering spraying process, a layer overlap occurs in particular, with several coating transitions being carried out, so that highly textured layer properties are achieved. Figure 6 shows an enlarged schematic representation of a semiconductor device 2 with a textured layer 12, which forms the contacting element 10 connected to the connection element 6 of the semiconductor element 4. The textured layer 12 can contain, among other things, copper and / or molybdenum particles and comprises flat-shaped deformed first particles P1 and molten second particles P2.which are also referred to as condensed metal vapor. As described in Figure 1, the larger first particles P1 assume a large part of the electrical properties due to their volume, while the smaller molten second particles P2, which are also referred to as condensed metal vapor, act as an adhesion agent. The further design of the semiconductor arrangement 2 in Figure 6 corresponds to that in Figure 1. Figure 7 shows an SEM image of a textured layer 12 in a side view. The textured layer structure leads to cracks 20 that arise, which can arise, among other things, due to pressure or thermal stress, being predominantly guided in the horizontal direction. This considerably relieves the load on the semiconductor element 4 located underneath. In particular, IGBTs and other silicon-based semiconductor elements 4 react due to their typical silicon orientation, e.g., 100.is very sensitive to vertically initiated cracks 20, which can easily propagate in the silicon of the IGBT. The further design of the textured layer 12 in Figure 7 corresponds to that in Figure 6. Figure 8 shows a schematic representation of a force introduction Fi into a semiconductor element 4 via a standard copper layer 22 under the influence of a force F acting, for example, perpendicularly to the surface 16. The force F is introduced almost vertically into the semiconductor substrate 24, e.g., silicon, of the semiconductor element 4. Figure 9 shows a schematic representation of a force introduction Fi into a semiconductor element 4 via a textured layer 12. The vertically acting force F is dissipated essentially horizontally. This results in the force F being distributed or the pressure being homogenized by the essentially horizontal force introduction Fi.i.e., the pressure is distributed over a larger area and the risk of pressure peaks is minimized. The particles P1, P2 can rearrange themselves, which additionally relieves the load on the semiconductor element 4, in particular the semiconductor substrate 24. Figure 10 shows a schematic representation of a semiconductor arrangement 2 with a bonding agent 26, which is designed, for example, as a bonding wire or bonding tape. The textured layer structure results in a force occurring during the bonding process being dissipated essentially horizontally. Furthermore, the textured layer 12 of the contacting element 10 has a material gradient, i.e., an uneven distribution of at least two different materials and / or material or process parameters. For example, the textured layer 12 contains molybdenum (Mo) and copper (Cu), with the proportion of molybdenum increasing toward the semiconductor element 4.while a copper portion increases away from the semiconductor element 4. This leads to a, in particular stepless, reduction in the coefficient of expansion of the contacting element 10 towards the semiconductor element 4. Furthermore, a material gradient can be produced by varying material parameters. The material parameters can be influenced via process parameters of the thermal spraying process, for example the particle velocity, the particle size, the temperature, the atmosphere, etc. This leads to location-dependent different properties. For example, the porosity, the degree of melting, the type of particle deformation, in particular depending on the distance from the semiconductor element 4, can be varied by changing process parameters. In particular, over several, in particular at least partially superimposed,Spray paths with different process parameters allow such properties to be varied depending on the location. The further embodiment of the semiconductor arrangement 2 in Figure 10 corresponds to that in Figure 1. Figure 11 shows a schematic representation of a semiconductor arrangement 2 with a press contact 28. Such a press contact 28 can be, among other things, a busbar. The press contact 28 is contacted with the connection element 10 by means of a force F acting orthogonally to the surface 16 of the metallic contacting element 10. The textured layer structure of the metallic contacting element 10 means that the vertically acting force F is diverted essentially horizontally. The further embodiment of the semiconductor arrangement 2 in Figure 11 corresponds to that in Figure 10. Figure 12 shows a schematic representation of a semiconductor arrangement 2 with metallic contacting elements 10 arranged on both sides of the semiconductor element 4,which each have a textured layer 12 and are integrally connected to the connection elements 6 of the semiconductor element 4 via the thermal spraying process. On the collector side, the semiconductor element 4 is connected via the metallic contacting elements 10 to a metallization 29, which is connected via a dielectric material layer 30 in an electrically insulating and thermally conductive manner to a cooling element 32, which is designed, for example, as a heat sink. The gate G can be connected, inter alia, via a bond connection, e.g., to a driver circuit. The dielectric material layer 30 comprises a ceramic material, for example, aluminum nitride or aluminum oxide, or an organic material, for example, a polyamide.and rests flat on the cooling element 32. In particular, the semiconductor element 4 rests floatingly on the dielectric material layer 30 via the metallic contact element 10, with a force-fitting connection being established by the press contact 28. Via the contact element 10 connected to the semiconductor element 4 on the collector side, forces are distributed to the metallization 29, the dielectric material layer 30, and the cooling element 32, so that good leveling also takes place here. Figure 13 shows a schematic representation of a power converter 34, which comprises, by way of example, a semiconductor arrangement 2. Not shown in the preceding figures,However, a structuring of the contacting elements 10 is nevertheless present. Several structuring options are illustrated by way of example in Figures 14 to 16. Figure 14 shows a side view of one of the structuring options. The illustration is not to scale. The structuring consists of a plurality of recesses 51. The recesses 51 extend vertically through the contacting element 10, starting from the side of the contacting element 10 facing away from the semiconductor element 4. The recesses 51 have a height h that corresponds to 75% of the thickness of the contacting element 10, in other words, they penetrate 3 / 4 of the contacting element 10. The thickness of the contacting element 10 in this example is 600 µm.the height h of the recesses is therefore 450 µm. 202321228 21 Figure 15 shows a plan view of the contacting element 10 with the recesses 51. In this example, the recesses 51 are punctiform, ie they correspond to the type of bores with the smallest possible diameter, which is ideally less than 100 µm, in particular less than 50 µm. The horizontal spacing of the recesses in this example is 200 µm. The recesses can, for example, be arranged in a square or hexagonal grid. Such a shape of recesses 51 can be achieved, for example, by means of punctiform irradiation with picosecond lasers. A corresponding emitter 59 is shown in Figure 14. During such irradiation, very high power levels are applied for a short time, and the irradiated material does not melt but sublimates. This allows for recesses with a very high aspect ratio,i.e., a large ratio of height h to diameter 55 can be produced. The recesses 51 ensure that the distance from any point in a large part of the contacting element 10 to a nearest surface, i.e., to the surrounding air, is no more than approximately 100 µm, whereas without the recesses 51, this distance would be up to 600 µm. This makes it possible to perform a reduction after production, even with a 600 µm thick contacting element 10, in which the majority of the contacting element 10 is also successfully reduced. The reduction is carried out with a reducing gas (for example, hydrogen or forming gas) at elevated temperature.However, due to the long diffusion paths for the out-diffused water molecules or other molecules, this is only successful within a reasonable timeframe to a depth of roughly 100 µm. The reduction reduces the contact element 10, which is very oxygen-containing after production by the thermal spraying process.i.e., metal oxide is converted to metal, thus increasing the metal content. This increases the quality of the contacting element 10. With the recesses 51, a high-quality contacting element 10 can be produced even with a thickness of significantly more than 100 µm. In addition to production by laser structuring, the recesses 51 can also be produced, for example, using a photolithographic process or by means of a sawing process. Depending on the capabilities of the structuring process or the desired design, the recesses 51 can also be linear or flat. Figure 16 shows a plan view of a contacting element 10 with linear recesses 57. A design with flat recesses refers to such a design,in which the horizontal extent of the cutouts is not the minimum extent specified by the structuring process. For example, rectangular or round cutouts can be created. Overall, the designs of the cutouts 51, 57 have in common that they are designed such that in the largest part of the contacting element 10, for example in at least 75%, in particular at least 90% of the contacting element 10, the distance to the nearest surface is not greater than 150 µm, in particular not greater than 100 µm. Fig. 17 shows a section of the contacting element 10 for clarification. The cutouts 51, 57 have a center-to-center distance R, which is, for example, 200 µm. The diameter or width of the cutouts 51, 57 is 50 µm here. As a result, the remaining area of ​​the contacting element 10 between the recesses 51,57150 µm wide. As a result, the distance from any point on the contacting element 10 to the depth into which the recesses 51, 57 extend is no greater than 75 µm. Even in the lower part of the contacting element 10, into which the recesses 51, 57 do not extend, the distance is no greater than approximately 100 µm. 202321228 23 This enables an efficient reduction of the contacting element 10 and thus the creation of a high-quality contacting element 10 with a thickness of significantly more than 100 µm, in particular at least 300 µm or at least 500 µm or at least 1 mm.

[0002] 202321228 24 Reference numeral 2 Semiconductor arrangement 4 Semiconductor element 6 Connection element 8 Substrate 10 Contacting element 12 Textured layer 14 Energy source 16 Surface 18 Spray path geometry 20 Cracks 22 Standard copper layer 24 Semiconductor substrate 26 Bonding agent 28 Press contact 29 Metallization 30 Dielectric material layer 32 Cooling element 34 Power converter 51 Recess h Height 55 Diameter 57 Linear recesses 59 Laser emitter F Force P1, P2 Particles C Collector connection E Emitter connection G Gate connection

Claims

202321228 25 claims 1. Method for producing a semiconductor arrangement (2) comprising a semiconductor element (4) with at least one connection element (6), wherein - at least one contacting element (10) is connected in a planar manner to the at least one connection element (6) of the semiconductor element (4), - the at least one contacting element (10) is produced by spraying onto the semiconductor element (4) by means of an atmospheric thermal spraying process, characterized in that - after spraying, a structuring of the contacting element (10) is carried out, in which recesses (51, 57) are created, - the recesses (51, 57) in a plan view of the contacting element (10) are punctiform or extend linearly or planarly, - the recesses (51, 57) extend from the side of the contacting element (10) facing away from the connection element (6) to a depth extend,which corresponds to the thickness of the contacting element (10) reduced by a maximum of 200 µm, in particular reduced by a maximum of 100 µm.

2. The method according to claim 1, wherein the recesses (51, 57) are created such that the distance between the nearest recesses (51, 57) is not more than 500 µm, in particular not more than 200 µm, in particular not more than 100 µm.

3. The method according to claim 1 or 2, wherein the recesses (51, 57) are created by laser structuring, in particular by picosecond or femtosecond lasers.

4. The method according to claim 1 or 2, wherein the recesses (51, 57) are created by sawing technology or photolithography. 202321228 26 5. The method according to one of the preceding claims, wherein a reduction of the contacting element 10 is carried out after structuring.

6. The method according to claim 5, wherein the reduction is carried out by exposing the contacting element 10 to a reducing gas, in particular hydrogen or forming gas, at a temperature of at least 200°C.

7. The method according to one of the preceding claims, wherein a bonding agent (26) or a press contact (28) is contacted with the connection element (6) of the semiconductor element (4) via a surface (16) of the metallic contacting element (10).

8. The method according to one of the preceding claims, wherein the press contact (28) is contacted with the connection element (6) via a force (F), in particular acting orthogonally to the surface (16) of the metallic contacting element (10). 9.Method according to one of the preceding claims, in which sprayed-on particles have a size of 1 µm to 100 µm, in particular 5 µm to 25 µm, and / or are sprayed on at a speed of 50 to 800 m / s.

10. Semiconductor arrangement (2) comprising a semiconductor element (4) with at least one connection element (6), wherein - a contacting element (10) is connected flat to the at least one connection element (6) of the semiconductor element (4), - the contacting element (10) is produced by spraying onto the semiconductor element (4) by means of an atmospheric thermal spraying process, characterized in that the metallic contacting element (10) has punctiform, linear or flat recesses (51, 57) which. 202321228 27 extend from the side of the contacting element (10) facing away from the connection element to a depth which corresponds to the thickness of the contacting element (10) reduced by at most 200 µm, in particular reduced by at most 100 µm.

11. Semiconductor arrangement (2) according to claim 10, wherein a bonding means (26), in particular copper bonding means, or a press contact (28) is contacted with the connection element (6) of the semiconductor element (4) via a surface (16) of the contacting element (10).

12. Semiconductor arrangement (2) according to claim 11, wherein the press contact (28) is contacted with the connection element (6) via a force (F), in particular acting orthogonally to the surface (16) of the contacting element (10).

13. Semiconductor arrangement (2) according to one of claims 10 to 12, wherein the contacting element (10) has a porosity in the range of 1% to 70%, in particular 2% to 50%. 14.Semiconductor arrangement (2) according to one of claims 10 to 13, wherein the contacting element (10) additionally contains particles of a non-metallic inorganic material.

15. Power converter (34) with at least one semiconductor arrangement (2) according to one of claims 10 to 14.

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