An electronic filter for band stop or band pass filtering

Abstract

An electronic filter (200a) for band stop or band pass filtering of an electrical input signal. The electronic filter (200a) comprises a memristive low-pass filter (210) comprising a first crossbar array of memristors (211, 212). Each memristor (211, 212) of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix. The electronic filter (200a) further comprises a memristive high-pass filter (220) comprising a second crossbar array of memristors (221, 222). Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

Description

[0001] AN ELECTRONIC FILTER FOR BAND STOP OR BAND PASS FILTERING

[0002] TECHNICAL FIELD

[0003] The embodiments herein relate to an electronic filter and a method for band stop or band pass filtering electrical signals. A corresponding computer program and a computer program carrier are also disclosed.

[0004] BACKGROUND

[0005] Filters are critical components in many signal processing applications. Filters have many use cases such as image, video, and speech processing, biomedical signal processing algorithms, machine learning applications, and wireless communication systems.

[0006] An important type of filter is a band stop filter, known also as notch filter or band rejection filter. This filter passes most frequencies unalerted, but it attenuates the frequencies within a specific range to a very low level, i.e. , discarding the pre-determined frequencies in a certain range.

[0007] Another important type of filter is a band-pass filter which allows through components in a specified band of frequencies, called its passband but blocks components with frequencies above or below this band.

[0008] The applications of the band-stop and band-pass filters include the following:

[0009] • In wireless communication systems, the band-stop filters are used to reduce distortion in the signals, to reduce unwanted harmonics and errors, and to prevent interference between different frequency bands. For example, a band stop filter may be used to prevent the phone's transmission signal from interfering with the reception of other signals on nearby frequency bands. Similarly, the band-pass filters are used to pass the desired frequency range.

[0010] • In biomedical instruments, the band-stop filter is used for the removal of noise. For example, in electrocardiogram (ECG) machines, band stop filters are used to remove the 50 or 60 Hz interference caused by the electrical power supply. In the image and signal processing applications, a band-stop filter is widely used to either reject the noise or reduce the noise effect.

[0011] • In optical communications, the band-stop filters are used to eliminate the distortion due to the interference of frequency signals. Also, they are used for filtering selected wavelengths from a source or to a detector.

[0012] • In telephone technology, a band-stop filter is used to reduce line noise which provides Digital Subscriber Line (DSL) internet services.

[0013] • In radar systems, band-stop filters are used to eliminate unwanted interference from other radar systems or other sources of electromagnetic radiation, which may result in false readings or reduce the accuracy of the radar system.

[0014] • In power electronics, band-stop filters are used to reduce the electromagnetic interference (EMI) generated by switching of power devices. This interference may lead to several problems in other electronic systems, including audio and video equipment, computers, and communication systems.

[0015] • The band-stop filter is used to filter out the mains hum from the power line. For example, for the countries where power transmission is at 60 Hz, the filter would have a 59-61 Hz range. Also, they are widely used in the electric guitar amplifiers, which produce a ‘hum’ at 60 Hz frequency.

[0016] • A band-stop filter is used as a “wave trap” to remove a specific interfering frequency resulted form a nearby wireless transmitter. This is needed when radio receivers are very close to a radio transmitter.

[0017] • To measure the non-linearities of power amplifiers, a very narrow notch filter is used to ensure that the maximum input power of a spectrum analyser used to detect spurious content will not be exceeded.

[0018] In many applications, high performance band-stop and band-pass filters are needed, which generally require a large number of filter taps (coefficient and delay pair). This increases the hardware complexity of such filters significantly. Moreover, as the filter order increases, a longest computational path of the circuit, also referred to as a critical path, will be increased as well. Thus, latency and throughput of the filter will be constrained, which leads to some challenges in high-throughput and low-latency applications. As a result, design of a high throughput and low power filter is a challenging task, especially for a large number of filter taps.

[0019] These filters are typically implemented as digital filters. A typical way to realize a digital filter is to implement it using a Digital Signaling Processor (DSP). DSPs are generally optimized to perform fast multiply-accumulates. In such cases, in order to maintain real-time operation, the DSP processor must be able to execute all the steps in the filter routine within one sampling clock period. A fast general purpose fixed-point DSP such as the ADSP-2189M at 75MIPS can execute a complete filter tap multiply- accumulate instruction in 13.3 ns. Thus, for a 100-tap filter, the total execution time is approximately 1.4 ps, which corresponds to a maximum possible sampling frequency of 714 kHz. This highly limits the upper signal bandwidth to a few hundred kHz.

[0020] In order to address this challenge, it is possible to design a special hardware to realize the desired digital filter and increase the sampling rates. However, such cases suffer from inflexibility in terms of filter order as well as the need for extra memory to design high-order filters.

[0021] Moreover, another challenge in the traditional approach of band-stop and band-pass filter design is that high-order filters, which are designed to improve the performance, suffer from computational complexity.

[0022] SUMMARY

[0023] Embodiments herein disclose an electronic filter and a method for band stop or band pass filtering electrical signals.

[0024] Specifically, embodiments herein disclose a memristive-based electronic filter for band stop or band pass filtering and a method for filtering electrical signals with the memristive-based electronic filter. The disclosed memristive-based electronic filter uses Processing In Memory (PIM) techniques. All functional blocks within the memristive-based electronic filter may be realized using analog crossbar arrays. However, in some embodiments a mixture of analog crossbar arrays and circuits without memristors, such as digital circuits, may be used to implement different functions of the memristive-based electronic filter.

[0025] An analog crossbar array, such as a 2-dimensional array, consists of M*N memristive devices, each of which can be programmed to represent an m-bit binary value. According to a first aspect, the object is achieved by an electronic filter for band stop or band pass filtering of an electrical input signal. The electronic filter comprises a memristive low-pass filter comprising a first crossbar array of memristors, wherein each memristor of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix.

[0026] The electronic filter further comprises a memristive high-pass filter comprising a second crossbar array of memristors. Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

[0027] According to a second aspect, the object is achieved by a method for band stop or band pass filtering of electrical signals. The method comprises filtering an electrical input signal with: a memristive low-pass filter comprising a first crossbar array of memristors. Each memristor of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix; and a memristive high-pass filter comprising a second crossbar array of memristors. Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

[0028] According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor, causes the processor to perform actions according to any of the aspects above.

[0029] According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0030] The memristive-based electronic filter is a fully parallel architecture, which may achieve an ultra-high throughput without the need for additional intermediate registers or buffers to increase the speed. Since the electronic filter comprises the memristive low- pass filter and the memristive high-pass filter the electronic filter is able to fully process the electronic signal in parallel. The crossbar arrays according to embodiments herein enable performing massive multiply-accumulate (MAC) operations in parallel. More specifically, the crossbar arrays may compute matrix-vector multiplication (MVM) by calculating a dot-product of the input vector applied to crossbar rows (i.e. , word lines) and every column of the crossbar (i.e., bit lines). This reduces the latency and increases throughput.

[0031] Filter coefficients may be updated by re-programming the memristive devices of the memristive-based electronic filter.

[0032] Since the electronic filter comprises the memristive low-pass filter and the memristive high-pass filter there is no need for analog-to-digital nor digital-to-analog conversion between the low-pass filter and the high-pass filter.

[0033] Since the electronic filter comprises the memristive low-pass filter and the memristive high-pass filter and since the memristive devices consume much less power compared to traditional multiply accumulate (MAC) modules, such as digital MAC modules, the proposed PIM-based filter has the potential of low power / energy consumption, which is a critical demand in many use cases (e.g., loT devices). The lower power consumption may in turn lead to increased battery life for battery-powered devices such as mobile phones.

[0034] The latency of the memristive-based electronic filter is only limited by the read cycle of the crossbar arrays of the memristive low-pass filter and the memristive high-pass filter, and it is not limited by the filter order, type, etc.

[0035] The memristive-based electronic filter is computationally efficient since the computational complexity of the filter is reduced from O(N) to 0(1), where N is the number of filter taps. This results in a significant reduction in hardware complexity of the filter.

[0036] The memristive-based electronic filter is fully flexible in terms of order of the filter as well as the filter coefficients.

[0037] The memristive-based electronic filter supports processing of complex-valued input samples as well as complex-valued filter coefficients without any degradation in the throughput and performance of the filter.

[0038] The memristive-based electronic filter enables realization of large filter banks, which include multiple filters with different filter orders and filtering characteristics.

[0039] The memristive-based electronic filter enables realization of an arbitrary frequency response. As a result, all above-mentioned advantages may be achieved regardless of the impulse response of the filter.

[0040] BRIEF DESCRIPTION OF THE DRAWINGS In the figures, features that appear in some embodiments are indicated by dashed lines.

[0041] The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

[0042] Figure 1 is a block diagram schematically illustrating a crossbar array of memristors,

[0043] Figure 2a is a block diagram schematically illustrating a memristive-based band stop filter according to embodiments herein,

[0044] Figure 2b is a block diagram schematically illustrating a further memristive-based band stop filter according to some further embodiments herein,

[0045] Figure 3a is a block diagram schematically illustrating a memristive-based band pass filter according to embodiments herein,

[0046] Figure 3b is a block diagram schematically illustrating a further memristive-based band pass filter according to some further embodiments herein,

[0047] Figure 3c is a block diagram schematically illustrating a further memristive-based band pass filter according to some further embodiments herein,

[0048] Figure 4 is a flowchart illustrating embodiments of a method for filtering an electrical signal with a memristive-based filter,

[0049] Figure 5 is a further flowchart illustrating embodiments of a method for filtering an electrical signal with a memristive-based filter,

[0050] Figure 6 is a further block diagram schematically illustrating a memristive-based filter bank according to embodiments herein,

[0051] Figure 7a is a block diagram schematically illustrating a further memristive-based band stop filter according to some further embodiments herein,

[0052] Figure 7b is a block diagram schematically illustrating a further memristive-based band pass filter according to some further embodiments herein,

[0053] Figure 8a is a block diagram schematically illustrating a further memristive-based filter according to embodiments herein,

[0054] Figure 8b is a block diagram schematically illustrating a further memristive-based filter according to embodiments herein,

[0055] Figure 9 is a block diagram schematically illustrating a further memristive-based filter according to embodiments herein,

[0056] Figure 10 is a block diagram schematically illustrating a further memristive-based filter according to embodiments herein, Figure 11 is a block diagram schematically illustrating a baseband processor in which embodiments herein may be implemented,

[0057] Figure 12 is a block diagram schematically illustrating a network node.

[0058] Figure 13 is a block diagram schematically illustrating a wireless communications device.

[0059] Figure 14 is a block diagram schematically illustrating a wireless communication system.

[0060] DETAILED DESCRIPTION

[0061] Embodiments herein relate to electronic band stop and band pass filters. Filters are widely used in many applications as listed above.

[0062] Unlike many analog filters, filter characteristics of digital filters may easily be changed by varying the filter coefficients. This makes digital filters attractive in filtering applications. An important part of digital filter design is the appropriate selection of the filter coefficients as well as specifying the number of taps to realize the desired frequency response (i.e., transfer function).

[0063] However, digital filters may not be computationally efficient since the computational complexity of the filter circuit may be high. Furthermore, latency and power consumption may be high.

[0064] More specifically, embodiments herein relate to memristive-based electronic filters, i.e. to electronic filters implemented with crossbar arrays of memristors. A memristor may also be referred to as a memristive device. Analog memristive devices have emerged as a new technology for storing and processing information in analog domain. These devices make it possible to perform computations in a place where data is stored. This concept is called in-memory computing (or processing in memory), which eliminates the need for moving data from a memory to a processing unit. There are different types of memristive devices, which are differentiated with respect to the used materials, switching principles, device endurance, retention, etc. The main types of memristive devices include phase change memory (PCM), resistive random-access memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric memristive devices (FeRAM). Memristive devices may support a limited bit precision, attributed to the limited number of conductance levels that may be reliably programmed in the device. For example, a PCM device may support around 50 conductance levels, meaning that it may represent around 6 bits. A number of memristor devices may be organized to form an analog crossbar array. Figure 1 illustrates an electronic device 301, such as a baseband signal processor, comprising a memristor crossbar array 310 which computes MVM by calculating a dotproduct of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines). The memristor crossbar array 310 is a two-dimensional array that comprises an MxN array of memristors 311, 312, 321, 322, each of which may be programmed to represent an m-bit binary value. A memristor is a tunable and programmable. The memristor may comprise a dielectric layer sandwiched by two electrodes. A unique feature of memristors is that the conductance depends on historical electrical signals, making them capable of working as nonvolatile memory. In addition, memristors may store multibit information with continuously tunable conductance, in contrast to binary states “0” and “1” in traditional digital storage systems, equipping them with higher bit density. Thus, the m-bit binary value of the memristor may be set or programmed by applying a current to the memristor. The binary value may depend on the amplitude of the current. Thus, an M x M matrix of binary words, G, may be represented by the memristor crossbar array 310 comprising M x M memristors. The input to the memristor crossbar array 310 is an electronic input signal of multiple samples, such as a vector of M analog voltages, e.g., V, which correspond to M binary values.

[0065] Analog crossbar arrays comprise parallel conductors, such as metal lines, termed word lines and bit lines, respectively, as electrodes of the memristors. The word lines and bit lines may be perpendicular to each other. The memristors are formed at the intersections of word and bit lines. In embodiments herein input conductors 331 of the analog crossbar array 310 corresponds to the word lines and output conductors 332 of the analog crossbar array 310 corresponds to the bit lines.

[0066] The analog crossbar array 310 computes MVM by calculating the dot-product of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines), all performed in analog domain using Ohm’s law for multiplication and Kirchhoff’s law for accumulation.

[0067] In Figure 1 the entries of a matrix G (an MxM matrix) are programmed to the memristive devices 311, 312, 321, 322 of the MxM crossbar array 310 while the input vector V (an Mxl vector) is applied to the crossbar rows. Note that, the vector V corresponds to the actual input vector (Input 1, ... , Input M), which may be converted to analog voltages using one or more Digital to Analog Converter (DAC) modules 304 illustrated in Figure 1. As a result, the following MVM may be realized using the illustrated crossbar array 310, where an output vector I is the output current of crossbar columns, which is equal to the result of matrix-vector multiplication, i.e., I = G- V. The output vector I may be converted to the corresponding binary words using one or more Analog to Digital Converter (ADC) modules 305 as shown in Figure 1. This conversion may be done either separately for each crossbar column (i.e. , one ADC for each binary word) or in a time-multiplexed fashion and hence reduce ADC overhead (i.e., multiple bit lines may share one ADC 305).

[0068] In this disclosure vectors and matrices are represented using capital boldface letters while their entries are shown using normal letters.

[0069] Thus, when the electronic input signal is digital then the electronic device 301 further comprises the one or more DACs 304 adapted to convert the input signal of multiple samples to corresponding analog voltages Vi, V2, ... VN.

[0070] In other words, when the input signal of the multiple samples is digital, the electronic device 301 may further comprise the DACs 304 configured to convert the digital input signal of the multiple samples to the analog voltages.

[0071] There may be one DAC 304 per input sample. In some other embodiments there may be less than one DAC 304 per input sample as one DAC 304 may be shared among several input samples by multiplexing. For example, two input samples may share the same DAC 304.

[0072] Output signals will be extracted from the bit lines (columns in Figure 1) of the crossbar array 310. If digital output values of the crossbar array 310 are needed then the outputs of the crossbar array 310 may be converted to digital values. Thus, the electronic device 301 may further comprise the one or more ADCs 305 adapted to convert the output samples, comprising analog output current, to corresponding digital output values. In other words, the electronic device 301 may further comprise ADCs 305 configured to convert the output from the respective output conductor to a digital signal.

[0073] If analog signals are needed in a next block in the processing chain, then the ADCs 305 in the electronic device 301 may not be needed.

[0074] Further, if the analog outputs are sent to another crossbar array, then they may be converted to voltage signals, which may be done by a resistor.

[0075] Embodiments herein relate to electronic filters for band stop or band pass filtering of an electrical input signal. Embodiments of an electronic filter 200a for band stop filtering of an electrical input signal will be presented in relation to Figure 2a and Figure 2b. Embodiments of an electronic filter 200b for band pass filtering of an electrical input signal will be presented in relation to Figure 3a, 3b, and 3c. The electronic filter 200a, 200b may comprise an electrical input port 200-in for receiving the input signal.

[0076] For both band stop and band pass filtering the electronic filter 200a, 200b comprises a memristive low-pass filter 210 comprising a first crossbar array of memristors 211, 212. Each memristor 211 , 212 of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix.

[0077] The electronic filter 200a, 200b further comprises a memristive high-pass filter 220 comprising a second crossbar array of memristors 221, 222. Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

[0078] Each of the memristive low-pass filter 210 and the memristive high-pass filter 220 may be a Finite Impulse Response (FIR) filter. In other embodiments the memristive low- pass filter 210 and the memristive high-pass filter 220 may each be an Infinite Impulse Response (HR) filter. The embodiments below will be exemplified with FIR filters.

[0079] Since the electronic filter 200a, 200b comprises the memristive low-pass filter 210 and the memristive high-pass filter 220 the electronic filter 200a, 200b is able to fully process the electronic signal in parallel. The crossbar arrays according to embodiments herein enable performing massive MAC operations in parallel. This reduces the latency and increases throughput.

[0080] Filter coefficients may be updated by re-programming the memristive devices of the memristive-based electronic filter 200a, 200b.

[0081] Since the electronic filter 200a, 200b comprises the memristive low-pass filter 210 and the memristive high-pass filter 220 there is no need for analog-to-digital nor digital- to-analog conversion between the low-pass filter 210 and the high-pass filter 220. Further, memristive devices consume much less power compared to traditional MAC modules.

[0082] The latency of the memristive-based electronic filter is only limited by the read cycle of the crossbar arrays of the memristive low-pass filter 210 and the memristive high-pass filter 220, and it is not limited by the filter order, type, etc.

[0083] The memristive-based electronic filter 200a, 200b is computationally efficient since the computational complexity of the filter is reduced from O(N) to 0(1), where N is the number of filter taps. This results in a significant reduction in hardware complexity of the filter.

[0084] The memristive-based electronic filter 200a, 200b is fully flexible in terms of order of the filter as well as the filter coefficients.

[0085] In some embodiments disclosed herein the electronic filter 200a, 200b further comprises one or more delay elements 202-1, 202-2, 203-1, 203-2 for delaying signals to respective memristors of the memristive low-pass filter 210 and the memristive high- pass filter 220. Note that in Figure 2a there is no delay element for the first filter coefficient. The delay elements 202-1 , 202-2, 203-1 , 203-2 may be implemented as registers. The one or more delay elements 202-1, 202-2, 203-1 , 203-2 may be analog delay elements. When the input is digital the delay elements 206 may be digital delay elements, such as digital registers.

[0086] In some embodiments disclosed herein the one or more delay elements 202-1 , 202- 2, 203-1 , 203-2 comprise one or more first delay elements 202-1, 202-2 operatively arranged to delay the input signal to respective memristors of the memristive low-pass filter 210 such that the respective memristors of the memristive low-pass filter 210 receive a delayed input signal.

[0087] Thus, the electronic filter 200a, 200b comprises one or more crossbar arrays with a total of at least two columns of memristors implementing the memristive low-pass filter 210 and the memristive high-pass filter 220.

[0088] In some embodiments herein the electronic filter 200a, 200b further comprises a delay line. Depending on whether the input signal is digital, and the type of delay elements used the electronic filter 200a, 200b may further comprise one or more DACs 208 operatively arranged before the memristive low-pass filter 210 and the memristive high-pass filter 220, such as between the one or more delay elements 202-1 , 202-2, 203- 1 , 203-2 and the memristive low-pass filter 210 and the memristive high-pass filter 220 respectively.

[0089] The delay elements 202-1 , 202-2, 203-1 , 203-2 or the DACs 208 or both may be part of the memristive-based low-pass and high-pass filters 210, 220 respectively. In Figures 2a-2b and Figures 3a-3c the "lowpass filter" and "highpass filter" labels are used to specify the corresponding memristors, which are used to implement these filters. However, a complete circuit of the "lowpass filter" and "highpass filter" may include one or more delay elements and / or DACs as well.

[0090] PIM-based Band-Stop Filters

[0091] A band-stop filter may be realized by combining an individual / V-tap low-pass filter and an / W-tap high-pass filter in a proper manner. Thus, the equivalent impulse response of the band-stop filter is achieved by adding the two individual impulse responses of low- pass and high-pass filters.

[0092] To this end, the low-pass and high-pass filters will receive and process the delayed- version of input samples of the signal in parallel and then their outputs will be added together to generate the output samples of the targeted band-stop filter, which correspond to the filtered-version of the input signal.

[0093] As mentioned above, Figure 2a illustrates the electronic filter 200a for band stop filtering. Thus, Figure 2a illustrates the PIM-based band stop filter 200a.

[0094] When the electronic filter is for band stop filtering then the memristive low-pass filter 210 and the memristive high-pass filter 220 may be arranged in parallel.

[0095] When the electronic filter is for band stop filtering then the one or more first delay elements 202-1 , 202-2 may be further operatively arranged to delay the input signal to respective memristors of the memristive high-pass filter 220 such that the respective memristors of the memristive high-pass filter 220 receive the delayed input signal. Thus, the memristive low-pass filter 210 and the memristive high-pass filter 220 may receive the same delayed input signal.

[0096] In some embodiments herein when the electronic filter 200a is for band stop filtering then the electronic filter 200a further comprises an adder circuit 204 for adding output signals from the low-pass filter 210 and the high-pass filter 220, i.e. , for adding output signals from the first crossbar array and the second crossbar array. Then the electronic filter 200a may further comprise a first current-to-voltage converter 205 operatively arranged between the low-pass filter 210 and the high-pass filter 220, i.e., between the first crossbar array and the adder circuit 204, and a second current-to-voltage converter 206 operatively arranged between the second crossbar array and the adder circuit 204.

[0097] The adder circuit 204 may be a memristive-based adder circuit. That is, the adder circuit 204 may comprise two memristors coupled in series. Then a first memristor of the adder circuit 204 is coupled to the low-pass filter 210 via the first current-to-voltage converter 205 and a second memristor of the adder circuit 204 is coupled to the high-pass filter 220 via the second current-to-voltage converter 206. Both memristors of the adder circuit 204 may be programmed with a value of 1.

[0098] For the band stop filter 200a of Figure 2a the memristors of each crossbar columns are programmed by the coefficients of the corresponding frequency response of the low- pass or high-pass filter. The samples of input signal, [n], are shifted in the time domain and converted to the analog voltages, which will be applied to the crossbar rows. As a result, two current signals will be produced, which are converted to corresponding voltage signals using the current-to-voltage convertors 205, 206 in Figure 2a.

[0099] One case of realization of current-to-voltage convertors is to use resistors. As mentioned above, these voltage signals may be added together in the analog domain using a memristive-based adder 204, which includes two memristors, as shown in Figure 2a. The output of the adder 204 may be converted to digital domain by an ADC 225 to produce the output samples of the band-stop filter 200a as where q, i = 0, . . . , N - 1 are the coefficients of the low-pass filter, C'j, j = 0, . . . , M - 1 are the coefficients of the high-pass filter, X[n - j] and X[n - j] are the delayed versions of the input signal.

[0100] As a result, by changing the values of the coefficients (Q and and the number of filter taps (N and M), the target frequency response and the desired characteristic for the band-stop filter may be obtained. Note that Q and N belong to the low-pass filter 210 and C'j and M belong to the high-pass filter. The memristive-based adder circuit 204 reduces the number of required ADCs in the band-stop filter to one, while if the above-mentioned two signals are added in digital domain, two ADCs will be needed.

[0101] Moreover, if for any reason an analog-domain output of the filter is needed, then the proposed scheme doesn’t need an ADC anymore (e.g., in case that the next block after the band-stop filter within the processing chain requires the analog-domain filtered signal as its input). For this reason, the ADC is shown by a dashed rectangle in Figure 2a.

[0102] Thus, the architecture in Figure 2a may be used as a band-stop filter with digital input-signal, digital output-signal, and analog output-signal.

[0103] PIM-based Band-Stop Filter with Analog Input Signal

[0104] In some applications, the input signal of the band-stop filter may be an analog signal. In such cases, a relatively simple solution is to use one additional ADC to convert the input signal to the digital domain and then send it to the architecture shown in Figure 2a to perform the filtering as described before. However, this increases the hardware cost of the band-stop filter.

[0105] Figure 2b illustrates some embodiments herein for use with an analog-domain input signal. A processing flow for the architecture in Figure 2b is the same as the one described above for Figure 2a. The main difference is that in the architecture shown in Figure 2b, “shifting the samples in time” is performed by using analog-domain delay elements instead of digital delays. As a result, since the input signal is already in the analog domain, all the DAC modules may be removed from the band-stop filter. The rest of the procedure is similar to the procedure described above in relation to Figure 2a.

[0106] Different realizations of analog-domain delays have been proposed. In some embodiments herein the analog-domain delay elements 202-1 , 202-2 comprises a one- period time-delay (OPTD), which may be created using a simple analog circuit. The OPTD block gets the input sample [n] and produces X[n - 1] (i.e., [n] which is delayed by one cycle). Thus, by connecting a series of such modules and applying [n] to the input of the first module, all the required delayed versions of X[n] may be generated.

[0107] For scenarios with analog input and output signals, the proposed band-stop filter doesn’t need any DAC nor ADC. The output signal of the architecture in Figure 2b is generated in analog domain. But, if for any reason the digital-domain output signal of the filter is needed, the ADC 225 may be used for this purpose.

[0108] It is worth to mention that even if the input signal of the band-stop filter 200a is in digital domain, it is still possible to employ the proposed architecture in Figure 2b instead of the one in Figure 2a. Then the band-stop filter 200a may further include a further DAC 235 to convert the input signal from digital domain to analog domain.

[0109] Thus, the architecture in Figure 2b supports realization of a band-stop filter for all possible scenarios: digital input-signal, analog input-signal, digital output-signal, and analog output-signal.

[0110] Table 1 summarizes all the possible Input / output configurations of the proposed band-stop filters and lists the number of required DACs, ADCs, OTPD, and digital delay elements (D).

[0111] Table 1. Various configurations of proposed band-stop filters and corresponding hardware requirements.

[0112] PIM-based Band-Pass Filters

[0113] A band-pass filter may be designed by cascading a low-pass and a high-pass filter. Thus, the equivalent impulse response of the band-pass filter is achieved by calculating convolution of the two individual impulse responses of low-pass and high-pass filters. The first filter is an / V-tap low-pass filter with the set of coefficients of CL, i = 0, . . . , N - 1 and the second filter is an / W-tap high-pass filter with the set of coefficients of C'j, j = 0, . . . , M - 1.

[0114] Figure 3a illustrates the PIM-based band pass filter 200b. Thus, in Figure 3a the electronic filter 200b is for band pass filtering. Then the one or more delay elements 202- 1 , 202-2, 203-1 , 203-2 further comprise one or more second delay elements 203-1 , 203-2 operatively arranged between the memristive low-pass filter 210 and the memristive high- pass filter 220 such that the respective memristors of the memristive high-pass filter 220 receive a delayed low-pass-filtered signal from the memristive low-pass filter 210. The one or more second delay elements 203-1 , 203-2 may be analog or digital delay elements. Note that according to the embodiment illustrated in Figure 3a there is no delay element for the first memristor (filter coefficient) of the low-pass filter 210 coefficient nor for the first memristor (filter coefficient) of the high-pass filter 220.

[0115] When the one or more second delay elements 203-1 , 203-2 are digital delay elements then the electronic filter 200a, 200b may further comprise a second ADC 241 operatively arranged between the first crossbar array and the second crossbar array.

[0116] Thus, the electronic filter 200b for band pass filtering comprises the memristive low- pass filter 210 and the memristive high-pass filter 220. In other words, the electronic filter 200b for band pass filtering comprises two crossbar arrays of memristors (each has one column of memristors). The electronic filter 200b for band pass filtering may further comprise a delay line comprising the one or more delay elements 202-1 , 202-2, 203-1, 203-2, a number of DACs 208 and the ADC 225 for the output signal.

[0117] For the electronic filter 200b for band pass filtering the memristors of each crossbar column are programmed by the coefficients of the corresponding frequency response of the low-pass or high-pass filter. The samples of the input signal, [n], are shifted in the time domain and possibly converted to analog voltages, which will be applied to the crossbar rows of the low-pass filter 210.

[0118] The output samples of the low-pass filter are generated as where X[n - j] are the delayed versions of the input signal. The output of the low- pass filter 210, y[n], is converted to the digital domain and are sent to the high-pass filter 220, which has the set of coefficients of The recently generated samples, y[n], are shifted in the time domain and converted to analog voltages, which are applied to the crossbar rows of the high-pass filter 220. Then, the output signal of the high-pass filter 220 is converted to digital samples, i.e., which is equivalent to the output signal of the band-pass filter 200b.

[0119] The impulse response of the band-pass filter 200b equals the convolution of the impulse responses of the cascaded low- and high-pass filters 210, 220. Thus, by changing the values of the coefficients (Q and and the number of filter taps (N and M), a target frequency response and a desired characteristic for the band-pass filter 200b is obtained.

[0120] If for any reason an analog-domain output signal of the band-pass filter 200b is needed, then the band-pass filter 200b doesn’t need the ADC 225 at the output (for example in case that the next block after the band-pass filter 220 within a processing chain requires an analog-domain filtered signal as its input). For this reason, the ADC 225 is shown by a dashed rectangle in Figure 3a.

[0121] Thus, the band-pass filter 200b in Figure 3a is compatible with a digital input-signal, a digital output-signal, and an analog output-signal.

[0122] Embodiments according to Figure 3a require the second ADC 241, which is operatively arranged between the low-pass filter 210 and the high-pass filter 220.

[0123] However, Figure 3b illustrates embodiments which are modified with respect to the embodiments according to Figure 3a to reduce the hardware cost of the band-pass filter 200b. In this architecture, the output current signal of the low-pass filter 210 is converted to a corresponding voltage signal using a resistor. Next, this signal is sent to a series of OPTD modules to generate the delayed versions of the output signal of the low-pass filter, which will be eventually applied to the crossbar rows of the high-pass filter 220. Figure 3b illustrates the electronic filter 200b for band pass filtering comprising one or more analog second delay elements 203-1 , 203-2.

[0124] When the one or more second delay elements 203-1 , 203-2 are analog delay elements then the electronic filter 200b may further comprise a third current-to-voltage converter 251 operatively arranged between the first crossbar array and the second crossbar array.

[0125] In case that an analog output signal of the band-pass filter 200b of Figure 3b is needed, there will be no need for any ADC in the proposed band-pass filter 200b of Figure 3b. Thus, the the band-pass filter 200b of Figure 3b supports band-pass filter with a digital input-signal, a digital output-signal, and an analog output-signal.

[0126] PIM-based band-pass filter with analog input signal

[0127] In some applications, the input signal of the band-pass filter 200b is an analog signal. In such cases, a simple solution is to use one additional ADC to convert the input signal to the digital domain and then send it to the architecture shown in Figure 3b to perform the filtering as described before. However, this increases the hardware cost of the band-pass filter 200b.

[0128] Instead, some further embodiments herein employ the architecture shown in Figure 3c in case of an analog-domain input signal. The processing flow of the architecture in Figure 3c is the same or similar as for Figure 3b. A difference is that in the architecture shown in Figure 3c, “shifting the samples in time” is performed by using analog-domain delay elements for both low-pass and high-pass filters. As a result, since the input signal is already in the analog domain, all the DAC modules may be removed from the bandpass filter. The rest of the procedure is similar to the procedure for Figure 3b.

[0129] Having considered the analog input and output signals of the architecture in Figure 3c, the band-pass filter 200b doesn’t need any DAC nor ADC.

[0130] The output signal of the architecture in Figure 3c is generated in analog domain. But, if for any reason the digital-domain output signal of the filter 200b is needed, then embodiments according to Figure 3c may comprise the ADC 225 (for example in case that the next block after the band-pass filter 200b within the processing chain requires the digital-domain filtered signal as its input).

[0131] It is worth to mention that even if the input signal of the band-pass filter 200b is in digital domain, it is still possible to employ the embodiments according to Figure 3c instead of the embodiments according to Figure 3b. The only thing which may be included is the DAC 235 to convert the input signal from digital domain to analog domain, which is shown by a dashed rectangle in Figure 3c.

[0132] Thus, the embodiments according to Figure 3c may be used for all possible scenarios: digital input-signal, analog input-signal, digital output-signal, and analog output- signal.

[0133] Table 2 summarizes all the possible Input / output configurations of the band-pass filters 200b and lists the number of required DACs, ADCs, OTPD, and digital delay elements (D).

[0134] Table 2. Various configurations of embodiments of band-pass filters 200b and corresponding hardware requirements.

[0135] All the above-mentioned current-to-voltage converters may be implemented as resistors, transimpedance amplifier (TIA), a sample-and-hold circuit, or with similar compact sensing circuitry.

[0136] Figure 4 illustrates a flowchart of a method for filtering electrical signals according to embodiments herein. The method actions below may be taken in any suitable order.

[0137] Action 400

[0138] The quantized filter coefficients corresponding to the targeted frequency response may be extracted. A frequency response of the targeted filter may be extracted, e.g., by means of fast Fourier transform (FFT), Z-Transform, etc., to calculate the corresponding quantized filter coefficients.

[0139] Action 401

[0140] A structure of the required crossbar arrays to realize the filter may be specified. For example, the number of filter coefficients may be specified.

[0141] Action 402

[0142] The method may further comprise configuring the memristive devices of the electronic filter 200a, 200b. The memristive devices of the electronic filter 200a, 200b may be configured according to the matrix coefficients, i.e. , according to the filter coefficients. Thus, the vector / matrix of filter coefficients will be programmed to the memristors of the electronic filter 200a, 200b.

[0143] Action 403

[0144] Then, the input samples may be sent to the first delay elements 202-1 , 202-2 and the DACs 208. The output voltage of the DACs 208 will be applied to the crossbar rows. Note that in Figures 2a, 2b and Figures 3a-3c there is no delay element for the first filter coefficient. The delay elements may be implemented as registers or analog delay elements. When the input is digital the delay elements may be digital delay elements, such as digital registers.

[0145] Action 404

[0146] After a read cycle of the crossbar arrays, the generated signal(s) at the crossbar column(s) will represent the filtered signal.

[0147] Action 405

[0148] If digital output of the filter is needed, the analog signals which are generated at the crossbar columns may be converted to binary values using ADCs.

[0149] This procedure will be repeated for the next sequence of input samples. If the size and type of the filter remain fixed, there is no need to reprogram the crossbar array.

[0150] However, if the filter coefficients are changed because of any reason such as changing the filtering scheme, etc., then the crossbar should be programmed with the new vector / matrix of coefficients. Figure 5 illustrates a flowchart of a method for filtering electrical signals with the electronic filter 200a, 200b. Specifically, the method is for band stop or band pass filtering of electrical signals.

[0151] The method may be performed by the electronic filter 200a, 200b or an electronic device comprising the electronic filter 200a, 200b. The method actions below may be taken in any suitable order.

[0152] Action 500

[0153] The method may comprise configuring the memristive devices of the electronic filter 200a, 200b. The memristive devices may be configured according to the matrix coefficients, i.e. , according to the filter coefficients.

[0154] Action 501

[0155] The method further comprises filtering an electrical input signal with the memristive-based electronic filter 200a, 200b to obtain the filtered electrical signal.

[0156] In some embodiments herein filtering comprises band pass filtering which comprises filtering the electrical input signal with the memristive low-pass filter 210 and then filtering the low-pass filtered signal with the memristive high-pass filter 220.

[0157] In some other embodiments herein filtering comprises band stop filtering which comprises filtering the electrical input signal with the memristive low-pass filter 210 and with the memristive high-pass filter 220 and adding the low-pass filtered signal with the high-pass filtered signal.

[0158] PIM-based Filter Bank

[0159] There are some use cases, which may benefit from employment of multiple filters with different frequency responses. This is due to the fact that depending on the environmental and system conditions, different filtering characteristics are required. Moreover, there are other use cases, which receive multiple streams of data / information in parallel and process them simultaneously. Therefore, in such cases, multiple filters with the same or different coefficients may be implemented in parallel.

[0160] Some embodiments herein are directed to filter banks, such as multidimensional filter banks, using processing in memory approach. Let’s consider an N x M-dimensional filter bank, which includes M filters and N is the length of the largest filter within the filter bank. In order to realize such a filter bank using processing in memory, first, a matrix of coefficients may be created. To this end, the quantized coefficients corresponding to each filter will be considered as a separate column of this matrix. Thus, an N x M matrix of coefficients will be obtained in which m-th column (m = 1, represents the coefficients of m-th filter of the filter bank.

[0161] Note that embodiments herein enable implementation of filters with different lengths / orders. For example, if the m-th filter has the length of L (L < N), the first L entries of m-th column of the matrix will represent L filter coefficients and the rest of the entries in the m-th column will be considered as zero. As a result, filtering operation will be performed for M separate streams in parallel, in which the length, order, and coefficients of these M filters may be the same or different.

[0162] Finally, the coefficient matrix will be programmed to the memristors of a crossbar array of size N x M. The rest of the procedure is similar the one which is explained in the flowchart of Figure 4. The output of each filter is generated via a corresponding crossbar column in a parallel manner.

[0163] A feature of the filter bank according to embodiments herein is that it has a fixed throughput and latency. This means that the output samples of all filters in the filter bank will be generated in parallel and the throughput and latency of each filter is independent of the order and length of the other ones.

[0164] An example of the filter bank concept is illustrated in Figure 6, which illustrates a general filter bank 600 comprising four memristive filters 601, 602, 603, 604. The output samples of j-th filter of the filter bank may be mathematically expressed as

[0165] Another feature of the filter bank according to embodiments herein is that only one set of delay elements and one set of DACs are needed as illustrated in Figure 6. This means that the hardware cost resulting from the delay line and DACs is the same in a single filter and a filter bank with multiple filters.

[0166] Hardware Sharing in the Filter Bank In order to reduce the hardware cost of the filter bank even more, the ADCs in Figure 6 may be shared between multiple columns. For example, in case of a filter bank with M filters, 1, ...,M ADCs may be used to generate all the output samples of the filter bank in M, 1 read cycles.

[0167] Figure 7a illustrates the band stop filter 200a with multiple low-pass filters and multiple high-pass filters. For example, there may be P low-pass filters with length N and Q high-pass filters with length M.

[0168] Similarly, the band pass filter 200b may comprise multiple low-pass filters and multiple high-pass filters to form a band pass filter bank. Figure 7b illustrates the band pass filter 200b with two low-pass filters and two high-pass filters.

[0169] Thus, in some embodiments herein, illustrated in Figure 7a and Figure 7b, the electronic filter 200a, 200b is configured to operate as a filter bank. Then the electronic filter 200a, 200b may further comprise at least a second memristive low-pass filter 210-2 operatively arranged in parallel with the memristive low-pass filter 210 and comprising a further first crossbar array of memristors. Each memristor of the further first crossbar array is configured to represent a respective filter coefficient of a further low- pass filter implemented as a filter matrix.

[0170] The electronic filter 200a, 200b may further comprise at least a second memristive high-pass filter 220-2 operatively arranged in parallel with the memristive high-pass filter 220 and comprising a further second crossbar array of memristors. Each memristor of the further second crossbar array is configured to represent a respective filter coefficient of a further high-pass filter function implemented as a filter matrix.

[0171] Of course there may be more than two memristive low-pass filters in the low-pass filter bank and more than two memristive high-pass filters in the high-pass filter bank. In the example of two memristive filters in each filter bank the two memristive low-pass filters 210, 210-2 may be combined with any of the two memristive high-pass filters 220, 220-2 which means that there are 4 possible band stop or band pass filters. In general, if there are M filters of each type then there are M2possible band stop or band pass filters. It is also possible that only one of the low-pass or high-pass filters are implemented as a filter bank. In general, if there are M filters of one of the types of low-pass or high-pass filters and the other filter type comprises a single filter then there are M possible band stop or band pass filters. When the electronic filter 200a, 200b is a filter bank then the electronic filter 200a, 200b may further comprise a first multiplexer 215-1 configured to multiplex filtered electrical signals from the memristive low-pass filters such that a single filtered electrical signal is obtained from the low-pass filters. The electronic filter 200a, 200b may further comprise a second multiplexer 215-2 configured to multiplex filtered electrical signals from the memristive high-pass filters such that a single filtered electrical signal is obtained from the high-pass filters. If the electronic filter 200a, 200b comprises two or more low- pass filters and two or more high-pass filters, then the electronic filter 200a, 200b may comprise both the first multiplexer 215-1 and the second multiplexer 215-2. The multiplexers may be implemented with analog switches.

[0172] Note that everything about the usage of digital / analog delay elements, the number of required DACs / ADCs, and the type of input / output signals, which have been described above is still valid and may be applied to the context of filter banks as well.

[0173] PIM-based filter with real or complex input samples and real or complex coefficients

[0174] Embodiments described below enable fully parallel implementation of PIM-based filters for real or complex input samples as well as real or complex coefficients. Figure 8a and Figure 8b illustrate embodiments in which the memristive-based band stop filter 200a or band pass filter 200b is adapted for real or complex input samples as well as real or complex filter coefficients. Figure 8a illustrate how the low-pass filter 210 may be adapted to complex filter coefficients or complex input while Figure 8b illustrate how the high-pass filter 220 may be adapted to complex filter coefficients or complex input. The same principle applies for both the low-pass filter and the high-pass filter. This is the most general case which supports any of the possible scenarios. The memristive-based band stop filter 200a or band pass filter 200b may comprise an / V-tap filter, such as a Finite Impulse Response (FIR) filter, with the complex coefficients Co, In the embodiments of Figure 8a and Figure 8b the input samples [n] are complex-valued. In order to realize this filter using PIM, N x 4 memristors may be used, which corresponds to four columns of memristors. Note that these four columns may be in four separate crossbars or within two crossbars, as shown in Figure 8a and Figure 8b. Two of the four columns are programmed with the real part of the coefficients, while the other two columns are programmed with the imaginary part of the coefficients. In Figure 8a and Figure 8b a first crossbar 210a, 220a comprising two columns of memristors, programmed with the real and imaginary part of the coefficients respectively, receives the real part of the input and a second crossbar 210b, 220b comprising two columns of memristors, programmed with the real and imaginary part of the coefficients respectively, receives the imaginary part of the input.

[0175] In Figure 8a and Figure 8b first and third columns are programmed with the real part of the coefficients, which will receive and process the real and imaginary part of the input samples respectively. As shown in Figure 8a and Figure 8b second and fourth columns are programmed with the imaginary parts of coefficient and these two columns will process the real and imaginary part of the input samples respectively. Thus, in the embodiments of Figure 8a and Figure 8b a first column 201 -RR of memristors is programmed with the real part of the coefficients and receives and processes the real part of the input samples. A second column 201 -Rl of memristors is programmed with the imaginary part of the coefficients and receives and processes the real part of the input samples. A third column 201 -IR of memristors is programmed with the real part of the coefficients and receives and processes the imaginary part of the input samples. A fourth column 201-11 of memristors is programmed with the imaginary part of the coefficients and receives and processes the imaginary part of the input samples. If the input samples are only real or complex and the coefficients are complex only two of the columns are needed, either the first and second columns or the third and fourth columns. If the coefficients are only real or imaginary and the input samples are complex only two of the columns are needed, either the first and third columns or the second and fourth columns. The embodiments of Figure 8a and Figure 8b are able to handle all cases.

[0176] The filtering operation may be performed following any of the flowcharts in Figures 4 and 5. Thus, in the most general case illustrated in Figure 8a and Figure 8b four current signals will be generated and then they may be converted to voltage signals (e.g., using resistors).

[0177] As shown in Figure 8a and Figure 8b, two memristor-based circuits (adder circuits) are designed to combine the output signals of the crossbars and generate outputs of the band stop filter 200a or band pass filter 200b. A current-to-voltage converter may convert the output from the memristor-based adder circuits.

[0178] As further shown in Figure 8a and Figure 8b each filter 200a, 200b may comprise two multiplexers (e.g., analog switches) to select the proper output signal. In some embodiments herein each of the memristive low-pass and high-pass filters 210, 220 is configured to filter a complex electrical signal or the filter coefficients are complex or both. Then each of the low-pass and high-pass filters 210, 220 comprises two crossbar arrays 201-RR, 201 -Rl, 201 -I R, 201-11 of memristors and further comprises two multiplexers 231, 232 adapted to select electrical signals from the two crossbar arrays 201 -RR, 201 -Rl, 201 -I R, 201-11 of memristors as the filtered electrical signal.

[0179] To combine the outputs from the different columns the electronic filter 200a, 200b may further comprise two adder circuits 243, 244 operatively arranged between the two crossbar arrays 201 -RR, 201 -Rl, 201 -I R, 201-11 of memristors of the respective memristive low-pass and high-pass filter 210, 220 and the two multiplexers 231 , 232. The two adder-circuits 243, 244 may be memristive-based, i.e. , the two adder-circuits 243, 244 may each comprise two memristors coupled in series.

[0180] A first multiplexer 231 may select electrical signals with a first selector Sei 1 based on outputs from the second column 201 -Rl and the third column 201 -I R, while a second multiplexer 232 may select electrical signals with a second selector Sei 2 based on outputs from the first column 201 -RR and the fourth column 201-11. The first multiplexer 231 may have 3 inputs: signals from the second column 201 -Rl and the third column 201-IR respectively and a combination of the signals from the second column 201 -Rl and the third column 201-IR. The second multiplexer 232 may have 2 inputs: signals from the first column 201-RR and a combination of the signals from the first column 201-RR and the fourth column 201-11. Table 1 below shows all four possible configurations of the multiplexers. Which configuration to choose is dependent on whether the coefficients and / or input samples are real or complex.

[0181] Table 1. Different configuration of the multiplexers to support both real and complex inputs and coefficients.

[0182] Sei 2

[0183] In some embodiments, for example when the the two adder-circuits 243, 244 are analog, then the electronic filter 200a, 200b further comprises a plurality of current-to- voltage converters 252, 253, 254, 255 operatively arranged between the two crossbar arrays 201 -RR, 201 -Rl, 201 -I R, 201-11 of memristors of the respective memristive low- pass and high-pass filter 210, 220 and the two adder circuits 243, 244. The electronic filter 200a, 200b may further comprise a respective current-to-voltage converter 261, 262 operatively arranged between the respective adder circuit of the two adder circuits 243, 244 and the two multiplexers 231 , 232.

[0184] All the above-mentioned current-to-voltage converters may be implemented as resistors, transimpedance amplifier (TIA), a sample-and-hold circuit, or with similar compact sensing circuitry.

[0185] An advantage of the above embodiments is that the output of the crossbars are combined in the analog domain rather than converting them to the digital values and then performing addition / subtraction. This reduces the hardware cost and number of required ADCs from four in case of combining the crossbar outputs in digital domain, to two ADCs in embodiments disclosed above. Besides, these two ADCs may be removed if for any reason an analog output signal is requested at the output of the filter.

[0186] PIM-based Filter with Large Lengths

[0187] Although the size of practical crossbars is large enough to implement many filtering schemes, sometimes the filter length is large such that it cannot be realized using a single crossbar array. In such cases, the coefficient matrix may be divided into multiple smaller matrices, which may be programmed to multiple crossbar arrays.

[0188] An example of this concept is shown in Figure 9 for a FIR filter with length of 64, in which the generator matrix is divided into two parts each of size 32 and then they are programmed into two smaller crossbar arrays. In the embodiment of Figure 9, an integrator block is used to add multiple current signals, which are generated in different crossbars. However, other hardware may be used to add the current signals. The output signal of the integrator block may be sent to an ADC module to generate binary-valued samples of the filtered signal.

[0189] PIM-based Filter with Bit-Serial Inputs

[0190] The input samples to the filter 200a, 200b may be represented by multiple bits, meaning that high-resolution ADCs and DACs may be needed. A supported bit resolution of ADCs determines the quantization error; the higher supported bit resolution the lower the quantization error and hence the better performance. Therefore, in case that either an ADC 270 does not support the required resolution or in order to improve the performance, each input sample, which is a binary word, may be sent to the DAC 208 in a bit-serial manner. Thus, at each time instance, which corresponds to the read cycle of the crossbar array, one bit of all input binary-words is applied to the corresponding DAC 208.

[0191] An example embodiment is illustrated for a filter 200a, 200b in Figure 10. In Figure 10 flip flops (FF) 271 are used as the delay elements. Also, due to the fact that the input is bit-serial, 1 -bit DACs are used, which reduces the hardware cost.

[0192] After W read cycles, the computation is completed where W is the number of bits per input binary-word (input sample). To calculate a final result in the bit-serial scheme, the filter 200a, 200b may comprise a shift and add circuit 281 operatively arranged after the ADC 270.

[0193] PIM-based filter with coefficients slicing

[0194] In order to improve the performance of the filter 200a, 200b and / or to reduce the hardware cost by using simpler and cheaper memristive devices, it is possible to assign more than one memristor of the filter 200a, 200b to every coefficient. In other words, each filter coefficient may be divided into multiple parts, which may be programmed to multiple memristive devices in a crossbar row of the filter 200a, 200b. Thus, each part of the filter coefficient may be programmed to a respective memristor.

[0195] For example, let’s consider each filter coefficient is represented by 8 bits, i.e., q = c c c o o o ci cf . As explained above, the coefficient Q is programmed into one memristor. However, in a coefficient slicing scenario, the coefficient Q is programmed into more than one memristor. Assuming two memristors per coefficient, is programmed to a first memristor and c c c cf may be programmed to a second memristor. Similar to the bit-serial input scenario, a shift & add circuit is employed to calculate the output samples of the filter 200a, 200b by combining the outputs of the corresponding crossbar columns.

[0196] As mentioned above, filters may be used in many applications. In particular, the filter 200a, 200b according to embodiments herein may be used in different electronic devices. Figure 11 illustrates a baseband processor 1300, for example for wireless communications signals, comprising the filter 200a, 200b. The filter 200a, 200b may for example filter the wireless communications signals. The baseband signal processor 1300 may comprise further baseband signal-processing circuits 1302 and the filter 200a, 200b may be adapted to be operatively coupled to the further signal processing circuits 1302 of the baseband signal processor 1300. Thus, an electronic device may comprise the electronic filter 200a, 200b.

[0197] Figure 12 illustrates a network node 601 of a wireless communications network 170, the network node 601 comprising an electronic device comprising the filter 200a, 200b.

[0198] Figure 13 illustrates a wireless communications device 602 comprising an electronic device comprising the filter 200a, 200b.

[0199] The network node 601 and the wireless device 602 may be configured to perform the method actions of Figures 4 and 5 above.

[0200] The embodiments herein may be implemented through a processor or one or more processors, such as the processor 1204, 1604 of a processing circuitry in the network node 601 and the wireless device 602 respectively and depicted in Figure 15 and 13 together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computer program code for performing the embodiments herein when being loaded into the network node 601 and the wireless device 602 respectively. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server and downloaded to the network node 601 and the wireless device 602 respectively.

[0201] The network node 601 and the wireless device 602 respectively may further comprise a memory 1502, 1602 comprising one or more memory units. The memory comprises instructions executable by the processor in the network node 601 and the wireless device 602 respectively.

[0202] The respective memory 1502, 1602 is arranged to be used to store e.g. information, data, configurations, and applications to perform the methods herein when being executed in the network node 601 and the wireless device 602 respectively.

[0203] In some embodiments, a computer program 1503, 1603 comprises instructions, which when executed by the at least one processor, cause the at least one processor of the network node 601 and the wireless device 602 respectively to perform the actions above.

[0204] In some embodiments, a carrier 1205, 1605 comprises the computer program, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0205] The network node 601 and the wireless device 602 respectively may further comprise an input and output interface, I / O, 1206, 1606 configured to communicate with other devices. The input and output interface 1206, 1606 may comprise a receiver, such as a wireless receiver, (not shown) and a transmitter, such as a wireless transmitter, (not shown).

[0206] Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configured with software and / or firmware, e.g., stored in the network node 601 and the wireless device 602 respectively, that when executed by the respective one or more processors such as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application-Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0207] Figure 14 illustrates a wireless communications network 170 in which embodiments herein may be implemented.

[0208] The wireless communications network 170 may use a number of different technologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems such as e.g., WCDMA and LTE and in future wireless communication systems, such as 6G systems.

[0209] Network nodes operate in the wireless communications network 170 such as the network node 601. The network node 601 provides radio coverage over a geographical area, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar. There may be more than one cell. For example, there may be a second cell 16 as well. The network node 601 may be a NR-RAN node, transmission and reception point e.g. a base station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless device within the service area depending e.g. on the radio access technology and terminology used. The respective network node 601 may be referred to as a serving radio access node and communicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE.

[0210] A number of wireless communications devices operate in the wireless communication network 170, such as the wireless communications device 602.

[0211] The wireless communications device 602 may be a mobile station, a non-access point (non-AP) STA, a STA, a user equipment and / or a wireless terminal, that communicate via one or more Access Networks (AN), e.g., RAN, e.g. via the network node 601 to one or more core networks (CN) e.g. comprising a CN node 13, for example comprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g., smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell.

[0212] When using the word "comprise" or “comprising” it shall be interpreted as nonlimiting, i.e. meaning "consist at least of". The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1. An electronic filter (200a, 200b) for band stop or band pass filtering of an electrical input signal, wherein the electronic filter (200a, 200b) comprises: a memristive low-pass filter (210) comprising a first crossbar array of memristors (211 , 212), wherein each memristor (211 , 212) of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix; and a memristive high-pass filter (220) comprising a second crossbar array of memristors (221 , 222), wherein each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

2. The electronic filter (200a, 200b) according to claim 1 , further comprising: one or more delay elements (202-1 , 202-2, 203-1, 203-2) for delaying signals to respective memristors of the memristive low-pass filter (210) and the memristive high-pass filter (220).

3. The electronic filter (200a, 200b) according to claim 2, wherein the one or more delay elements (202-1 , 202-2, 203-1 , 203-2) are analog delay elements.

4. The electronic filter (200a, 200b) according to any of the claims 2-3, wherein the one or more delay elements (202-1 , 202-2, 203-1 , 203-2) comprise one or more first delay elements (202-1 , 202-2) operatively arranged to delay the input signal to respective memristors of the memristive low-pass filter (210) such that the respective memristors of the memristive low-pass filter (210) receive a delayed input signal.

5. The electronic filter (200a) according to claim 4, wherein the electronic filter (200a) is for band stop filtering and wherein the one or more first delay elements (202-1 , 202-2) are further operatively arranged to delay the input signal to respective memristors of the memristive high-pass filter (220) such that the respective memristors of the memristive high-pass filter (220) receive the delayed input signal.

6. The electronic filter (200b) according to claim 4, wherein the electronic filter (200b) is for band pass filtering and wherein the one or more delay elements (202-1 , 202-2, 203-1 , 203-2) further comprise one or more second delay elements (203-1 , 203-2)operatively arranged between the memristive low-pass filter (210) and the memristive high-pass filter (220) such that the respective memristors of the memristive high-pass filter (220) receive a delayed low-pass-filtered signal from the memristive low-pass filter (210).

7. The electronic filter (200a) according to claim 5, further comprising: an adder circuit (204) for adding output signals from the first crossbar array and the second crossbar array; and a first current-to-voltage converter (205) operatively arranged between the first crossbar array and the adder circuit (204), and a second current-to-voltage converter (206) operatively arranged between the second crossbar array and the adder circuit (204).

8. The electronic filter (200a) according to claim 7, wherein the adder circuit (204) is a memristive-based adder circuit.

9. The electronic filter (200b) according to claim 6, wherein the one or more second delay elements (203-1 , 203-2) comprises analog second delay elements and the electronic filter (200b) further comprises: a third current-to-voltage converter (251) operatively arranged between the first crossbar array and the one or more analog second delay elements (203-1, 203- 2).

10. The electronic filter (200b) according to claim 6 or 9, wherein the one or more second delay elements (203-1 , 203-2) comprises digital second delay elements and the electronic filter (200b) further comprises: an analog-to-digital converter, ADC, (241) operatively arranged between the first crossbar array and the one or more digital second delay elements (203-1, 203-2).

11. The electronic filter (200a, 200b) according to any of the claims 1-10, configured to operate as a filter bank and further comprising: at least a second memristive low-pass filter (210-2) operatively arranged in parallel with the memristive low-pass filter (210) and comprising a further first crossbar array of memristors, wherein each memristor of the further first crossbar array is configured to represent a respective filter coefficient of a further low-pass filter implemented as a filter matrix; andat least a second memristive high-pass filter (220-2) operatively arranged in parallel with the memristive high-pass filter (220) and comprising a further second crossbar array of memristors, wherein each memristor of the further second crossbar array is configured to represent a respective filter coefficient of a further high-pass filter function implemented as a filter matrix.

12. The electronic filter (200a, 200b) according to claim 11 , further comprising: a first multiplexer (215-1) configured to multiplex filtered electrical signals from the memristive low-pass filters such that a single filtered electrical signal is obtained from the low-pass filters; and a second multiplexer (215-2) configured to multiplex filtered electrical signals from the memristive high-pass filters such that a single filtered electrical signal is obtained from the high-pass filters.

13. The electronic filter (200a, 200b) according to any of claims 1-12, wherein each of the memristive low-pass and high-pass filters is configured to filter a complex electrical signal or wherein the filter coefficients are complex or both, and wherein each of the low-pass and high-pass filters comprises two crossbar arrays (201-RR, 201 -Rl, 201- IR, 201-11) of memristors and further comprises two multiplexers (231 , 232) adapted to select electrical signals from the two crossbar arrays (201-RR, 201 -Rl , 201-IR, 201-11) of memristors as the filtered electrical signal.

14. The electronic filter (200a, 200b) according to claim 13, further comprising: two adder circuits (243, 244) operatively arranged between the two crossbar arrays (201-RR, 201-RI, 201-IR, 201-11) of memristors of the respective memristive low-pass and high-pass filter and the two multiplexers (231 , 232).

15. The electronic filter (200a, 200b) according to claim 14, further comprising: a plurality of current-to-voltage converters (252, 253, 254, 255) operatively arranged between the two crossbar arrays (201-RR, 201-RI, 201-IR, 201-11) of memristors of the respective memristive low-pass and high-pass filter and the two adder circuits (243, 244) and a respective current-to-voltage converter (261 , 262) operatively arranged between the respective adder circuit of the two adder circuits (243, 244) and the two multiplexers (231 , 232).

16. An electronic device (1300) comprising the electronic filter (200a, 200b) according to any of the claims 1-15.

17. A network node (601) of a wireless communications network (100), the network node (130) comprising the electronic device (1300) of claim 16.

18. A wireless communications device (602) comprising the electronic device (1300) of claim 16.

19. A method for band stop or band pass filtering of electrical signals, the method comprising: filtering (501) an electrical input signal with an electronic filter (200a, 200b) for band stop or band pass filtering, the electronic filter (200a, 200b) comprising: a memristive low-pass filter (210) comprising a first crossbar array of memristors (211 , 212), wherein each memristor (211 , 212) of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix; and a memristive high-pass filter (220) comprising a second crossbar array of memristors (221 , 222), wherein each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

20. The method according to claim 19, wherein filtering (501) comprises band pass filtering which comprises filtering the electrical input signal with the memristive low- pass filter (210) and then filtering the low-pass filtered signal with the memristive high-pass filter (220).

21. The method according to claim 19, wherein filtering (501) comprises band stop filtering which comprises filtering the electrical input signal with the memristive low- pass filter (210) and with the memristive high-pass filter (220) and adding the low- pass filtered signal with the high-pass filtered signal.

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