Electronic component and method for manufacturing same

Abstract

[PROBLEM] To enhance the reliability of an electronic component which is provided with a conductor pattern covered with a dielectric film. [SOLUTION] An electronic component 100 comprises: a substrate 110 including regions 111, 112; a resistance element 40 formed in region 112; a dielectric film 21 covering region 111 and the resistance element 40; a conductor pattern 31 formed in region 111 via the dielectric film 21; an adhesion film 50 covering an upper surface 31a and a side surface 31b of the conductor pattern 31, without covering region 112; and a dielectric film 22 covering the upper surface 31a and the side surface 31b of the conductor pattern 31 via the adhesion film 50.

Description

Electronic components and their manufacturing method

[0001] The present disclosure relates to electronic components and methods for manufacturing the same.

[0002] Patent Document 1 discloses an electronic component having a conductor pattern covered with a dielectric film.

[0003] Japanese Patent Application Laid-Open No. 2021-101480

[0004] When a conductor pattern is directly covered with a dielectric film, peeling at the interface between the two can affect the reliability of the electronic component.

[0005] This disclosure describes a technique for improving product reliability in an electronic component having a conductor pattern covered with a dielectric film and a manufacturing method thereof.

[0006] An electronic component according to one aspect of the present disclosure comprises a substrate including a first region and a second region spaced apart from the first region, a resistive element formed in the second region, a first dielectric film covering the first region and the resistive element, a first conductor pattern formed in the first region via the first dielectric film, an adhesive film covering an upper surface and side surfaces of the first conductor pattern without covering the second region, and a second dielectric film covering the upper surface and side surfaces of the first conductor pattern via the adhesive film.

[0007] A method for manufacturing an electronic component according to one aspect of the present disclosure includes the steps of forming a resistive element in a second region of a substrate having a first region and a second region, covering the first region and the resistive element with a first dielectric film, forming a first conductor pattern on a surface of the first dielectric film located on the first region, forming an adhesive film on the first and second regions so as to be in contact with the first conductor pattern, forming a second dielectric film on the first and second regions so as to be in contact with the adhesive film, forming a resist that covers the second dielectric film located in the first region and exposes the second dielectric film located in the second region, removing the second dielectric film using the resist as a mask, and removing the adhesive film using the resist as a mask.

[0008] According to the present disclosure, a technique for improving product reliability is provided in an electronic component having a conductor pattern covered with a dielectric film and a manufacturing method thereof.

[0009] FIG. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the technology disclosed herein. FIG. 2 is a schematic cross-sectional view of the electronic component 100. FIG. 3 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 4 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 5 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 6 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 7 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 8 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 9 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 10 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 11 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 12 is a schematic cross-sectional view of an electronic component 200 according to a modified example.

[0010] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] Fig. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the technology disclosed herein. Fig. 2 is a schematic cross-sectional view of the electronic component 100.

[0012] 1, the electronic component 100 includes a substrate 110, a functional layer 120 formed on the surface of the substrate 110, and a plurality of terminal electrodes 131 to 134 formed on the surface of the functional layer 120. The number of terminal electrodes is not particularly limited. The material of the substrate 110 is not particularly limited as long as it is chemically and thermally stable, generates little stress, and can maintain a smooth surface. Examples of materials that can be used for the substrate 110 include silicon single crystal, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO single crystal, surface-oxidized silicon, glass, quartz, ferrite, and organic films.

[0013] In the embodiment shown in Fig. 2, the surface of the substrate 110 is covered with a planarization layer 20. The planarization layer 20 is made of alumina (Al ２ O ３ ), silicon nitride (Si ３ N４ ), silicon oxide (SiO ２ ) or other inorganic insulating materials can be used. The functional layer 120 provided on the substrate 110 is a layer on which passive elements such as inductive elements, capacitive elements, and resistive elements, as well as other circuit elements, can be formed. The functional layer 120 may include, as appropriate, conductive patterns, dielectric films, insulating films, resistive films, and other materials. In the embodiment illustrated in FIG. 2 , the functional layer 120 includes a planarization layer 20, a resistive element 40 formed on the planarization layer 20, conductor layers M1, MM, and M2, and insulating layers 11 and 12. The resistive element 40 and conductor layers M1 and MM are embedded in the insulating layer 11, and the conductor layer M2 is embedded in the insulating layer 12. The insulating layers 11 and 12 may be made of, for example, organic insulating materials such as polyimide resin, epoxy resin, or benzocyclobutene resin.

[0014] The resistive element 40 is a conductive film made of, for example, a Cr-based alloy, and is provided in a region 112 of the substrate 110. The resistive element 40 is not provided in other regions 111, 113, and 114 of the substrate 110. In the example shown in FIG. 2, the resistive element 40 is in contact with the planarizing layer 20. The resistive element 40 is covered with a dielectric film 21. The dielectric film 21 is provided over almost the entire surface of the substrate 110, and in regions 111, 113, and 114 of the substrate 110 other than the region 112, the dielectric film 21 and the planarizing layer 20 are in contact with each other. Note that the material for forming the resistive element is not particularly limited, and a material having an appropriate resistance value may be selected as appropriate.

[0015] The conductor layer M1 is the bottommost conductor layer and includes a conductor pattern 31. The conductor pattern 31 is formed on the substrate 110 via a planarization layer 20 and a dielectric film 21 (sometimes referred to as a first dielectric film). In the embodiment illustrated in FIG. 2 , region 111 is the region on the substrate 110 where the conductor pattern 31 is formed. In the embodiment illustrated in FIG. 2 , no conductor patterns constituting the conductor layer M1 are arranged in the other regions 112 to 114. Regions 113 and 114 are located between regions 111 and 112. In the example illustrated in FIG. 2 , regions 111 and 112 are adjacent to each other via regions 113 and 114 where no conductor patterns constituting the conductor layer M1 are arranged. However, another conductor pattern constituting the conductor layer M1 may be arranged between regions 111 and 112. In this case, the other conductor pattern may be, for example, part of an inductor or a capacitor.

[0016] The conductor pattern 31 may constitute the lower electrode of the capacitor C. The conductor pattern 31 may be in contact with the dielectric film 21 and may be composed of a thin seed layer containing, for example, titanium (Ti), chromium (Cr), or tantalum (Ta), and a plating layer made of, for example, copper (Cu) provided on the seed layer and having a thickness greater than that of the seed layer and a resistance value lower than that of the seed layer. Similarly, the conductor patterns located on the other conductor layers MM and M2 may be composed of, for example, a stack of a seed layer and a plating layer.

[0017] The top surface 31a and side surface 31b of the conductor pattern 31 are covered with a dielectric film 22 (sometimes referred to as a second dielectric film) via an adhesive film 50. That is, the top surface 31a and side surface 31b of the conductor pattern 31 are covered with the adhesive film 50, and the top surface 31a and side surface 31b of the conductor pattern 31 are further covered with the dielectric film 22 via the adhesive film 50. Here, the top surface 31a of the conductor pattern 31 is a surface that is approximately parallel to the surface of the substrate 110. The side surface 31b of the conductor pattern 31 is a surface that is approximately perpendicular to the surface of the substrate 110. Note that due to manufacturing errors or the like, the top surface 31a of the conductor pattern 31 may be slightly inclined with respect to the surface of the substrate 110 (for example, approximately ±5° with respect to the surface of the substrate 110), and this is also included in the range of being approximately parallel. Similarly, the side surface 31b of the conductor pattern 31 may be slightly inclined with respect to the direction perpendicular to the surface of the substrate 110 (for example, approximately ±5° with respect to the direction perpendicular to the surface of the substrate 110), which is also included in the range of approximately perpendicular. The same applies to other conductor patterns hereinafter in this specification.

[0018] The surface roughness of the surface 22a of the dielectric film 22 may be smaller than the surface roughness of the surface 21a of the dielectric film 21 in the regions 112 and 113. This improves the reliability of the capacitor C, for example, when the dielectric film 22 is used as a capacitive insulating film of the capacitor C. Furthermore, in the regions 112 and 113, the unevenness of the surface 21a improves adhesion between the dielectric film 21 and elements formed thereon (e.g., the insulating layer 11, the conductor pattern 34, etc.). Furthermore, the surface roughness of the surface 21b of the dielectric film 21 in the regions 111 and 114 may be smaller than the surface roughness of the surface 21a of the dielectric film 21 in the regions 112 and 113. In this case, the unevenness of the surface 21a also improves adhesion between the dielectric film 21 and the insulating layer 11. Furthermore, the thickness of the dielectric film 21 in the regions 111 and 114 may be thicker than the thickness of the dielectric film 21 in the regions 112 and 113. This reduces the stress of the dielectric film 21 in the regions 112 and 113, thereby further improving the adhesion between the dielectric film 21 and the insulating layer 11.

[0019] The adhesive film 50 may be made of, for example, titanium (Ti), chromium (Cr), tantalum (Ta), or at least one of oxides and nitrides thereof. ３ N ４ ) or other inorganic insulating material. The adhesive film 50 may have higher adhesiveness to the conductor layer M1 and the dielectric film 21 than the dielectric film 22. The adhesive film 50 is interposed between the conductor pattern 31 included in the conductor layer M1 and the dielectric film 22, and thus, for example, silicon nitride (Si ３ N ４ The adhesive film 50 improves the adhesion at the interface between the dielectric film 22 made of copper (Cu) and the conductor pattern 31 made of, for example, copper (Cu). This can suppress peeling at the interface, compared to when the dielectric film 22 and the conductor pattern 31 are in direct contact with each other. In particular, the adhesive film 50 covers not only the top surface 31 a of the conductor pattern 31 but also the side surface 31 b, thereby improving the adhesion of the dielectric film 22 over a wider range.

[0020] The laminated film of the adhesive film 50 and the dielectric film 22 is formed not only on the upper surface 31a and side surface 31b of the conductor pattern 31 but also on a region 114 of the substrate 110. In the embodiment illustrated in FIG. 2 , the region 114 is a region where the laminated film of the adhesive film 50 and the dielectric film 22 is formed continuously from the side surface 31b of the conductor pattern 31 in a direction parallel to the surface of the substrate 110. The region 114 is located between the regions 111 and 112 and adjacent to the region 111. For example, the width of the region 114 (the length in a direction substantially parallel to the surface of the substrate 110) may be in a range of approximately 0.1 to 2.0 times the thickness of the conductor pattern 31 (the height in a direction substantially perpendicular to the surface of the substrate 110). The region 113 is a region located between the regions 112 and 114.

[0021] One of the side surfaces of the conductor pattern 31 is located on the boundary between the region 111 and the region 114. Here, the laminated film of the adhesive film 50 and the dielectric film 22 covering the upper surface 31a of the conductor pattern 31, the laminated film of the adhesive film 50 and the dielectric film 22 covering the side surface 31b of the conductor pattern 31, and the laminated film of the adhesive film 50 and the dielectric film 22 covering the region 114 of the substrate 110 are continuously formed.

[0022] In contrast, in the example shown in FIG. 2 , neither the adhesive film 50 nor the dielectric film 22 is formed on the regions 112 and 113. As a result, even if the adhesive film 50 were made of a conductive material, the conductor pattern 31 would not be short-circuited with the resistor element 40 or other conductor patterns located on the conductor layer M1 via the adhesive film 50. Furthermore, even if at least one of the adhesive film 50 and the dielectric film 22 were made of a material with high stress, the adhesive film 50 and the dielectric film 22 have been removed from the regions 112 and 113, thereby releasing stress in these areas. The end faces 50s of the adhesive film 50 covering the conductor pattern 31 and the end faces 22s of the dielectric film 22 are aligned in plan view, and these end faces 50s and 22s are located on the boundary between the regions 113 and 114. Furthermore, since the region 113 of the substrate 110 is covered with the dielectric film 21, the planarization layer 20 and the insulating layer 11 are not in direct contact. Here, if the planarization layer 20 is made of, for example, alumina (Al ２ O ３ In the present embodiment, the planarization layer 20 is made of a material (e.g., silicon nitride (Si)) that has higher adhesion to the insulating layer 11 than the planarization layer 20. ３ N ４ ))) covers the region 113 of the substrate 110. This makes it less likely that peeling will occur on the region 113 of the substrate 110 compared to when the planarizing layer 20 and the insulating layer 11 are in direct contact with each other.

[0023] A conductor pattern 32 is formed on the upper surface 31a of the conductor pattern 31, with an adhesive film 50 and a dielectric film 22 interposed therebetween. The conductor pattern 32 belongs to a conductor layer MM located between the conductor layers M1 and M2, and may constitute the upper electrode of a capacitor C. In this case, a capacitor C is formed in which the conductor pattern 31 serves as the lower electrode, the conductor pattern 32 serves as the upper electrode, and the dielectric film 22 serves as a capacitive insulating film. In the embodiment illustrated in Fig. 2, the thickness of the conductor layer MM is thinner than that of the conductor layers M1 and M2, thereby improving the pattern accuracy of the conductor layer MM.

[0024] The conductor layers M1, MM, and resistor element 40 are embedded in the insulating layer 11. The conductor layer M2 is a second conductor layer provided on the surface of the insulating layer 11 and includes conductor patterns 33 to 35. The conductor pattern 33 is connected to a conductor pattern 32, which may constitute an upper electrode of the capacitor C, through a via provided in the insulating layer 11. In the example shown in FIG. 2, the conductor pattern 34 is connected to one end of the resistor element 40 through a via conductor 34V embedded in a via V1 that penetrates the insulating layer 11 and the dielectric film 21. In the example shown in FIG. 2, the conductor pattern 35 is connected to the other end of the resistor element 40 through a via conductor 35V embedded in a via V2 that penetrates the insulating layer 11 and the dielectric film 21. The conductor layer M2 is embedded in the insulating layer 12. The terminal electrodes 131 to 134 shown in FIG. 1 are provided on the surface of the insulating layer 12, for example.

[0025] As described above, the electronic component 100 according to this embodiment includes the adhesive film 50, which improves adhesion at the interface between the conductor layer M1 and the dielectric film 22. Moreover, the resistive element 40 is covered with the dielectric film 21, which prevents direct contact between the resistive element 40 and the insulating layer 11. The dielectric film 21 is located between the conductor pattern 31 and the planarizing layer 20 and is in contact with the lower surface 31c of the conductor pattern 31. Therefore, by selecting a material for the dielectric film 21 that has higher adhesion to the conductor pattern 31 than the planarizing layer 20, it is also possible to prevent peeling of the conductor pattern 31.

[0026] Next, a method for manufacturing the electronic component 100 according to this embodiment will be described.

[0027] 3 to 11 are process diagrams illustrating the manufacturing method of electronic component 100 according to this embodiment. In the manufacturing process of electronic component 100, a large number of electronic components 100 are obtained using an aggregate substrate, but the manufacturing process shown in FIGS. 3 to 11 focuses on a single electronic component 100.

[0028] First, as shown in FIG. 3 , a planarization layer 20 is formed on the surface of a substrate 110 using a sputtering method or the like, and the surface is smoothed by grinding or mirror-finishing treatment such as CMP. Thereafter, a resistance element 40 is formed on the surface of the planarization layer 20 located in a region 112 using a sputtering method or the like. Next, as shown in FIG. 4 , a dielectric film 21 is formed on the entire surface including the region 112 where the resistance element 40 is formed. As a result, the resistance element 40 is covered with the dielectric film 21. The dielectric film 21 can be formed by a method such as sputtering, plasma CVD, MOCVD, sol-gel, or electron beam evaporation. The dielectric film 22, which will be described later, can also be formed by a similar method.

[0029] Next, as shown in FIG. 5 , a conductor layer M1 including a conductor pattern 31 is formed on the surface of the dielectric film 21 located in region 111. The conductor layer M1 can be formed, for example, by forming a seed layer over the entire surface, forming a resist layer on the seed layer, patterning the resist layer so that the seed layer in the region where the conductor layer M1 is to be formed is exposed, and then performing electrolytic plating using the seed layer as a power source. The resist layer is then removed, and the seed layer exposed on the surface is removed, completing the conductor layer M1. The seed layer can be removed by etching such as ion milling.

[0030] Next, as shown in FIG. 6 , an adhesive film 50 is formed on the entire surface of the conductor layer M1, including the top and side surfaces, using, for example, a sputtering method. As a result, the top surface 31 a and side surface 31 b of the conductor pattern 31 and the surface of the dielectric film 21 exposed from the conductor layer M1 are covered with the adhesive film 50. The adhesive film 50 is in contact with the conductor pattern 31, achieving high adhesion between them. Furthermore, as shown in FIG. 7 , a dielectric film 22 is formed on the entire surface, thereby covering the surface of the adhesive film 50 with the dielectric film 22. As a result, the top surface 31 a and side surface 31 b of the conductor pattern 31 are covered with a laminated film of the adhesive film 50 and the dielectric film 22, and regions 112 to 114 of the substrate 110 where no conductor pattern is formed on the conductor layer M1 are covered with a laminated film of the adhesive film 50 and the dielectric film 22. The dielectric film 22 is in contact with the adhesive film 50, achieving high adhesion between them. 2, a conductor pattern 32 may be formed on at least a portion of the upper surface 31a of the conductor pattern 31 via an adhesive film 50 and a dielectric film 22 by using a method similar to that used to form the conductor layer M1. This completes the conductor layer MM. The conductor patterns 31 and 32 may be the lower and upper electrodes of the capacitor C, respectively.

[0031] Next, as shown in FIG. 8 , a resist layer 60 is formed to cover the conductor pattern 31 and its surroundings. Then, as shown in FIG. 9 , the dielectric film 22 is patterned using the resist layer 60 as a mask. The dielectric film 22 can be patterned by, for example, RIE (reactive ion etching). As a result, the dielectric film 22 exposed from the resist layer 60 is removed, exposing the adhesive film 50. The patterning of the dielectric film 22 is performed under conditions where the etching rate for the adhesive film 50 is sufficiently lower than the etching rate for the dielectric film 22, so that the adhesive film 50 functions as an etching stopper. Next, as shown in FIG. 10 , the adhesive film 50 is patterned using the resist layer 60 as a mask. The patterning of the adhesive film 50 can be performed by, for example, ion milling or wet etching. As a result, the adhesive film 50 exposed from the resist layer 60 is removed, exposing the dielectric film 21. The patterning of the adhesive film 50 is performed under conditions where the etching rate for the dielectric film 21 is sufficiently lower than the etching rate for the adhesive film 50, so that the dielectric film 21 functions as an etching stopper. In this way, by sequentially performing two patterning processes under different conditions using the same resist layer 60, the dielectric film 22 and the adhesive film 50 are patterned in this order.

[0032] As a result, the dielectric film 21 is exposed on regions 112 and 113 of the substrate 110. Because region 114 of the substrate 110 is covered with the resist layer 60, the laminated film of the adhesion film 50 and the dielectric film 22 formed on region 114 of the substrate 110 remains. As a result, an end face 50s of the adhesion film 50 and an end face 22s of the dielectric film 22 are formed on the boundary between regions 113 and 114 of the substrate 110. Since the dielectric film 21 on regions 112 and 113 is exposed to an etching environment when patterning the adhesion film 50, the surface roughness of its surface 21a increases and its film thickness decreases. As a result, the surface roughness of the surface 21a of the dielectric film 21 on regions 112 and 113 becomes greater than the surface roughness of the surface 21b of the dielectric film 21 and the surface roughness of the surface 22a of the dielectric film 22 on regions 111 and 114. Furthermore, the thickness of the dielectric film 21 on the regions 112 and 113 is thinner than the thickness of the dielectric film 21 on the regions 111 and 114 .

[0033] 11 , an insulating layer 11 is formed in which conductor layers M1, MM, and resistor element 40 are embedded, and then vias V1 to V3 are formed through insulating layer 11. Vias V1 and V2 also penetrate dielectric film 21, exposing one end and the other end of resistor element 40, respectively. Via V3 exposes conductor pattern 32. Via conductors 34V, 35V, and 33V are then formed inside vias V1 to V3, respectively, and conductor layer M2 including conductor patterns 33 to 35 is formed on the surface of insulating layer 11. Furthermore, an insulating layer 12 is formed in which conductor layer M2 is embedded, and terminal electrodes 131 to 134 are formed on its surface, completing electronic component 100 according to this embodiment.

[0034] As described above, in the method for manufacturing electronic component 100 according to the present embodiment, adhesive film 50 and dielectric film 22 are successively formed, and then conductor pattern 32, which serves as the upper electrode, is formed without patterning these films. This makes it difficult for foreign matter to get between conductor pattern 31, which serves as the lower electrode, and conductor pattern 32, which serves as the upper electrode. For example, compared to a method in which adhesive film 50 is patterned after it is formed and before dielectric film 22 is formed, in the method for manufacturing electronic component 100 according to the present embodiment, residues of the resist layer used for patterning are less likely to remain on the surface of adhesive film 50. In this embodiment, patterning of adhesive film 50 and dielectric film 22 is not performed until conductor pattern 32 is formed, and the laminated film of adhesive film 50 and dielectric film 22 is patterned after conductor pattern 32 is formed. As a result, compared to a method in which, for example, adhesive film 50 and dielectric film 22 are successively formed and then patterned before forming conductor pattern 32, which is the upper electrode, the method for manufacturing electronic component 100 according to this embodiment makes it less likely that foreign matter such as residues of a resist layer will remain between conductor pattern 31, which is the lower electrode, and conductor pattern 32, which is the upper electrode. This improves the reliability of capacitor C when conductor patterns 31 and 32 respectively form the lower electrode and upper electrode of capacitor C.

[0035] Furthermore, since the dielectric film 22 and the adhesive film 50 are patterned sequentially using the same resist layer 60, the number of steps can be reduced. Moreover, the adhesive film 50, which is the underlying layer, functions as an etching stopper when patterning the dielectric film 22, and the dielectric film 21, which is the underlying layer, functions as an etching stopper when patterning the adhesive film 50, so that the dielectric film 21 covering the resistance element 40 is not removed by etching. As a result, the resistance element 40 is reliably covered by the dielectric film 21, so that contact between the resistance element 40 and the insulating layer 11 does not occur, and reliability can be improved.

[0036] FIG. 12 is a schematic cross-sectional view of an electronic component 200 according to a modified example.

[0037] The electronic component 200 shown in Fig. 12 differs from the electronic component 100 shown in Fig. 2 in that a dielectric film 23 (sometimes referred to as a third dielectric film) is added. The other basic configuration is the same as that of the electronic component 100 shown in Fig. 2, and therefore the same elements are denoted by the same reference numerals and redundant explanations will be omitted.

[0038] The dielectric film 23 is formed immediately before the insulating layer 11 is formed. That is, it is formed between the step shown in Fig. 10 and the step shown in Fig. 11. The dielectric film 23 is made of silicon nitride (Si ３ N ４ The dielectric film 23 may be made of the same inorganic insulating material as the dielectric films 21, 22, such as silicon nitride (Si). The dielectric film 23 prevents direct contact between the conductor pattern 32 and the insulating layer 11 by covering the top surface 32a and side surface 32b of the conductor pattern 32 that constitutes the upper electrode. For example, if the insulating layer 11 is made of an organic insulating material such as polyimide resin, even if moisture is absorbed into the insulating layer 11, the dielectric film 23 can reduce the influence on other circuit elements. Specifically, by preventing direct contact between the conductor pattern 32 and the insulating layer 11 by the dielectric film 23, the influence of moisture on the conductor pattern 32 (e.g., a decrease in the reliability of the conductor pattern 32) can be reduced. In the electronic component 200 shown in FIG. 12, the top surface 32a and side surface 32b of the conductor pattern 32 are made of silicon nitride (Si ３ N ４ Since the conductive pattern 32 is covered with the dielectric film 23 made of an inorganic insulating material such as silicon nitride (Si), the moisture resistance is improved and the reliability of the conductive pattern 32 is enhanced. ３ N ４ In the case where the dielectric film 23 is made of silicon nitride (Si ), almost the entire surface of the conductor pattern 32, including the upper surface 32a, the side surface 32b, and the lower surface 32c, is in contact with the same inorganic insulating material, so that local stress is less likely to be applied to the conductor pattern 32. ３ N ４ ) makes it difficult for the metal material such as copper (Cu) that forms the conductor pattern 32 to diffuse into the insulating layer 11 .

[0039] 12 , the dielectric film 23 may be formed, for example, over the entire surface. As a result, the dielectric film 23 is formed not only on the upper surface 32 a and the side surface 32 b of the conductor pattern 32, but also on the portion of the surface of the dielectric film 22 that is not covered by the conductor pattern 32, and on the portion of the surface of the dielectric film 21 that is not covered by the dielectric film 22. Furthermore, the end face 50 s of the adhesive film 50 and the end face 22 s of the dielectric film 22 are located on the boundary between the region 113 and the region 114 of the substrate 110. These end faces 50 s, 22 s are also covered with the dielectric film 23. As a result, the end face 50 s of the adhesive film 50 and the insulating layer 11 are not in direct contact with each other, and therefore corrosion of the adhesive film 50 can be prevented.

[0040] The thickness of the dielectric film 23 may be thinner than the thickness of the dielectric film 22. This is because, when the dielectric film 22 is used as a capacitive insulating film of the capacitor C, its thickness is determined by the capacitance required for the capacitor C and a certain thickness is required to achieve a sufficient withstand voltage, whereas the dielectric film 23 is used to protect the conductor pattern 32 and the adhesive film 50, and therefore these functions can be achieved even if the thickness is thinner than the dielectric film 22. Furthermore, if the thickness of the dielectric film 23 is made thinner than the thickness of the dielectric film 22, the process time required to form the dielectric film 23 can be shortened.

[0041] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.

[0042] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0043] 2, for example, the conductor pattern 31 and the conductor pattern 32 form the capacitor C, but the conductor pattern 31 is not limited to this. The conductor pattern 31 may be, for example, another element formed on the M1 layer (e.g., a circuit element such as an inductor, a connection pattern or electrode that connects between the circuit elements, etc.). Furthermore, in the embodiment shown in FIG. 2, the electronic component 100 includes the conductor layers M1, MM, and M2 and the insulating layers 11 and 12, but is not limited thereto and may include more conductor layers and insulating layers.

[0044] According to one aspect of the present disclosure, an electronic component includes a substrate including a first region and a second region spaced apart from the first region, a resistive element formed in the second region, a first dielectric film covering the first region and the resistive element, a first conductor pattern formed in the first region via the first dielectric film, an adhesive film covering an upper surface and side surfaces of the first conductor pattern without covering the second region, and a second dielectric film covering the upper surface and side surfaces of the first conductor pattern via the adhesive film. This improves adhesion between the first conductor pattern and the second dielectric film in the electronic component including the resistive element, making it possible to prevent peeling at the interface between them.

[0045] In the electronic component, the surface roughness of the second dielectric film may be smaller than the surface roughness of the first dielectric film in the second region, thereby improving the reliability of the capacitor when the second dielectric film is used as a capacitive insulating film of the capacitor.

[0046] In the electronic component, the substrate may further include a third region located between the first region and the second region, and the third region may be covered with the first dielectric film without being covered with the adhesive film, thereby making it possible to prevent short-circuit defects through the adhesive film.

[0047] In the electronic component, the substrate may further include a fourth region located between the first region and the third region, and the fourth region may be covered with the first dielectric film, the adhesive film, and the second dielectric film, thereby more effectively preventing peeling at the interface between the first conductor pattern and the second dielectric film.

[0048] In the electronic component, the surface roughness of the first dielectric film in the fourth region may be smaller than the surface roughness of the first dielectric film in the second region, thereby improving adhesion between the first dielectric film in the second region and an insulating layer made of an organic insulating material, even when the first dielectric film in the second region is in contact with the insulating layer.

[0049] The electronic component may further include a planarization layer formed on the first region and the second region of the substrate, and the resistive element may be provided on the planarization layer, thereby preventing contact between the substrate and the resistive element.

[0050] The electronic component may further include a second conductor pattern covering at least a portion of the upper surface of the first conductor pattern via the adhesive film and the second dielectric film, and the first conductor pattern, the second dielectric film, and the second conductor pattern may form a capacitor, thereby providing an electronic component having a highly reliable capacitor.

[0051] The electronic component may further include an insulating layer in which the first conductor pattern and the adhesive film are embedded, and a third conductor pattern provided on the insulating layer, wherein the third conductor pattern is connected to the resistive element through a via conductor provided to penetrate the insulating layer and the first dielectric film, thereby enabling electrical connection between the resistive element and the third conductor pattern.

[0052] The electronic component may further include a third dielectric film that covers the second dielectric film in the first region and the first dielectric film in the second region, thereby making it possible to protect the end faces of the adhesive film 50 with the third dielectric film.

[0053] In the electronic component, the thickness of the first dielectric film in the first region may be greater than the thickness of the first dielectric film in the second region, thereby reducing stress in the first dielectric film in the second region.

[0054] A method for manufacturing an electronic component according to one aspect of the present disclosure includes the steps of: forming a resistive element in a second region of a substrate having a first region and a second region; covering the first region and the resistive element with a first dielectric film; forming a first conductor pattern on a surface of the first dielectric film located on the first region; forming an adhesive film on the first and second regions so as to contact the first conductor pattern; forming a second dielectric film on the first and second regions so as to contact the adhesive film; forming a resist that covers the second dielectric film located in the first region and exposes the second dielectric film located in the second region; removing the second dielectric film using the resist as a mask; and removing the adhesive film using the resist as a mask. This method enables unnecessary portions of the second dielectric film and the adhesive film to be removed with a small number of steps.

[0055] In the method for manufacturing an electronic component described above, the step of removing the second dielectric film may be performed under conditions in which the etching rate for the second dielectric film is higher than that for the adhesion film, and the step of removing the adhesion film may be performed under conditions in which the etching rate for the adhesion film is higher than that for the first dielectric film, whereby the adhesion film functions as an etching stopper in the step of removing the second dielectric film, and the first dielectric film functions as an etching stopper in the step of removing the adhesion film.

[0056] The method for manufacturing an electronic component may further include, after forming the second dielectric film and before forming the resist, forming a second conductor pattern on the second dielectric film so as to overlap the first conductor pattern, thereby enabling the first conductor pattern, the second dielectric film, and the second conductor pattern to form a capacitor.

[0057] The method for manufacturing an electronic component may further include the steps of, after removing the resist, forming an insulating layer in which the first conductor pattern and the adhesive film are embedded, forming a via that penetrates the insulating layer and the first dielectric film to expose a portion of the resistor element, and forming a via conductor that is embedded in the via and contacts the resistor element, thereby enabling electrical connection of the resistor element to an upper conductor layer.

[0058] 11, 12 Insulating layer 20 Planarizing layer 21-23 Dielectric film 21a, 21b, 22a Surface of dielectric film 22s End face of dielectric film 31-35 Conductive pattern 31a, 32a Upper face of conductive pattern 31b, 32b Side face of conductive pattern 31c, 32c Lower face of conductive pattern 33V-35V Via conductor 40 Resistive element 50 Adhesion film 50s End face of adhesion film 60 Resist layer 100 Electronic component 110 Substrate 111-114 Region 120 Functional layer 131-134 Terminal electrode 200 Electronic component C Capacitor M1, MM, M2 Conductive layer V1-V3 Via

Claims

1. An electronic component comprising: a substrate including a first region and a second region spaced apart from the first region; a resistive element formed in the second region; a first dielectric film covering the first region and the resistive element; a first conductor pattern formed in the first region via the first dielectric film; an adhesive film covering an upper surface and side surfaces of the first conductor pattern without covering the second region; and a second dielectric film covering the upper surface and side surfaces of the first conductor pattern via the adhesive film.

2. The electronic component according to claim 1, wherein the surface roughness of the second dielectric film is smaller than the surface roughness of the first dielectric film in the second region.

3. The electronic component according to claim 1, wherein the substrate further includes a third region located between the first region and the second region, and the third region is not covered by the adhesive film but is covered by the first dielectric film.

4. The electronic component according to claim 3, wherein the substrate further includes a fourth region located between the first region and the third region, and the fourth region is covered with the first dielectric film, the adhesion film and the second dielectric film.

5. The electronic component according to claim 4, wherein the surface roughness of said first dielectric film in said fourth region is smaller than the surface roughness of said first dielectric film in said second region.

6. The electronic component according to claim 1, further comprising a planarization layer formed on the first and second regions of the substrate, the resistor element being provided on the planarization layer.

7. The electronic component according to any one of claims 1 to 6, further comprising a second conductor pattern covering at least a portion of the upper surface of the first conductor pattern via the adhesive film and the second dielectric film, wherein a capacitor is formed by the first conductor pattern, the second dielectric film, and the second conductor pattern.

8. An electronic component as claimed in any one of claims 1 to 6, further comprising: an insulating layer in which the first conductor pattern and the adhesive film are embedded; and a third conductor pattern provided on the insulating layer, the third conductor pattern being connected to the resistive element through a via conductor provided to penetrate the insulating layer and the first dielectric film.

9. The electronic component according to any one of claims 1 to 6, further comprising a third dielectric film covering the second dielectric film in the first region and covering the first dielectric film in the second region.

10. An electronic component according to any one of claims 1 to 6, wherein the thickness of the first dielectric film in the first region is greater than the thickness of the first dielectric film in the second region.

11. A method for manufacturing an electronic component, comprising the steps of: forming a resistive element in a second region of a substrate having a first region and a second region; covering the first region and the resistive element with a first dielectric film; forming a first conductor pattern on a surface of the first dielectric film located on the first region; forming an adhesion film on the first and second regions so as to be in contact with the first conductor pattern; forming a second dielectric film on the first and second regions so as to be in contact with the adhesion film; forming a resist that covers the second dielectric film located in the first region and exposes the second dielectric film located in the second region; removing the second dielectric film using the resist as a mask; and removing the adhesion film using the resist as a mask.

12. A method for manufacturing an electronic component as described in claim 11, wherein the step of removing the second dielectric film is performed under conditions in which the etching rate for the second dielectric film is higher than the etching rate for the adhesion film, and the step of removing the adhesion film is performed under conditions in which the etching rate for the adhesion film is higher than the etching rate for the first dielectric film.

13. The method for manufacturing an electronic component according to claim 11, further comprising the step of forming a second conductor pattern on the second dielectric film so as to overlap the first conductor pattern after forming the second dielectric film and before forming the resist.

14. A method for manufacturing an electronic component as described in any one of claims 11 to 13, further comprising the steps of: after removing the resist, forming an insulating layer in which the first conductor pattern and the adhesive film are embedded; forming a via that penetrates the insulating layer and the first dielectric film and exposes a portion of the resistive element; and forming a via conductor that is embedded in the via and contacts the resistive element.

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