Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes: a source electrode including a drift region having a first conductivity type, a body region provided over the drift region and having a second conductivity type different from the first conductivity type, and a source region provided over the body region so as to be spaced apart from the drift region and having the first conductivity type, the source electrode being electrically connected to the source region; and a drain electrode electrically connected to the drift region. When the first output capacitance is defined as Coss1 with a voltage of 1 V applied between the source electrode and the drain electrode, and the second output capacitance is defined as Coss100 with a voltage of 100 V applied between the source electrode and the drain electrode, the value expressed by "(Coss1-Coss100) / Coss100" is 20 or less.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2023-204484 filed on December 4, 2023, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] As one of silicon carbide semiconductor devices, a trench MOSFET (metal oxide semiconductor field effect transistor) in which a current diffusion region is provided in a drift region has been disclosed.

[0004] Japanese Patent Application Publication No. 2021-182639

[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drift region, wherein when a first output capacitance is Coss1 when a voltage of 1 V is applied between the source electrode and the drain electrode, and a second output capacitance is Coss100 when a voltage of 100 V is applied between the source electrode and the drain electrode, a value represented by "(Coss1-Coss100) / Coss100" is 20 or less.

[0006] Fig. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to an embodiment. Fig. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to an embodiment. Fig. 3 is a diagram showing the relationship between parameters and softness factors.

[0007] [Problem to be Solved by the Present Disclosure] In conventional silicon carbide semiconductor devices, there is a risk of large electromagnetic noise being generated during reverse recovery operation of the body diode.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can suppress electromagnetic noise.

[0009] [Effects of the Present Disclosure] According to the present disclosure, electromagnetic noise can be suppressed.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are denoted by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of a silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drift region, wherein a value represented by "(Coss1-Coss100) / Coss100" is 20 or less, where Coss1 is a first output capacitance when a voltage of 1 V is applied between the source electrode and the drain electrode, and Coss100 is a second output capacitance when a voltage of 100 V is applied between the source electrode and the drain electrode.

[0013] The value expressed by "(Coss1-Coss100) / Coss100" reflects the magnitude of change in output capacitance during reverse recovery of the body diode parasitic on the silicon carbide semiconductor device. When this value is 20 or less, the change in output capacitance is small, and electromagnetic noise associated with the change in output capacitance can be suppressed.

[0014] [2] In the device of [1], a gate trench may be provided in the first main surface, the gate trench having a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, a gate insulating film that contacts the side surface and the bottom surface of the gate trench, and a gate electrode that is provided on the gate insulating film so as to sandwich the gate insulating film between the gate insulating film and the silicon carbide substrate. In this case, on-resistance is reduced and conduction loss is likely to be reduced.

[0015] [3] In [2], an electric field relaxation region of the second conductivity type may be provided below the body region, in contact with the body region, and the distance between a lower end surface of the electric field relaxation region and the second main surface may be smaller than the distance between the bottom surface and the second main surface. In this case, the voltage applied to the gate insulating film may be more easily relaxed.

[0016] [4] In [3], the distance between the lower end surface of the electric field buffer region and the second main surface may be 0.2 to 0.5 times the distance between the bottom surface and the second main surface, which makes it easy to reduce noise during switching operations and to avoid an excessive increase in on-resistance.

[0017] [5] In [3] or [4], the gate trench may extend along a first axis parallel to the first main surface, a plurality of the gate trenches may be provided in the first main surface at a constant first pitch along a second axis parallel to the first main surface and perpendicular to the first axis, the silicon carbide substrate may have the electric field relaxation region on both sides of the gate trench in a cross section perpendicular to the first axis, and a distance between the electric field relaxation regions may be 0.5 times or less the first pitch. In this case, noise during switching operation may be easily reduced.

[0018] [6] In [5], the distance between the electric field buffer regions may be 0.2 to 0.5 times the first pitch, which makes it easier to avoid an excessive increase in on-resistance.

[0019] [7] In any one of [2] to [6], the drift region may have a first semiconductor region in contact with the side surface and the body region, and a second semiconductor region provided between the first semiconductor region and the second main surface and in contact with the first semiconductor region, wherein a first effective concentration of the first conductivity type impurity in the first semiconductor region is higher than a second effective concentration of the first conductivity type impurity in the second semiconductor region. In this case, an on-current is likely to flow in a wide range of the drift region, and on-resistance is likely to be reduced.

[0020] [8] In [7], the maximum value of the third effective concentration of the second conductivity type impurity in the body region may be 10 to 100 times the maximum value of the first effective concentration. In this case, it is easy to make the value expressed by "(Coss1-Coss100) / Coss100" 20 or less, and it is easy to suppress electromagnetic noise.

[0021] [9] In any one of [2] to [8], the conductivity type of the semiconductor between the bottom surface and the second main surface may be the first conductivity type. In this case, the on-resistance is more likely to be reduced.

[0022]

[10] In any one of [2] to [9], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0023] [Embodiments of the Present Disclosure] An embodiment of the present disclosure relates to a so-called vertical MOS field effect transistor (FET) using silicon carbide, and this MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0024] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the embodiment mainly has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0025] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0026] The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8 degrees or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8 degrees or less in the off direction. The first main surface 1 may be a (0001) plane or a (0001) plane tilted at an off angle of 8 degrees or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 degree or more, or 2 degrees or more. The off angle may be 6 degrees or less, or 4 degrees or less.

[0027] The silicon carbide epitaxial layer 40 mainly includes a drift region 11 , a body region 12 , a source region 13 , an electric field reduction region 14 , and a contact region 18 .

[0028] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 mainly has a first region 11A and a second region 11B.

[0029] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0030] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0031] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first major surface 1. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and a portion of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first major surface 1 and the second major surface 2. In a cross-sectional view perpendicular to the Y axis, an angle θ1 of the side surfaces 3 with respect to an imaginary plane 31 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The Y axis is an example of the first axis, and the X axis is an example of the second axis.

[0032] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0033] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0034] The electric field relaxation region 14 contains p-type impurities such as aluminum and has p-type conductivity. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 is located between adjacent gate trenches 5 along the X-axis. The electric field relaxation region 14 is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The electric field relaxation region 14 is spaced apart from the gate trench 5 along the X-axis relative to the body region 12. The electric field relaxation region 14 is located below the body region 12 and in contact with the body region 12. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 overlaps the contact region 18. The electric field relaxation region 14 may be in contact with the body region 12 and the contact region 18. The electric field relaxation region 14 may extend along the Y-axis. Multiple electric field relaxation regions 14 are arranged at regular intervals along the X-axis. Multiple electric field relaxation regions 14 may be arranged in an array. A lower end surface 15 of the electric field relaxation region 14 is closer to the second main surface 2 than the bottom surface 4. That is, distance L2 between lower end surface 15 of electric field relaxation region 14 and second main surface 2 is smaller than distance L3 between bottom surface 4 and second main surface 2. Lower end surface 15 of electric field relaxation region 14 is the surface facing silicon carbide single crystal substrate 50. Contact region 18, body region 12, and electric field relaxation region 14 are electrically connected to one another.

[0035] The first region 11A of the drift region 11 is exposed to the side surface 3 and is in contact with the body region 12 and the electric field relaxation region 14. The thickness of the first region 11A is, for example, 0.1 μm or more and 0.6 μm or less. The second region 11B of the drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The first region 11A is located between the second region 11B and the body region 12. The lower end surface of the first region 11A is in contact with the upper end surface of the second region 11B. The second region 11B may be exposed to the side surface 3. The second region 11B may be exposed to the bottom surface 4. The lower end surface of the first region 11A may be on an imaginary plane 31 including the bottom surface 4, or may be closer to the first main surface 1 than the imaginary plane 31. The first region 11A is an example of a first semiconductor region, and the second region 11B is an example of a second semiconductor region.

[0036] The second effective concentration of the n-type impurity in the second region 11B is lower than the first effective concentration of the n-type impurity in the first region 11A. For example, the second effective concentration is 1×10 １６ cm －３ 1x10 or more １７ cm －３ and the first effective concentration is 1×10 １７ cm －３ 1x10 or more １８ cm －３ The first region 11A is sometimes called a current spreading region.

[0037] The maximum value of the third effective concentration of the p-type impurity in the body region 12 is higher than the maximum value of the first effective concentration, for example, 10 to 100 times the maximum value of the first effective concentration.

[0038] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type. Along the Z axis, no semiconductor of conductivity type p-type exists between bottom surface 4 and second main surface 2.

[0039] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the second region 11B at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 contacts the first region 11A and the second region 11B at the side surface 3. As long as the gate insulating film 81 contacts the first region 11A at the side surface 3, it does not have to contact the second region 11B. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0040] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0041] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0042] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged so that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0043] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0044] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0045] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0046] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a part of source electrode 60 may be provided.

[0047] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 may be, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The effective concentration of p-type impurities in the body region 12 is 5×10 １７ cm －３ 1x10 or more １８ cm －３ The following is the result.

[0048] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 １９ cm －３ The effective concentration of the p-type impurity in the electric field relaxation region 14 is, for example, 5×10 １７ cm －３ 5x10 or more １８ cm －３ The following is the result.

[0049] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0050] Drift region 11 has n-type conductivity, and body region 12 and electric field relaxation region 14 have p-type conductivity. Therefore, the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and electric field relaxation region 14 are clear.

[0051] In silicon carbide semiconductor device 100, parameter P expressed by "(Coss1-Coss100) / Coss100" is equal to or less than 20. Here, Coss1 is the first output capacitance when a voltage of 1 V is applied between source electrode 60 and drain electrode 70, and Coss100 is the second output capacitance when a voltage of 100 V is applied between source electrode 60 and drain electrode 70.

[0052] A body diode is parasitic on silicon carbide semiconductor device 100. During reverse recovery of the body diode, the voltage VDS between source electrode 60 and drain electrode 70 increases, causing a depletion layer to extend from the PN junction interface, resulting in a decrease in output capacitance. The more abrupt the decrease in output capacitance, the greater the induced voltage superimposed on voltage VDS of silicon carbide semiconductor device 100 via the inductance of the inductive load connected to silicon carbide semiconductor device 100. As a result, silicon carbide semiconductor device 100 is overloaded, and voltage VDS oscillates, making it more likely to generate electromagnetic noise. In contrast, if parameter P is 20 or less, a rapid decrease in output capacitance during reverse recovery of the body diode can be suppressed, thereby suppressing electromagnetic noise. Parameter P may be 15 or less, or may be 10 or less.

[0053] When the gate trench 5 is provided and a so-called trench gate structure is adopted, it is easy to reduce the on-resistance and the conduction loss.

[0054] When the distance L2 between the lower end surface 15 of the electric field relaxation region 14 and the second main surface 2 is smaller than the distance L3 between the bottom surface 4 and the second main surface 2, the electric field applied to the gate insulating film 81 is easily relaxed. When the distance L2 is 0.5 times the distance L3 or less, electromagnetic noise during switching operations is easily reduced. When the distance L2 is 0.4 times the distance L3 or less, electromagnetic noise during switching operations is easily reduced. Furthermore, when the distance L2 is 0.2 times the distance L3 or more, an excessive increase in on-resistance is easily avoided.

[0055] The distance L1 between two electric field relaxation regions 14 sandwiching the gate trench 5 therebetween in a plan view perpendicular to the first main surface 1 may be, for example, 0.5 times the first pitch P1 or less. The distance L1 is the distance between the side end surfaces 16 of two adjacent electric field relaxation regions 14 sandwiching the gate trench 5 therebetween. When the distance L1 is 0.5 times the first pitch P1 or less, electromagnetic noise during switching operation is easily reduced. When the distance L1 is 0.4 times the first pitch P1 or less, electromagnetic noise during switching operation is easily reduced. Furthermore, when the distance L1 is 0.2 times the first pitch P1 or more, an excessive increase in on-resistance is easily avoided.

[0056] When the first effective concentration in the first region 11A of the drift region 11 is higher than the second effective concentration in the second region 11B, the on-current tends to flow over a wide range of the drift region 11, and the on-resistance tends to be reduced.

[0057] When the maximum value of the third effective concentration of the p-type impurity in the body region 12 is 10 to 100 times the maximum value of the first effective concentration, it is easy to set the parameter P to 20 or less, and it is easy to suppress electromagnetic noise. The maximum value of the third effective concentration of the p-type impurity in the body region 12 may be 20 to 90 times, or 30 to 80 times, the maximum value of the first effective concentration.

[0058] Along the Z axis, if the conductivity type of the semiconductor (silicon carbide substrate 10) between the bottom surface 4 and the second main surface 2 is n-type and there is no semiconductor with p-type conductivity between the bottom surface 4 and the second main surface 2, the on-resistance is more likely to be reduced.

[0059] The inventors of the present application fabricated various MOSFETs with different values ​​of parameter P and measured the softness factor in reverse recovery of the body diode. The results are shown in FIG. 3. FIG. 3 is a diagram showing the relationship between parameter P and softness factor. Parameter P was changed by changing the distance L1 between electric field relaxation regions 14 relative to first pitch P1. When L1 / P1 was 0.7, parameter P was 30; when L1 / P1 was 0.5, parameter P was 20; and when L1 / P1 was 0.4, parameter P was 10.

[0060] As shown in Figure 3, when the parameter P was 20 or less, the softness factor was 0.4 or more. The softness factor reflects the gradualness of the change in the voltage VDS during the reverse recovery operation of the body diode, and the higher the softness factor, the more gradual the change in the voltage VDS and the more electromagnetic noise is suppressed. The results shown in Figure 3 also show that a parameter P of 20 or less is effective in suppressing electromagnetic noise.

[0061] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0062] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11A First region 11B Second region 12 Body region 13 Source region 14 Electric field relaxation region 15 Lower end surface 16 Side end surface 18 Contact region 31 Virtual plane 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 90 Contact hole 100 Silicon carbide semiconductor device L1, L2, L3 Distance P1 First pitch θ1 Angle

Claims

1. A silicon carbide semiconductor device comprising: a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type provided on the body region so as to be separated from the drift region; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drift region, wherein: when a first output capacitance is Coss1 when a voltage of 1 V is applied between the source electrode and the drain electrode, and a second output capacitance is Coss100 when a voltage of 100 V is applied between the source electrode and the drain electrode, a value represented by "(Coss1-Coss100) / Coss100" is 20 or less.

2. The silicon carbide semiconductor device according to claim 1, wherein a gate trench is provided in the first main surface, the gate trench having a side surface that penetrates through the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, a gate insulating film in contact with the side surface and the bottom surface of the gate trench, and a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate insulating film and the silicon carbide substrate.

3. The silicon carbide semiconductor device according to claim 2, further comprising an electric field relaxation region provided below said body region, in contact with said body region, and having said second conductivity type, wherein a distance between a lower end surface of said electric field relaxation region and said second main surface is smaller than a distance between said bottom surface and said second main surface.

4. The silicon carbide semiconductor device according to claim 3, wherein the distance between a lower end surface of said electric field relaxation region and said second main surface is equal to or greater than 0.2 times and equal to or less than 0.5 times the distance between said bottom surface and said second main surface.

5. The silicon carbide semiconductor device according to claim 3 or 4, wherein the gate trench extends along a first axis parallel to the first main surface, a plurality of the gate trenches are provided in the first main surface at a constant first pitch along a second axis parallel to the first main surface and perpendicular to the first axis, and in a cross-sectional view perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation regions on both sides of the gate trench, and a distance between the electric field relaxation regions is 0.5 times or less the first pitch.

6. The silicon carbide semiconductor device according to claim 5, wherein a distance between said electric field relaxation regions is not less than 0.2 times and not more than 0.5 times said first pitch.

7. The silicon carbide semiconductor device according to any one of claims 2 to 6, wherein the drift region has: a first semiconductor region in contact with the side surface and the body region; and a second semiconductor region provided between the first semiconductor region and the second main surface and in contact with the first semiconductor region, and a first effective concentration of the first conductivity type impurity in the first semiconductor region is higher than a second effective concentration of the first conductivity type impurity in the second semiconductor region.

8. The silicon carbide semiconductor device according to claim 7, wherein a maximum value of a third effective concentration of the impurity of the second conductivity type in said body region is not less than 10 times and not more than 100 times the maximum value of said first effective concentration.

9. The silicon carbide semiconductor device according to claim 2, wherein a conductivity type of a semiconductor between said bottom surface and said second main surface is said first conductivity type.

10. The silicon carbide semiconductor device according to claim 2, wherein the side surface of the gate trench includes a {0-33-8} plane.

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