In-SITU process monitoring of photoresist using optical sensor

Abstract

An optical sensor system performs in-situ process monitoring of one or more photoresist processes. Photoresist processes may include deposition of photoresist, development, bevel edge and / or backside clean, bake, etch, and chamber clean operations. The optical sensor system may include a broadband light source and a spectral reflectometer. As the photoresist process proceeds, the optical sensor system provides incident light on a semiconductor substrate and receives reflected light. The spectral reflectometer measures an intensity of the reflected light over time, where changes in the intensity to the reflected light correlates with changes to a thickness or other material property of the photoresist over time, thereby monitoring a progress of the photoresist process and / or determining an endpoint of the photoresist process.

Description

IN-SITU PROCESS MONITORING OF PHOTORESIST USING OPTICAL SENSORINCORPORATION BY REFERENCE

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.FIELD

[0001] The present disclosure relates to photoresist processing in semiconductor fabrication, and more particularly to in-situ process monitoring of photoresist processing in deposition, bevel edge and / or backside clean, bake, development, chamber clean, and other photoresist-related operations in semiconductor fabrication.BACKGROUND

[0002] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. In general, the process includes the deposition of material on a wafer, and patterning the material through lithographic techniques to form structural features (e.g., transistors and circuitry) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing the substrate; applying a photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern, causing the exposed areas of the photoresist to become more or less soluble in a developer solution; developing by applying a developer solution to remove either the exposed or the unexposed areas of the photoresist; and subsequent processing to create features on the areas of the substrate from which the photoresist has been removed, such as by etching or material deposition.

[0003] The evolution of semiconductor design has created the need, and has been driven by the ability, to create ever smaller features on semiconductor substrate materials. This progression of technology has been characterized in “Moore’s Law” as a doubling of the density of transistors in dense integrated circuits every two years. Indeed, chip design and manufacturing has progressed such that modern microprocessors may contain billions of transistors and other circuit features on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or smaller, in some cases less than 10 nm.

[0004] One challenge in manufacturing devices having such small features is the ability to reliably and reproducibly create photolithographic masks having sufficient resolution. Currentphotolithography processes typically use 193 nm ultraviolet (UV) light to expose a photoresist. The fact that the light has a wavelength significantly greater than the desired size of the features to be produced on the semiconductor substrate creates inherent issues. Achieving feature sizes smaller than the wavelength of the light requires use of complex resolution enhancement techniques, such as multipatteming. Thus, there is significant interest and research effort in developing photolithographic techniques using shorter wavelength light, such as extreme ultraviolet radiation (EUV), having a wavelength of from 10 nm to 15 nm, e.g., 13.5 nm.

[0005] EUV photolithographic processes can present challenges, however, including low power output and loss of light during patterning. Traditional organic chemically amplified resists (CAR) similar to those used in 193 nm UV lithography have potential drawbacks when used in EUV lithography, particularly as they have low absorption coefficients in EUV region and the diffusion of photo-activated chemical species can result in blur or line edge roughness. Furthermore, in order to provide the etch resistance required to pattern underlying device layers, small features patterned in conventional CAR materials can result in high aspect ratios at risk of pattern collapse. Accordingly, there remains a need for improved EUV photoresist materials, having such properties as decreased thickness, greater absorbance, and greater etch resistance.

[0006] The background description provided herein is for the purpose of generally presenting the context of the present technology. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present technology.SUMMARY

[0007] Provided herein is a method of monitoring a photoresist process on a semiconductor substrate. The method includes performing a photoresist process in a process chamber involving the semiconductor substrate with a metal-containing EUV photoresist material, exposing the semiconductor substrate to incident radiation using an optical sensor, and monitoring changes to the metal-containing EUV photoresist material over time on the semiconductor substrate in the process chamber using the optical sensor.

[0008] In some implementations, performing the photoresist process includes depositing the metal-containing EUV photoresist material on the semiconductor substrate. In some implementations, performing the photoresist process includes baking the semiconductor substrate with the metal-containing EUV photoresist material formed thereon. In some implementations, performing the photoresist process includes developing the metal-containing EUV photoresistmaterial formed on the semiconductor substrate. In some implementations, monitoring the changes to the metal-containing EUV photoresist material over time includes receiving reflected radiation in the process chamber at the optical sensor, and measuring an intensity of the reflected radiation, where changes in the intensity of the reflected radiation over time is used to determine a progress of the photoresist process. In some implementations, the changes in the intensity of the reflected radiation is correlated with changes to a thickness of the metal-containing EUV photoresist material. In some implementations, the method further includes determining an endpoint of the photoresist process by determining that the intensity of the reflected radiation reached a threshold value. In some implementations, the optical sensor includes a spectral reflectometer. In some implementations, the optical sensor includes a broadband light source. In some implementations, the broadband light source is configured to emit radiation at a broadband range of wavelengths between about 200 nm and about 900 nm. In some implementations, the incident radiation is provided normal to a surface of the semiconductor substrate. In some implementations, the metal-containing EUV photoresist material comprises organotin oxide. In some implementations, the method further includes detecting a change in a functional group on the semiconductor substrate during the photoresist process using a Fourier Transform Infrared (FTIR) spectrometer or ultraviolet (UV) spectrometer. In some implementations, the incident radiation is provided through a window optically coupled to the process chamber. In some implementations, the method further includes heating the window to limit deposition or condensation of byproducts or other materials on the window. In some implementations, the window is configured to block transmission of UV radiation into the process chamber. In some implementations, the method further includes flowing one or more non-reactive gases in a region proximate to the window to limit deposition or condensation of byproducts or other materials on the window. In some implementations, the method further includes exposing the window to plasma in the process chamber to perform in-situ clean of materials formed on the window. In some implementations, monitoring changes to the metal-containing EUV photoresist material using the optical sensor includes monitoring changes to the metal-containing EUV photoresist material over time at a first position of the semiconductor substrate using a first optical sensor, and monitoring changes to the metal-containing EUV photoresist material over time at a second position of the semiconductor substrate using a second optical sensor. In some implementations, the first position corresponds to a center of the semiconductor substrate and where the second position corresponds to an edge of the semiconductor substrate. In some implementations, the optical sensor is integrated with a showerhead in the process chamber.

[0009] Also provided herein is an apparatus for performing a photoresist process. The apparatus includes a process chamber with a substrate support, where the substrate support is configured to support a semiconductor substrate, a vacuum line coupled to the process chamber, a gas line coupled to the process chamber, one or more optical sensors optically coupled to the process chamber, and a controller configured with instructions for performing the following operations: perform a photoresist process in the process chamber, where the photoresist process comprises depositing a metal-containing EUV photoresist material on the semiconductor substrate, baking the semiconductor substrate with the metal-containing EUV photoresist material formed thereon, or developing the metal-containing EUV photoresist material formed on the semiconductor substrate, expose the semiconductor substrate to incident radiation using the optical sensor, and determine a progress of the photoresist process by monitoring changes to the metal-containing EUV photoresist material over time on the semiconductor substrate using the one or more optical sensors.

[0010] In some implementations, each of the one or more optical sensors includes a spectral reflectometer and a broadband light source. In some implementations, the controller configured with instructions to determine the progress of the photoresist process is configured with instructions to perform the following operations: receive reflected radiation in the process chamber at the one or more optical sensors, measure an intensity of the reflected radiation, where changes in the intensity of the reflected radiation over time are used to determine the progress of the photoresist process. In some implementations, the controller is further configured with instructions to perform the following operations: determine an endpoint of the photoresist process by determining that the intensity of the reflected radiation reached a threshold value. In some implementations, the metal-containing EUV photoresist material comprises organotin oxide. In some implementations, the apparatus further includes a window optically coupled to the process chamber and through which the incident radiation is emitted to the process chamber. In some implementations, the controller is further configured with instructions to perform the following operations: heat the window to limit deposition or condensation of byproducts or other materials on the window. In some implementations, the controller is further configured with instructions to perform the following operations: flow one or more non-reactive gases in a region proximate to the window to limit deposition or condensation of byproducts or other materials on the window. In some implementations, the one or more optical sensors includes: a first optical sensor configured to monitor changes to the metal-containing EUV photoresist material at a first position of the semiconductor substrate, and a second optical sensor configured to monitor changes to the metalcontaining EUV photoresist material at a second position of the semiconductor substrate.BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 presents a flow diagram of an example method for depositing and developing a photoresist according to some implementations.

[0012] Figures 2A-2C present cross-sectional schematic illustrations of various processing stages including development of photoresist and pattern transfer according to some implementations.

[0013] Figures 3A-3D present cross-sectional schematic illustrations of a progression for development of photoresist according to some implementations.

[0014] Figure 4 depicts a schematic illustration of a process chamber for processing a photoresist and an optical sensor optically coupled to the process chamber for in-situ process monitoring of the photoresist according to some implementations.

[0015] Figure 5 shows a schematic illustration of a substrate having multiple interfaces for spectral reflection at normal incidence.

[0016] Figure 6 shows a graph illustrating intensity of reflected radiation over time during development of a photoresist according to some implementations, with cross-sectional schematic illustrations showing a progression of the development of the photoresist at various times.

[0017] Figure 7A shows a graph illustrating a thickness or material property change as a function of time during photoresist deposition for process condition A and process condition B.

[0018] Figure 7B shows a graph illustrating a thickness or material property change as a function of time during photoresist development for process condition A and process condition B.

[0019] Figure 7C shows a graph illustrating a thickness or material property change as a function of time during photoresist bake for process condition A and process condition B.

[0020] Figure 8 presents a flow diagram of an example method of monitoring a photoresist process according to some implementations.

[0021] Figure 9 depicts a schematic illustration of an example apparatus including a process chamber, an optical sensor optically coupled to the process chamber, a gas line coupled to the process chamber, and a vacuum line coupled to the process chamber according to some implementations.

[0022] Figure 10 depicts a schematic illustration of an example multi-station processing tool suitable for implementation of various operations in accordance with certain disclosed embodiments.

[0023] Figure 11 shows a cross-sectional schematic view of an example inductively-coupled plasma apparatus for implementing certain implementations and operations described herein.

[0024] Figure 12 depicts a semiconductor process cluster tool architecture with vacuum- integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein.DETAILED DESCRIPTIONDefinitions

[0025] The term “inert gas” generally represents a gas phase material that does not react with other chemicals in a processing chamber during substrate processing. Example inert gases include helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), as well as nitrogen (N2) in some processes.

[0026] The term “plasma” generally represents a gas comprising cations, free radicals and free electrons. The term “in-situ plasma” generally represents a plasma formed at a processing station in a processing chamber. The term “remote plasma” generally represents a plasma formed at a location away from a processing station in a processing chamber.

[0027] The term “plasma generator” generally represents a combination of components that can be used to form a plasma. Example components include a radio-frequency power source, an impedance matching network, and one or more electrodes.

[0028] The term “precursor” generally represents a chemical species that adsorbs to a substrate surface in an ALD or CVD process. The precursor is reacted with a reactant to convert the adsorbed precursor to a film layer.

[0029] The term “processing chamber” or “process chamber” generally represents an enclosure in which chemical and / or physical processes are performed on substrates. The pressure, substrate temperature and atmospheric composition within a processing chamber can be controllable to perform the chemical and / or physical processes.

[0030] The term “processing tool” may generally represent a machine comprising a processing chamber and other hardware configured to enable processing to be carried out in the processing chamber.

[0031] The term “processing station” generally represents a location in a processing chamber at which a substrate is positioned during processing.

[0032] The term “reactant” generally represents a chemical species that reacts with a precursor adsorbed to a substrate surface to form a film layer in an ALD or CVD process. A reaction between a reactant and a precursor can be facilitated by thermal energy and / or a plasma in various processes.

[0033] The term “semiconductor substrate” as used herein refers to a substrate at any stage of semiconductor device fabrication containing a semiconductor material anywhere within its structure. It is understood that the semiconductor material in the semiconductor substrate does not need to be exposed. Semiconductor wafers having a plurality of layers of other materials (e.g., dielectrics) covering the semiconductor material, are examples of semiconductor substrates. The following detailed description assumes the disclosed implementations are implemented on a semiconductor wafer, such as on a 200 mm, 300 mm, or 450 mm semiconductor wafer. However, the disclosed implementations are not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed implementations include various articles such as printed circuit boards and the like.

[0034] The implementations disclosed below involve a substrate such as a wafer, semiconductor substrate, or other work piece. The work piece may be of various shapes, sizes, and materials. In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise stated, the processing details recited herein (e.g., flow rates, power levels, etc.) are relevant for processing 300 mm diameter substrates, or for treating chambers that are configured to process 300 mm diameter substrates and can be scaled as appropriate for substrates or chambers of other sizes. In addition to semiconductor wafers, other work pieces that may be used implementations disclosed herein include various articles such as printed circuit boards and the like. The processes and apparatuses can be used in the fabrication of semiconductor devices, displays, LEDs, photovoltaic panels and the like,

[0035] As used herein, the term “photoresist” and derivatives thereof refer to a light-sensitive material used in processes such as photolithography, photoetching or photoengraving to form a patterned coating on a surface. Photoresist materials change solubility with respect to a wet development chemistry or etch selectivity with respect to a dry development chemistry when exposed to certain wavelengths of light.

[0036] For the purposes of this disclosure, “metal” used in this context should be understood tomean conductor with a maximum resistivity of 500 micro Ohm cm, including metals and conductive metal salts, in particular conductive metal nitrides, e.g., TiN.

[0037] As used herein, “metal-containing photoresist” includes, but is not limited to a metal photoresist, a metalloid photoresist, a metal oxide photoresist, or an organometal oxide photoresist.

[0038] “Tin oxide” is referred to herein as including any and all stoichiometric possibilities for SnxOy, including integer values of x and y and non-integer values of x and y. For example, “tin oxide” includes compounds having the formula SnOn, where 1 < n < 2, where n can be an integer or non-integer values. “Tin oxide” can include sub-stoichiometric compounds such as SnOi.s- “Tin oxide” also includes tin dioxide (SnO or stannic oxide) and tin monoxide (SnO or stannous oxide). “Tin oxide” also includes both natural and synthetic variations and also includes any and all crystalline and molecular structures. “Tin oxide” also includes amorphous tin oxide.

[0039] As used herein, the phrase “at least one of A, B, and C” should be construed to mean a logical (A or B or C), using a non-exclusive logical “or”, and should not be construed to mean “at least one of A, at least one of B and at least one of C”.

[0040] As used herein, the term “about” is understood to account for minor increases and / or decreases beyond a recited value, which changes do not significantly impact the desired function of the parameter beyond the recited value(s). In some cases, “about” encompasses + / - 10% of any recited value. As used herein, this term modifies any recited value, range of values, or endpoints of one or more ranges.

[0041] As used herein, the terms “top,” “bottom,” “upper,” “lower,” “above,” and “below” are used to provide a relative relationship between structures. The use of these terms does not indicate or require that a particular structure must be located at a particular location in the apparatus.Introduction

[0042] This disclosure relates generally to the field of semiconductor processing. In particular aspects, the disclosure is directed to processes and apparatuses for processing of photoresists (e.g., EUV-sensitive metal and / or metal oxide-containing photoresists). Such processing of photoresists may involve deposition of photoresist material, bevel edge and / or backside clean of photoresist material, bake of photoresist material, development of photoresist material, or treatment of photoresist material. While discussion below may be focused on EUV photoresists, it will be apparent that the photoresists discussed herein may also be appropriate for use with other wavelengths of radiation, and the techniques and apparatuses discussed herein are not limited solely to EUV photoresist manufacturing.

[0043] Patterning of thin films in semiconductor processing is often an important step in the fabrication of semiconductors. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, patterns are printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that, after development, removes certain portions of the photoresist to form the pattern. The patterned and developed photoresist film then can be used as an etch mask to transfer the pattern into underlying films that are composed of metal, oxide, etc.

[0044] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and beyond. In the 16 nm node, for example, the width of a typical via or line in a Damascene structure is typically no greater than about 30 nm. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0045] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to smaller imaging source wavelengths than would be achievable with conventional photolithography methods. EUV light sources at approximately 10-20 nm, or 11-14 nm wavelength, for example 13.5 nm wavelength, can be used for leading-edge lithography tools, also referred to as scanners. The EUV radiation is strongly absorbed in a wide range of solid and fluid materials including quartz and water vapor, and so operates in a vacuum.

[0046] EUV lithography makes use of EUV resists that are patterned to form masks for use in etching underlying layers. EUV resists may be polymer-based chemically amplified resists (CARs) produced by liquid-based spin-on techniques. An alternative to CARs is directly photopatternable metal oxide-containing films, such as those available from Inpria, Corvallis, OR, and described, for example, in US Patent Publications US 2017 / 0102612, US 2016 / 021660 and US 2016 / 0116839, incorporated by reference herein at least for their disclosure of photopatternable metal oxide-containing films. Such films may be produced by spin-on techniques or dry vapor-deposited. The metal oxide-containing film can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum ambient providing sub- 30 nm patterning resolution, for example as described in U.S. Patent No. 9,996,004, issued lune 12, 2018 and titled “EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE- CONTAINING HARDMASKS,” and / or in International Patent Application No. PCT / US2019 / 31618, filed May 9, 2019, and titled “METHODS FOR MAKING EUV PATTERNABLE HARD MASKS,” the disclosures of which at least relating to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks is incorporated by reference herein. Generally, the patterning involves exposure of the EUV resistwith EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask.

[0047] It should also be understood that the while present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it is also applicable to other next generation lithographic techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and development, the radiation sources most relevant to such lithography are DUV (deep-UV), which generally refers to use of 248 nm or 193 nm excimer laser sources, X-ray, which formally includes EUV at the lower energy range of the X-ray range, as well as e-beam, which can cover a wide energy range. The specific methods may depend on the particular materials and applications used in the semiconductor substrate and ultimate semiconducting device. Thus, the methods described in this application are merely exemplary of the methods and materials that may be used in present technology.

[0048] These directly photo-patternable EUV or DUV resists may be composed of or contain metals and / or metal oxides mixed within organic components. The metals / metal oxides can enhance the EUV or DUV absorption, generate secondary electrodes, and / or show increased etch selectivity to an underlying film stack and device layers. These resists can be developed using a wet (solvent) approach, which requires the wafer to move to the track, where it is exposed to developing solvent, dried, and then baked. Such resists may also be developed using a dry approach or a combination of wet and dry approaches.

[0049] Generally, the patterning involves exposure of the EUV resist with EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask. Resists can be employed as a positive tone resist or a negative tone resist by controlling the chemistry of the resist and / or the solubility or reactivity of the developer. It would be beneficial to have an EUV or DUV resist that can serve as either a negative tone resist or a positive tone resist.

[0050] When fabricating semiconductor devices, it is important to monitor and track how a semiconductor fabrication process is progressing. Usually, the semiconductor fabrication process includes deposition, treatment, or removal of certain materials. One important step in these procedures is triggering a process when specific conditions are met. Another important step in these procedures is terminating a process when specific conditions are met, such as when a target thickness or material property change is reached. A technique of determination of that process point at which the processing should be terminated is called “endpoint detection.” An endpoint detector can terminate a process in response to a signal that determines that a target condition has been reached.

[0051] Real-time process monitoring and endpoint detection can provide important controls in photolithography. Various photolithography operations, or photoresist processing, can involve deposition of photoresist material, bevel edge and / or backside clean of photoresist material, baking of photoresist material, and development of photoresist material. Without accurate monitoring and endpoint detection, a photoresist process does not run to completion or runs in excess. This can result in defective wafers, add to the cost of ownership, and lead to a loss of time. By way of an example, under-development of photoresist material can result in a line critical dimension (line CD) that is too large and over-development of photoresist material can result in a line critical dimension (line CD) that is too small. Ex-situ process monitoring can be problematic because the wafer must be removed from the tool and analyzed. This leads to lots of wafers being wasted and lots of experiments to analyze the wafers, further increasing processing time and increasing cost.

[0052] Optical emission spectroscopy (OES) is often used for endpoint control of various semiconductor processes. Vaporized atoms from a sample are brought to a high energy state in a discharge plasma. Excited atoms and ions in the discharge plasma create a unique emission spectrum specific to each element. Optical emission spectroscopy monitors the emission intensity of light at a pre-specified wavelength in time. Such a method may identify a wavelength corresponding to a chemical species present in the semiconductor process, such as a volatile byproduct or reactive species in the discharge plasma. A resultant signal is analyzed to detect distinct variations in the emission intensity which is used to correlate with the completion of a semiconductor process. For example, as the film interface is reached during etching, the emission species related to the etch of the film will either decrease in the case of volatile byproducts or increase in the case of reactive species.

[0053] Conventional endpoint detection systems such as OES may rely on plasma to monitor changes to a semiconductor substrate over time. However, OES may not be suitable for photoresist processes where plasma exposure can damage the photoresist material. Alternative monitoring and endpoint detection techniques are necessary for photoresist materials, and particularly EUV photoresist materials.In-Situ Process Monitoring of Photoresist Processes

[0054] The present disclosure provides for in-situ process monitoring and endpoint detection of a photoresist process using an optical sensor. The optical sensor may include a spectral reflectometer. The optical sensor may further include a light source such as a broadband light source. The optical technique may be applied to photoresist deposition, bevel edge and / or backsideclean, post-application bake, post-exposure bake, development, or chamber clean operations. In some implementations, the optical technique is an in-situ technique performed in the same chamber as the photoresist process. Incident light is provided onto a semiconductor substrate and reflected light is received by the spectral reflectometer. A progress of the photoresist process is determined based on changes in the intensity to the reflected light, which can correlate with changes to a thickness or other material property of the photoresist. In some implementations, the photoresist material includes a metal-containing EUV photoresist material.

[0055] Figure 1 presents a flow diagram of an example method for depositing, developing, and treating a photoresist according to some implementations. The operations of a process 100 may be performed in different orders and / or with different, fewer, or additional operations. One or more operations of the process 100 may be performed using an apparatus described in any one of Figures 4 and 9-12. In some embodiments, the operations of the process 100 may be implemented, at least in part, according to software stored in one or more non-transitory computer readable media. In some implementations, dry chamber clean may be performed after deposition, bevel edge and / or backside clean, post-application bake, exposure, post-exposure bake, dry development, or post-dry development bake.

[0056] At block 102 of the process 100, a layer of photoresist is deposited. This may be either a dry deposition process such as a vapor deposition process or a wet process such as a spin-on deposition process. In one embodiment, a metal-containing precursor is deposited as a solution by using a liquid-based spin-on technique. In another embodiment, a metal-containing precursor is deposited in vapor form by using a dry technique (e.g., chemical vapor deposition). While the present disclosure often shows the metal-containing precursor being a tin-containing precursor, other metal atoms can be employed.

[0057] The photoresist may be a metal-containing EUV resist. An EUV-sensitive metal or metal oxide-containing film may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, described processes have been demonstrated for EUV photoresist compositions based on organotin oxides, being applicable to both commercially spin-coatable formulations (e.g., such as are available from Inpria Corp, Corvallis, OR) and formulations applied using dry vacuum deposition techniques, further described below.

[0058] Semiconductor substrates may include any material construct suitable for photolithographic processing, particularly for the production of integrated circuits and other semiconducting devices. In some embodiments, semiconductor substrates are silicon wafers. Semiconductor substrates may be silicon wafers upon which features have been created("underlying features"), having an irregular surface topography. As referred to herein, the "surface" of a substrate is a surface onto which a film of the present disclosure is to be deposited or that is to be exposed to EUV during processing. Underlying features may include regions in which material has been removed (e.g., by etching) or regions in which materials have been added (e.g., by deposition) during processing prior to conducting a method of this disclosure. Such prior processing may include methods of this disclosure or other processing methods in an iterative process by which two or more layers of features are formed on the substrate.

[0059] In some embodiments, the film is a radiation-sensitive film (e.g., an EUV-sensitive film). This film, in turn, can serve as an EUV resist, as further described herein. In particular embodiments, the layer or film can include one or more ligands (e.g., EUV labile ligands) that can be removed, cleaved, or cross-linked by radiation (e.g., EUV or DUV radiation).

[0060] The precursor can provide a patternable film that is sensitive to radiation (or a patterning radiation-sensitive film or a photopattemable film). Such radiation can include EUV radiation, DUV radiation, or UV radiation that is provided by irradiating through a patterned mask, thereby being a patterned radiation. The film itself can be altered by being exposed to such radiation, such that the film is radiation-sensitive or photosensitive. In particular embodiments, the precursor is an organometallic compound, which includes at least one metal center.

[0061] The precursor can have any useful number and type of ligand(s). In some embodiments, the ligand can be characterized by its ability to react in the presence of a counter-reactant, or in the presence of patterned radiation. For instance, the precursor can include a ligand that reacts with a counter-reactant, which can introduce linkages between metal centers (e.g., an -O- linkage). In another instance, the precursor can include a ligand that eliminates in the presence of patterned radiation.

[0062] The precursor may include a metal or a metalloid or an atom with a high patterning radiation-absorption cross-section (e.g., an EUV absorption cross-section that is equal to or greater than IxlO7cm2 / mol). In some embodiments, M is tin (Sn), bismuth (Bi), tellurium (Te), cesium (Cs), antimony (Sb), indium (In), molybdenum (Mo), hafnium (Hf), iodine (I), zirconium (Zr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), silver (Ag), platinum (Pt), and lead (Pb).

[0063] In particular embodiments, the precursor includes tin. Non-limiting tin precursors include SnF2, SnH i, SnBr4, SnCl i, Snl i, tetramethyl tin (SnMe i), tetraethyl tin (SnEu), trimethyl tin chloride (SnMe^CI), dimethyl tin dichloride (SnMezCh), methyl tin trichloride (SnMeCh), tetraallyltin, tetravinyl tin, hexaphenyl ditin (IV) (PbvSn-SnPU, in which Ph is phenyl), dibutyldiphenyltin (SnBu2Ph2), trimethyl(phenyl) tin (SnMesPh), trimethyl(phenylethynyl) tin, tricyclohexyl tin hydride, tributyl tin hydride (SnBinH), dibutyltin diacetate (SnBmiCHsCOOh). tin(II) acetylacetonate (Sn(acac)2), tributyltin ethoxide (SnBu3(OEt)), dibutyltin dimethoxide(SnBu2(OMe)2), tributyltin methoxide (SnBusCOMe)), tin(IV) tert-butoxide (Sn( / -BuO)4), n- butyltin tributoxide (Sn(n-Bu)(r-Bu0)3), tetrakis(dimethylamino)tin (Sn(NMe2)4), tetrakis(ethylmethylamino)tin (Sn(NMeEt)4), tetrakis(diethylamino)tin(IV) (Sn(NEt2)4), (dimethylamino)trimethyl tin(IV) (Sn(Me)3(NMe2), Sn(z-Pr)(NMe2)3, Sn(n-Bu)(NMe2)3, Sn(s- Bu)(NMe2)3, Sn(i-Bu)(NMe2)3, Sn(t-Bu)(NMe2)3, Sn(t-Bu)2(NMe2)2, Sn(t-Bu)(NEt2)3, Sn(tbba), Sn(II) ( 1 , 3 -bis ( 1 , 1 -dimethylethyl )-4,5-dimethy 1 -(4 / ? , 5 / ?)- 1 ,3,2-diazastannolidin-2-ylidene), or bis[bis(trimethylsilyl)amino] tin (Sn[N(SiMe3)2h).

[0064] Exemplary deposition techniques (e.g., for a film) include any described herein, such as ALD (e.g., thermal ALD and plasma-enhanced ALD), spin-coat deposition, PVD including PVD co- sputtering, CVD (e.g., PE-CVD or LP-CVD), sputter deposition, e-beam deposition including e-beam co-evaporation, etc., or a combination thereof, such as ALD with a CVD component, such as a discontinuous, ALD-like process in which precursors and counter-reactants are separated in either time or space.

[0065] Further description of precursors and methods for their deposition as EUV photoresist films applicable to this disclosure may be found in International Application No. PCT / US19 / 31618, published as International Publication No. WO 2019 / 217749, filed May 9, 2019, and titled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS. The thin films may include optional materials in addition to a precursor and a counter-reactant to modify the chemical or physical properties of the film, such as to modify the sensitivity of the film to EUV or enhancing etch resistance. Such optional materials may be introduced, such as by doping during vapor phase formation prior to deposition on the substrate, during deposition on the substrate, and / or after deposition of the film. In some embodiments, a gentle remote H2 plasma may be introduced so as to replace some Sn-L bonds with Sn-H, for example, which can increase reactivity of the resist under EUV. In other embodiments, CO2 may be introduced to replace some Sn-0 bonds with S11-CO3 bonds, which can be more resistant to wet development.

[0066] Various atoms present in the precursor and / or counter-reactant can be provided within a capping layer, which in turn is disposed on any useful layer or structure. The capping layer can be any useful thickness (e.g., any thickness described herein, including from about 0.1 nm to about 5 nm).

[0067] Furthermore, two or more different precursors can be employed within each layer (e.g., a film or a capping layer). For instance, two or more of any metal-containing precursors herein can be employed to form an alloy. Yet other exemplary EUV-sensitive materials, as well as processing methods and apparatuses, are described in U.S. Patent No. 9,996,004; International Patent Publication No. WO 2020 / 102085; and International Patent Publication No.WO 2019 / 217749, each of which is incorporated herein by reference in its entirety and for all purposes.

[0068] At block 104, an optional cleaning process is performed to clean a backside and / or bevel edge of the semiconductor substrate. Alternatively, an edge bead of the photoresist that was deposited in the prior step can be removed. The removing step can include processing the wafer with a wet metal oxide (MeOx) edge bead removal (EBR) step. Backside and / or bevel edge clean may non-selectively etch EUV resist film to equally remove fdm with various levels of oxidation or crosslinking on the substrate backside and bevel edge. During application of the EUV- patternable film, either by wet deposition processing or dry deposition processing, there may be some unintended deposition of resist material on the substrate bevel edge and / or backside. The unintended deposition may lead to undesirable particles later moving to a top surface of the semiconductor substrate and becoming particle defects. Moreover, this bevel edge and backside deposition can cause downstream processing problems, including contamination of the patterning (scanner) and development tools. Conventionally, removal of this bevel edge and backside deposition is done by wet cleaning techniques. For spin-coated photoresist material, this process is called edge bead removal and is performed by directing a stream of solvent from above and below the bevel edge while the substrate is spinning. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques.

[0069] The substrate bevel edge and / or backside clean may also be a dry clean process. In some implementations, the dry clean process involves a vapor and / or plasma having one or more of the following gases: HBr, HC1, BCh, SOCh, Ch, BBn, H2, O2, PCI3, CH4, methanol, ammonia, formic acid, NF3, HF. In some implementations, the dry clean process may use the same chemistries as a dry development process described herein. For example, the bevel edge and / or backside clean may use hydrogen halide development chemistry. For the bevel edge and / or backside clean process, the vapor and / or the plasma has to be limited to a specific region of the substrate to ensure that only the backside and the bevel are removed, without any film degradation on a frontside of the substrate. Bevel edge and / or backside clean may be accomplished using a Coronus® tool available from Lam Research Corporation, Fremont, CA, though a wider range of process conditions may be used according to the capabilities of the processing reactor.

[0070] Bevel edge and / or backside clean may alternatively be extended to a full photoresist removal or photoresist “rework” in which an applied EUV photoresist is removed and the semiconductor substrate prepared for photoresist reapplication, such as when the original photoresist is damaged or otherwise defective. Photoresist rework should be accomplished without damaging the underlying semiconductor substrate, so an oxygen-based etch should beavoided. Instead, organic vapor chemistries or variants of halogen-containing chemistries may be used. It will be understood that the photoresist rework operation may be applied at any stage during the process 100. Thus, the photoresist rework operation may be applied after deposition, after bevel edge and / or backside clean, after PAB treatment, after EUV exposure, after PEB treatment, after development, or after hard bake. In some implementations, the photoresist rework may be performed for non-selective removal of exposed and unexposed regions of the photoresist but selective to an underlayer.

[0071] At block 106 of the process 100, an optional post-application bake (PAB) is performed after deposition of the photoresist and prior to EUV exposure. Such treatment can improve etch resistance of unexposed material to aqueous or non-aqueous solution. In one instance, such treatment can enhance the chemical composition difference (or contrast) between unexposed and exposed regions, thus the PAB operation is conducted. In another instance, such treatment can reduce the chemical composition difference (or contrast) between unexposed and exposed regions, thus the PAB operation is not conducted. In yet another instance, use of PAB removes residual moisture from the layer to form a hardened resist film. The PAB can involve some combination of thermal treatment, chemical exposure, and / or moisture to increase the EUV sensitivity of the film, thereby reducing the EUV dose to develop a pattern in the film. In particular embodiments, the PAB step is conducted at a temperature greater than about 100°C or at a temperature of from about 100°C to about 200°C or from about 100°C to about 250°C. In other embodiments, the PAB step is conducted at a temperature from about 190°C to about 35O°C in the absence of an oxygencontaining gas. In another instance, post-application treatment includes exposing the film to an inert gas or CO2, which can optionally include cooling or heating. Use of an inert gas can provide metal-oxygen-metal species, and use of CO2 can provide metal carbonate species within the film.

[0072] At block 108 of the process 100, the film is exposed to EUV radiation to develop a pattern. Generally, the EUV exposure causes a change in the chemical composition of the film, creating a contrast in etch selectivity that can be used to remove a portion of the film. Such a contrast can provide a positive tone resist. However, it will be understood that the EUV exposure can alternatively cause a contrast such that unexposed regions are selectively removed. Such a contrast can provide a negative tone resist, as described herein. EUV exposure can include, e.g., an exposure having a wavelength in the range of about 10 nm to about 20 nm in a vacuum ambient (e.g., about 13.5 nm in a vacuum ambient).

[0073] Without limiting the mechanism, function or utility of present technology, EUV exposure, for example, at doses of from 10 mJ / cm2to 100 mJ / cm2results in the cleavage of Sn- C bonds resulting is loss of the alkyl substituent, alleviating steric hindrance and allowing the low-density film to collapse. In addition, reactive metal-H bond generated in the beta-hydride elimination reactions can react with neighboring active groups such as hydroxyls in the film, leading to further cross-linking and densification, and creating chemical contrast between exposed and unexposed region(s). Following exposure of the photoresist to EUV light, a photopattemed EUV resist is provided. The photopattemed metal-containing EUV resist includes EUV-exposed and unexposed regions.

[0074] At block 110 of the process 100, a post-exposure bake (PEB) is performed on the exposed film, thereby further removing residual moisture, promoting chemical condensation within the film, or increasing contrast in etch selectivity of the exposed film; or post-treating the film in any useful manner. In one instance, such treatment can reduce the chemical composition difference (or contrast) between unexposed and exposed regions, thus the PEB operation is not conducted. In another instance, the exposed film can be thermally treated (e.g., at a low temperature and / or optionally in the presence of various chemical species) to promote reactivity within the EUV exposed or unexposed portions of the resist upon exposure to a stripping agent or a positive tone developer (e.g., a halide-based aqueous acid, such as HC1, HBr, HI, or combinations thereof). In another instance, the exposed film can be thermally treated (e.g., at a low temperature) to further cross-link ligands within the EUV unexposed portions of the resist, thereby providing EUV exposed portions that can be selectively removed upon exposure to a stripping agent (e.g., a positive tone developer). In yet another instance, PEB is omitted.

[0075] At block 112 of the process 100, the photoresist pattern is developed to form a resist mask by way of positive tone development or negative tone development. In various implementations, the exposed regions are removed (positive tone) or the unexposed regions are removed (negative tone). In some implementations, development may be done with exposure to an etch gas comprising halide-containing chemistry. The development may be done without striking a plasma in some implementations. Or, development may be done with flows of one or more halide-containing etch gases activated in a remote plasma source or activated by exposure to remote UV radiation. The photoresist for development may include an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element may have a high patterning radiation-absorption cross-section. In some implementations, the element may have a high EUV-absorption cross-section. In some implementations, the metal-containing EUV resist may have an overall absorption greater than 30%. In an all-dry lithography process, this provides more efficient utilization of EUV photons, enabling development of thicker and more EUV-opaque resists.

[0076] In particular embodiments, the development step is a wet process applied to a tin-basedfilm. In other embodiments, the development step is a dry process applied to a tin-based film. For example, the dry process includes a halide-containing chemistry.

[0077] After block 112, an after-development inspection may be performed. If needed, rework is performed by returning to repeat blockl02.

[0078] At block 114 of the process 100, the photoresist undergoes treatment prior to pattern transfer. The treatment may be a thermal treatment, plasma treatment, chemical treatment, selective deposition treatment, or a combination of the aforementioned treatments. Thermal treatment may expose the photoresist to an elevated temperature between about 200°C and about 300°C to reduce defectivity and LWR. Plasma treatment may expose the photoresist to plasma such as a direct (in-situ) plasma or remote plasma in order to densify the photoresist and reduce LWR. Chemical treatment may expose the photoresist to reactive chemical species such as halide- based species (e.g., tungsten hexafluoride) or carbon-containing precursor (e.g., carbon monoxide, metal organic precursors) to improve etch resistance, reduce outgassing, and increase line CD. Selective deposition treatment may expose the photoresist to chemical precursors for selectively depositing a protective coating on the photoresist to reduce DtS, improve etch resistance, reduce outgassing, and increase line CD. Any one or more of the foregoing treatments are applied to the photoresist after development to improve the performance of the photoresist during pattern transfer.

[0079] At block 116 of the process 100, one or more substrate layers are etched using the photoresist mask for pattern transfer. Such substrate layers are underlying the photoresist mask and may be removable by lithographic etching. Pattern transfer etching may etch material to a desired depth to form a plurality of patterned features. In some embodiments, the one or more substrate layers may include amorphous carbon (a-C), amorphous silicon (a-Si), tin oxide (e.g., SnOx), silicon oxide (e.g., SiCL), silicon oxynitride (e.g., SiOxNy), silicon oxycarbide (e.g., SiOxCy), silicon nitride (e.g., SisNA, titanium oxide (e.g., TiCb), titanium nitride (e.g., TiN), tungsten (e.g., W), doped carbon (e.g., W-doped C), tungsten oxide (e.g., WOX), hafnium oxide (e.g., HfCh), zirconium oxide (e.g., ZrCL), and aluminum oxide (e.g., AI2O3). Any defects or variations in CD in the photoresist mask are replicated in the material being patterned during pattern transfer etching. Additionally, poor etch resistance adversely impacts transfer of patterns to underlying substrate layers over the course of etching. Post-development treatment of the photoresist mask mitigates the foregoing issues to ensure successful pattern transfer during pattern transfer etching.

[0080] After pattern transfer, an after etch inspection may be performed. If needed, rework is performed by returning to repeat block 102.

[0081] Figures 2A-2C present cross-sectional schematic illustrations of various processing stages including development of photoresist and pattern transfer according to some implementations. As shown in Figure 2 A, wafer 200 includes a substrate 202 and a substrate layer 204 to be etched. The patterning structure can include any useful substrate. For instance, an incoming wafer can be prepared with a substrate surface of a desired material, with the uppermost material being the layer into which the resist pattern is transferred. While the material selection may vary depending on integration, it is generally desired to select a material which can be etched with high selectivity to (i.e., much faster than) the EUV resist or imaging layer.

[0082] In some embodiments, the substrate is a hardmask, which is used in lithographic etching of an underlying semiconductor material. The hardmask may comprise any of a variety of materials, including amorphous carbon (a-C), tin oxide (e.g., SnOx), silicon oxide (e.g., SiOx, including SiCh), silicon oxynitride (e.g., SiOxNy), silicon oxycarbide (e.g., SiOxCy), silicon nitride (e.g., Si3N4), titanium oxide (e.g., TiCF), titanium nitride (e.g., TiN), tungsten (e.g., W), doped carbon (e.g., W-doped C), tungsten oxide (e.g., WOX), hafnium oxide (e.g., HI'O ), zirconium oxide (e.g., ZrC) ), and aluminum oxide (e.g., AI2O3). Suitable substrate materials can include various carbon-based films (e.g., ashable hardmask (AHM), silicon-based films (e.g., SiOx, SiCx, SiOxCy, SiOxNy, SiOxCyNz), a-Si:H, poly-Si, or SiN), or any other (generally sacrificial) film applied to facilitate the patterning process). For example, the substrate may preferably comprise SnOx, such as SnCF. In various embodiments, the layer may be from 1 nm to 100 nm thick, or from 2 nm to 10 nm thick.

[0083] In some embodiments, the substrate layer 204 includes an ashable hard mask such as amorphous carbon, spin-on carbon, or other material, e.g., silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer 204 may be a layer stack disposed on the substrate 202. The wafer 200 further includes a photopatterned metal-containing EUV resist film 206. For example, the photopattemed metal -containing EUV resist film 206 may be an organometal-containing layer disposed on the substrate layer 204 to be etched. The photopatterned metal-containing EUV resist film 206 may have a thickness between about 5 nm and about 50 nm or between about 10 nm and about 30 nm. The photopatterned metal-containing EUV resist film 206 may be provided in a process chamber after photopatterning in an EUV scanner and / or after a PEB treatment. The photopattemed metal-containing EUV resist film 206 includes non-EUV exposed regions 206a and EUV exposed regions 206b.

[0084] As shown in Figure 2B, the non-EUV exposed regions 206a of the photopatterned metalcontaining EUV resist film 206 is removed in a development process. The development may use a wet development chemistry or dry development chemistry. Where dry development chemistry is applied, the dry development may proceed with or without striking a plasma. In someimplementations, the dry development chemistry may include a halide-containing chemistry. A photoresist mask of the photopattemed metal-containing EUV resist film 206 is formed after development by removal of the non-EUV exposed regions 206a. Though Figures 2A-2C depict negative tone development, it will be understood that positive tone development may alternatively be applied in the present disclosure.

[0085] As shown in Figure 2C, the substrate layer 204 is etched using the photoresist mask 208 to form recessed features in the wafer 200 defined by the photoresist mask 208. The wafer 200 undergoes pattern transfer etching so that an etchant selectively removes the substrate layer 204 relative to the chemically modified photoresist mask 208. Pattern transfer etching may be performed with dry etching or wet etching. For example, dry etching may utilize a fluorine-based plasma etch process or oxygen-based plasma etch process. Pattern transfer etching may etch through the substrate layer 204 according to a pattern defined by the photoresist mask 208. In some embodiments, the photoresist mask 208 preserves or at least substantially preserves the increased line CD after pattern transfer etching.

[0086] Optical emission spectroscopy has been integrated in plasma etch chambers to detect and monitor etch processes in real-time. Optical emission spectroscopy requires plasma ignition because optical emission spectroscopy monitors the intensity of optical emission by active species produced by the plasma. However, optical emission spectroscopy can easily damage photoresist materials (e.g., metal-containing EUV photoresist materials) by UV light and ions produced by plasma ignition.

[0087] A photoresist material such as a metal-containing EUV photoresist material may undergo any of the photolithography steps described in the process 100 of Figure 1 and illustrated in Figures 2A-2C. In-situ process monitoring may be applied to a photolithography process to control deposition, bake, development, and other photoresist patterning or processes. As such, in-situ process monitoring of the present disclosure may be integrated with chambers configured for deposition, bake, development, or other photoresist patterning or processes. One or more optical sensors may be integrated with such chambers. In-situ process monitoring of the present disclosure enables accurate endpoint detection, reduces the cost of process development, improves precision and repeatability, and controls variability of processes and chambers.

[0088] Figures 3A-3D present cross-sectional schematic illustrations of a progression for development of photoresist according to some implementations. In Figure 3 A, a wafer 300 includes a substrate 302 and a substrate layer 304 to be etched. In some embodiments, the substrate layer 304 includes an ashable hard mask such as amorphous carbon, spin-on carbon, or other material, e.g., silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, thesubstrate layer 304 includes a bake-sensitive underlayer such as a carbon-containing film, a silicon-containing film, a doped carbon-containing film, or doped silicon-containing film. The wafer 300 further includes a photoresist film 306 over the substrate layer 304. The photoresist film 306 may be a photopattemed metal-containing EUV resist film. In some implementations, the photopattemed metal-containing EUV resist film includes an organometallic material such as an organotin oxide.

[0089] The photoresist film 306 may be provided on the wafer 300 after photopatterning in an EUV scanner and / or after a PEB treatment. After scanning the photoresist film 306, the photoresist film 306 includes non-exposed regions 306a and exposed regions 306b. The non-exposed regions 306a may be non-EUV exposed regions and the exposed regions 306b may be EUV exposed regions. The wafer 300 with the photoresist film 306 having non-exposed regions 306a and exposed regions 306b may be provided in a process chamber configured to perform development (e.g., dry development). The non-exposed regions 306a may represent a patterning structure for a pattern mask having a predetermined line CD. Prior to development, the line CD of the nonexposed regions 306a may be a target line CD1. The target line CD1 may be the desired half-pitch of the patterning structure.

[0090] In Figure 3B, the wafer 300 begins to undergo development. The non-exposed regions 306a are partially removed by exposure to development chemistry. The development may involve a wet development chemistry or dry development chemistry. Where dry development chemistry is applied, the dry development may proceed with or without striking a plasma. In some implementations, dry development may initially proceed with exposure to thermal dry development (plasma-free dry development) and may be followed by plasma dry development. In some implementations, dry development may initially proceed with exposure to plasma dry development and may be followed by thermal dry development. In some implementations, dry development may proceed by only plasma dry development or only thermal dry development. In some cases, the dry development chemistry may include a halide-containing chemistry such as hydrogen chloride (HC1), hydrogen bromide (HBr), or combinations thereof. Though Figures 3B- 3D depict negative tone development, it will be understood that positive tone development may alternatively be applied in the present disclosure. The line CD2 in Figure 3B may be larger than the target line CD1 in Figure 3 A.

[0091] In Figure 3C, the wafer 300 continues to undergo development. The development of the photoresist film 306 has not reached completion. A substantial fraction of the non-exposed regions 306a has been removed by exposure to the development chemistry. In some implementations, “a substantial fraction” of the non-exposed regions 306a that is removed constitutes at least 60% byvolume, at least 70% by volume, at least 80% by volume, or at least 90% by volume of the nonexposed regions 306a of the photoresist film 306. Some of the non-exposed regions 306a remain as residue on the substrate layer 304 and on sidewalls of the exposed regions 306b. The line CD3 in Figure 3C may be larger than the target line CD1 in Figure 3 A.

[0092] In Figure 3D, the wafer 300 completes development. Upon completion of development, the non-exposed regions 306a are completely removed. A photoresist mask 308 is formed after completion of development by removal of the non-exposed regions 306a. The photoresist mask 308 represents the patterning structure comprised of the exposed regions 306b. The photoresist mask 308 has a line CD4 that may be the same as target line CD1 or less than the target line CD1.

[0093] Typically, ex-situ monitoring of development of photoresist material may be performed by comparing the line CDs of wafer samples to the target line CD1. The target line CD1 may represent the desired half-pitch (HP) of the patterning structure of the wafer 300. At Figure 3B, the line CD2 may be much greater than the target line CD1 or desired half-pitch. Because the nonexposed regions 306a have not been entirely removed, remaining portions of the non-exposed regions 306a may add to the line CD. The wafer 300 is under-developed in Figure 3B. At Figure 3C, the line CD3 may still be much greater than the target line CD1 or desired half-pitch. Similarly, remaining portions of the non-exposed regions 306a may add to the line CD. Thus, the wafer 300 is still under-developed in Figure 3C. At Figure 3D, the line CD4 may be the same as the target line CD1 or desired half-pitch, or may be less than the target line CD1 or desired halfpitch. If the line CD4 is equal to or substantially equal to the desired half-pitch, then the wafer is neither under-developed nor over-developed. This represents the endpoint of development. However, if the line CD4 is less than the desired half-pitch, then the wafer is over-developed.

[0094] In- situ monitoring techniques of the present disclosure may be employed to determine the endpoint of development in Figures 3 A-3D. That way, the wafer 300 undergoing development can be monitored in-situ so that the wafer 300 is not under-developed or over-developed. This determination can be made in-situ without requiring lots of wafers and experiments to compare line CDs to the target line CD1.

[0095] Figure 4 depicts a schematic illustration of a process chamber for processing a photoresist and an optical sensor optically coupled to the process chamber for in-situ process monitoring of the photoresist according to some implementations. A photoresist processing apparatus 400 includes a process chamber 450. An optical sensor 410 may be optically coupled to the process chamber 450. In some cases, the optical sensor 410 may be positioned outside the process chamber 450. In some other cases, the optical sensor 410 may be positioned within the process chamber 450, where the optical sensor 410 may be integrated with a hardware component (e.g.,showerhead). In some implementations, the optical sensor 410 may be optically coupled to the process chamber 450 via a window 420.

[0096] The optical sensor 410 may include a light source 412 and a spectral reflectometer 414. The light source 412 may emit radiation into the process chamber. The window 420 may be optically transparent to the radiation. Incident radiation emitted by the light source 412 may be provided to a substrate 430 in the process chamber 450. The substrate 430 may be supported on a substrate support 440 such as an electrostatic chuck (ESC). In some implementations, the incident radiation emitted by the light source 412 may be provided normal to a surface of the substrate 430. Radiation is reflected from the substrate 430 as reflected radiation. The reflected radiation is detected by the spectral reflectometer 414. Interference patterns are measured by the spectral reflectometer 414.

[0097] The light source 412 may emit radiation at a broadband range of discrete or continuous wavelengths. In some implementations, the light source 412 may include a lamp such as an arc discharge lamp. Other suitable lamps may include but are not limited to mercury-vapor lamps, doped mercury-vapor lamps, electrode lamps, excimer lamps, pulsed xenon lamps, xenon flash lamps, and doped xenon lamps. In some implementations, the light source 412 may include a light emitting diode (LED) or an array of LEDs. The light source 412 may generate a broad spectrum of radiation, from UV to infrared, though it is possible that the light source 412 may emit a smaller spectrum. In some implementations, the light source 412 is configured to emit radiation at a broadband range of wavelengths between about 200 nm and about 900 nm, between about 200 nm and about 800 nm, between about 300 nm and about 800 nm, or between about 400 nm and about 800 nm. However, it will be understood that the light source 412 may be configured to emit radiation at wavelengths greater than about 900 nm. By having a broadband range of wavelengths, the light source 412 can advantageously emit different wavelengths, where the phase shift will be different depending on the wavelength as the radiation is reflected. This effectively enables the spectral reflectometer 414 to measure more changes in the reflected radiation since the measurements are not limited to a single wavelength, thereby providing greater flexibility and accuracy for the spectral reflectometer 414.

[0098] The spectral reflectometer 414 serves as a detector of reflected radiation, where the spectral reflectometer 414 collects spectral data associated with reflected light from the substrate 430. In some implementations, the spectral reflectometer 414 includes a charge coupled device (CCD) that is a light-sensitive detector. The spectral reflectometer 414 measures intensity of light as a function of wavelength. More specifically, the spectral reflectometer 414 receives the reflected radiation and measures an intensity of the reflected radiation. Changes in the intensityof the reflected radiation over time is correlated with changes to a thickness of film(s) on the substrate 430. These changes in thickness can determine the progress of photoresist processing in the process chamber 450. For example, as photoresist undergoes development, changes in thickness of the photoresist during development can be correlated with changes in the intensity of the reflected radiation. As such, an endpoint can be determined when the intensity of the reflected radiation reaches a threshold value.

[0099] Figure 5 shows a schematic illustration of a substrate having multiple interfaces for spectral reflection at normal incidence. The optical sensor 410 including the light source 412 and the spectral reflectometer 414 as described above leverages the optical principles illustrated in Figure 5 to perform broadband in-situ reflectometry. When a light beam is incident on a film, a portion of the light beam is reflected at the surface and a remaining portion of the light beam is transmitted through and strikes a boundary with the substrate underneath the film. A portion of this remaining light beam gets reflected back. When the two reflected light beams - one from the surface of the film and one from the boundary - meet, they cause interference. Data is extracted from the varying levels of constructive or destructive interference patterns. A model is fit to the reflected intensity versus wavelength to determine film thickness. As shown in Figure 5, spectral reflection at normal incidence across multiple interfaces leads to interference, which is analyzed by a spectral reflectometer to determine reflected intensity and thereby determine film thickness. Changes in film thickness can correspond to a progress of a photoresist process such as photoresist deposition, bake, and development.

[0100] Returning to Figure 4, the light source 412 and the spectral reflectometer 414 may be electrically coupled by an optical cable 416.

[0101] The window 420 may be transmissive or at least partially transmissive to the radiation emitted by the light source 412. Incident radiation passes through the window 420 and is reflected back from the substrate 430 as reflected radiation through the window 420. In some implementations, the window 420 is made of quartz such as high-purity silica quartz. In some implementations, the window 420 is made of some other dielectric material. In some cases, the window 420 may be composed of material (or doped) that reduces transmission of certain wavelengths. Thus, the spectrum of radiation transmission through the window 420 may be controlled to cut off or reduce transmission at shorter wavelengths. For example, the window 420 may be configured to reduce or block transmission of wavelengths less than about 400 nm. Alternatively, a cut-off filter is used to reduce or block transmission of wavelengths less than about 400 nm. Many photoresist materials are vulnerable to damage at wavelengths in the UV range (i.e., 100-400 nm). By employing certain materials for the window 420 or using a cut-off filter,such high-energy wavelengths are prevented from damaging photoresist material on the substrate 430.

[0102] In some implementations, the window 420 may be thermally coupled to one or more heating elements (not shown). Unwanted deposition of materials may occur on the window 420. Unwanted byproducts or materials from the process chamber 450 may accumulate on the window 420. In some instances, deposition of film may occur on the window 420 during photoresist dry deposition. In some instances, deposition of byproducts may occur on the window 420 during photoresist development or bake processes. Unwanted byproducts or films on the window 420 can adversely affect the performance of the optical sensor 410. The one or more heating elements may heat the window 420 to elevated temperatures to cause vaporization of unwanted materials to clean the window 420 or otherwise prevent condensation / deposition of the unwanted materials on the window 420.

[0103] In some implementations, a gas curtain may prevent deposition of unwanted materials on the window 420 or clean the window 420 of unwanted materials. One or more gas inlets may be coupled to the process chamber 450 for delivering non-reactive gas(es) towards the window 420. The non-reactive gas(es) may be flowed to a region proximate the window 420 to limit deposition or condensation of byproducts or other materials on the window 420. In some implementations, the non-reactive gas(es) may include helium, neon, argon, krypton, xenon, nitrogen, or combinations thereof. For example, the non-reactive gases may include argon, nitrogen, or a combination of argon and nitrogen. In some implementations, the gas curtain of non-reactive gas(es) may be utilized in conjunction with the heated window 420 to limit deposition of unwanted materials on the window 420.

[0104] The process chamber 450 includes a substrate support 440 configured to support the substrate 430. In some implementations, the substrate support 440 is a pedestal or electrostatic chuck (ESC). In some implementations, the substrate support 440 includes one or more temperature control elements (not shown) to heat and / or cool the substrate 430. The substrate 430 is located beneath the optical sensor 410. The light source 412 may provide incident radiation to the substrate 430 that is normal to the surface of the substrate 430. The substrate 430 may have a photoresist material such as a metal-containing EUV photoresist material formed on the substrate 430. For example, the metal-containing EUV photoresist material may include an organometallic material such as organotin oxide. The process chamber 450 is configured to process the photoresist material in a photolithography process operation, where the process chamber 450 may be configured to deposit the photoresist material on the substrate 430, bake the substrate 430 with the photoresist material formed thereon, develop the photoresist material formed on the substrate 430,or perform bevel edge and / or backside clean of photoresist material formed on the substrate 430. Accordingly, the process chamber 450 may be a deposition chamber, a bake chamber, a development chamber, or bevel edge and / or backside clean chamber. The optical sensor 410 performs in-situ monitoring of photoresist processing on the substrate 430 in the process chamber 450.

[0105] The apparatus 400 may include a controller 460 employed to control process conditions and hardware states of the apparatus 400. The controller 460 may include one or more memory devices and one or more processors. The controller 460 may control photoresist processing in the process chamber 450 and in-situ process monitoring using the optical sensor 410. The controller 460 may include system control software with instructions for controlling process activities and conditions in the process chamber 450 such as timing, mixture of gases, gas flow rates, chamber pressure, chamber temperature, substrate temperature, target power levels, RF power levels, substrate support position, window temperature, curtain gas flow, process monitoring, spectroscopy measurements, and other processes performed by the apparatus 400. The controller 460 can be configured with instructions for performing photoresist processing such as photoresist deposition, bake, development, bevel edge and / or backside clean, etc. in the process chamber 450. The controller 460 may also be configured with instructions for performing in-situ monitoring of photoresist processing in the process chamber 450 using the optical sensor 410. Using incident radiation from the light source 412 and detecting reflected radiation at the spectral reflectometer 414, a progress of the photoresist process (e.g., deposition, bake, development, etc.) can be determined. In some implementations, controller 460 is configured with instructions to determine an endpoint of the photoresist process using the spectral reflectometer 414. For instance, the endpoint of the photoresist process can be determined when an intensity of the reflected radiation reaches a threshold value.

[0106] Figure 6 shows a graph illustrating intensity of reflected radiation over time during development of a photoresist according to some implementations, with cross-sectional schematic illustrations showing a progression of the development of the photoresist at various times. Broadband in-situ reflectometry or interferometer measures of reflectance of a substrate surface can be performed during photoresist development. A light beam can be emitted onto the substrate surface during photoresist development and measurements of the intensity of the reflected light in a plurality of wavelengths can be obtained. Measurements of the intensity of the reflected light is recorded over time. The light beam can be provided normal to the substrate surface.

[0107] Information is gathered of the intensity of the reflected light as a function of time. Accordingly, continual changes in the intensity are obtained for a plurality of times. Thisinformation will show what intensity changes occur as the photoresist material is being developed. This information can be used to determine the endpoint of photoresist development. In some implementations, the spectral data can be linked to critical dimension measurements, line width, pitch, spacing, and other measurable metrics.

[0108] The photoresist on the substrate is undergoing development such as dry development. The photoresist may include a metal-containing EUV photoresist material such as an organometallic material. For example, the metal-containing EUV photoresist material may include organotin oxide. A thickness of the metal-containing EUV photoresist material may be between about 10 nm and about 50 nm, or between about 15 nm and about 40 nm, or between about 20 nm and about 30 nm. Dry development of the metal-containing EUV photoresist material may involve flowing a halide-containing gas. By way of an example, the dry development chemistry can include a hydrogen halide such as hydrogen fluoride (HF), hydrogen chloride (HC1), hydrogen bromide (HBr), hydrogen iodide (HI), or combinations thereof. Process conditions for dry development may occur at a suitable temperature, e.g., between about -30°C and about 150°C, between about -20°C and about 120°C, or between about -10°C and about 100°C. Process conditions for dry development may occur at a suitable pressure, e.g., between about 5 mTorr and about 2000 mTorr, between about 10 mTorr and about 1000 mTorr, or between about 20 mTorr and about 800 mTorr.

[0109] The thickness of the photoresist material changes as photoresist development proceeds. Changes in the intensity of the reflected light can be correlated with the changes in the thickness of the photoresist material. For example, at t=50s, the intensity of the reflected light is at a normalized value of about 340. From ex-situ line CD measurements at 50s , the line CD of patterned features of the substrate is about 17.6 nm. At t=120s, the intensity of the reflected light is at a normalized value of about 340. From ex-situ line CD measurements at 120s, the line CD of patterned features of the substrate is about 17.5 nm. At t=200s, the intensity of the reflected light is at a normalized value of about 275. From ex-situ line CD measurements at 200s, the line CD of patterned features of the substrate is about 17.6 nm. At t=400s, the intensity of the reflected light is at a normalized value of about 225. From ex-situ line CD measurements at 400s, the line CD of patterned features of the substrate is about 16 nm. This shows that after about 400 seconds of dry development, over-etch of the patterned features is already happening. In fact, over-etch of the patterned features may occur between about 200 seconds and about 400 seconds while the main etch of the patterned features may occur before about 200 seconds. At t=800s, the intensity of the reflected light is at a normalized value of about 215. From ex-situ line CD measurements at 800s, the line CD of patterned features of the substrate is about 14 nm. This shows that at after about800 seconds, photoresist material is completely or substantially removed. Changes in the intensity of the reflected light by about 800 seconds or more have become negligible, which shows that the changes in the thickness of the photoresist material is negligible. At t= 1600s, the intensity of the reflected light is at a normalized value of about 200. From ex-situ line CD measurements at 1600s, the line CD of patterned features of the substrate is about 13 nm.

[0110] Of course, broadband in-situ reflectometry is not limited to photoresist development processes. Broadband in-situ reflectometry can be applied to other photoresist processes such as photoresist deposition, photoresist bake, and photoresist bevel edge and backside clean, among other photoresist processes. Figures 7A-7C show thickness or material property changes as a function of time for photoresist deposition, photoresist development, and photoresist bake operations. These thickness or material property changes can be correlated with changes in intensity of reflected light in broadband in-situ reflectometry measurements.

[0111] Figure 7A shows a graph illustrating a thickness or material property change as a function of time during photoresist deposition for process condition A and process condition B. As more photoresist material is deposited over time, the thickness increases. The differences between process condition A and process condition B may reflect different deposition rates.

[0112] Figure 7B shows a graph illustrating a thickness or material property change as a function of time during photoresist development for process condition A and process condition B. As photoresist material undergoes development such as dry development over time, the thickness decreases. The differences between process condition A and process condition B may reflect different etch rates. The inflection point may correspond to the point in time where the dry development transitions from a main etch phase to an over-etch phase. In Figure 7B, the inflection point for process condition A may be later than the inflection point for process condition B.

[0113] Figure 7C shows a graph illustrating a thickness or material property change as a function of time during photoresist bake for process condition A and process condition B. As photoresist material undergoes baking over time, the thickness decreases or other material property changes. The differences between process condition A and process condition B may reflect different baking parameters (e.g., temperature). The inflection point may correspond to the point in time where baking achieves its desired change in the photoresist material. In Figure 7C, the inflection point for process condition A occurs earlier than the inflection point for process condition B.

[0114] Figure 8 presents a flow diagram of an example method of monitoring a photoresist process according to some implementations. The operations of a process 800 may be performed in different orders and / or with different, fewer, or additional operations. One or more operationsof the process 800 may be performed using an apparatus described in any one of Figures 4 and 9- 12. In some implementations, the operations of the process 800 may be implemented, at least in part, according to software stored in one or more non-transitory computer readable media.

[0115] At block 802 of the process 800, a photoresist process is performed in a process chamber involving a semiconductor substrate with a metal-containing EUV photoresist material. The photoresist process may be associated with an EUV photolithographic process. EUV photolithography may include deposition of EUV photoresist material on the semiconductor substrate, bevel edge and / or backside clean of EUV photoresist material, pretreatment of EUV photoresist material such as post-application bake, rework of EUV photoresist material, chamber clean of EUV photoresist material, EUV exposure for photopatterning of the EUV photoresist material, post-treatment of EUV photoresist material such as post-exposure bake, dry development of EUV photoresist material, post-dry development bake of EUV photoresist material, and pattern transfer, among other EUV photoresist processes. The metal-containing EUV photoresist material may be an organometallic material such as organotin oxide. An element in the metal-containing EUV photoresist material may be selected from a group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof.

[0116] In some implementations, the photoresist process is deposition of the metal-containing EUV photoresist material on the semiconductor substrate. The metal-containing EUV photoresist material may be dry deposited or wet deposited. In some cases, the metal-containing EUV photoresist material may be deposited by a suitable vapor deposition technique, where the process chamber may be configured for CVD or ALD. In some implementations, an underlayer may be deposited on the semiconductor substrate prior to deposition of the metal-containing EUV photoresist material. The underlayer may provide an increase in radiation absorptivity and / or patterning performance of the photoresist material.

[0117] In some implementations, the photoresist process is baking the semiconductor substrate with the metal-containing EUV photoresist material formed thereon. Photolithography processes typically involve bake steps to facilitate the chemical reactions required to produce chemical contrast between exposed and unexposed areas of the photoresist material. Baking the semiconductor substrate involves careful control of the bake ambient, possible introduction of reactive gases, and careful control of the bake temperature. Without being limited by any theory, bake may be performed to promote removal of volatile species and / or acceleration of cross-linking within the photoresist material. In some cases, the metal-containing EUV photoresist material is baked in the process chamber that is configured as a bake chamber. The bake chamber may include, for example, a hot plate or bake plate that is thermally coupled to the semiconductorsubstrate. The bake chamber may also include, for example, one or more gas inlets for providing a desired processing atmosphere. In some implementations, baking the metal-containing EUV photoresist material may occur after the photoresist material is deposited in a post-application bake, after the photoresist material is exposed to EUV for photopatteming in a post-exposure bake, or after dry development of the photoresist material in a post-dry development bake.

[0118] In some implementations, the photoresist process is development of the metal-containing EUV photoresist material. The metal-containing EUV photoresist material may be dry developed or wet developed. In some cases, the metal-containing EUV photoresist material is dry developed using a dry development chemistry. The dry development chemistry may include a halide- containing chemistry. In one example, the dry development chemistry may include a hydrogen and a halide, such as H2 and Ch or H2 and Br2. In another example, the dry development chemistry may include a hydrogen halide such as HF, HBr, HC1, HI, or combinations thereof. The dry development process may be a thermal dry development, a plasma dry development, or a combination of thermal and plasma dry development. Development of the metal-containing EUV photoresist material occurs after exposure. Development may be negative tone dry development or positive tone dry development. Negative tone dry development selectively removes non-EUV exposed regions of the photoresist material and positive tone dry development selectively removes EUV-exposed regions of the photoresist material. The process chamber may be configured for development of the metal-containing EUV photoresist material. For instance, the process chamber may include one or more gas inlets for delivery of the dry development chemistry.

[0119] In some implementations, the photoresist process is bevel edge and / or backside clean of the metal-containing EUV photoresist material. Unintended deposition of photoresist material may accumulate on the substrate bevel edge and / or backside. The bevel edge and / or backside clean may be performed by a wet cleaning technique or dry cleaning technique. In a dry cleaning technique, dry development chemistry such as a hydrogen halide chemistry may be used. During bevel edge and / or backside cleaning, the dry development chemistry may be flowed to the bevel edge and / or backside of the semiconductor substrate to selectively remove unwanted metalcontaining EUV photoresist material from the bevel edge and / or backside.

[0120] At block 804 of the process 800, the semiconductor substrate is exposed to incident radiation using an optical sensor. Such exposure to the incident radiation occurs simultaneous or concurrent with the photoresist process being performed on the semiconductor substrate. This enables in-situ monitoring of the photoresist process by the optical sensor. The optical sensor may include a light source. The incident radiation is provided from the light source. In someimplementations, the optical sensor may be integrated with a showerhead or other hardware component in the process chamber that is above the semiconductor substrate.

[0121] The light source may emit radiation into the process chamber. In some implementations, a window may be positioned between the semiconductor substrate and the light source. For instance, the window may be positioned directly above the semiconductor substrate, where the incident radiation is provided normal to the surface of the semiconductor substrate. The window may be transparent or at least partially transparent to the radiation emitted from the light source.

[0122] The light source may emit radiation at a broadband range of discrete or continuous wavelengths. In some implementations, the light source may include a lamp such as an arc discharge lamp. Other suitable lamps may include but are not limited to mercury-vapor lamps, doped mercury-vapor lamps, electrode lamps, excimer lamps, pulsed xenon lamps, xenon flash lamps, and doped xenon lamps. In some implementations, the light source may include an LED or an array of LEDs. The light source may generate a broad spectrum of radiation, from UV to infrared, though it is possible that the light source may emit a smaller spectrum. In some implementations, the light source is configured to emit radiation at a broadband range of wavelengths between about 200 nm and about 900 nm, between about 200 nm and about 800 nm, between about 300 nm and about 800 nm, or between about 400 nm and about 800 nm. However, it will be understood that the light source may be configured to emit radiation at a broadband range of wavelengths greater than about 900 nm in some other implementations. In some implementations, the light source is configured to emit radiation at a discrete wavelength between about 200 nm and about 900 nm.

[0123] Photoresist material such as the metal-containing EUV photoresist material may be easily damaged by UV radiation and ions produced by plasma. Usage of the optical sensor for in-situ monitoring of the photoresist process avoids exposure to ions and radicals produced by plasma that could potentially damage the photoresist material. UV radiation may be filtered by the window and / or cut-off filter placed between the light source and the semiconductor substrate. Accordingly, the window may be configured to block wavelengths equal to or less than about 400 nm. In addition or in the alternative, a cut-off filter placed between the light source and the semiconductor substrate may be configured to block wavelengths equal to or less than about 400 nm.

[0124] The window may be prone to unwanted accumulation of materials from the photoresist process. Where the photoresist process is deposition of photoresist material, the window may be prone to deposition of unintended photoresist film. As substrates are processed in the process chamber, unintended metal-containing EUV photoresist material may grow on internal surfaces ofthe process chamber including any windows in the process chamber. Where the photoresist process is bake or dry development of photoresist material, the window may be prone to accumulation of byproducts. Reactive gases employed in bake or dry development processes may form byproducts that may condense on internal surfaces of the process chamber including any windows in the process chamber. Unintended materials or byproducts on the window may adversely impact the optical properties of the incident radiation on the semiconductor substrate and reflected radiation reflected from the semiconductor substrate. This would compromise the accuracy spectral data received by the optical sensor. Techniques are needed to remove unwanted deposits on the window or to prevent deposition of unwanted materials on the window.

[0125] In some embodiments, the process 800 further includes heating the window to limit deposition or condensation of byproducts or other materials on the window. The window may be thermally coupled to one or more heating elements. The one or more heating elements may heat the window to an elevated temperature. In some implementations, the elevated temperature is between about 40°C and about 400°C, between about 80°C and about 350°C, between about 100°C and about 300°C, or between about 100°C and about 200°C. Above certain temperatures, gaseous byproducts, precursors, and reactant gases in the process chamber may be prevented from depositing or condensing into unwanted materials on the window. Below certain temperatures, decomposition of organic compounds and possible complications of hardware components are avoided. Heating the window may occur simultaneous with the photoresist process.

[0126] In some embodiments, the process 800 further includes flowing one or more non-reactive gases in a region proximate to the window to limit deposition or condensation of byproducts or other materials on the window. The one or more non-reactive gases may include He, Ne, Ar, Kr, Xe, N2, or mixtures thereof. The one or more non-reactive gases may be flowed as a gas curtain towards the window. One or more gas distributors may deliver the one or more non-reactive gases to the region proximate the window. The gas curtain may spread across exposed surfaces of the window so that gaseous byproducts, precursors, and reactant gases are unable to reach the exposed surfaces of the window. Flowing the one or more non-reactive gases may occur simultaneous with the photoresist process.

[0127] In some embodiments, the process 800 further includes exposing the window to plasma in the process chamber to perform in-situ clean of materials formed on the window. Plasma- activated species comprising ions and / or radicals may react with the materials formed on the window to form volatile products. Plasma ignition of one or more process gases may form the plasma, where the one or more process gases may include a halide-containing chemistry. In one example, the one or more process gases include HBr, HC1, Cb, BCh, or mixtures thereof. Inanother example, the one or more process gases may include Ch, H2, CH4, a mixture of CH4 and H2, or a mixture of CH4 and CI2. Any of the aforementioned chemistries may be used to remove any tin species. In some implementations, the plasma may include an oxygen-containing chemistry such as O2, where the oxygen-based chemistry can remove any residual carbon. In some implementations, the plasma may include a fluorine-based chemistry to remove any silicon species. The process chamber may be free of the semiconductor substrate, or any other substrate, during plasma exposure to clean the window. Plasma exposure to clean the window may occur before or after the photoresist process.

[0128] At block 806 of the process 800, a progress of the photoresist process is determined by monitoring changes to the metal-containing EUV photoresist material over time on the semiconductor substrate using the optical sensor. The optical sensor may include a spectral reflectometer in addition to the light source. Changes to the metal-containing EUV photoresist material may involve changes to the thickness of the metal -containing EUV photoresist material over time. The spectral reflectometer may track changes to the intensity of reflected radiation over time to perform in-situ monitoring of the photoresist process.

[0129] After incident radiation is provided to the surface of the semiconductor substrate, at least some of the radiation is reflected from the surface of the semiconductor substrate as reflected radiation. The optical sensor functions as a detector of the reflected radiation. The spectral reflectometer in the optical sensor may include a light-sensitive detector that is able to measure the interference patterns of the reflected radiation. As such, the spectral reflectometer is able to measure the intensity of the reflected radiation. Changes in the intensity of the reflected radiation may be correlated with changes to a thickness of the metal-containing EUV photoresist material. The changes in thickness can determine the progress of the photoresist process in the process chamber. This can provide direct, real-time measurement of photoresist deposition, development, bake, bevel edge and / or backside clean, and other photolithographic operations that undergo changes in thickness over time.

[0130] It will be understood that other material property changes to the metal-containing EUV photoresist may be monitored by the optical sensor during the photoresist process. In some implementations, the optical sensor may be able to measure changes in composition or changes in functional groups to the photoresist material. Tracking such changes to chemical makeup can assist in understanding and monitoring the photoresist process more carefully. In some implementations, tracking changes in composition or functional groups can assist in monitoring crosslinking in the photoresist material during bake. In some implementations, the optical sensor may include a Fourier Transform Infrared (FTIR) spectrometer or ultraviolet (UV) spectrometer.This enables monitoring in the UV range using a UV spectrometer, monitoring in the IR range using an FTIR spectrometer, monitoring in the visible light range using a spectral reflectometer of the present disclosure, or monitoring in a combination of spectral ranges. The FTIR or UV spectrometer may be employed to detect changes in a functional group on the semiconductor substrate during the photoresist process. In some cases, the FTIR or UV spectrometer may be part of the optical sensor with the spectral reflectometer. In some other cases, the FTIR or UV spectrometer may be part of a different sensor unit for performing in-situ process monitoring of the photoresist process. In some implementations that utilize an FTIR spectrometer, a different light source such as a laser may be implemented.

[0131] A thickness of the photoresist material may not be uniform across the surface of the semiconductor substrate. As such, changes in thickness may be different at one location of the semiconductor substrate than at another location of the semiconductor substrate. Rather than utilizing a single optical sensor to monitor the progress of the photoresist process in the process chamber, multiple optical sensors may be used. Multiple optical sensors may monitor multiple points on the substrate to check the uniformity of the photoresist material during deposition, bake, development, bevel edge and / or backside clean, and other photolithographic operations. This enables broadband in-situ monitoring of different areas of the semiconductor substrate during the photoresist process. In some implementations, a first optical sensor may monitor the progress of the photoresist process at the center of the semiconductor substrate and a second optical sensor may monitor the progress of the photoresist process at the edge of the semiconductor substrate. In some cases, placement of the multiple optical sensors may be in various locations in a showerhead of the process chamber. In other cases, placement of the multiple optical sensors may be in various locations on a ceiling of the process chamber. In some other cases, placement of the multiple optical sensors may be in various locations outside the process chamber. The optical sensors may be optically coupled to the process chamber via one or more holes, openings, or windows.

[0132] At block 808 of the process 800, an endpoint of the photoresist process is determined by determining that an intensity of the reflected radiation reached a threshold value. As the optical sensor tracks the intensity of the reflected radiation that can be correlated with a thickness of the photoresist material, the threshold value may be indicative of when the target thickness of the photoresist material is reached. Confirmation or calibration of the endpoint may be made by ex- situ measurements. Ex-situ measurements may include ex-situ thickness measurements of photoresist material performed by ellipsometry or ex-situ line CD measurements of photoresist material. These ex-situ measurements can provide calibration for a target such as a target line CD. The target from the ex-situ measurements can then be calibrated for a target intensity of thereflected radiation, which is indicative of the endpoint of the photoresist process. Put another way, the predetermined threshold value of the intensity of the reflected radiation may be calibrated experimentally using ex-situ measurements.

[0133] In-situ process monitoring using an optical sensor enables a fast learning cycle in deposition, development, and bake chambers for photoresist technology. Instead of testing numerous wafer samples to determine an endpoint of a photoresist process, in-situ process monitoring using the optical sensor can provide direct, real-time measurements that determine the endpoint of the photoresist process. That way, the photoresist process runs to completion without running in excess. This improves the throughput of semiconductor substrate process. For instance, by avoiding running a photoresist process in excess, this can reduce purge times which thereby increases throughput. Additionally, by avoiding running a photoresist process in excess, this can optimize waferless automated clean (WAC) cycles and thereby increase throughput. In-situ process monitoring using an optical sensor can also facilitate improvements in high volume manufacturing, as different chambers / stations at different sites can be monitored without having to perform different ex-situ measurements for each chamber / station.Apparatus

[0134] An apparatus of the present disclosure is configured in-situ process monitoring of a photoresist process using an optical sensor. The apparatus is configured for photolithographic operations such as photoresist deposition, bevel edge and / or backside cleaning, baking, development, and other operations. In some implementations, the apparatus is configured to perform all dry operations. In some implementations, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or multiple stations in the same process chamber.

[0135] The apparatus configured for in-situ process monitoring of a photoresist process includes a process chamber with a substrate support. The substrate support may be configured to support a semiconductor substrate having a metal-containing photoresist material formed thereon. The apparatus may include a gas line coupled to the process chamber for delivery of gases. Gases may include reactant gases, process gases, precursors, inert gases, etch gases, and the like. The apparatus may include a vacuum line coupled to the process chamber. The vacuum line may be configured for pumping / purging of gases from the process chamber. In some implementations, the apparatus may include one or more heaters for temperature control. Such heaters may be provided in the process chamber and / or in the substrate support. As discussed herein, the apparatusmay include an optical sensor used for in-situ process monitoring of a photoresist process performed in the process chamber.

[0136] Figure 9 depicts a schematic illustration of an example apparatus 900 including a process chamber 902, one or more optical sensors 920 optically coupled to the process chamber 902, a gas delivery system 916 coupled to the process chamber 902, and a vacuum line 926 coupled to the process chamber 902 according to some implementations. The process chamber 902 may be a single processing chamber for maintaining a low-pressure environment. The process chamber 902 may be in fluid communication with a gas delivery system 916 for delivering one or more gases to a gas distributor 906. In some cases, the gas distributor 906 is a showerhead. The gas delivery system 916 may optically include a mixing vessel 940 for blending and / or conditioning process gases for delivery to the gas distributor 906. Inlet valve 934 may control introduction of process gases to the mixing vessel 940 and inlet valve 936 may control introduction of carrier gas to the mixing vessel 940. In some cases, vaporized liquid reactant may be provided at vaporization point 942, where the inlet valve 936 may control introduction of the vaporized liquid reactant to the mixing vessel 940.

[0137] The gas distributor 906 may distribute process gases into the process chamber 902 and toward a substrate 904, the flow of which is controlled by one or more valves (e.g., valves 932, 934, 936) upstream from the gas distributor 906. The substrate 904 is located beneath the gas distributor 906 and is shown resting on a substrate support 908. The gas distributor 906 may have any suitable shape, and may have any suitable number and arrangement of ports for distributing process gases to the substrate 904. The process gases delivered into the process chamber 902 by the gas distributor 906 may include process gases for performing photoresist deposition, bevel edge and / or backside clean, bake, or development on the substrate 904.

[0138] The substrate support 908 may be raised or lowered to expose the substrate 904 to a chamber space between the substrate 904 and the gas distributor 906. In some implementations, pedestal height may be adjusted programmatically by a suitable computer controller such as controller 950. In some implementations, the gas distributor 906 may have multiple plenum volumes with multiple temperature controls.

[0139] In some implementations, the substrate support 908 may be temperature controlled via one or more heaters 910. In some implementations, the substrate support 908 may be heated to a temperature greater than -40°C and up to 400°C, for example, -20°C to 300°C, such as about 40°C to 160°C. In some implementations, the one or more heaters 910 of the substrate support 908 may include a plurality of independently controllable temperature control zones.

[0140] Further, in some implementations, pressure control for the process chamber 902 may be provided by a vacuum line 926. The vacuum line 926 includes a throttle valve 928. In some cases, the throttle valve 928 is a butterfly valve. As shown in Figure 9, the throttle valve 928 throttles a vacuum provided by a downstream vacuum pump (not shown). The throttle valve 928 may serve to regulate pressure in the process chamber 902. However, in some implementations, pressure control of the process chamber 902 may also be adjusted by varying a flow rate of one or more gases introduced to the process chamber 902.

[0141] In some implementations, a position of the gas distributor 906 may be adjusted relative to the substrate support 908 to vary a volume between the substrate 904 and the gas distributor 906.

[0142] Where plasma may be used, for example in dry development operations, the gas distributor 906 and / or substrate support 908 may electrically communicate with a radio-frequency (RF) power supply and matching network for powering a plasma. Thus, one or both of the gas distributor 906 and the substrate support 908 may be powered for plasma generation. In some implementations, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply and matching network may be operated via the controller 950 to form a plasma having a desired composition of radicals and ions.

[0143] The apparatus 900 may further include a window 930 positioned between the one or more optical sensors 920 and the substrate 904. The window 930 permits passage of light from the one or more optical sensors 920 and permits reflected light to be received by the one or more optical sensors 920. In some implementations, the one or more optical sensors 920 are optically coupled to the process chamber 902 via the window 930.

[0144] The window 930 may be configured block certain wavelengths of light from the one or more optical sensors 920. For instance, the window 930 may be configured to block wavelengths in the UV range (i.e., 100-400 nm). Alternatively, a cut-off filter may be used to block wavelengths in the UV range.

[0145] The window 930 may include one or more heating elements (not shown) thermally coupled to the window 930. The one or more heating elements may heat the window 930 to an elevated temperature to prevent or otherwise reduce accumulation of unwanted materials on the window 930. In addition or in the alternative, a gas curtain may be provided to the window 930 to prevent or otherwise reduce accumulation or unwanted materials on the window 930. A flow of one or more non-reactive gases may be supplied towards the window 930 that inhibits a flow ofreactive gases from reaching the window 930. In addition or in the alternative, periodic cleaning of the window 930 may take place to prevent or otherwise reduce accumulation of unwanted materials on the window 930. For example, an in-situ plasma clean may remove unwanted materials from the window 930.

[0146] The apparatus 900 further includes one or more optical sensors 920 configured to provide broadband in-situ monitoring of the photoresist process performed by the apparatus 900. In some implementations, the one or more optical sensors 920 include a single light source and a single spectral reflectometer for in-situ monitoring of the photoresist process. In some implementations, one or more optical sensors 920 include a plurality of optical sensors for in-situ monitoring of the photoresist process at different areas of the substrate 904. Each of the one or more optical sensors 920 includes a broadband light source 912 / 922 and a spectral reflectometer 914 / 924.

[0147] A first light source 912 may provide incident radiation to the surface of the substrate 904 at a first position of the substrate 904. The incident radiation may be provided normal to the surface of the substrate 904. At least some of the incident radiation is reflected as reflected radiation. A first spectral reflectometer 914 may receive the reflected radiation and determine interference patterns at the first position of the substrate 904. The first spectral reflectometer 914 may measure the intensity of the reflected radiation at the first position of the substrate 904. Such measurements can be used to determine changes in thickness to photoresist material on the substrate 904. In some implementations, the first position of the substrate 904 corresponds to a center of the substrate 904.

[0148] A second light source 922 may provide incident radiation to the surface of the substrate 904 at a second position of the substrate 904. The incident radiation may be provided normal to the surface of the substrate 904. At least some of the incident radiation is reflected as reflected radiation. A second spectral reflectometer 924 may receive the reflected radiation and determine interference patterns at the second position of the substrate 904. The second spectral reflectometer 924 may measure the intensity of the reflected radiation at the second position of the substrate 904. Such measurements can be used to determine changes in thickness to photoresist material on the substrate 904. In some implementations, the second position of the substrate 904 corresponds to an edge of the substrate 904.

[0149] In some implementations, the apparatus 900 may further include other sensors (not shown) for monitoring changes occurring on the substrate 904. The other sensors may include, for example, FTIR or UV spectrometers for monitoring changes in functional groups on the substrate 904. FTIR or UV spectrometers may be used in conjunction with the one or more opticalsensors 920 to provide direct, real-time measurements of thickness and material property changes occurring on the substrate 904 during a photoresist process.

[0150] In some implementations, the controller 950 controls all of the activities of the apparatus 900. The controller 950 may include one or more memory devices, one or more mass storage devices, and one or more processors. Processors may include a CPU or computer, analog, and / or digital input / output connections, stepper motor controller boards, etc. The controller 950 may execute system control software stored in a mass storage device, loaded into a memory device, and executed on a processor. Alternatively, the control logic may be hard coded in the controller 950. In some implementations, the system control software may include input / output sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on the mass storage device and / or memory device associated with the controller 950 may be employed in some implementations. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, a plasma control program, and a process monitoring program.

[0151] In some implementations, the controller 950 may be configured with instructions for performing the following operation: perform a photoresist process in the process chamber 902, wherein the photoresist process can include depositing a metal-containing EUV photoresist material on the substrate 904, baking the substrate 904 with the metal-containing EUV photoresist material formed thereon, or developing the metal-containing EUV photoresist material formed on the substrate 904. The controller 950 may be further configured with instructions for performing the following operations: expose the substrate 904 to incident radiation using the one or more optical sensors 920, and determine a progress of the photoresist process by monitoring changes to the metal-containing EUV photoresist material over time on the substrate 904 using the one or more optical sensors 920. Such operations may perform in-situ monitoring of the photoresist process simultaneous with performing the photoresist process. Each of the one or more optical sensors 920 may include a broadband light source 912 / 922 and a spectral reflectometer 914 / 924. The light source 912 / 922 provides incident radiation to the surface of the substrate 904, and the spectral reflectometer 914 / 924 may obtain measurements of the intensity of reflected radiation from the substrate 904. In some implementations, the controller 950 may be further configured with instructions for performing the following operations: determine an endpoint of the photoresist process by determining that the intensity of the reflected radiation reached a threshold value.

[0152] In some implementations, the controller 950 may be configured with instructions for performing the following operation: heat the window 930 to limit deposition or condensation ofbyproducts or other materials on the window 930. In some implementations, the controller 950 may be configured with instructions for performing the following operation: flow one or more non-reactive gases to a region proximate to the window 930 to limit deposition or condensation of byproducts or other materials on the window 930. In some implementations, the controller 950 may be configured with instructions for performing the following operation: expose the window 930 to plasma in the process chamber 902 to perform in-situ clean of materials formed on the window 930.

[0153] Process stations for performing one or more photoresist processes may be included in a multi-station processing tool. Figure 10 depicts a schematic illustration of an example multistation processing tool suitable for implementation of various operations in accordance with certain disclosed embodiments. The multi-station processing tool 1000 includes an inbound load lock 1002 and an outbound load lock 1004, either or both of which may include a remote plasma source. A robot 1006 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 1008 into inbound load lock 1002 via an atmospheric port 1010. A wafer is placed by the robot 1006 on a pedestal 1012 in the inbound load lock 1002, the atmospheric port 1010 is closed, and the inbound load lock 1002 is pumped down. Where the inbound load lock 1002 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment to treat the substrate surface in the load lock 1002 prior to being introduced into a processing chamber 1014. Further, the wafer also may be heated in the inbound load lock 1002 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 1016 to processing chamber 1014 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the implementation depicted in Figure 10 includes load locks, it will be appreciated that, in some implementations, direct entry of a wafer into a process station may be provided.

[0154] The depicted processing chamber 1014 includes four process stations, numbered from 1 to 4 in the implementation shown in Figure 10. Each station has a heated pedestal (shown at 1018 for station 1), and gas line inlets. It will be appreciated that in some implementations, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between dry development and deposition process modes, or a process station may be switchable between dry development and etch process modes. Additionally or alternatively, in some embodiments, processing chamber 1014 may include one or more matched pairs of dry development and etch process stations. While the depicted processing chamber 1014 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in someimplementations, a processing chamber may have five or more stations, while in other implementations a processing chamber may have three or fewer stations.

[0155] Figure 10 depicts an embodiment of a wafer handling system 1090 for transferring wafers within processing chamber 1014. In some embodiments, wafer handling system 1090 may transfer wafers between various process stations and / or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. Figure 10 also depicts an embodiment of a system controller 1050 employed to control process conditions and hardware states of process tool 1000. System controller 1050 may include one or more memory devices 1056, one or more mass storage devices 1054, and one or more processors 1052. Processor 1052 may include a CPU or computer, analog, and / or digital input / output connections, stepper motor controller boards, etc.

[0156] In some implementations, system controller 1050 controls all of the activities of process tool 1000. System controller 1050 executes system control software 1058 stored in mass storage device 1054, loaded into memory device 1056, and executed on processor 1052. Alternatively, the control logic may be hard coded in the system controller 1050. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. System control software 1058 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, in-situ process monitoring, and other parameters of a particular process performed by process tool 1000. System control software 1058 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. System control software 1058 may be coded in any suitable computer readable programming language.

[0157] In some implementations, system control software 1058 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on mass storage device 1054 and / or memory device 1056 associated with system controller 1050 may be employed in some implementations. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0158] A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 1018 and to control the spacing between the substrate and other parts of process tool 1000.

[0159] A process gas control program may include code for controlling process gas (e.g., etch gas) composition and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

[0160] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate or window. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate or window.

[0161] A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the implementations herein.

[0162] In some implementations, there may be a user interface associated with system controller 1050. The user interface may include a display screen, graphical software displays of the apparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0163] In some implementations, parameters adjusted by system controller 1050 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

[0164] Signals for monitoring the process may be provided by analog and / or digital input connections of system controller 1050 from various process tool sensors. The process tool sensors may include the optical sensors as described above as well as any FTIR spectrometer or UV spectrometer. The signals for controlling the process may be output on the analog and digital output connections of process tool 1000. Other examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0165] System controller 1050 may provide program instructions for implementing the above- described deposition processes. The program instructions may control a variety of processparameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate deposition, development, clean, bake, and / or etch processes according to various implementations described herein.

[0166] The system controller 1050 will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed implementations. Machine-readable media containing instructions for controlling process operations in accordance with disclosed implementations may be coupled to the system controller 1050.

[0167] Broadly speaking, the system controller 1050 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller 1050 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system.

[0168] The system controller 1050, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1050 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 1050 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 1050 is configured to interface with or control. Thus as described above, the system controller 1050may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0169] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (C VD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0170] As noted above, depending on the process step or steps to be performed by the tool, the system controller 1050 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0171] ICP reactors which, in certain implementations, may be suitable for dry development or etch operations suitable for implementation of some implementations, are now described. Although ICP reactors are described herein, in some implementations, it should be understood that capacitively coupled plasma reactors may also be used.

[0172] Figure 11 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 1100 appropriate for implementing certain implementations or aspects of implementations such as dry development, clean, and / or etch, an example of which is a Kiyo® reactor, produced by Lam Research Corp, of Fremont, CA. In other implementations, other tools or tool types having the functionality to conduct the dry development, clean, and / or etch processes described herein may be used for implementation.

[0173] The inductively coupled plasma apparatus 1100 includes an overall process chamber 1124 structurally defined by chamber walls 1101 and a window 1111. The chamber walls 1101 may be fabricated from stainless steel, aluminum, or plastic. The window 1 111 may be fabricatedfrom quartz or other dielectric material. An optional internal plasma grid 1150 divides the overall process chamber into an upper sub-chamber 1102 and a lower sub chamber 1103. In most implementations, plasma grid 1150 may be removed, thereby utilizing a chamber space made of sub chambers 1102 and 1103. A chuck 1117 is positioned within the lower sub-chamber 1103 near the bottom inner surface. The chuck 1117 is configured to receive and hold a wafer 1119 upon which the etching and deposition processes are performed. The chuck 1117 can be an electrostatic chuck for supporting the wafer 1 119 when present. In some implementations, an edge ring (not shown) surrounds chuck 1117, and has an upper surface that is approximately planar with a top surface of the wafer 1119, when present over chuck 1117. The chuck 1117 also includes electrostatic electrodes for chucking and dechucking the wafer 1119. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 1119 off the chuck 1117 can also be provided. The chuck 1117 can be electrically charged using an RF power supply 1123. The RF power supply 1123 is connected to matching circuitry 1121 through a connection 1127. The matching circuitry 1121 is connected to the chuck 1117 through a connection 1125. In this manner, the RF power supply 1123 is connected to the chuck 1117. In various implementations, a bias power of the electrostatic chuck may be set at about 50 V or may be set at a different bias power depending on the process performed in accordance with disclosed implementations. For example, the bias power may be between about 20 Vb and about 100 V, or between about 30 V and about 150 V.

[0174] Elements for plasma generation include a coil 1133 is positioned above window 1111. In some implementations, a coil is not used in disclosed implementations. The coil 1133 is fabricated from an electrically conductive material and includes at least one complete turn. The example of a coil 1133 shown in Figure 11 includes three turns. The cross sections of coil 1133 are shown with symbols, and coils having an “X” extend rotationally into the page, while coils having a extend rotationally out of the page. Elements for plasma generation also include an RF power supply 1141 configured to supply RF power to the coil 1133. In general, the RF power supply 1141 is connected to matching circuitry 1139 through a connection 1145. The matching circuitry 1139 is connected to the coil 1133 through a connection 1143. In this manner, the RF power supply 1141 is connected to the coil 1133. An optional Faraday shield 1149 is positioned between the coil 1133 and the window 1111. The Faraday shield 1149 may be maintained in a spaced apart relationship relative to the coil 1133. In some implementations, the Faraday shield 1149 is disposed immediately above the window 1111. In some implementations, the Faraday shield 1149 is between the window 1111 and the chuck 1117. In some implementations, the Faraday shield 1149 is not maintained in a spaced apart relationship relative to the coil 1133. Forexample, the Faraday shield 1149 may be directly below the window 1111 without a gap. The coil 1133, the Faraday shield 1149, and the window 1111 are each configured to be substantially parallel to one another. The Faraday shield 1149 may prevent metal or other species from depositing on the window 1111 of the process chamber 1124.

[0175] Process gases may be flowed into the process chamber through one or more main gas flow inlets 1160 positioned in the upper sub-chamber 1102 and / or through one or more side gas flow inlets 1170. Likewise, though not explicitly shown, similar gas flow inlets may be used to supply process gases to a capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and / or turbomolecular pump 1140, may be used to draw process gases out of the process chamber 1124 and to maintain a pressure within the process chamber 1124. For example, the vacuum pump may be used to evacuate the lower sub-chamber 1103 during a purge operation. A valve-controlled conduit may be used to fluidically connect the vacuum pump to the process chamber 1124 so as to selectively control application of the vacuum environment provided by the vacuum pump. This may be done employing a closed loop-controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during operational plasma processing. Likewise, a vacuum pump and valve controlled fluidic connection to the capacitively coupled plasma processing chamber may also be employed.

[0176] During operation of the apparatus 1100, one or more process gases may be supplied through the gas flow inlets 1160 and / or 1 170. In certain implementations, process gas may be supplied only through the main gas flow inlet 1160, or only through the side gas flow inlet 1170. In some cases, the gas flow inlets shown in the figure may be replaced by more complex gas flow inlets, one or more showerheads, for example. The Faraday shield 1149 and / or optional grid 1150 may include internal channels and holes that allow delivery of process gases to the process chamber 1124. Either or both of Faraday shield 1149 and optional grid 1 150 may serve as a showerhead for delivery of process gases. In some implementations, a liquid vaporization and delivery system may be situated upstream of the process chamber 1124, such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 1124 via a gas flow inlet 1160 and / or 1 170.

[0177] RF power is supplied from the RF power supply 1141 to the coil 1133 to cause an RF current to flow through the coil 1133. The RF current flowing through the coil 1133 generates an electromagnetic field about the coil 1133. The electromagnetic field generates an inductive current within the upper sub-chamber 1102. The physical and chemical interactions of various generated ions and radicals with the wafer 1119 etch features of and selectively deposit layers on the wafer 1119.

[0178] If the plasma grid 1150 is used such that there is both an upper sub-chamber 1102 and a lower sub-chamber 1103, the inductive current acts on the gas present in the upper sub-chamber1102 to generate an electron-ion plasma in the upper sub-chamber 1102. The optional internal plasma grid 1150 limits the amount of hot electrons in the lower sub-chamber 1103. In some implementations, the apparatus 1100 is designed and operated such that the plasma present in the lower sub-chamber 1103 is an ion- ion plasma.

[0179] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, though the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and / or deposition byproducts may be removed from the lower sub-chamber1103 through port 1122. The chuck 1117 disclosed herein may operate at elevated temperatures ranging between about 10°C and about 250°C. The temperature will depend on the process operation and specific recipe.

[0180] Apparatus 1100 may be coupled to facilities (not shown) when installed in a clean room or a fabrication facility. Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to apparatus 1100, when installed in the target fabrication facility. Additionally, apparatus 1100 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out of apparatus 1100 using typical automation.

[0181] In some implementations, a system controller 1130 (which may include one or more physical or logical controllers) controls some or all of the operations of a process chamber 1124. The system controller 1130 may include one or more memory devices and one or more processors. In some implementations, the apparatus 1100 includes a switching system for controlling flow rates and durations when disclosed implementations are performed. In some implementations, the apparatus 1100 may have a switching time of up to about 500 ms, or up to about 750 ms. Switching time may depend on the flow chemistry, recipe chosen, reactor architecture, and other factors.

[0182] In some implementations, the system controller 1130 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be integrated into the system controller 1130, which may control various components or subparts of the system or systems. The system controller 1130, depending on the processing parameters and / or the type of system, may be programmed to control any of the processes disclosed herein, including thedelivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0183] EUVL patterning may be conducted using any suitable tool, often referred to as a scanner, for example the TWINSCAN NXE: 3300B® platform supplied by ASML of Veldhoven, NL). The EUVL patterning tool may be a standalone device from which the substrate is moved into and out of for deposition and etching as described herein. Or, as described below, the EUVL patterning tool may be a module on a larger multi-component tool. Figure 12 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition, EUV patterning and dry development / etch modules that interface with a vacuum transfer module, suitable for implementation of the processes described herein. While the processes may be conducted without such vacuum integrated apparatus, such apparatus may be advantageous in some implementations.

[0184] Figure 12 depicts a semiconductor process cluster tool architecture with vacuum- integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein. The arrangement of transfer modules to “transfer” wafers among multiple storage facilities and processing modules may be referred to as a “cluster tool architecture” system. Deposition and patterning modules are vacuum-integrated, in accordance with the requirements of a particular process. Other modules, such as for etch, may also be included on the cluster.

[0185] A vacuum transport module (VTM) 1238 interfaces with four processing modules 1220a-1220d, which may be individually optimized to perform various fabrication processes. By way of example, processing modules 1220a-1220d may be implemented to perform deposition, evaporation, ELD, dry development, clean, etch, strip, and / or other semiconductor processes. For example, module 1220a may be an ALD reactor that may be operated to perform in a vapor deposition process as described herein, such as Vector tool, available from Lam Research Corporation, Fremont, CA. And module 1220b may be a PECVD tool, such as the Lam Vector®. It should be understood that the figure is not necessarily drawn to scale.

[0186] Airlocks 1242 and 1246, also known as a loadlocks or transfer modules, interface with the VTM 1238 and a patterning module 1240. For example, as noted above, a suitable patterning module may be the TWINSCAN NXE: 3300B® platform supplied by ASML of Veldhoven, NL). This tool architecture allows for work pieces, such as semiconductor substrates or wafers, to be transferred under vacuum so as not to react before exposure. Integration of the deposition moduleswith the lithography tool is facilitated by the fact that EUVL also requires a greatly reduced pressure given the strong optical absorption of the incident photons by ambient gases such as H2O, O2, etc.

[0187] As noted above, this integrated architecture is just one possible implementation of a tool for implementation of the described processes. The processes may also be implemented with a more conventional stand-alone EUVL scanner and a deposition reactor, such as a Lam Vector tool, either stand alone or integrated in a cluster architecture with other tools, such as etch, strip etc. (e.g., Lam Kiyo or Gamma tools), as modules, for example as described with reference to Figure 12 but without the integrated patterning module.

[0188] Airlock 1242 may be an “outgoing” loadlock, referring to the transfer of a substrate out from the VTM 1238 serving a deposition module 1220a to the patterning module 1240, and airlock 1246 may be an “ingoing” loadlock, referring to the transfer of a substrate from the patterning module 1240 back in to the VTM 1238. The ingoing loadlock 1246 may also provide an interface to the exterior of the tool for access and egress of substrates. Each process module has a facet that interfaces the module to VTM 1238. For example, deposition process module 1220a has facet 1236. Inside each facet, sensors, for example, sensors 1-18 as shown, are used to detect the passing of wafer 1226 when moved between respective stations. Patterning module 1240 and airlocks 1242 and 1246 may be similarly equipped with additional facets and sensors, not shown.

[0189] Main VTM robot 1222 transfers wafer 1226 between modules, including airlocks 1242 and 1246. In one implementation, robot 1222 has one arm, and in another implementation, robot 1222 has two arms, where each arm has an end effector 1224 to pick wafers such as wafer 1226 for transport. Front-end robot 1244, in is used to transfer wafers 1226 from outgoing airlock 1242 into the patterning module 1240, from the patterning module 1240 into ingoing airlock 1246. Front-end robot 1244 may also transport wafers 1226 between the ingoing loadlock and the exterior of the tool for access and egress of substrates. Because ingoing airlock module 1246 has the ability to match the environment between atmospheric and vacuum, the wafer 1226 is able to move between the two pressure environments without being damaged.

[0190] It should be noted that an EUVL tool typically operates at a higher vacuum than a deposition tool. If this is the case, it is desirable to increase the vacuum environment of the substrate during the transfer between the deposition to the EUVL tool to allow the substrate to degas prior to entry into the patterning tool. Outgoing airlock 1242 may provide this function by holding the transferred wafers at a lower pressure, no higher than the pressure in the patterning module 1240, for a period of time and exhausting any off-gassing, so that the optics of thepatterning module 1240 are not contaminated by off-gassing from the substrate. A suitable pressure for the outgoing, off-gassing airlock is no more than IE-8 Torr.

[0191] In some implementations, a system controller 1250 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. It should be noted that the controller can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. The system controller 1250 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other like components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on the memory devices associated with the controller or they may be provided over a network. In certain implementations, the system controller executes system control software. A controller as described above with respect to any of Figures 9, 10, and 11 may be implemented with the tool in Figure 12.Conclusion

[0192] It is understood that the examples and implementations described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art. Although various details have been omitted for clarity’s sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein, but may be modified within the scope of the disclosure.

Claims

CLAIMS1. A method of monitoring a photoresist process on a semiconductor substrate, the method comprising: performing a photoresist process in a process chamber involving the semiconductor substrate with a metal-containing EUV photoresist material; exposing the semiconductor substrate to incident radiation using an optical sensor; and monitoring changes to the metal-containing EUV photoresist material over time on the semiconductor substrate in the process chamber using the optical sensor.

2. The method of claim 1 , wherein performing the photoresist process comprises: depositing the metal-containing EUV photoresist material on the semiconductor substrate.

3. The method of claim 1 , wherein performing the photoresist process comprises: baking the semiconductor substrate with the metal-containing EUV photoresist material formed thereon.

4. The method of claim 1 , wherein performing the photoresist process comprises: developing the metal-containing EUV photoresist material formed on the semiconductor substrate.

5. The method of claim 1, wherein monitoring the changes to the metal-containing EUV photoresist material over time comprises: receiving reflected radiation in the process chamber at the optical sensor; and measuring an intensity of the reflected radiation, wherein changes in the intensity of the reflected radiation over time is used to determine a progress of the photoresist process.

6. The method of claim 5, wherein the changes in the intensity of the reflected radiation is correlated with changes to a thickness of the metal-containing EUV photoresist material.

7. The method of claim 5, further comprising: determining an endpoint of the photoresist process by determining that the intensity of the reflected radiation reached a threshold value.

8. The method of claim 1 , wherein the optical sensor comprises a spectral reflectometer.

9. The method of claim 1 , wherein the optical sensor comprises a broadband light source.

10. The method of claim 9, wherein the broadband light source is configured to emit radiation at a broadband range of wavelengths between about 200 nm and about 900 nm.

11. The method of claim 1 , wherein the incident radiation is provided normal to a surface of the semiconductor substrate.

12. The method of claim 1, wherein the metal-containing EUV photoresist material comprises organotin oxide.

13. The method of claim 1 , further comprising: detecting a change in a functional group on the semiconductor substrate during the photoresist process using a Fourier Transform Infrared (FTIR) spectrometer or ultraviolet (UV) spectrometer.

14. The method of claim 1 , wherein the incident radiation is provided through a window optically coupled to the process chamber.

15. The method of claim 14, further comprising: heating the window to limit deposition or condensation of byproducts or other materials on the window.

16. The method of claim 14, wherein the window is configured to block transmission of UV radiation into the process chamber.

17. The method of claim 14, further comprising: flowing one or more non-reactive gases in a region proximate to the window to limit deposition or condensation of byproducts or other materials on the window.

18. The method of claim 14, further comprising: exposing the window to plasma in the process chamber to perform in-situ clean of materials formed on the window.

19. The method of claim 1, wherein monitoring changes to the metal-containing EUV photoresist material using the optical sensor comprises: monitoring changes to the metal-containing EUV photoresist material over time at a first position of the semiconductor substrate using a first optical sensor; and monitoring changes to the metal-containing EUV photoresist material over time at a second position of the semiconductor substrate using a second optical sensor.

20. The method of claim 19, wherein the first position corresponds to a center of the semiconductor substrate and wherein the second position corresponds to an edge of the semiconductor substrate.

21. The method of claim 1, wherein the optical sensor is integrated with a showerhead in the process chamber.

22. An apparatus for performing a photoresist process, the apparatus comprising: a process chamber with a substrate support, wherein the substrate support is configured to support a semiconductor substrate; a vacuum line coupled to the process chamber; a gas line coupled to the process chamber; one or more optical sensors optically coupled to the process chamber; and a controller configured with instructions for performing the following operations: perform a photoresist process in the process chamber, wherein the photoresist process comprises depositing a metal-containing EUV photoresist material on the semiconductor substrate, baking the semiconductor substrate with the metal-containing EUV photoresist material formed thereon, or developing the metal-containing EUV photoresist material formed on the semiconductor substrate; expose the semiconductor substrate to incident radiation using the optical sensor; anddetermine a progress of the photoresist process by monitoring changes to the metal-containing EUV photoresist material over time on the semiconductor substrate using the one or more optical sensors.

23. The apparatus of claim 22, wherein each of the one or more optical sensors comprises a spectral reflectometer and a broadband light source.

24. The apparatus of claim 22, wherein the controller configured with instructions to determine the progress of the photoresist process is configured with instructions to perform the following operations: receive reflected radiation in the process chamber at the one or more optical sensors; and measure an intensity of the reflected radiation, wherein changes in the intensity of the reflected radiation over time are used to determine the progress of the photoresist process.

25. The apparatus of claim 24, wherein the controller is further configured with instructions to perform the following operations: determine an endpoint of the photoresist process by determining that the intensity of the reflected radiation reached a threshold value.

26. The apparatus of claim 24, wherein the metal-containing EUV photoresist material comprises organotin oxide.

27. The apparatus of claim 24, further comprising: a window optically coupled to the process chamber and through which the incident radiation is emitted to the process chamber.

28. The apparatus of claim 27, wherein the controller is further configured with instructions to perform the following operations: heat the window to limit deposition or condensation of byproducts or other materials on the window.

29. The apparatus of claim 27, wherein the controller is further configured with instructions to perform the following operations:flow one or more non-reactive gases in a region proximate to the window to limit deposition or condensation of byproducts or other materials on the window.

30. The apparatus of claim 27, wherein the one or more optical sensors comprises: a first optical sensor configured to monitor changes to the metal-containing EUV photoresist material at a first position of the semiconductor substrate; and a second optical sensor configured to monitor changes to the metal-containing EUV photoresist material at a second position of the semiconductor substrate.

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