Display substrate and display device having same

Abstract

A display substrate (10, 20) and a display device (1500), the display substrate (10, 20) comprising: a substrate (400); a first conductive layer (405) located on the substrate (400); a first insulating layer (415) located on the first conductive layer (405), the first insulating layer (415) having a first opening (O1) exposing the first conductive layer (405); and a second conductive layer (420) located on the first insulating layer (415), the second conductive layer (420) having a first portion (P1) filling the first opening (O1) and being in contact with the first conductive layer (405) and a second portion (P2) located outside the opening. The dimension of the first opening (O1) is configured to reduce the stress on the first portion (P1) of the second conductive layer (420), so as to prevent delamination between the first portion (P1) of the second conductive layer (420) and the first conductive layer (405).

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate and a display device thereof. Background Art

[0002] With the rapid development of display-related technologies, while ensuring narrow bezels and display stability, it is also necessary to simplify the production process to reduce costs. Therefore, halftone mask technology can be used to uniformly pattern the active layer and source / drain electrode layers during the production process.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a related display device.

[0005] According to a first aspect of the present disclosure, a display substrate is provided. The display substrate includes: a substrate; a first conductive layer located on the substrate; a first insulating layer located on the first conductive layer, the first insulating layer having a first opening exposing the first conductive layer; and a second conductive layer located on the first insulating layer, the second conductive layer having a first portion filling the first opening and contacting the first conductive layer, and a second portion located outside the first opening. The first opening has an area of ​​108 square microns or less.

[0006] In an embodiment of the present disclosure, the first insulating layer includes a first sub-insulating layer located on the substrate and a second sub-insulating layer located on the first sub-insulating layer, the display substrate further includes a third conductive layer located between the first sub-insulating layer and the second sub-insulating layer, the second sub-insulating layer has a second opening exposing the third conductive layer, and the second portion of the second conductive layer fills the second opening and contacts the third conductive layer.

[0007] In an embodiment of the present disclosure, the first opening is configured to have at least one of the following shapes: a rectangular shape, a circular shape, or an elliptical shape.

[0008] In an embodiment of the present disclosure, the rectangular shape has a width less than or equal to 9 microns and a length less than or equal to 12 microns.

[0009] In an embodiment of the present disclosure, the circular shape has a radius less than or equal to 5.86 microns.

[0010] In an embodiment of the present disclosure, the elliptical shape includes a major semi-axis less than or equal to 6 micrometers and a minor semi-axis less than or equal to 4.5 micrometers.

[0011] In an embodiment of the present disclosure, the display substrate has a display area and a non-display area surrounding the display area, wherein the first opening and the second opening are located in the non-display area of ​​the display substrate.

[0012] In an embodiment of the present disclosure, the display substrate further includes a transistor. The transistor includes: a gate electrode layer located on the substrate; a gate insulation layer located on the gate electrode layer; an active layer located on the gate insulation layer; and a source / drain electrode layer located on the active layer. The display substrate further includes: a buffer layer located on the source / drain electrode layer; and a transparent conductive layer located on the buffer layer.

[0013] In an embodiment of the present disclosure, the first insulating layer includes a first sub-insulating layer located on the substrate and a second sub-insulating layer located on the first sub-insulating layer, the first sub-insulating layer includes the gate insulating layer, the second sub-insulating layer includes the buffer layer, the first conductive layer includes the gate electrode layer, the third conductive layer includes the source / drain electrode layer, and the second conductive layer includes the transparent conductive layer.

[0014] In an embodiment of the present disclosure, the transparent conductive layer includes metal oxide.

[0015] In an embodiment of the present disclosure, the metal oxide includes indium zinc oxide.

[0016] In an embodiment of the present disclosure, the display substrate further includes a fourth conductive layer located above the second conductive layer, and the fourth conductive layer fills the first opening and the second opening.

[0017] In an embodiment of the present disclosure, the fourth conductive layer completely fills the first opening and the second opening.

[0018] In an embodiment of the present disclosure, the fourth conductive layer includes a stack of metal materials.

[0019] In an embodiment of the present disclosure, the stack of metal materials includes a stack of Mo / Al / Mo.

[0020] In an embodiment of the present disclosure, the display substrate further includes: a planarization layer located between the buffer layer and the transparent conductive layer; a passivation layer located on the planarization layer; and a pixel electrode layer located on the passivation layer.

[0021] In an embodiment of the present disclosure, the display substrate includes an electrostatic ring located in the non-display area, and the first opening and the second opening are conductive through holes for the electrostatic ring.

[0022] In an embodiment of the present disclosure, the display substrate further includes an on-substrate gate driving circuit located in the non-display area. The first opening and the second opening are conductive through holes for the on-substrate gate driving circuit.

[0023] According to a second aspect of the present disclosure, a display device is provided, comprising the display substrate according to any one of the embodiments in the first aspect.

[0024] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present application, wherein:

[0026] FIG1 shows a top view of a display substrate;

[0027] FIG2 shows a cross-sectional view of the display substrate along line CC′ in FIG1 ;

[0028] FIG3 is a schematic diagram showing a display substrate having a delamination phenomenon;

[0029] FIG4 shows a cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0030] FIG5 shows a cross-sectional view of a display substrate according to another embodiment of the present disclosure;

[0031] FIG6 is a schematic diagram showing an opening portion of a display substrate according to an embodiment of the present disclosure;

[0032] FIG7 illustrates a top view of a first opening and a second opening according to an embodiment of the present disclosure;

[0033] 8A to 8B respectively illustrate enlarged views of a first opening and a second opening according to an embodiment of the present disclosure;

[0034] FIG9 shows a schematic diagram of forming a first conductive layer of a display substrate according to an embodiment of the present disclosure;

[0035] FIG10 is a schematic diagram showing a process of forming a third conductive layer on a display substrate according to an embodiment of the present disclosure;

[0036] FIG11 is a schematic diagram showing a planarization layer formed on a display substrate according to an embodiment of the present disclosure;

[0037] FIG12 is a schematic diagram showing a fourth conductive layer formed on a display substrate according to an embodiment of the present disclosure;

[0038] FIG13 is a schematic diagram showing an opening portion of a display substrate according to another embodiment of the present disclosure;

[0039] FIG14 shows a cross-sectional view of a display substrate according to another embodiment of the present disclosure; and

[0040] FIG15 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0041] Throughout the various views of the drawings, corresponding reference numerals indicate corresponding parts or features. The drawings only illustrate the positional relationship of the various elements and are not drawn to scale. DETAILED DESCRIPTION

[0042] First, it should be noted that, unless the context clearly indicates otherwise, the singular form of the words used in this document and the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "include" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless otherwise indicated herein. Where the term "example" is used in this document, especially when it is placed after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0043] In addition, it should be noted that when introducing elements of the present application and embodiments thereof, the articles "a", "an", "the" and "said" are intended to indicate the presence of one or more elements; unless otherwise specified, "plurality" means two or more; the terms "comprising", "including", "containing" and "having" are intended to be inclusive and indicate that there may be additional elements in addition to the listed elements; the terms "first", "second", "third", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance and formation order.

[0044] It should be understood that when a layer, region, or component is referred to as being "on" another part, it means that it is directly on the other part, or there may be other components intervening therebetween. When A and B are referred to as being disposed in the same layer, this refers to the different parts A and B formed during the fabrication process by disposing (e.g., depositing) a layer of material and then processing (e.g., patterning) the material layer. Conversely, when a component is referred to as being "directly" on another component, it means that there are no other components intervening therebetween.

[0045] As mentioned above, the production process of the display substrate can be simplified by using the half-tone mask technology. Generally, in order to be compatible with the half-tone mask technology, a via mask technology is used to achieve connections between different metal layers.

[0046] A display substrate using the via mask technology will now be described with reference to FIG. 1 and FIG. 2 .

[0047] Figure 1 shows a top view of a display substrate. As shown in Figure 1, the display substrate 10 has a display area AA and a non-display area BB surrounding the display area AA. In the non-display area BB, the display substrate 10 includes an electrostatic discharge (ESD) ring and a gate driver on array (GOA) on the substrate. The electrostatic discharge ring ESD is used to release static electricity on the display substrate 10, thereby preventing static electricity from damaging the display substrate 10. The gate drive circuit GOA on the array substrate is used to provide a gate drive signal to the pixel drive circuit in the display area AA. In the non-display area BB, the display substrate 10 includes a plurality of openings for connecting different conductive layers (for example, metal layers). Specifically, the opening can be located in the ESD and / or GOA.

[0048] FIG2 shows a cross-sectional view of the display substrate taken along line CC′ in FIG1 . In the non-display area BB, the display substrate 20 includes a gate electrode layer 205, a gate insulating layer 210 located on the gate electrode layer 205, a semiconductor layer 215 located on the gate insulating layer 210, a source / drain electrode layer 220 located on the semiconductor layer 215, a buffer layer 225 located on the gate insulating layer 210 and the source / drain electrode layer 220, a passivation layer 230 located on the buffer layer 225, and a liner layer 235 located on the passivation layer 230. The liner layer 235 couples the gate electrode layer 205 to the source / drain electrode layer 220 via an opening V1 exposing the gate electrode layer 205 and an opening V2 exposing the source / drain electrode layer 220. In the display substrate 20, the opening V1 passes through the passivation layer 230, the buffer layer 225, and the gate insulating layer 210, exposing the gate electrode layer 205. Opening V2 penetrates the passivation layer 230 and the buffer layer 225, exposing the source / drain electrode layer 220. Because the liner layer 235 is located on the passivation layer 230, it lacks protection and is susceptible to corrosion and oxidation. Consequently, this arrangement reduces the display quality and lifespan of a display device including the display substrate 20.

[0049] This problem is typically overcome by placing a liner layer connecting different metal layers below the passivation layer. In this arrangement, the openings need to be filled with metal to prevent subsequent processing from affecting the liner layer, such as corrosion. The filled metal causes stress in the liner layer that causes it to shift relative to the gate electrode layer and / or the source / drain electrode layer. When the stress exceeds a certain threshold, delamination occurs between the liner layer and the gate electrode layer and / or the source / drain electrode layer, particularly between the liner layer and the gate electrode layer. Delamination is described in detail below with reference to FIG3 .

[0050] Figure 3 shows a schematic diagram of a display substrate exhibiting delamination. As shown in Figure 3 , a gap Ga appears between the liner layer 235 and the gate electrode layer 205. This gap Ga can cause an unstable or even disconnected electrical connection between the liner layer 235 and the gate electrode layer 205, thereby affecting the display quality and service life of a display device including this display substrate.

[0051] To address the aforementioned delamination issues, a display substrate has been proposed. By defining the opening dimensions and the metal used to fill the openings, the stress in the openings that could cause the liner layer to shift relative to the conductive layer to which it is connected is reduced, thus preventing delamination. This configuration can improve the display quality and extend the life of display devices incorporating such a display substrate.

[0052] The following non-restrictive description of the display substrate provided in the embodiments of the present disclosure is provided in conjunction with Figures 4 to 11. As described below, the different features in these specific embodiments can be combined with each other without conflicting with each other to obtain new embodiments, and these new embodiments also fall within the scope of protection of the present disclosure.

[0053] FIG4 shows a cross-sectional view of a display substrate according to an embodiment of the present disclosure. The top view of the display substrate according to an embodiment of the present disclosure is similar to FIG1 . The display substrate 40 shown in FIG4 can also be cut along the section line CC'. It should be understood that although the display substrate shown in FIG1 is circular, this is merely exemplary. In other embodiments of the present disclosure, the display substrate can be of any other shape, such as a square or rectangular shape. As shown in FIG4 , the display substrate 40 includes a display area AA and a non-display area BB surrounding the display area AA. The display substrate 40 includes a substrate 400. In the display area AA, the display substrate 40 includes a transistor T. The transistor T includes a gate electrode layer G located on the substrate 400, a gate insulating layer GI located on the gate electrode layer G, an active layer A located on the gate insulating layer GI, and a source / drain electrode layer SD located on the active layer A. In the display area AA, the display substrate 40 further includes: a buffer layer BUF located on the source / drain electrode layer SD, and a transparent conductive layer PC located on the buffer layer BUF.

[0054] In an embodiment of the present disclosure, in the non-display area BB, the display substrate 40 further includes a first conductive layer 405 located on the substrate 400 and a first insulating layer 415 located on the first conductive layer 405. As shown in FIG4 , the first insulating layer 415 has a first opening O1 exposing the first conductive layer 405. In an embodiment of the present disclosure, the first insulating layer 415 includes: a first sub-insulating layer 4150 located on the substrate 400; and a second sub-insulating layer 4155 located on the first sub-insulating layer 4150. The display substrate 40 includes a third conductive layer 410 located between the first sub-insulating layer 4150 and the second sub-insulating layer 4155. The first insulating layer 415 has a second opening O2 exposing the third conductive layer 410. The first opening O1 penetrates the first sub-insulating layer 4150 and the second sub-insulating layer 4155, exposing the first conductive layer 405. The second opening O2 penetrates the second sub-insulating layer 4155, exposing the third conductive layer 410. The first opening O1 and the second opening O2 are described in detail below in conjunction with FIG6 and FIG7A and FIG7B.

[0055] In the embodiment of the present disclosure, the first sub-insulating layer 4150 includes a gate insulating layer GI. The second sub-insulating layer 4155 includes a buffer layer BUF. As shown in FIG4 , the first sub-insulating layer 4150 and the gate insulating layer GI are provided in the same layer. The second sub-insulating layer 4155 and the buffer layer BUF are provided in the same layer.

[0056] In the embodiment of the present disclosure, the first conductive layer 405 includes a gate electrode layer G, and the third conductive layer 410 includes a source / drain electrode layer SD. As shown in FIG4 , the first conductive layer 405 and the gate electrode layer G are provided in the same layer, and the third conductive layer 410 and the source / drain electrode layer SD are provided in the same layer.

[0057] In an embodiment of the present disclosure, in the non-display area BB, the display substrate 40 further includes a second conductive layer 420 located on the first insulating layer 415. The second conductive layer 420 includes a first portion P1 that fills the first opening O1 and contacts the first conductive layer 405, and a second portion P2 located outside the opening. As shown in FIG4 , the second portion P2 includes a portion that fills the second opening O2 and contacts the third conductive layer 410, and another portion that connects the second portion P2 to the first portion P1. In an embodiment of the present disclosure, the first portion P1 directly contacts and is electrically connected to the first conductive layer 405. The second portion P2 directly contacts and is electrically connected to the third conductive layer 410. In an embodiment of the present disclosure, the second conductive layer 420 includes a transparent conductive layer PC. As shown in FIG4 , the second conductive layer 420 is disposed in the same layer as the transparent conductive layer PC. In an embodiment of the present disclosure, the transparent conductive layer includes a metal oxide, such as indium zinc oxide.

[0058] In the embodiment of the present disclosure, the dimensions of the first opening O1 are configured to reduce stress in the first portion P1 of the second conductive layer 420 and prevent delamination between the first portion P1 of the second conductive layer 420 and the first conductive layer 405. Specifically, the dimensions of the first opening O1 include an area of ​​108 square microns or less. Delamination has been described in detail above with reference to FIG. 3 and will not be repeated here. The dimensions of the opening will be described in detail below with reference to FIG. 6.

[0059] In an embodiment of the present disclosure, the display substrate 40 further includes a fourth conductive layer 425 located above the second conductive layer 420. The fourth conductive layer 425 fills the first opening O1 and the second opening O2. As shown in FIG4 , the fourth conductive layer 425 completely fills the first opening O1 and the second opening O2 and covers the portion of the second conductive layer 420 between the first opening O1 and the second opening O2. FIG4 shows that the fourth conductive layer 425 completely fills the first opening O1 and the second opening O2, but this is merely illustrative. In other embodiments of the present disclosure, the fourth conductive layer 425 may partially fill the first opening O1 and / or the second opening O2. Filling the first opening O1 and the second opening O2 with the fourth conductive layer 425 and covering the second conductive layer 420 between the first opening O1 and the second opening O2 can prevent subsequent processing (e.g., etching) from corroding the second conductive layer 420, thereby improving the display quality of the display device and extending its service life. In an embodiment of the present disclosure, the fourth conductive layer 425 includes a metal stack material, such as a Mo / Al / Mo stack. Compared with a single metal material (e.g., Cu), the fourth conductive layer 425 made of such material can subject the second conductive layer 420 to less stress relative to the first conductive layer 405, thereby preventing delamination between the second conductive layer 420 and the first conductive layer 405, thereby improving the display quality of the display device and extending its service life.

[0060] Although the portions of the fourth conductive layer 425 filling the first opening O1 and the second opening O2 are separated in the drawings of the present disclosure, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the portion of the fourth conductive layer 425 filling the first opening O1 and the portion of the fourth conductive layer 425 filling the second opening O2 may be connected to each other. This will be described below with reference to FIG. 5 .

[0061] Furthermore, in the embodiment of the present disclosure, the display substrate 40 includes: a planarization layer 430 located between the buffer layer BUF and the transparent conductive layer PC; a passivation layer 435 located on the planarization layer 430; and a pixel electrode layer PA located on the passivation layer 435. As shown in FIG4 , in the display area AA, the pixel electrode layer PA contacts the source / drain electrode layer SD of the transistor T via an opening in the buffer layer BUF.

[0062] As previously described, in the non-display area BB, the display substrate 40 includes multiple circuits, such as an electrostatic discharge loop ESD and an on-substrate gate driver GOA. In the embodiment of the present disclosure, openings (e.g., first opening O1 and second opening O2) are located in the discharge loop ESD and / or the on-substrate gate driver GOA and serve as conductive vias.

[0063] In addition, as mentioned above, in the general display substrate shown in Figure 2 (for example, in the electrostatic discharge ring ESD and the gate driver GOA on the substrate), the pad layer 235 is located on the passivation layer 230. Therefore, the pad layer 235 is susceptible to corrosion and oxidation, affecting its conductivity (for example, the conductivity in the openings V1 and V2), thereby affecting the stability and service life of the display substrate. However, in the embodiment of the present disclosure, the second conductive layer 420 is located below the fourth conductive layer 425, and the second conductive layer 420 and the fourth conductive layer 425 are both located below the passivation layer 435. Compared with the pad layer 235 in Figure 2, the second conductive layer 420 is not easily corroded and oxidized. Therefore, the conductivity of the second conductive layer 420 (for example, the conductivity in the first opening O1 and the second opening O2) is more stable, and the display substrate shown in Figure 4 has better stability and a longer service life.

[0064] FIG5 shows a cross-sectional view of a display substrate according to another embodiment of the present disclosure. As shown in FIG5 , the display substrate 50 differs from the display substrate 40 shown in FIG4 only in that the portion of the fourth conductive layer 425 filling the first opening O1 and the portion of the fourth conductive layer 425 filling the second opening O2 are connected to each other.

[0065] FIG6 is a schematic diagram showing an opening portion of a display substrate according to an embodiment of the present disclosure. In the embodiment of the present disclosure, the first opening O1 is configured to reduce stress in the first portion P1 of the second conductive layer 420 to prevent delamination between the first portion P1 of the second conductive layer 420 and the first conductive layer 405. Furthermore, the area of ​​the first opening O1 is limited to be less than or equal to 108 μm. 2 To prevent the first portion P1 of the second conductive layer 420 from being delaminated from the first sub-conductive layer 4050. Specifically, as shown in FIG6 , the first opening O1 and the second opening O2 in the display substrate 60 are rectangular. The length and width of the first opening O1 are a1 and b1, and the length and width of the second opening O2 are a2 and b2, and a2=a1, b2=b1. In the embodiment of the present disclosure, the area S1 of the first opening O1 should meet the following conditions: S1=a1*b1≤108μm 2In an embodiment of the present disclosure, the length a1 and width b1 of the first opening O1 may satisfy the following conditions: a1 ≤ 12 μm and b1 ≤ 9 μm. FIG6 shows that the first opening O1 is rectangular. However, this is not restrictive. In other embodiments of the present disclosure, the first opening may have any other shape, such as a rectangular shape, a circular shape, or an elliptical shape.

[0066] 6 , the shape and size of the second opening O2 are the same as those of the first opening O1 , but this is not restrictive, and in other embodiments of the present disclosure, the second opening O2 may have any shape and size.

[0067] Alternatively, in another embodiment of the present disclosure, the first opening O1 is circular, and the radius is r1. In this embodiment, the area S1 of the first opening O1 should satisfy the following condition: S1 = π*r1 2 ≤108μm 2 Furthermore, the radius r1 of the first opening O1 may satisfy the following condition: r1 ≤ 5.86 μm.

[0068] Alternatively, in another embodiment of the present disclosure, the first opening O1 has an elliptical shape, with the minor axis being E1 and the major axis being F1. The area S1 of the first opening O1 should satisfy the following condition: S1 = π*E1*F1 ≤ 108 μm 2 Furthermore, the semi-major axis E1 and the semi-minor axis F1 of the first opening O1 may satisfy the following conditions: E1 ≤ 6 μm and F1 ≤ 4.5 μm.

[0069] FIG7 illustrates a top view of the first opening O1 and the second opening O2 in FIG4 according to an embodiment of the present disclosure. In an embodiment of the present disclosure, FIG7 illustrates the first opening O1 and the second opening O2 in FIG4 . As shown in FIG7 , the display substrate 70 includes the first opening O1 and the second opening O2. The contour around the first opening O1 has three steps, and the contour around the second opening O2 has one step. The stepped contours around the first opening O1 and the second opening O2 will be described in detail below with reference to FIG8A and FIG8B .

[0070] Figures 8A and 8B respectively show enlarged views of the first opening and the second opening shown in Figure 7 . As shown in Figure 8A , a portion E1 of the second conductive layer 420 adjacent to the first opening O1 has three steps. The first opening O1 passes through the planarization layer 430, the second sub-insulating layer 4155 (e.g., a buffer layer), and the first insulating layer 4150 (e.g., a gate insulating layer), exposing the first conductive layer 405. In an embodiment of the present disclosure, at portion E1 of the second conductive layer 420, the second sub-insulating layer 4155 is precisely bonded to the first sub-insulating layer 4150. Therefore, portion E1 of the second conductive layer 420 has no steps at the boundary between the second sub-insulating layer 4155 and the first insulating layer 4150. In other embodiments of the present disclosure, due to precision issues in the manufacturing process, one or more boundaries may exist between the second sub-insulating layer 4155 and the first insulating layer 4150 due to incomplete etching of other film layers. Therefore, portion E1 of the second conductive layer 420 may include four or more steps. Similarly, the portion E2 of the second conductive layer 420 may include two steps or a plurality of steps.

[0071] 8B , a portion E2 of the second conductive layer 420 adjacent to the second opening O2 has a step. The second opening O2 passes through the second sub-insulating layer 4155 to expose the third conductive layer 410 .

[0072] In practical applications, small openings can increase the resistance of the electrical connection between the conductive layers. This resistance can be reduced by increasing the number of openings. This arrangement is described below with reference to Figures 13 and 14.

[0073] The material layers in the display substrate 40 shown in FIG. 4 will be described below with reference to FIG. 9 to FIG. 12 .

[0074] In an embodiment of the present disclosure, a display substrate includes a first conductive layer located on the substrate.

[0075] Figure 9 shows a schematic diagram of forming a first conductive layer on a display substrate according to an embodiment of the present disclosure. The method for manufacturing a display substrate includes forming a first conductive layer 405 on a substrate 400. As shown in Figure 9, the first conductive layer 405 is formed on the substrate 400 in the non-display area BB of the display substrate 40, and a gate electrode layer G is formed on the substrate 400 in the display area AA of the display substrate 40. The gate electrode layer G is provided on the same layer as the first conductive layer 405.

[0076] In an embodiment of the present disclosure, the display substrate includes a first insulating layer located on the first conductive layer, the first insulating layer includes a first sub-insulating layer located on the substrate, and the display substrate further includes a third conductive layer located on the first sub-insulating layer.

[0077] Figure 10 shows a schematic diagram of forming a third conductive layer on a display substrate according to an embodiment of the present disclosure. The method for preparing the display substrate 40 includes: forming a first sub-insulating layer 4150 on the first conductive layer 405; and forming a third conductive layer 410 on the first sub-insulating layer 4150. As shown in Figure 10, the first sub-insulating layer 4150 is formed on the first conductive layer 405 and the substrate 400 in the non-display area BB of the display substrate 40, and the gate insulating layer GI is formed on the gate electrode layer G and the substrate 400 in the display area AA of the display substrate 40. The gate insulating layer GI is provided on the same layer as the first sub-insulating layer 4150. The third conductive layer 410 is formed on the first sub-insulating layer 4150 in the non-display area BB of the display substrate 40, and a source / drain electrode layer SD is formed on the gate insulating layer GI in the display area AA of the display substrate 40. The source / drain electrode layer SD is provided on the same layer as the third conductive layer 410.

[0078] In an embodiment of the present disclosure, the method for forming the display substrate 40 further includes forming an active layer A between the gate insulating layer GI and the source / drain electrode layer SD in the display area AA of the display substrate 40. The method for preparing the display substrate 40 further includes forming a material layer disposed in the same layer as the active layer A between the first sub-insulating layer 4150 and the third conductive layer 410 in the non-display area BB of the display substrate 40.

[0079] In an embodiment of the present disclosure, the first insulating layer further includes a second sub-insulating layer located on the first sub-insulating layer and the second conductive layer. The first insulating layer has a first opening exposing the first conductive layer and a second opening exposing the third conductive layer. The display substrate includes a planarization layer located on the second sub-insulating layer.

[0080] Figure 11 shows a schematic diagram of forming a planarization layer for a display substrate according to an embodiment of the present disclosure. The method for preparing the display substrate 40 includes: forming a second sub-insulating layer 4155 on the second conductive layer 410, and forming a first opening O1 in the first sub-insulating layer 4150 and the second sub-insulating layer 4155, exposing the first conductive layer 405; forming a planarization layer 430 on the second sub-insulating layer 4155, and forming a second opening O2 in the second sub-insulating layer 4155, exposing the second conductive layer 410. In an embodiment of the present disclosure, the first opening O1 and the second opening O2 are formed in the non-display area BB of the display substrate 40. The orthographic projection of the first opening O1 on the substrate 400 does not overlap with the orthographic projection of the second opening O2 on the substrate 400. The third conductive layer 410 is located between the first sub-insulating layer 4150 and the second sub-insulating layer 4155. As described above, the size of the first opening O1 is configured to be sufficiently small to reduce stress between the second conductive layer 420 and the first conductive layer 405, which will not be further described here.

[0081] In an embodiment of the present disclosure, the display substrate includes: a second conductive layer located on a first insulating layer, wherein the second conductive layer has a first portion filling a first opening and contacting the first conductive layer and a second portion located outside the first opening, the second portion filling the second opening and contacting a third conductive layer; and a fourth conductive layer located above the second conductive layer, the fourth conductive layer filling the first opening and the second opening.

[0082] Figure 12 shows a schematic diagram of forming a fourth conductive layer on a display substrate according to an embodiment of the present disclosure. As shown in Figure 12, the method for preparing the display substrate 40 further includes forming a second conductive layer 420 on the second sub-insulating layer 4155 and the planarization layer 430 in the display area AA and the non-display area BB of the display substrate 40. In the non-display area BB, the first portion P1 of the second conductive layer 420 fills the first opening O1 and contacts the first conductive layer 405. The second portion P2 of the second conductive layer 420 includes a portion that fills the second opening O2 and contacts the third conductive layer 410, and another portion that connects the first portion P1 to the portion. In addition, in the display area AA, the second conductive layer 420 includes a portion for forming a transparent conductive layer PC (which serves as one of the electrodes in the pixel electrode). The method for preparing the display substrate 40 further includes forming a fourth conductive layer 425 on the second conductive layer 420. As shown in Figure 12, in the non-display area BB of the display substrate 40, the fourth conductive layer 425 completely fills the first opening O1 and the second opening O2. In the display area AA, the fourth conductive layer 425 is located on the transparent conductive layer PC.

[0083] In an embodiment of the present disclosure, a display substrate includes: a passivation layer located on a planarization layer, and a pixel electrode layer located on the passivation layer.

[0084] 4 , the method for preparing the display substrate 40 further includes: forming a passivation layer 435 on the buffer layer 430, the second conductive layer 420, and the fourth conductive layer 425 in the display area AA and the non-display area BB of the display substrate 40; and in the display area AA, forming a pixel electrode layer PA (serving as another electrode of the pixel) on the passivation layer 435 and the source / drain electrode layer SD, the pixel electrode layer being in contact with the source / drain electrode layer SD via openings on the passivation layer 435 and the second sub-insulating layer 4155.

[0085] It should be noted that in the embodiments of the present disclosure, there is no specific limitation on the method of forming each material layer. For example, the material layers may be formed by patterning.

[0086] In addition, although the above description is based on a display substrate 40 having one first opening O1 and one second opening O2, the present disclosure is not limited thereto. As described above, the number of first openings O1 and second openings O2 can be any number, and can be the same or different. Another embodiment of the present disclosure will be described below with reference to FIG. 13 and FIG. 14 .

[0087] Figure 13 shows a schematic diagram of the opening portion of the display substrate according to another embodiment of the present disclosure. Each opening in Figure 13 is the first opening O1 or the second opening O2 shown in Figure 4. In an embodiment of the present disclosure, the display substrate may include a plurality of openings for realizing an electrical connection. As shown in Figure 13, the display substrate 1300 includes four openings for realizing an electrical connection: two first openings O1 and two second openings O2. As mentioned above, the shapes and sizes of the two first openings O1 and the two second openings O2 may be the same or different. As shown in Figure 13, the two first openings O1 and the two second openings O2 are arranged in a 2*2 array. This arrangement is only schematic and not restrictive. In other embodiments of the present disclosure, other arrangements may be adopted according to specific needs or the space of the non-display area of ​​the array substrate, such as one or more linear or circular arrangements.

[0088] Alternatively, in other embodiments disclosed herein, the number of first openings O1 may be different from the number of openings that are equal to the second openings O2. For example, there are three first openings O1 and one second opening O2. The first conductive layer 405 is electrically connected to the third conductive layer 410 via three first openings O1 and one second opening O2. Although four openings are shown in FIG13 , this is merely exemplary and not restrictive. In other embodiments of the present disclosure, other numbers of openings are also feasible, such as 3, 5, 6, 7, 8, etc. In actual applications, those skilled in the art can balance between the electrical properties of the display substrate (e.g., the resistance of the electrical connection) and the physical properties (e.g., the size of the frame) and select a compromise.

[0089] Figure 14 shows a cross-sectional view of a display substrate according to another embodiment of the present disclosure. Figure 14 shows a cross-sectional view of the display substrate shown in Figure 13 . Unlike Figure 5 , display substrate 1400 includes two first openings O10 and O15, and two second openings O20 and O25. The first portion P1 of the second conductive layer 420 includes a portion P10 that fills the first opening O11 and another portion P15 that fills the first opening O15. In the non-display area BB, the second portion P2 of the second conductive layer 420 includes a portion that fills the second opening O20, another portion that fills the second opening O25, and a portion that connects the two first openings O10 and O15 and the second openings O20 and O25.

[0090] FIG15 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in FIG15 , a display device 1500 may include the display substrate 40 / 50 / 60 / 70 / 1300 / 1400 according to any embodiment of the present disclosure.

[0091] The display device 1500 can be any product or component with a display function, such as a VR or AR display device, EVF, sight, FPV device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0092] The display device provided by the embodiment of the present disclosure has the same or similar beneficial effects as the display substrate provided by the aforementioned embodiment of the present disclosure. Since the display substrate has been described in detail in the aforementioned embodiment, it will not be repeated here.

[0093] The foregoing description of the embodiments is provided above for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present application. The individual elements or features of a particular embodiment are generally not limited to a particular embodiment, but, where appropriate, these elements and features are interchangeable and can be used in selected embodiments, even if not specifically shown or described. Also, it is possible to change in many ways. This change cannot be considered to be out of the present application, and all such modifications are included within the scope of the present application.

Claims

1. A display substrate, the display substrate comprising: Substrate; A first conductive layer located on the substrate; A first insulating layer located on the first conductive layer, the first insulating layer having a first opening exposing the first conductive layer; And A second conductive layer located on the first insulating layer, the second conductive layer having a first portion filling the first opening and contacting the first conductive layer and a second portion located outside the first opening, wherein, the size of the first opening includes an area less than or equal to 108 square micrometers.

2. The display substrate according to claim 1, wherein, The first insulating layer includes a first sub-insulating layer located on the substrate and a second sub-insulating layer located on the first sub-insulating layer, the display substrate further includes a third conductive layer located between the first sub-insulating layer and the second sub-insulating layer, the second sub-insulating layer having a second opening exposing the third conductive layer, and the second portion of the second conductive layer filling the second opening and contacting the third conductive layer.

3. The display substrate according to claim 2, wherein, The first opening is configured to have at least one of the following shapes: a rectangular shape, a circular shape, or an elliptical shape.

4. The display substrate according to claim 3, wherein, The rectangular shape has a width less than or equal to 9 micrometers and a length less than or equal to 12 micrometers.

5. The display substrate according to claim 3, wherein, The circular shape has a radius less than or equal to 5.86 micrometers.

6. The display substrate according to claim 3, wherein, The elliptical shape includes a major axis less than or equal to 6 micrometers and a minor axis less than or equal to 4.5 micrometers.

7. The display substrate according to any one of claims 1-6, the display substrate having a display area and a non-display area surrounding the display area, wherein, The first opening and the second opening are located in the non-display area of the display substrate.

8. The display substrate according to claim 7, the display substrate further comprising a transistor, the transistor further comprising: A gate electrode layer located on the substrate; A gate insulating layer located on the gate electrode layer; An active layer located on the gate insulating layer; And A source / drain electrode layer located on the active layer, The display substrate further includes: A buffer layer located on the source / drain electrode layer; And A transparent conductive layer located on the buffer layer.

9. The display substrate according to claim 8, wherein, The first insulating layer includes a first sub-insulating layer located on the substrate and a second sub-insulating layer located on the first sub-insulating layer, the first sub-insulating layer includes the gate insulating layer, the second sub-insulating layer includes the buffer layer, the first conductive layer includes the gate electrode layer, the third conductive layer includes the source / drain electrode layer, and the second conductive layer includes the transparent conductive layer.

10. The display substrate according to claim 9, wherein, The transparent conductive layer includes a metal oxide.

11. The display substrate according to claim 10, wherein, The metal oxide includes indium zinc oxide.

12. The display substrate according to claim 3, the display substrate further comprising a fourth conductive layer located above the second conductive layer, the fourth conductive layer filling the first opening and the second opening.

13. The display substrate according to claim 12, wherein,The fourth conductive layer completely fills the first opening and the second opening.

14. The display substrate according to claim 13, wherein, The fourth conductive layer includes a stack of metal materials.

15. The display substrate according to claim 14, wherein, The metal materials include a Mo / Al / Mo stack.

16. The display substrate according to claim 15, further comprising: A planarization layer located between the buffer layer and the transparent conductive layer; A passivation layer located on the planarization layer; And a pixel electrode layer located on the passivation layer.

17. The display substrate according to claim 16, further comprising an electrostatic ring located in the non-display area, wherein, The first opening and the second opening are for the electrostatic ring conductive vias.

18. The display substrate according to claim 16, further comprising a gate driving circuit on the substrate located in the non-display area, wherein, The first opening and the second opening are for the conductive vias of the gate driving circuit on the substrate.

19. A display device, the display device comprising the display substrate according to any one of claims 1 to 18.

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