Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of pixel driving circuits arranged in multiple rows and multiple columns; each pixel driving circuit among the plurality of pixel driving circuits comprises a plurality of transistors; the plurality of transistors at least comprise a write transistor. The array substrate comprises a base substrate, a first source-drain metal layer provided on one side of the base substrate, a transistor distribution layer provided on the side of the first source-drain metal layer away from the base substrate, and a second source-drain metal layer provided on the side of the transistor distribution layer away from the base substrate. The first source-drain metal layer comprises a data signal line. The transistor distribution layer is provided with an active layer pattern of the write transistor, and the active layer pattern of the write transistor is electrically connected to the data signal line. The second source-drain metal layer comprises an anode connection pattern. The array substrate is used for displaying an image.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Large-size, ultra-high-definition displays are increasingly popular among users. Display resolutions are constantly upgrading, from 720P to 1080P, from 2K to 4K, and finally to 8K. PPI (pixels per inch) is a unit of image resolution, representing the number of pixels per inch. Therefore, a higher PPI value indicates a higher image density capable of displaying images. The higher the display density, the greater the fidelity, enabling high-definition and ultra-high-definition displays.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided, comprising a plurality of pixel driving circuits arranged in multiple rows and columns, wherein each of the plurality of pixel driving circuits comprises a plurality of transistors, and the plurality of transistors comprises at least a write transistor.

[0005] The array substrate includes a base substrate, a first source-drain metal layer disposed on one side of the base substrate, a transistor distribution layer disposed on a side of the first source-drain metal layer away from the base substrate, and a second source-drain metal layer disposed on a side of the transistor distribution layer away from the base substrate. The first source-drain metal layer includes a data signal line. The transistor distribution layer is provided with an active layer pattern of the write transistor, which is electrically connected to the data signal line. The second source-drain metal layer includes an anode transfer pattern.

[0006] In some embodiments, the transistor distribution layer includes at least two stacked sub-transistor distribution layers. Each of the at least two sub-transistor distribution layers includes a stacked active film layer and a gate film layer. The active film layer includes an active layer pattern for the transistor, and the gate film layer includes a gate pattern for the transistor. The write transistor is located in one of the sub-transistor distribution layers.

[0007] The active layer pattern of the write transistor is electrically connected to the data signal line through the drain transfer pattern of the write transistor, and the drain transfer pattern of the write transistor is located in a first transfer gate film layer. The first transfer gate film layer is located in the sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers.

[0008] In some embodiments, the active layer pattern of the write transistor is connected to the source transfer pattern of the write transistor, wherein the source transfer pattern of the write transistor is located in a second transfer gate film layer, and the second transfer gate film layer is located in the sub-transistor distribution layer or between two adjacent sub-transistor distribution layers.

[0009] In some embodiments, the pixel circuit further includes a driving transistor and a sensing transistor, wherein an active layer pattern of the driving transistor is electrically connected to the anode switching pattern, and an active layer pattern of the sensing transistor is electrically connected to the anode switching pattern.

[0010] The active layer pattern of the driving transistor is connected to the anode switching pattern through the source switching pattern of the driving transistor. The source switching pattern of the driving transistor is located in the third switching gate film layer. The third switching gate film layer is located in the sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers.

[0011] In some embodiments, the transistor distribution layer includes a first sub-transistor distribution layer and a second sub-transistor distribution layer that are stacked, and the first sub-transistor distribution layer is closer to the substrate than the second sub-transistor distribution layer.

[0012] The transistor distribution layer further includes a fourth gate film layer located between the first sub-transistor distribution layer and the second sub-transistor distribution layer. The write transistor is located in the first sub-transistor distribution layer. The drain and source transfer patterns of the write transistor are located in the fourth gate film layer.

[0013] In some embodiments, the pixel driving circuit further includes a driving transistor, the driving transistor being located in the first sub-transistor distribution layer, and a source transfer pattern of the driving transistor being located in the fourth gate film layer.

[0014] In some embodiments, the pixel driving circuit further includes a sensing transistor, the sensing transistor being located in the second sub-transistor distribution layer. The second source / drain metal layer further includes a first sensing signal line, and the active layer pattern of the sensing transistor is further connected to the first sensing signal line.

[0015] In some embodiments, the active film layer of the first sub-transistor distribution layer is a polysilicon active film layer, and the active film layers of the second sub-transistor distribution layer are all oxide active film layers.

[0016] In some embodiments, the transistor distribution layer includes a first sub-transistor distribution layer, a second sub-transistor distribution layer, and a third sub-transistor distribution layer stacked in sequence, and the first sub-transistor distribution layer is closer to the substrate than the second sub-transistor distribution layer.

[0017] The transistor distribution layer further includes a fourth gate film layer located between the first sub-transistor distribution layer and the second sub-transistor distribution layer.

[0018] The write transistor is located in the second sub-transistor distribution layer, and the drain switching pattern of the write transistor includes a first drain switching pattern and a second drain switching pattern. The first drain switching pattern of the write transistor is located in the fourth gate film layer, and the first drain switching pattern of the write transistor is connected to the second drain switching pattern of the write transistor and is connected to the data signal line.

[0019] The second drain switching pattern of the write transistor is located in the gate film layer of the second sub-transistor distribution layer, and the second drain switching pattern of the write transistor is connected to the active film layer of the write transistor.

[0020] The source transfer pattern of the write transistor is located on the gate film layer of the second sub-transistor distribution layer.

[0021] In some embodiments, the pixel driving circuit further includes a driving transistor and a sensing transistor; the driving transistor is located in the first sub-transistor distribution layer, and the sensing transistor is located in the third sub-transistor distribution layer.

[0022] In some embodiments, the third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is closer to the base substrate than the third gate film layer.

[0023] The source transfer pattern of the driving transistor includes a first source transfer pattern and a second source transfer pattern. The first source transfer pattern of the driving transistor is located in the fourth gate film layer, and the second source transfer pattern of the driving transistor is located in the gate film layer of the second sub-transistor distribution layer. The first source transfer pattern of the driving transistor is connected to the active layer pattern of the driving transistor, and the second source transfer pattern of the driving transistor is connected to the first source transfer pattern of the driving transistor and to the anode transfer pattern.

[0024] In some embodiments, the third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is farther away from the base substrate than the third gate film layer.

[0025] The second sub-transistor distribution layer includes a second active film layer and a second gate film layer. The second active film layer is closer to the base substrate than the second gate film layer.

[0026] The third gate film layer and the second gate film layer are the same film layer, and the source switching pattern of the driving transistor is located in the fourth gate film layer.

[0027] In some embodiments, the second source-drain metal layer further includes a first voltage signal line. The active layer pattern of the driving transistor is connected to the first voltage signal line via a drain transfer pattern of the driving transistor. The drain transfer pattern of the driving transistor is located in the fourth gate film layer.

[0028] In some embodiments, the array substrate further includes a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate; the second source-drain metal layer further includes a sensing pattern, the active layer pattern of the sensing transistor is further connected to the sensing pattern, and the third source-drain metal layer includes a first sensing signal line, which is connected to the sensing pattern.

[0029] In some embodiments, the active film layer of the first sub-transistor distribution layer is a polysilicon active film layer, and the active film layers of the second sub-transistor distribution layer and the third sub-transistor distribution layer are both oxide active film layers.

[0030] In some embodiments, the transistor distribution layer includes a first sub-transistor distribution layer, a second sub-transistor distribution layer, and a third sub-transistor distribution layer that are stacked, and the first sub-transistor distribution layer is closer to the substrate than the second sub-transistor distribution layer.

[0031] The write transistor is located in the first sub-transistor distribution layer. The drain transfer pattern of the write transistor is located in the gate film layer of the second sub-transistor distribution layer, or the drain transfer pattern of the write transistor is located in the gate film layer of the first sub-transistor distribution layer. The source transfer pattern of the write transistor is located in the gate film layer of the second sub-transistor distribution layer.

[0032] In some embodiments, the pixel driving circuit further includes a driving transistor and a sensing transistor, wherein the driving transistor is located in the second sub-transistor distribution layer, and the sensing transistor is located in the third sub-transistor distribution layer.

[0033] The second source-drain metal layer further includes a first sensing signal line, and the active layer pattern of the sensing transistor is further connected to the first sensing signal line.

[0034] In some embodiments, the third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is close to the substrate relative to the third gate film layer; or, the third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is far away from the substrate relative to the third gate film layer; the fourth gate film layer is located between the second sub-transistor distribution layer and the third active film layer; the fourth gate film layer and the third gate film layer are the same film layer.

[0035] The source transfer pattern of the driving transistor is located on the fourth gate film layer.

[0036] In some embodiments, the active film layer of the first sub-transistor distribution layer, the active film layer of the second sub-transistor distribution layer, and the active film layer of the third sub-transistor distribution layer are all oxide active film layers.

[0037] In some embodiments, the array substrate further includes a light shielding layer located on one side of the array substrate.

[0038] The light shielding layer is located on a side of the first source / drain metal layer close to the array substrate, or the light shielding layer is located on a side of the first source / drain metal layer away from the array substrate.

[0039] At least one of the transistors arranged in the sub-transistor distribution layer closest to the array substrate is a dual-gate transistor; the gate film layer of the sub-transistor distribution layer closest to the array substrate is located on the side of the active film layer away from the array substrate, the gate film layer includes a top gate pattern of the dual-gate transistor, and the light-shielding layer includes a bottom gate pattern of the dual-gate transistor.

[0040] On the other hand, a display panel is provided, comprising the array substrate according to any one of the above embodiments and an anode layer disposed on the array substrate, wherein the anode layer is connected to the anode switching pattern.

[0041] In yet another aspect, a display device is provided, comprising the display panel according to the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0043] FIG1 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0044] FIG2 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0045] FIG3 is a structural diagram of an array substrate according to some embodiments of the present disclosure;

[0046] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0047] FIG5 is a structural diagram of an array substrate according to related art;

[0048] FIG6 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0049] FIG7 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0050] FIG8 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0051] FIG9A is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0052] FIG9B is a planar structural diagram of the first source / drain metal layer of the array substrate according to FIG9A ;

[0053] FIG9C is a planar structural diagram of the first active film layer of the array substrate according to FIG9A ;

[0054] FIG9D is a planar structural diagram of the first gate film layer of the array substrate according to FIG9A ;

[0055] FIG9E is a planar structural diagram of the third gate insulating layer of the array substrate according to FIG9A ;

[0056] FIG9F is a planar structural diagram of the fourth gate film layer of the array substrate according to FIG9A ;

[0057] FIG9G is a planar structural diagram of the second active film layer of the array substrate according to FIG9A ;

[0058] FIG9H is a planar structural diagram of the fourth gate insulating layer of the array substrate according to FIG9A ;

[0059] FIG9I is a planar structural diagram of the second gate film layer of the array substrate according to FIG9A ;

[0060] FIG9J is a planar structural diagram of the third active film layer of the array substrate according to FIG9A ;

[0061] FIG9K is a planar structural diagram of the third gate film layer of the array substrate according to FIG9A ;

[0062] FIG9L is a planar structural diagram of an interlayer dielectric layer of the array substrate according to FIG9A ;

[0063] FIG9M is a planar structural diagram of the second source / drain metal layer of the array substrate according to FIG9A ;

[0064] FIG9N is a planar structural diagram of the flat layer according to FIG9A ;

[0065] FIG9O is a diagram showing a film layer stacking structure of the array substrate shown in FIG9A ;

[0066] FIG9P is a diagram illustrating a film layer stacking arrangement structure of the array substrate shown in FIG9A ;

[0067] FIG10 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0068] FIG11 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0069] FIG12 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0070] FIG13 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0071] FIG14 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0072] FIG15 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0073] FIG16 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0074] FIG17 is another structural diagram of an array substrate according to some embodiments of the present disclosure;

[0075] FIG18A is a structural diagram of a drain transfer pattern of a driving transistor according to some embodiments of the present disclosure;

[0076] FIG18B is another structural diagram of a drain switching pattern of a driving transistor according to some embodiments of the present disclosure;

[0077] FIG19A is another structural diagram of a drain transfer pattern of a driving transistor according to some embodiments of the present disclosure;

[0078] FIG19B is another structural diagram of a drain transfer pattern of a driving transistor according to some embodiments of the present disclosure;

[0079] FIG20A is another structural diagram of a drain transfer pattern of a driving transistor according to some embodiments of the present disclosure;

[0080] FIG. 20B is another structural diagram of a drain switching pattern of a driving transistor according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0082] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0083] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0084] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0085] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0086] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0087] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0088] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0089] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0090] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0091] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0092] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0093] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0094] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. Display device 1000 can be any product or component with a display function, such as a television, monitor, laptop, tablet computer, mobile phone, or navigation system. FIG1 illustrates an example of a mobile phone as display device 1000.

[0095] Exemplarily, the display device 1000 may be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0096] For example, the display device 1000 may be an electroluminescent display device or a photoluminescent display device. If the display device 1000 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device 1000 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0097] The following takes the display device 1000 as an OLED display device as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation methods of the present disclosure include but are not limited to this, and any other display devices can also be considered as long as the same technical concept is applied.

[0098] Continuing to refer to FIG. 1 , the display device 1000 includes a display panel 100 .

[0099] Since the present disclosure uses an OLED display device as an example for description, when the display device 1000 is an OLED display device, the display panel 100 is an OLED display panel. However, the type of display panel 100 is not limited to this, and other display panels 100 having the following structures may also be used. In addition, the display panel 100 may be a transparent display panel. The display panel 100 may be applied to virtual reality (VR) technology. Specifically, when the display panel 100 in the embodiments of the present disclosure is applied to a VR device, the image viewed by the human eye through the VR device having the display panel 100 is a virtual image.

[0100] For example, the display panel 100 can be a flexible display panel, which is made of a flexible material. The selected flexible material can be made of a polymer material such as polyethylene terephthalate, polyarylethersulfone, polyethylene naphthalate, polyimide, etc. It should be noted that the present disclosure does not specifically limit the material of the flexible display panel. Regardless of the material selected (including all flexible materials that can be used as flexible substrates in the prior art), it needs to have a certain degree of stretchability to form a flexible display substrate. In the specific preparation process, it is necessary to select a flexible material that meets the stretchability requirements based on the actual needs of the display panel 100.

[0101] The structure of the display panel 100 is described in detail below.

[0102] As shown in Figure 2, a structural diagram of a display panel 100 provided by some embodiments of the present disclosure is shown. The display panel 100 includes an array substrate 10, a planar layer 30, a light emitting device layer 40, and an encapsulation layer (not shown) stacked in sequence.

[0103] The encapsulation layer is located on the side of the cathode layer away from the array substrate 10. For example, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer is used to encapsulate the light-emitting device layer 40 and protect the light-emitting device layer 40 from corrosion caused by external water and oxygen.

[0104] The light-emitting device layer 40 includes an anode layer 401, a pixel defining layer 402, a light-emitting layer 403, and a cathode layer 404. The anode layer 401 is disposed on the side of the planar layer 30 away from the array substrate 10. The anode layer 401 includes multiple anodes 4011. The light-emitting layer 403 includes multiple light-emitting portions, each of which overlaps with an anode 4011. Multiple pixel openings are formed in the pixel defining layer 402, each of which exposes a portion of an anode 4011. The light-emitting portions in the light-emitting layer 403 are disposed in a one-to-one correspondence within the pixel openings, so that the edges of the light-emitting portions coincide with the edges of the pixel openings. The cathode layer 404 is located on the side of the pixel defining layer 402 and the light-emitting layer 403 away from the array substrate 10.

[0105] The planar layer 30 is mainly used to block water, oxygen and alkaline ions, and can be obtained by coating PI (Polyimide) using a spin coating process, or by depositing silicon nitride, silicon oxide or silicon oxynitride using a PECVD process.

[0106] The array substrate 10 includes an anode switching pattern 1152 . The anode switching pattern 1152 is connected to the anode layer 401 through a via hole penetrating the planar layer 30 .

[0107] The structure of the array substrate 10 is described in detail below.

[0108] As shown in FIG3 , the array substrate 10 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA includes a plurality of sub-pixel regions A1 arranged according to a predetermined rule within the display area AA. Each sub-pixel region A1 includes a pixel driver circuit 20.

[0109] Exemplarily, the plurality of sub-pixel regions A1 are arranged in multiple rows and columns. Since a pixel driving circuit 20 is disposed in each sub-pixel region A1 , the pixel driving circuits 20 are also arranged in multiple rows and columns.

[0110] The pixel driving circuit 20 includes a plurality of transistors. As shown in FIG4 , FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit 20 provided in some embodiments of the present disclosure. It should be noted that FIG4 is taken as an example of a 3T1C structure of the pixel driving circuit 20 for illustration, but the structure of the pixel driving circuit 20 in the present disclosure is not limited thereto. For example, the pixel driving circuit 20 may be a 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T represents a transistor, and the number in front of T represents the number of transistors; C represents a capacitor, and the number in front of C represents the number of capacitors.

[0111] 4 , the pixel driving circuit 20 includes three transistors and one storage capacitor C. The three transistors are a driving transistor T1 , a writing transistor T2 , and a sensing transistor T3 .

[0112] Exemplarily, the driving transistor T1, the writing transistor T2, and the sensing transistor T3 in the pixel driving circuit 20 may be low-temperature polysilicon transistors, or may be oxide transistors, or may be low-temperature polysilicon transistors and oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have the advantages of high mobility and fast charging, while oxide transistors have the advantages of low leakage current. Low-temperature polysilicon transistors and oxide transistors are integrated on an array substrate 10 to form a low-temperature polycrystalline oxide (LTPO) array substrate. By utilizing the advantages of both, the refresh frequency of the array substrate 10 can be switched to achieve low-frequency driving, which is beneficial to reducing power consumption and improving display quality.

[0113] For example, the drive transistor T1, write transistor T2, and sense transistor T3 can be top-gate transistors, bottom-gate transistors, or dual-gate transistors. A dual-gate transistor includes an active layer pattern and top and bottom gate patterns disposed on either side of the active layer pattern. The top and bottom gate patterns drive the active layer pattern, making it easier to control the threshold voltage and improving carrier mobility. This means that compared to top-gate and bottom-gate transistors, dual-gate transistors offer greater stability.

[0114] Exemplarily, the driving transistor T1, the writing transistor T2 and the sensing transistor T3 may be P-type transistors, or may be N-type transistors. For example, the driving transistor T1, the writing transistor T2 and the sensing transistor T3 may include P-type transistors and N-type transistors; for another example, the driving transistor T1, the writing transistor T2 and the sensing transistor T3 may all be N-type transistors or all be P-type transistors. Using the same type of transistors in the pixel driving circuit 20 can simplify the process flow, reduce the process difficulty of the array substrate 10, and improve the yield of the product. The following takes the driving transistor T1, the writing transistor T2 and the sensing transistor T3 as N-type transistors as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure include but are not limited to this, and any other types of transistors can also be considered, as long as the same technical ideas are applied.

[0115] The connection relationship among the driving transistor T1 , the writing transistor T2 , the sensing transistor T3 , the storage capacitor C, and the signal lines in the pixel driving circuit 20 shown in FIG. 4 is schematically described below.

[0116] The drain of the driving transistor T1 is connected to the first voltage signal line VDD, the source of the driving transistor T1 is connected to the anode of the light-emitting device D, and the gate of the driving transistor T1 is connected to the source of the write transistor T2; the drain of the write transistor T2 is connected to the data signal line DATA, the source of the write transistor T2 is respectively connected to the gate of the driving transistor T1 and one end of the storage capacitor C, and the gate of the write transistor T2 is connected to the scan signal line SCAN; the drain of the sensing transistor T3 is connected to the sensing signal line SENSE, the source of the sensing transistor is respectively connected to the anode of the light-emitting device D and the other end of the storage capacitor C, and the gate of the sensing transistor T3 is connected to the scan signal line.

[0117] The pixel driving circuit 20 is disposed in the film structure of the array substrate 10. The following describes the film structures of the array substrate 10 and the arrangement of the transistors in the pixel driving circuit 20.

[0118] As shown in Figure 5, which is a structural diagram of an array substrate 10' in the related art, the array substrate 10' comprises a base substrate 101, a transistor distribution layer 2, a second source-drain metal layer 115' and a first source-drain metal layer 109' stacked in sequence.

[0119] The first source-drain metal layer 109' includes a data signal line 1091 and an anode transfer pattern 1152. The second source-drain metal layer 115' includes a first drain transfer pattern 1122 of the write transistor T2 and an anode transfer pattern 1152. It is understood that the anode transfer pattern 1152 is distributed in two metal layers.

[0120] The driving transistor T1, the writing transistor T2 and the sensing transistor T3 of the pixel driving circuit 20 are disposed in the transistor distribution layer 2. The transistor distribution layer 2 includes an active layer pattern T11 of the driving transistor T1 and an active layer pattern T21 of the writing transistor T2.

[0121] The active layer pattern T21 of the write transistor T2 needs to be electrically connected to the data signal line 1091 on the first source-drain metal layer 109' through the via and the first drain transfer pattern 1122 of the write transistor T2 on the second source-drain metal layer 115', and the active layer pattern T11 of the driving transistor T1 is electrically connected through the anode transfer pattern on the second source-drain metal layer 115' and the anode transfer pattern on the first source-drain metal layer 109'. On the one hand, the first source-drain metal layer 109' is provided with a plurality of signal lines and a plurality of transfer patterns, such as a data signal line 1091 and an anode transfer pattern 1152, and the second source-drain metal layer 115' is also provided with a plurality of signal lines and a plurality of transfer patterns, such as a first drain transfer pattern 1122 and an anode transfer pattern 1152 of the write transistor T2, which increases the wiring difficulty of the first source-drain metal layer 109' and the second source-drain metal layer 115', and reduces the number of pixel driving circuits 20 that can be set in the array substrate 10'; on the other hand, the active layer pattern T21 of the write transistor T2 needs to be electrically connected to the data signal line 1091 on the first source-drain metal layer 109' through a via hole, and the active layer pattern T11 of the drive transistor T1 also needs to be electrically connected to the data signal line 1091 on the first source-drain metal layer 109'. To electrically connect in sequence through another via and the anode transfer pattern on the second source-drain metal layer 115' and the anode transfer pattern on the first source-drain metal layer 109', the above two vias are located on the same side of the active layer pattern of the corresponding transistors (write transistor T2 and drive transistor T1) (for the convenience of description, collectively referred to as same-direction vias below), resulting in a large number of same-direction vias in the array substrate 10. The active layer patterns of each transistor in the sub-pixel area A1 need not overlap with each other to facilitate the reservation of space for multiple same-direction vias, resulting in a larger space occupied by the pixel driving circuit 20. The number of pixel driving circuits 20 that can be set in the array substrate 10' is further reduced, which is not conducive to the display panel 100 achieving high PPI (Pixels Per Inch, pixel density).

[0122] Based on this, as shown in Figures 6 to 9A and 10 to 17, Figures 6 to 9A and 10 to 17 are structural diagrams of an array substrate 10 provided according to some embodiments of the present disclosure. Array substrate 10 includes a base substrate 101, a first source / drain metal layer 109, a transistor distribution layer 2, and a second source / drain metal layer 115, which are stacked in sequence. Specifically, the first source / drain metal layer 109 and the second source / drain metal layer 115 are disposed on opposite sides of the transistor distribution layer 2, with the first source / drain metal layer 109 being closer to the base substrate 101 than the second source / drain metal layer 115.

[0123] For example, the base substrate 101 may be a hard substrate made of a light-conducting and non-metallic material with a certain degree of durability, such as glass, quartz, or common resin. Alternatively, the base substrate 101 may be a flexible substrate made of a flexible material such as polyimide (PI).

[0124] The first source / drain metal layer 109 includes a data signal line 1091, and the second source / drain metal layer 115 includes an anode transfer pattern 1152. For example, the first source / drain metal layer 109 and the second source / drain metal layer 115 can be formed by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD (Physical Vapor Deposition) process.

[0125] A write transistor T2 is disposed within the transistor distribution layer 2. The write transistor T2 includes an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0126] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 . Specifically, the drain region T21 b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 .

[0127] By disposing the first source-drain metal layer 109 and the second source-drain metal layer 115 on opposite sides of the transistor distribution layer 2, that is, the second source-drain metal layer 115 is not disposed between the first source-drain metal layer 109 and the transistor distribution layer 2, the active layer pattern T21 of the write transistor T2 in the transistor distribution layer 2 and the data signal line 1091 on the first source-drain metal layer 109 do not need to pass through the second source-drain metal layer 115 when electrically connecting. Therefore, the first drain electrode transfer pattern 1122 of the write transistor T2 does not need to be disposed on the second source-drain metal layer 115, which can reduce the wiring difficulty of the second source-drain metal layer 115. The number of pixel driving circuits 20 disposed in the array substrate 10 having the same area as the array substrate 10 ′ shown in FIG. 5 is increased, which is conducive to improving the PPI (Pixels Per Inch) of the display panel 100. Moreover, the anode transfer pattern 1152 on the second source-drain metal layer 115 and the anode layer 401 in the light-emitting device layer 40 do not need to pass through the first source-drain metal layer 109 when being electrically connected. Therefore, the anode transfer pattern 1152 does not need to be set on the first source-drain metal layer 109, which can reduce the wiring difficulty of the first source-drain metal layer 109. The number of pixel driving circuits 20 that can be set in the array substrate 10 with the same area as the array substrate 10' shown in Figure 5 above is increased, which is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0128] On the other hand, the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 on the first source-drain metal layer 109' through a via hole facing the base substrate 101, and the active layer pattern T11 of the drive transistor T1 is electrically connected to the anode transfer pattern on the second source-drain metal layer 109' through another via hole facing the side away from the base substrate 101. The above two vias are located on both sides of the active layer pattern of the corresponding transistors (the write transistor T2 and the drive transistor T1), that is, they are not unidirectional vias, which can reduce the number of unidirectional vias in the array substrate 10, which is beneficial to increase the number of pixel driving circuits 20 that can be set in the array substrate 10' and further improve the PPI (Pixels Per Inch) of the display panel 100.

[0129] It should be noted that the aforementioned "area of ​​the array substrate 10" refers to the lateral dimensions of the array substrate 10 on a reference plane (the reference plane is parallel to the base substrate 101 within the array substrate 10), i.e., the area of ​​the array substrate 10's orthographic projection onto the reference plane. Similarly, the aforementioned "area of ​​the array substrate 10'" refers to the lateral dimensions of the array substrate 10' on the reference plane, i.e., the area of ​​the array substrate 10's orthographic projection onto the reference plane. This description also applies to the following descriptions of the "area of ​​the array substrate 10" and "area of ​​the array substrate 10'."

[0130] In some embodiments, referring to Figures 6 to 9A and 10 to 17 , the transistor distribution layer 2 includes at least two stacked sub-transistor distribution layers and a fourth gate film layer 112 . The drive transistor T1, write transistor T2, and sense transistor T3 in the pixel drive circuit 20 are disposed in the at least two sub-transistor distribution layers. Each of the at least two sub-transistor distribution layers includes a stacked active film layer and a gate film layer; the active film layer includes an active layer pattern for the transistor, and the gate film layer includes a gate pattern for the transistor. Specifically, the drive transistor T1 includes an active layer pattern T11 for the drive transistor T1 and a gate pattern T12 for the drive transistor T1; the write transistor T2 includes an active layer pattern T21 for the write transistor T2 and a gate pattern T22 for the write transistor T2; and the sense transistor T3 includes an active layer pattern T31 for the sense transistor T3 and a gate pattern T32 for the sense transistor T3. The first plate C1 of the storage capacitor C in the pixel driving circuit 20 is disposed on the fourth gate film layer 112 , and the gate pattern T12 of the driving transistor T1 also serves as the second plate C2 of the storage capacitor C.

[0131] Among them, the active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 includes a source region T21c of the writing transistor T2, a drain region T21b of the writing transistor T2, and a channel region T21a of the writing transistor T2 located between the source region T21c and the drain region T21b of the writing transistor T2; the active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0132] It should be noted that the phrase "the transistor distribution layer 2 includes at least two stacked sub-transistor distribution layers" means that the number of sub-transistor distribution layers in the transistor distribution layer 2 is greater than or equal to two. For example, as shown in Figures 6, 7, and 8, the number of sub-transistor distribution layers in the transistor distribution layer 2 can be two, including a first sub-transistor distribution layer 21 and a second sub-transistor distribution layer 22; or, as shown in Figures 9A to 17, the number of sub-transistor distribution layers in the transistor distribution layer 2 can be three, including a first sub-transistor distribution layer 21, a second sub-transistor distribution layer 22, and a third sub-transistor distribution layer 23. Of course, the number of sub-transistor distribution layers in the transistor distribution layer 2 can also be four, five, or six, etc., according to actual needs, and this disclosure does not impose any specific limitations on this.

[0133] For example, at least two transistors arranged in different sub-transistor distribution layers have their corresponding transistor active layer patterns with at least partially overlapping orthographic projections on the base substrate 101, which can reduce the total area of ​​the orthographic projections of multiple transistors on the base substrate 101 in a single pixel driving circuit 20, thereby reducing the area of ​​a single pixel driving circuit 20 and further increasing the number of pixel driving circuits 20 in the array substrate 10 per unit area, which is beneficial to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0134] In some embodiments, referring to Figures 6 to 9A and 10 to 17 , the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 on the first source-drain metal layer 109 via the drain transfer pattern of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 via the drain transfer pattern of the write transistor T2. The drain transfer pattern of the write transistor T2 is located in the first transfer gate film layer, that is, the film layer in the array substrate 10 on which the drain transfer pattern of the write transistor T2 is provided serves as the first transfer gate film layer. The first transfer gate film layer can be located in a sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers. Compared with Figure 5, the source transfer pattern / drain transfer pattern of each transistor is set in the second source-drain metal layer 115', and the film layer in the sub-transistor distribution layer and / or the film layer located between two adjacent sub-transistor distribution layers is used as the first transfer gate film layer for setting the drain transfer pattern of the write transistor T2. In other words, the drain transfer pattern of the write transistor T2 is dispersed to the film layer located between the first source-drain metal layer 109 and the second source-drain metal layer 115. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, which is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0135] For example, the number of first transfer gate film layers in the array substrate 10 can be one. For example, the first transfer gate film layer can be disposed between two adjacent sub-transistor distribution layers, or the gate film layer in one of at least two sub-transistor distribution layers can serve as the first transfer gate film layer. The number of first transfer gate film layers in the array substrate 10 can also be two, with one first transfer gate film layer disposed between two adjacent sub-transistor distribution layers and the other first transfer gate film layer serving as the gate film layer in one of the at least two sub-transistor distribution layers.

[0136] In some embodiments, referring to Figures 6 to 9A and 10 to 17 , the active layer pattern T21 of the write transistor T2 is connected to the source transfer pattern of the write transistor T2. Specifically, the source region T21c of the active layer pattern T21 of the write transistor T2 is connected to the source transfer pattern of the write transistor T2. The source transfer pattern of the write transistor T2 is located in a second transfer gate film layer, that is, the film layer in the array substrate 10 on which the source transfer pattern of the write transistor T2 is provided serves as the second transfer gate film layer. The second transfer gate film layer is located in a sub-transistor distribution layer or between two adjacent sub-transistor distribution layers. Compared with Figure 5, the source transfer pattern / drain transfer pattern of each transistor is set in the second source-drain metal layer 115', and the film layer in the sub-transistor distribution layer or the film layer located between two adjacent sub-transistor distribution layers is used as the second transfer gate film layer for setting the source transfer pattern of the write transistor T2. In other words, the source transfer pattern of the write transistor T2 is dispersed to the film layer located between the first source-drain metal layer 109 and the second source-drain metal layer 115. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, which is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0137] For example, the second transfer gate film layer in the array substrate 10 may be disposed between two adjacent sub-transistor distribution layers, or the gate film layer in one of at least two sub-transistor distribution layers may be used as the second transfer gate film layer.

[0138] In some embodiments, referring to Figures 6 to 9A and 10 to 17 , the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 via the source transfer pattern of the driving transistor T1. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 via the source transfer pattern of the driving transistor T1.

[0139] The source transfer pattern of the driving transistor T1 is located in the third transfer gate film layer, which is located in the sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers. Compared to Figure 5, the source transfer pattern / drain transfer pattern of each transistor is set in the second source-drain metal layer 115'. The film layer in the sub-transistor distribution layer and / or the film layer between two adjacent sub-transistor distribution layers is used as the third transfer gate film layer for setting the source transfer pattern of the driving transistor T1. This can reduce the wiring difficulty of other film layers (second source-drain metal layer 115) in the array substrate 10, which is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0140] For example, the number of third transfer gate film layers in the array substrate 10 can be one. For example, the third transfer gate film layer can be disposed between two adjacent sub-transistor distribution layers, or the gate film layer in one of the at least two sub-transistor distribution layers can serve as the third transfer gate film layer. The number of third transfer gate film layers in the array substrate 10 can also be two, with one third transfer gate film layer disposed between two adjacent sub-transistor distribution layers and the other third transfer gate film layer serving as the gate film layer in one of the at least two sub-transistor distribution layers.

[0141] Hereinafter, please refer to FIG. 6 to FIG. 17 again to describe each embodiment of the present disclosure.

[0142] It should be noted that in this disclosure and the accompanying drawings, the same reference numerals are used to denote the same elements as previously described, and detailed descriptions are omitted as appropriate. The "Z" direction in Figures 6 to 9A and 10 to 17 refers to the thickness direction of the array substrate 10.

[0143] First, an embodiment in which the transistor distribution layer 2 includes two sub-transistor distribution layers is described.

[0144] The array substrate shown in FIG6 is described below. In some embodiments, as shown in FIG6 , FIG6 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, an interlayer dielectric layer 108, and a second source-drain metal layer 115, which are stacked in sequence.

[0145] The first active film layer 110 may be made of low-temperature polysilicon; the second active film layer 113 may be made of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) or IGZTO (Indium gallium zinc tin oxide).

[0146] For example, the first active film layer 110 may be formed by an excimer laser annealing process; and the second active film layer 113 may be formed by a PVD (Physical Vapor Deposition) process.

[0147] For example, the first buffer layer 102 and the second buffer layer 106 may be prepared by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the materials thereof may be silicon nitride, silicon oxide or silicon oxynitride, which have the function of water and gas barrier.

[0148] For example, the materials of the first gate insulating layer 103 , the second gate insulating layer 104 , the third gate insulating layer 105 and the fourth gate insulating layer 107 may be silicon nitride, silicon oxide or silicon oxynitride, and may be deposited by a PECVD process.

[0149] For example, the first gate film layer 110 , the fourth gate film layer 112 , and the second gate film layer 114 can be formed by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD process.

[0150] Illustratively, the material of the interlayer dielectric layer 108 may be any one of silicon nitride, silicon oxide or silicon oxynitride, or a combination of any two of these materials, and may be deposited using a PECVD process.

[0151] Referring again to Figure 6 , the transistor distribution layer 2 includes a stacked first sub-transistor distribution layer 21, a fourth gate film layer 112, and a second sub-transistor distribution layer 22. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the second sub-transistor distribution layer 22. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the second sub-transistor distribution layer 22 and the base substrate 101. The fourth gate film layer 112 is disposed between the first sub-transistor distribution layer 21 and the second sub-transistor distribution layer 22.

[0152] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The driving transistor T1 and the writing transistor T2 of the pixel driving circuit 20 are arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 is low-temperature polysilicon, the driving transistor T1 and the writing transistor T2 are low-temperature polysilicon transistors.

[0153] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0154] In this embodiment, the driving transistor T1 may be a top-gate transistor, including an active layer pattern T11 of the driving transistor T1 and a gate pattern T12 of the driving transistor T1 . The active layer pattern T11 of the driving transistor T1 is disposed on the first active film layer 110 , and the gate pattern T12 of the driving transistor is disposed on the first gate film layer 111 .

[0155] In this embodiment, the write transistor T2 may be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, and the gate pattern T22 of the write transistor T2 is disposed on the first gate film layer 111.

[0156] In this embodiment, the sensing transistor T3 may be a top-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a gate pattern T32 of the sensing transistor T3 . The active layer pattern T31 of the sensing transistor T3 is disposed on the second active film layer 113 , and the gate pattern T32 of the sensing transistor T3 is disposed on the second gate film layer 114 .

[0157] The first source / drain metal layer 109 includes a data signal line 1091 .

[0158] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the drive transistor T1, a first drain transfer pattern 1122 of the write transistor T2, and a source transfer pattern 1123 of the write transistor T2. It should be noted that in this embodiment, the fourth gate film layer 112 serves as both the first transfer gate film layer, the second transfer gate film layer, and the third transfer gate film layer.

[0159] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115′, the fourth gate film layer 112 in this embodiment serves as the first transfer gate film layer, the second transfer gate film layer, and the third transfer gate film layer, and is used to provide the first source transfer pattern 1121 of the driving transistor T1, the first drain transfer pattern 1122 of the writing transistor T2, and the source transfer pattern 1123 of the writing transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0160] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0161] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. The active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1. Specifically, the source region T11c of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1.

[0162] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and a first drain transfer pattern 1122 of the write transistor T2. Specifically, the drain region T21b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the first drain transfer pattern 1122 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2.

[0163] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c of the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0164] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sense transistor T3 disposed in the second sub-transistor distribution layer 22. That is, within a sub-pixel region A1, the write transistor T2 and the sense transistor T3 have an overlapping region CC. Providing the overlapping region CC can further reduce the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0165] The array substrate 10 shown in FIG. 7 and FIG. 8 is introduced below. In some embodiments, as shown in FIG. 7 and FIG. 8 , both FIG. 7 and FIG. 8 are structural diagrams of the array substrate 10 provided according to some embodiments of the present disclosure.

[0166] As shown in FIG7 , the array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source / drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, an interlayer dielectric layer 108, and a second source / drain metal layer 115, which are stacked in sequence. The light shielding layer 117 is located on the side of the first source / drain metal layer 109 close to the base substrate 101, that is, the light shielding layer 117 is located between the first source / drain metal layer 109 and the base substrate 101.

[0167] Alternatively, as shown in FIG8 , the array substrate 10 includes a base substrate 101, a first buffer layer 102, a first source / drain metal layer 109, a third buffer layer 116, a light shielding layer 117, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, an interlayer dielectric layer 108, and a second source / drain metal layer 115, which are stacked in sequence. The light shielding layer 117 is located on a side of the first source / drain metal layer 109 away from the base substrate 101, that is, the first source / drain metal layer 109 is located between the light shielding layer 117 and the base substrate 101.

[0168] The light shielding layer 117 can block light from entering the array substrate 10 from the side of the base substrate 101 away from the light shielding layer 117. The light shielding layer 117 overlaps with the active layer pattern T11 of the driving transistor T1. Specifically, the light shielding layer 117 overlaps with the channel region T11a of the active layer pattern T11 of the driving transistor T1. This can block light from entering the driving transistor T1, thereby preventing the characteristics of the driving transistor T1 from being affected by light. Exemplarily, the material of the light shielding layer 117 can be amorphous silicon.

[0169] The third buffer layer 116 can be prepared by using PECVD (Plasma Enhanced Chemical Vapor Deposition), and its material can be silicon nitride, silicon oxide or silicon oxynitride, which has the function of water and gas barrier.

[0170] The materials and preparation process of the first active film layer 110, the second active film layer 113, the first buffer layer 102, the second buffer layer 106, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114 and the interlayer dielectric layer 108 are basically the same as those in the embodiment shown in Figure 6 and will not be repeated here.

[0171] Referring again to Figures 7 and 8, the transistor distribution layer 2 includes a stacked first sub-transistor distribution layer 21, a fourth gate film layer 112, and a second sub-transistor distribution layer 22. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the second sub-transistor distribution layer 22. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the second sub-transistor distribution layer 22 and the base substrate 101. The fourth gate film layer 112 is disposed between the first sub-transistor distribution layer 21 and the second sub-transistor distribution layer 22.

[0172] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The driving transistor T1 and the writing transistor T2 of the pixel driving circuit 20 are arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 is low-temperature polysilicon, the driving transistor T1 and the writing transistor T2 are low-temperature polysilicon transistors.

[0173] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0174] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the first active film layer 110, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the first gate film layer 111, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0175] In this embodiment, the write transistor T2 can be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, and the gate pattern T22 of the write transistor T2 is disposed on the first gate film layer 111. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0176] In this embodiment, the sensing transistor T3 may be a dual-gate transistor, including an active layer pattern T31 of the sensing transistor T3, a gate pattern T32 (top gate pattern) of the sensing transistor T3, and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the second active film layer 113, the gate pattern T32 (top gate pattern) of the sensing transistor T3 is disposed on the second gate film layer 114, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the first gate film layer 111. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0177] The first source / drain metal layer 109 includes a data signal line 1091 .

[0178] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the drive transistor T1, a first drain transfer pattern 1122 of the write transistor T2, and a source transfer pattern 1123 of the write transistor T2. It should be noted that in this embodiment, the fourth gate film layer 112 serves as both the first transfer gate film layer, the second transfer gate film layer, and the third transfer gate film layer.

[0179] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115′, in this embodiment, the fourth gate film layer 112 is simultaneously used as the first transfer gate film layer, the second transfer gate film layer, and the third transfer gate film layer to provide the first source transfer pattern 1121 of the driving transistor T1, the first drain transfer pattern 1122 of the writing transistor T2, and the source transfer pattern 1123 of the writing transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0180] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0181] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. The active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1.

[0182] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and a first drain transfer pattern 1122 of the write transistor T2. Specifically, the drain region T21b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the first drain transfer pattern 1122 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2.

[0183] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0184] The embodiments shown in FIG7 and FIG8 differ from the embodiment shown in FIG6 in that:

[0185] In the embodiments shown in Figures 7 and 8 , the array substrate 10 further includes a light shielding layer 117 and a third buffer layer 116. In the embodiment shown in Figure 7 , the light shielding layer 117 and the third buffer layer 116 are disposed between the first buffer layer 102 and the first source / drain metal layer 109. In the embodiment shown in Figure 8 , the third buffer layer 116 and the light shielding layer 117 are disposed between the first source / drain metal layer 109 and the first gate insulating layer 103.

[0186] 7 and 8 , the driving transistor T1 and the sensing transistor T3 are both dual-gate transistors, wherein the bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117 , and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the first gate film layer 111 .

[0187] Next, an embodiment in which the transistor distribution layer 2 includes three sub-transistor distribution layers is described.

[0188] The following introduces the array substrate 10 shown in Figures 9A to 9P. In some embodiments, as shown in Figures 9A to 9P, Figure 9A is a structural diagram of the array substrate 10 provided according to some embodiments of the present disclosure, Figures 9B to 9N are planar structural diagrams of the various film layers of the array substrate 10 in Figure 9A, Figure 9O is a film layer stacking structure diagram of the array substrate 10 shown in Figure 9A, and Figure 9P is a film layer stacking arrangement structure diagram of the array substrate 10 shown in Figure 9A. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, a fourth buffer layer 121, a third active film layer 119, a fifth gate insulating layer 118, a third gate film layer 120, an interlayer dielectric layer 108 and a second source-drain metal layer 115, which are stacked in sequence.

[0189] The first active film layer 110 may be made of low-temperature polysilicon; the second active film layer 113 may be made of indium gallium zinc oxide or a low-temperature polycrystalline oxide, such as IGZO (Indium gallium zinc oxide) or IGZTO (Indium gallium zinc tin oxide); and the third active film layer 119 may be made of indium gallium zinc oxide or a low-temperature polycrystalline oxide, such as IGZO (Indium gallium zinc oxide) or IGZTO (Indium gallium zinc tin oxide). If the first active film layer 110 is made of low-temperature polysilicon, the corresponding drive transistor T1 is a low-temperature polysilicon transistor. If the second and third active film layers 113 and 119 are both made of indium gallium zinc oxide or a low-temperature polycrystalline oxide, the corresponding write transistor T2 and sensing transistor T3 are oxide transistors. Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Low-temperature polysilicon transistors and oxide transistors are integrated on an array substrate 10 to form a low-temperature polycrystalline oxide (LTPO) array substrate. By leveraging the advantages of both, the refresh frequency of the array substrate 10 can be switched to achieve low-frequency drive, which helps reduce power consumption and improve display quality. For example, the first active film layer 110 can be obtained using an excimer laser annealing process; the second active film layer 113 and the third active film layer 119 can be obtained using a PVD (Physical Vapor Deposition) process.

[0190] For example, the fourth buffer layer 121 may be prepared by using PECVD (Plasma Enhanced Chemical Vapor Deposition), and its material may be silicon nitride, silicon oxide or silicon oxynitride, which has the function of blocking water and gas.

[0191] For example, the material of the fifth gate insulating layer 118 may be silicon nitride, silicon oxide, or silicon oxynitride, and may be deposited using a PECVD process.

[0192] For example, the third gate film layer 120 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) through a PVD process.

[0193] The materials and preparation process of the first buffer layer 102, the second buffer layer 106, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114 and the interlayer dielectric layer 108 are basically the same as those in the embodiment shown in Figure 6 and will not be repeated here.

[0194] Referring again to FIG. 9A , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a fourth gate film layer 112, a second sub-transistor distribution layer 22, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the substrate 101. The fourth gate film layer 112 is disposed between the first sub-transistor distribution layer 21 and the second sub-transistor distribution layer 22.

[0195] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The driving transistor T1 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 is low-temperature polysilicon, the driving transistor T1 is a low-temperature polysilicon transistor.

[0196] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The write transistor T2 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0197] The third sub-transistor distribution layer 23 includes a third active film layer 119 and a third gate film layer 120. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0198] In this embodiment, the driving transistor T1 can be a top-gate transistor, including an active layer pattern T11 of the driving transistor T1 and a gate pattern T12 of the driving transistor T1. As shown in Figure 9C, the active layer pattern T11 of the driving transistor T1 is disposed on the first active film layer 110. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1. As shown in Figure 9D, the gate pattern T12 of the driving transistor is disposed on the first gate film layer 111.

[0199] In this embodiment, the write transistor T2 can be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. As shown in Figure 9G, the active layer pattern T21 of the write transistor T2 is disposed in the second active film layer 113. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2. The gate pattern T22 of the write transistor T2 is disposed in the second gate film layer 114.

[0200] In this embodiment, the sensing transistor T3 can be a top-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a gate pattern T32 of the sensing transistor T3. As shown in Figure 9J , the active layer pattern T31 of the sensing transistor T3 is disposed in the third active film layer 119. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3. As shown in Figure 9K , the gate pattern T32 of the sensing transistor T3 is disposed in the third gate film layer 120.

[0201] As shown in FIG. 9B and FIG. 9O , the first source / drain metal layer 109 includes a data signal line 1091 .

[0202] As shown in Figures 9F and 9O, the fourth gate film layer 112 includes a first source transfer pattern 1121 of the drive transistor T1, a drain transfer pattern 1124 of the drive transistor T1, and a first drain transfer pattern 1122 of the write transistor T2. It should be noted that in this embodiment, the fourth gate film layer 112 serves as both the third transfer gate film layer and the first transfer gate film layer.

[0203] As shown in Figures 9I and 9O, the second gate film layer 114 includes a second source transfer pattern 1141 of the drive transistor T1, a source transfer pattern 1123 of the write transistor T2, and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both the third transfer gate film layer, the second transfer gate film layer, and the first transfer gate film layer.

[0204] Compared to the embodiment shown in FIG. 5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115 ′, in this embodiment, the second gate film layer 114 in the second sub-transistor distribution layer 22 serves simultaneously as the third transfer gate film layer, the second transfer gate film layer, and the first transfer gate film layer for disposing the second source transfer pattern 1141 of the drive transistor T1, the source transfer pattern 1123 of the write transistor T2, and the second drain transfer pattern 1142 of the write transistor T2. Furthermore, the fourth gate film layer 112 serves simultaneously as the third transfer gate film layer and the first transfer gate film layer for disposing the first source transfer pattern 1121 of the drive transistor T1, the drain transfer pattern 1124 of the drive transistor T1, and the first drain transfer pattern 1122 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115 ) in the array substrate 10, thereby further improving the PPI (Pixels Per Inch) of the display panel 100.

[0205] As shown in FIG. 9M and FIG. 9O , the second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0206] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via, the first source transfer pattern 1121 of the driving transistor T1, the second source transfer pattern 1141 of the driving transistor T1, and the anode transfer pattern 1152. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via, the first source transfer pattern 1121 of the driving transistor T1, the second source transfer pattern 1141 of the driving transistor T1, and the anode transfer pattern 1152.

[0207] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via, a first drain transfer pattern 1122 of the write transistor T2, and a second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via, the first drain transfer pattern 1122 of the write transistor T2, and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2.

[0208] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through the via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through the via. Specifically, the source region T31c of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through the via.

[0209] For example, referring again to FIG. 9A , along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the second sub-transistor distribution layer 22 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. Providing the overlapping region CC further reduces the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0210] In some embodiments, as shown in FIG. 9O , at least three sub-pixel regions A1 constitute a pixel unit region P.

[0211] The above “at least three sub-pixel regions A1 constitute a pixel unit region P” means that each pixel unit region P may include three, four or more sub-pixel regions A1, and the multiple sub-pixel regions A1 included in each pixel unit region P may be a row, a column or a group of sub-pixel regions A1, a group of sub-pixel regions A1 may be multiple sub-pixel regions A1 adjacent to each other, and the adjacent multiple sub-pixel regions A1 are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc. At the same time, the luminous areas of the multiple sub-pixel regions A1 included in each pixel unit region P may be the same or not completely the same. The above is only an exemplary description and is not a limitation of the present disclosure. It can be adaptively designed according to actual needs.

[0212] In some examples, the multiple sub-pixel regions A1 emit light of the same color, and the array substrate 10 may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixel regions A1.

[0213] For example, multiple sub-pixel areas A1 all emit white light, red light, green light or blue light. In this case, the colored light emitted by the sub-pixel area A1 remains the same color light after passing through the color filter layer, or is converted into other color light and emitted. Therefore, when multiple sub-pixel areas A1 emit the same color light, the array substrate 10 can achieve multi-color light output.

[0214] In other examples, multiple sub-pixel areas A1 emit light of different colors. For example, multiple sub-pixel areas A1 include a red sub-pixel area A1 that emits red light, a green sub-pixel area A1 that emits green light, and a blue sub-pixel area A1 that emits blue light, thereby realizing multi-color light output of the array substrate 10.

[0215] 9O , and in combination with FIG. 9A to FIG. 9N , the array substrate 10 further includes a second sensing signal line 1125 disposed on the fourth gate film layer 112 , and the second sensing signal line 1125 is connected to a first sensing signal line 1153 disposed on the second source / drain metal layer 115 through a via.

[0216] In some embodiments, as shown in FIG9P , and in combination with FIG9A to FIG9O , FIG9P takes the arrangement of four pixel unit areas P as an example. The four pixel unit areas P are arranged in a 2*2 arrangement, and two adjacent unit areas P are symmetrically arranged with each other. For example, the four pixel unit areas P have a first symmetry axis M extending along the first direction X and a second symmetry axis N extending along the second direction Y. The four pixel unit areas P are symmetrically arranged along the first symmetry axis M and symmetrically arranged along the second symmetry axis N. In this way, the multiple pixel unit areas P can be closely arranged, and the spacing between the pixel unit areas P can be reduced, which is beneficial to improving the PPI of the array substrate 10.

[0217] The second sensing signal line 1125 extends along the second direction Y. In the first direction X, the pixel unit areas P on both sides of the second sensing signal line 1125 can share the same second sensing signal line 1125, which can reduce the number of second sensing signal lines 1125 in the array substrate 10, so that there is more space in the array substrate 10 for setting the pixel unit area P, which is conducive to further improving the PPI of the array substrate 10.

[0218] It should be noted that FIG9P only illustrates the arrangement of the pixel unit area P using the array substrate 10 shown in FIG9A as an example. The arrangement of the pixel unit area P is also applicable to the array substrate 10 in other embodiments of the present disclosure and will not be repeated here.

[0219] The array substrate 10 shown in FIG10 is described below. In some embodiments, as shown in FIG10 , FIG10 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, a fourth buffer layer 121, a third active film layer 119, a fifth gate insulating layer 118, a third gate film layer 120, an interlayer dielectric layer 108, and a second source-drain metal layer 115, which are stacked in sequence.

[0220] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0221] The light shielding layer 117 can block light emitted from the side of the base substrate 101 away from the light shielding layer 117 to the inside of the array substrate 10. Exemplarily, the material of the light shielding layer 117 can be amorphous silicon.

[0222] The third buffer layer 116 can be prepared by using PECVD (Plasma Enhanced Chemical Vapor Deposition), and its material can be silicon nitride, silicon oxide or silicon oxynitride, which has the function of water and gas barrier.

[0223] The materials and preparation process of the first active film layer 110, the second active film layer 113, the third active film layer 119, the first buffer layer 102, the second buffer layer 106, the fourth buffer layer 121, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114, the third gate film layer 120 and the interlayer dielectric layer 108 are basically the same as those in the embodiment shown in Figure 9A and will not be repeated here.

[0224] Referring again to Figure 10 , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a fourth gate film layer 112, a second sub-transistor distribution layer 22, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the base substrate 101. The fourth gate film layer 112 is disposed between the first sub-transistor distribution layer 21 and the second sub-transistor distribution layer 22.

[0225] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The driving transistor T1 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 is low-temperature polysilicon, the driving transistor T1 is a low-temperature polysilicon transistor.

[0226] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The write transistor T2 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0227] The third sub-transistor distribution layer 23 includes a third active film layer 119 and a third gate film layer 120. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0228] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the first active film layer 110, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the first gate film layer 111, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0229] In this embodiment, the write transistor T2 can be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the second active film layer 113, and the gate pattern T22 of the write transistor T2 is disposed on the second gate film layer 114. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0230] In this embodiment, the sensing transistor T3 may be a top-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a gate pattern T32 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, and the gate pattern T32 of the sensing transistor T3 is disposed on the third gate film layer 120. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0231] The first source / drain metal layer 109 includes a data signal line 1091 .

[0232] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1, a drain transfer pattern 1124 of the driving transistor T1, and a first drain transfer pattern 1122 of the write transistor T2. It should be noted that in this embodiment, the fourth gate film layer 112 serves as both the third transfer gate film layer and the first transfer gate film layer.

[0233] The second gate film layer 114 includes a second source transfer pattern 1141 of the drive transistor T1, a source transfer pattern 1123 of the write transistor T2, and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both the third transfer gate film layer, the second transfer gate film layer, and the first transfer gate film layer.

[0234] Compared to the embodiment shown in FIG. 5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115 ′, in this embodiment, the second gate film layer 114 in the second sub-transistor distribution layer 22 serves simultaneously as the third transfer gate film layer, the second transfer gate film layer, and the first transfer gate film layer for disposing the second source transfer pattern 1141 of the drive transistor T1, the source transfer pattern 1123 of the write transistor T2, and the second drain transfer pattern 1142 of the write transistor T2. Furthermore, the fourth gate film layer 112 serves simultaneously as the third transfer gate film layer and the first transfer gate film layer for disposing the first source transfer pattern 1121 of the drive transistor T1, the drain transfer pattern 1124 of the drive transistor T1, and the first drain transfer pattern 1122 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115 ) in the array substrate 10, thereby further improving the PPI (Pixels Per Inch) of the display panel 100.

[0235] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0236] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via, the first source transfer pattern 1121 of the driving transistor T1, the second source transfer pattern 1141 of the driving transistor T1, and the anode transfer pattern 1152. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via, the first source transfer pattern 1121 of the driving transistor T1, the second source transfer pattern 1141 of the driving transistor T1, and the anode transfer pattern 1152.

[0237] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via, a first drain transfer pattern 1122 of the write transistor T2, and a second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via, the first drain transfer pattern 1122 of the write transistor T2, and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2.

[0238] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c of the sensing transistor T3 in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0239] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the second sub-transistor distribution layer 22 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. Providing the overlapping region CC further reduces the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0240] The embodiment shown in FIG10 differs from the embodiment shown in FIG9A in that:

[0241] In the embodiment shown in FIG. 10 , the array substrate 10 further includes a light shielding layer 117 and a third buffer layer 116 .

[0242] In the embodiment shown in FIG10 , the driving transistor T1 is a dual-gate transistor, wherein the bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117 .

[0243] The array substrate 10 shown in FIG11 is described below. In some embodiments, as shown in FIG11 , FIG11 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a third gate insulating layer 105, a fourth gate film layer 112, a second buffer layer 106, a second active film layer 113, a fourth gate insulating layer 107, a second gate film layer 114, a fifth gate insulating layer 118, a third active film layer 119, a second source-drain metal layer 115, a passivation layer 122, and a third source-drain metal layer 123, which are stacked in sequence.

[0244] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0245] The light shielding layer 117 can block light emitted from the side of the base substrate 101 away from the light shielding layer 117 to the inside of the array substrate 10. Exemplarily, the material of the light shielding layer 117 can be amorphous silicon.

[0246] The third buffer layer 116 can be prepared by using PECVD (Plasma Enhanced Chemical Vapor Deposition), and its material can be silicon nitride, silicon oxide or silicon oxynitride, which has the function of water and gas barrier.

[0247] The material of the passivation layer 122 may be silicon nitride, silicon oxide or silicon oxynitride.

[0248] The third source / drain metal layer 123 can be formed by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) through a PVD process.

[0249] The materials and preparation process of the first active film layer 110, the second active film layer 113, the third active film layer 119, the first buffer layer 102, the second buffer layer 106, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the fourth gate film layer 112 and the second gate film layer 114 are basically the same as those in the embodiment shown in Figure 9A and will not be repeated here.

[0250] Referring again to Figure 11 , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a fourth gate film layer 112, a second sub-transistor distribution layer 22, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the base substrate 101. The fourth gate film layer 112 is disposed between the first sub-transistor distribution layer 21 and the second sub-transistor distribution layer 22.

[0251] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The driving transistor T1 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 is low-temperature polysilicon, the driving transistor T1 is a low-temperature polysilicon transistor.

[0252] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The write transistor T2 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0253] The third sub-transistor distribution layer 23 includes a third active film layer 119. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0254] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the first active film layer 110, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the first gate film layer 111, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0255] In this embodiment, the write transistor T2 can be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the second active film layer 113, and the gate pattern T22 of the write transistor T2 is disposed on the second gate film layer 114. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0256] In this embodiment, the sensing transistor T3 may be a bottom-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the second gate film layer 114. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0257] The first source / drain metal layer 109 includes a data signal line 1091 .

[0258] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1, a drain transfer pattern 1124 of the driving transistor T1, and a first drain transfer pattern 1122 of the write transistor T2. It should be noted that in this embodiment, the fourth gate film layer 112 serves as both the third transfer gate film layer and the first transfer gate film layer.

[0259] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2 and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both a second transfer gate film layer and a first transfer gate film layer.

[0260] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115 ′, in this embodiment, the second gate film layer 114 in the second sub-transistor distribution layer 22 serves as both a second transfer gate film layer and a first transfer gate film layer for disposing the source transfer pattern 1123 of the write transistor T2 and the second drain transfer pattern 1142 of the write transistor T2. The fourth gate film layer 112 serves as both a third transfer gate film layer and a first transfer gate film layer for disposing the first source transfer pattern 1121 of the drive transistor T1, the drain transfer pattern 1124 of the drive transistor T1, and the first drain transfer pattern 1122 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115 ) in the array substrate 10, thereby further improving the PPI (Pixels Per Inch) of the display panel 100.

[0261] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a sensing pattern 1154 .

[0262] The third source / drain metal layer 123 includes a first sensing signal line 1153 , which is electrically connected to a sensing pattern 1154 through a via hole.

[0263] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1. Specifically, the source region T11c of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1.

[0264] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via, a first drain transfer pattern 1122 of the write transistor T2, and a second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via, the first drain transfer pattern 1122 of the write transistor T2, and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c of the write transistor T2 in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and a source transfer pattern 1123 of the write transistor T2.

[0265] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the sensing pattern 1154. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. The active layer pattern T31 of the sensing transistor T3 and the sensing pattern 1154 can be directly connected without the need for a via to achieve electrical connection. The active layer pattern T31 of the sensing transistor T3 and the anode transfer pattern 1152 can also be directly connected without the need for a via to achieve electrical connection. This can further reduce the number of vias on the second source-drain metal layer 115, reduce the wiring pressure of the second source-drain metal layer 115, and further reduce the area of ​​the sub-pixel area A1, which is beneficial to improving the PPI of the array substrate 10.

[0266] The embodiment shown in FIG11 differs from the embodiment shown in FIG9A in that:

[0267] In the embodiment shown in FIG. 11 , the array substrate 10 does not include the fourth buffer layer 121 , the third gate film layer 120 and the interlayer dielectric layer 108 .

[0268] In the embodiment shown in FIG11 , the array substrate 10 further includes a light shielding layer 117, a third buffer layer 116, a passivation layer 122, and a third source / drain metal layer 123. The third source / drain metal layer 123 includes a first sensing signal line 1153, and the second source / drain metal layer 115 includes a sensing pattern 1154 electrically connected to the first sensing signal line 1153.

[0269] 11 , the driving transistor T1 is a dual-gate transistor, and the sensing transistor T3 is a bottom-gate transistor. The bottom gate pattern T13 of the driving transistor T1 is disposed on the light shielding layer 117 , and the bottom gate pattern T13 of the sensing transistor T3 is disposed on the second gate film layer 114 .

[0270] In the embodiment shown in Figure 11, the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1; the active layer pattern T31 of the sensing transistor T3 is electrically connected to the sensing pattern 1154; and the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode switching pattern 1152.

[0271] The array substrate 10 shown in Figures 12 and 13 is described below. In some embodiments, as shown in Figures 12 and 13, Figures 12 and 13 are structural diagrams of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a second buffer layer 106, a second active film layer 113, a third gate insulating layer 105, a second gate film layer 114, a fourth gate insulating layer 107, a fourth gate film layer 112, a fourth buffer layer 121, a third active film layer 119, a fifth gate insulating layer 118, a third gate film layer 120, an interlayer dielectric layer 108, and a second source-drain metal layer 115, which are stacked in sequence.

[0272] Among them, the material of the first active film layer 110, the material of the second active film layer 113 and the material of the third active film layer 119 can all be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0273] For example, the first active film layer 110 , the second active film layer 113 and the third active film layer 119 can all be obtained by a PVD (Physical Vapor Deposition) process.

[0274] The materials and preparation processes of the first buffer layer 102, the second buffer layer 106, the fourth buffer layer 121, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114, the third gate film layer 120 and the interlayer dielectric layer 108 are basically the same as those in the aforementioned embodiments and will not be repeated here.

[0275] Referring again to Figures 12 and 13 , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a second sub-transistor distribution layer 22, a fourth gate film layer 112, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the base substrate 101. The fourth gate film layer 112 is disposed between the second sub-transistor distribution layer 22 and the third sub-transistor distribution layer 23.

[0276] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The write transistor T2 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0277] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The driving transistor T1 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the driving transistor T1 is an oxide transistor.

[0278] The third sub-transistor distribution layer 23 includes a third active film layer 119 and a third gate film layer 120. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0279] In this embodiment, the driving transistor T1 can be a top-gate transistor, as shown in FIG12 , including an active layer pattern T11 of the driving transistor T1 and a gate pattern T12 (top gate pattern) of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, and the gate pattern T12 (top gate pattern) of the driving transistor is disposed on the second gate film layer 114. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c of the driving transistor T1 and the drain region T11b of the driving transistor T1. Alternatively, in this embodiment, the driving transistor T1 can also be a dual-gate transistor, as shown in FIG13 , including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, the gate pattern T12 (top gate pattern) of the driving transistor is disposed on the second gate film layer 114, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0280] As shown in Figures 12 and 13, in this embodiment, the write transistor T2 can be a top-gate transistor, including an active layer pattern T21 of the write transistor T2 and a gate pattern T22 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, and the gate pattern T22 of the write transistor T2 is disposed on the first gate film layer 111. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0281] In this embodiment, the sensing transistor T3 can be a top-gate transistor, as shown in FIG12 , including an active layer pattern T31 of the sensing transistor T3 and a gate pattern T32 (top gate pattern) of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, and the gate pattern T32 (top gate pattern) of the sensing transistor T3 is disposed on the third gate film layer 120. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3. Alternatively, in this embodiment, the sensing transistor T3 can be a dual-gate transistor, as shown in FIG13 , including the active layer pattern T31 of the sensing transistor T3, the gate pattern T32 (top gate pattern) of the sensing transistor T3, and the bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, the gate pattern T32 (top gate pattern) of the sensing transistor T3 is disposed on the third gate film layer 120, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the fourth gate film layer 112. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0282] The first source / drain metal layer 109 includes a data signal line 1091 .

[0283] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1 and a drain transfer pattern 1124 of the driving transistor T1. It should be noted that, in this embodiment, the fourth gate film layer 112 serves as a third transfer gate film layer.

[0284] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2 and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both a second transfer gate film layer and a first transfer gate film layer.

[0285] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115′, in this embodiment, the second gate film layer 114 in the second sub-transistor distribution layer 22 is used as both the second transfer gate film layer and the first transfer gate film layer for disposing the source transfer pattern 1123 of the write transistor T2 and the second drain transfer pattern 1142 of the write transistor T2, and the fourth gate film layer 112 is used as the third transfer gate film layer for disposing the first source transfer pattern 1121 of the drive transistor T1 and the drain transfer pattern 1124 of the drive transistor T1. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0286] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0287] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1. Specifically, the source region T11c of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1.

[0288] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2.

[0289] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0290] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. Providing the overlapping region CC further reduces the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0291] The embodiment shown in FIG12 differs from the embodiment shown in FIG9A in that:

[0292] In the embodiment shown in FIG. 12 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0293] In the embodiment shown in Figure 12, the active layer pattern T11 of the driving transistor T1 is connected through a via and a first source switching pattern 1121 and an anode switching pattern 1152 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through a via and a second drain switching pattern 1142 of the writing transistor T2.

[0294] The embodiment shown in FIG13 differs from the embodiment shown in FIG9A in that:

[0295] In the embodiment shown in FIG. 13 , the driving transistor T1 , the writing transistor T2 , and the sensing transistor T3 are all oxide transistors.

[0296] 13 , both the driving transistor T1 and the sensing transistor T3 are dual-gate transistors, wherein the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111 , and the bottom gate pattern T13 of the sensing transistor T3 is disposed on the fourth gate film layer 112 .

[0297] In the embodiment shown in FIG. 13 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0298] In the embodiment shown in Figure 13, the active layer pattern T11 of the driving transistor T1 is connected through the via and the first source switching pattern 1121 and the anode switching pattern 1152 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain switching pattern 1142 of the writing transistor T2.

[0299] The array substrate 10 shown in FIG14 is described below. In some embodiments, as shown in FIG14, FIG14 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a second buffer layer 106, a second active film layer 113, a third gate insulating layer 105, a second gate film layer 114, a fourth gate insulating layer 107, a fourth gate film layer 112, a fourth buffer layer 121, a third active film layer 119, a fifth gate insulating layer 118, a third gate film layer 120, an interlayer dielectric layer 108, and a second source-drain metal layer 115, which are stacked in sequence.

[0300] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0301] Among them, the material of the first active film layer 110, the material of the second active film layer 113 and the material of the third active film layer 119 can all be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0302] For example, the first active film layer 110 , the second active film layer 113 and the third active film layer 119 can all be obtained by a PVD (Physical Vapor Deposition) process.

[0303] The materials and preparation processes of the first buffer layer 102, the second buffer layer 106, the second buffer layer 106, the fourth buffer layer 121, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114, the third gate film layer 120, the interlayer dielectric layer 108 and the light-shielding layer 117 are basically the same as those in the aforementioned embodiments and will not be repeated here.

[0304] Referring again to FIG. 14 , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a second sub-transistor distribution layer 22, a fourth gate film layer 112, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the base substrate 101. The fourth gate film layer 112 is disposed between the second sub-transistor distribution layer 22 and the third sub-transistor distribution layer 23.

[0305] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The write transistor T2 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0306] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The driving transistor T1 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the driving transistor T1 is an oxide transistor.

[0307] The third sub-transistor distribution layer 23 includes a third active film layer 119 and a third gate film layer 120. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0308] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the second gate film layer 114, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0309] In this embodiment, the write transistor T2 can be a dual-gate transistor, including an active layer pattern T21 of the write transistor T2, a gate pattern T22 (top gate pattern) of the write transistor T2, and a bottom gate pattern T23 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, the gate pattern T22 (top gate pattern) of the write transistor T2 is disposed on the first gate film layer 111, and the bottom gate pattern T23 of the write transistor T2 is disposed on the light shielding layer 117. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0310] In this embodiment, the sensing transistor T3 may be a dual-gate transistor, including an active layer pattern T31 of the sensing transistor T3, a gate pattern T32 (top gate pattern) of the sensing transistor T3, and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, the gate pattern T32 (top gate pattern) of the sensing transistor T3 is disposed on the third gate film layer 120, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the fourth gate film layer 112. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0311] The first source / drain metal layer 109 includes a data signal line 1091 .

[0312] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1 and a drain transfer pattern 1124 of the driving transistor T1. It should be noted that, in this embodiment, the fourth gate film layer 112 serves as a third transfer gate film layer.

[0313] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2 and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both a second transfer gate film layer and a first transfer gate film layer.

[0314] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115′, in this embodiment, the second gate film layer 114 in the second sub-transistor distribution layer 22 is used as both the second transfer gate film layer and the first transfer gate film layer for disposing the source transfer pattern 1123 of the write transistor T2 and the second drain transfer pattern 1142 of the write transistor T2, and the fourth gate film layer 112 is used as the third transfer gate film layer for disposing the first source transfer pattern 1121 of the drive transistor T1 and the drain transfer pattern 1124 of the drive transistor T1. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0315] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0316] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1. Specifically, the source region T11c of the driving transistor T1 in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1.

[0317] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2.

[0318] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0319] For example, along the Z direction, there is an overlapping region CC between the active layer pattern T21 of the write transistor T2 arranged in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sensing transistor T3 arranged in the third sub-transistor distribution layer 23. That is, in a sub-pixel area A1, the write transistor T2 and the sensing transistor T3 have an overlapping region CC. By setting the overlapping region CC, the area of ​​the sub-pixel area A1 can be further reduced, which is conducive to further improving the PPI of the array substrate 10.

[0320] The embodiment shown in FIG14 differs from the embodiment shown in FIG9A in that:

[0321] In the embodiment shown in FIG. 14 , the driving transistor T1 , the writing transistor T2 , and the sensing transistor T3 are all oxide transistors.

[0322] 14 , the driving transistor T1 and the sensing transistor T3 are both dual-gate transistors, wherein the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111 , and the bottom gate pattern T13 of the sensing transistor T3 is disposed on the fourth gate film layer 112 .

[0323] In the embodiment shown in FIG. 14 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0324] In the embodiment shown in Figure 14, the active layer pattern T11 of the driving transistor T1 is connected through the via and the first source switching pattern 1121 and the anode switching pattern 1152 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain switching pattern 1142 of the writing transistor T2.

[0325] The array substrate 10 shown in FIG15 is described below. In some embodiments, as shown in FIG15 , FIG15 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a second buffer layer 106, a second active film layer 113, a third gate insulating layer 105, a second gate film layer 114, a fourth gate insulating layer 107, a fourth gate film layer 112, a fourth buffer layer 121, a third active film layer 119, a fifth gate insulating layer 118, a third gate film layer 120, an interlayer dielectric layer 108, and a second source-drain metal layer 115, which are stacked in sequence.

[0326] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0327] Among them, the material of the first active film layer 110, the material of the second active film layer 113 and the material of the third active film layer 119 can all be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0328] For example, the first active film layer 110 , the second active film layer 113 and the third active film layer 119 can all be obtained by a PVD (Physical Vapor Deposition) process.

[0329] The materials and preparation processes of the first buffer layer 102, the second buffer layer 106, the second buffer layer 106, the fourth buffer layer 121, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the fourth gate film layer 112, the second gate film layer 114, the third gate film layer 120, the interlayer dielectric layer 108 and the light-shielding layer 117 are basically the same as those in the aforementioned embodiments and will not be repeated here.

[0330] Referring again to FIG. 15 , the transistor distribution layer 2 includes a first sub-transistor distribution layer 21, a second sub-transistor distribution layer 22, a fourth gate film layer 112, and a third sub-transistor distribution layer 23, which are stacked in sequence. The first sub-transistor distribution layer 21 is closer to the base substrate 101 than the third sub-transistor distribution layer 23. That is, the distance between the first sub-transistor distribution layer 21 and the base substrate 101 is smaller than the distance between the third sub-transistor distribution layer 23 and the base substrate 101. The fourth gate film layer 112 is disposed between the second sub-transistor distribution layer 22 and the third sub-transistor distribution layer 23.

[0331] The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The write transistor T2 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0332] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The driving transistor T1 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the driving transistor T1 is an oxide transistor.

[0333] The third sub-transistor distribution layer 23 includes a third active film layer 119 and a third gate film layer 120. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0334] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the second gate film layer 114, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0335] In this embodiment, the write transistor T2 can be a dual-gate transistor, including an active layer pattern T21 of the write transistor T2, a gate pattern T22 (top gate pattern) of the write transistor T2, and a bottom gate pattern T23 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, the gate pattern T22 (top gate pattern) of the write transistor T2 is disposed on the first gate film layer 111, and the bottom gate pattern T23 of the write transistor T2 is disposed on the light shielding layer 117. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0336] In this embodiment, the sensing transistor T3 may be a dual-gate transistor, including an active layer pattern T31 of the sensing transistor T3, a gate pattern T32 (top gate pattern) of the sensing transistor T3, and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, the gate pattern T32 (top gate pattern) of the sensing transistor T3 is disposed on the third gate film layer 120, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the fourth gate film layer 112. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0337] The first source / drain metal layer 109 includes a data signal line 1091 .

[0338] The first gate film layer 111 includes a second drain transfer pattern 1142 of the write transistor T2. It should be noted that, in this embodiment, the first gate film layer 111 serves as a first transfer gate film layer.

[0339] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2. It should be noted that, in this embodiment, the second gate film layer 114 serves as a second transfer gate film layer.

[0340] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1 and a drain transfer pattern 1124 of the driving transistor T1. It should be noted that, in this embodiment, the fourth gate film layer 112 serves as a third transfer gate film layer.

[0341] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115 ′, in this embodiment, the fourth gate film layer 112 is used as a third transfer gate film layer for disposing the first source transfer pattern 1121 and the drain transfer pattern 1124 of the driving transistor T1, the second gate film layer 114 in the second sub-transistor distribution layer 22 is used as a second transfer gate film layer for disposing the source transfer pattern 1123 of the write transistor T2, and the first gate film layer 111 in the first sub-transistor distribution layer 21 is used as a first transfer gate film layer for disposing the second drain transfer pattern 1142 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115 ) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0342] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0343] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via and the drain transfer pattern 1124 of the driving transistor T1. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through the via and the drain transfer pattern 1124. The active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode transfer pattern 1152 through a via and the first source transfer pattern 1121 of the driving transistor T1.

[0344] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2.

[0345] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153 through a via. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152 through a via.

[0346] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. Providing the overlapping region CC further reduces the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0347] The embodiment shown in FIG15 differs from the embodiment shown in FIG9A in that:

[0348] In the embodiment shown in FIG. 15 , the driving transistor T1 , the writing transistor T2 , and the sensing transistor T3 are all oxide transistors.

[0349] 15 , the driving transistor T1 and the sensing transistor T3 are both dual-gate transistors, wherein the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111 , and the bottom gate pattern T13 of the sensing transistor T3 is disposed on the fourth gate film layer 112 .

[0350] In the embodiment shown in FIG. 15 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0351] In the embodiment shown in Figure 15, the active layer pattern T11 of the driving transistor T1 is connected through the via and the first source switching pattern 1121 and the anode switching pattern 1152 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain switching pattern 1142 of the writing transistor T2.

[0352] The array substrate 10 shown in FIG16 is described below. In some embodiments, as shown in FIG16 , FIG16 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a second buffer layer 106, a second active film layer 113, a third gate insulating layer 105, a second gate film layer 114, a fourth gate insulating layer 107, a fourth gate film layer 112, a fifth gate insulating layer 118, a third active film layer 119, a second source-drain metal layer 115, and a passivation layer 122, which are stacked in sequence.

[0353] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0354] Among them, the material of the first active film layer 110, the material of the second active film layer 113 and the material of the third active film layer 119 can all be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0355] For example, the first active film layer 110 , the second active film layer 113 and the third active film layer 119 can all be obtained by a PVD (Physical Vapor Deposition) process.

[0356] The materials and preparation processes of the first buffer layer 102, the second buffer layer 106, the third buffer layer 116, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the second gate film layer 114, the fourth gate film layer 112, the passivation layer 122 and the light-shielding layer 117 are basically the same as those in the aforementioned embodiments and will not be repeated here.

[0357] Please refer to Figure 16 again. The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The write transistor T2 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0358] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The driving transistor T1 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the driving transistor T1 is an oxide transistor.

[0359] The third sub-transistor distribution layer 23 includes a third active film layer 119. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0360] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the second gate film layer 114, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0361] In this embodiment, the write transistor T2 can be a dual-gate transistor, including an active layer pattern T21 of the write transistor T2, a gate pattern T22 (top gate pattern) of the write transistor T2, and a bottom gate pattern T23 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, the gate pattern T22 (top gate pattern) of the write transistor T2 is disposed on the first gate film layer 111, and the bottom gate pattern T23 of the write transistor T2 is disposed on the light shielding layer 117. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0362] In this embodiment, the sensing transistor T3 may be a bottom-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the fourth gate film layer 112. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0363] The first source / drain metal layer 109 includes a data signal line 1091 .

[0364] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2 and a second drain transfer pattern 1142 of the write transistor T2. It should be noted that in this embodiment, the second gate film layer 114 serves as both a second transfer gate film layer and a first transfer gate film layer.

[0365] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1. It should be noted that, in this embodiment, the fourth gate film layer 112 serves as a third transfer gate film layer.

[0366] Compared with the embodiment shown in Figure 5 in which the source transfer pattern / drain transfer pattern of each transistor is set on the second source-drain metal layer 115', in this embodiment, the fourth gate film layer 112 is used as the third transfer gate film layer to set the first source transfer pattern 1121 of the driving transistor T1, and the second gate film layer 114 in the second sub-transistor distribution layer 22 is used as the second transfer gate film layer and the first transfer gate film layer to set the source transfer pattern 1123 of the write transistor T2 and the second drain transfer pattern 1142 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115) in the array substrate 10, which is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0367] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0368] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. The active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1.

[0369] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2.

[0370] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. The active layer pattern T31 of the sensing transistor T3 is directly electrically connected to the sensing signal line 1153 and the anode transfer pattern 1152, respectively, without the need for vias. This can reduce the number of vias on the second source-drain metal layer 115, further reduce the number of same-direction vias in the array substrate 10, and further reduce the area of ​​the sub-pixel area A1, which is beneficial to improving the PPI of the array substrate 10.

[0371] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. Providing the overlapping region CC further reduces the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0372] The embodiment shown in FIG16 differs from the embodiment shown in FIG9A in that:

[0373] In the embodiment shown in FIG. 16 , the driving transistor T1 , the writing transistor T2 , and the sensing transistor T3 are all oxide transistors.

[0374] In the embodiment shown in FIG16 , the driving transistor T1 and the writing transistor T2 are both dual-gate transistors, and the sensing transistor T3 is a bottom-gate transistor. The bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111 , while the bottom gate pattern T13 of the sensing transistor T3 is disposed on the fourth gate film layer 112 .

[0375] In the embodiment shown in FIG. 16 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0376] In the embodiment shown in FIG16 , the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain switching pattern 1142 of the writing transistor T2.

[0377] The array substrate 10 shown in FIG17 is described below. In some embodiments, as shown in FIG17 , FIG17 is a structural diagram of an array substrate 10 provided according to some embodiments of the present disclosure. The array substrate 10 includes a base substrate 101, a first buffer layer 102, a light shielding layer 117, a third buffer layer 116, a first source-drain metal layer 109, a first gate insulating layer 103, a first active film layer 110, a second gate insulating layer 104, a first gate film layer 111, a second buffer layer 106, a second active film layer 113, a third gate insulating layer 105, a second gate film layer 114, a fourth gate insulating layer 107, a fourth gate film layer 112, a fifth gate insulating layer 118, a third active film layer 119, a second source-drain metal layer 115, and a passivation layer 122, which are stacked in sequence.

[0378] It should be noted that, in this embodiment, the light-shielding layer 117 is located on the side of the first source-drain metal layer 109 close to the base substrate 101, that is, the light-shielding layer 117 is located between the first source-drain metal layer 109 and the base substrate 101. However, the positional relationship between the light-shielding layer 117 and the first source-drain metal layer 109 is not limited to this. For example, the positions of the light-shielding layer 117 and the first source-drain metal layer 109 can be interchangeable. The light-shielding layer 117 is located on the side of the first source-drain metal layer 109 away from the base substrate 101, that is, the first source-drain metal layer 109 is located between the light-shielding layer 117 and the base substrate 101.

[0379] Among them, the material of the first active film layer 110, the material of the second active film layer 113 and the material of the third active film layer 119 can all be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0380] For example, the first active film layer 110 , the second active film layer 113 and the third active film layer 119 can all be obtained by a PVD (Physical Vapor Deposition) process.

[0381] The materials and preparation processes of the first buffer layer 102, the second buffer layer 106, the third buffer layer 116, the first gate insulation layer 103, the second gate insulation layer 104, the third gate insulation layer 105, the fourth gate insulation layer 107, the fifth gate insulation layer 118, the first gate film layer 110, the second gate film layer 114, the fourth gate film layer 112, the passivation layer 122 and the light-shielding layer 117 are basically the same as those in the aforementioned embodiments and will not be repeated here.

[0382] Please refer to Figure 17 again. The first sub-transistor distribution layer 21 includes a first active film layer 110 and a first gate film layer 111. The write transistor T2 of the pixel driving circuit 20 is arranged in the first sub-transistor distribution layer 21. Since the material of the first active film layer 110 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the write transistor T2 is an oxide transistor.

[0383] The second sub-transistor distribution layer 22 includes a second active film layer 113 and a second gate film layer 114. The driving transistor T1 of the pixel driving circuit 20 is disposed in the second sub-transistor distribution layer 22. Since the second active film layer 113 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the driving transistor T1 is an oxide transistor.

[0384] The third sub-transistor distribution layer 23 includes a third active film layer 119. The sensing transistor T3 of the pixel driving circuit 20 is disposed in the third sub-transistor distribution layer 23. Since the third active film layer 119 can be either indium gallium zinc oxide or low-temperature polycrystalline oxide, the sensing transistor T3 is an oxide transistor.

[0385] In this embodiment, the driving transistor T1 can be a dual-gate transistor, including an active layer pattern T11 of the driving transistor T1, a gate pattern T12 (top gate pattern) of the driving transistor T1, and a bottom gate pattern T13 of the driving transistor T1. The active layer pattern T11 of the driving transistor T1 is disposed on the second active film layer 113, the gate pattern T12 (top gate pattern) of the driving transistor T1 is disposed on the second gate film layer 114, and the bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111. The active layer pattern T11 of the driving transistor T1 includes a source region T11c of the driving transistor T1, a drain region T11b of the driving transistor T1, and a channel region T11a of the driving transistor T1 located between the source region T11c and the drain region T11b of the driving transistor T1.

[0386] In this embodiment, the write transistor T2 can be a dual-gate transistor, including an active layer pattern T21 of the write transistor T2, a gate pattern T22 (top gate pattern) of the write transistor T2, and a bottom gate pattern T23 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 110, the gate pattern T22 (top gate pattern) of the write transistor T2 is disposed on the first gate film layer 111, and the bottom gate pattern T23 of the write transistor T2 is disposed on the light shielding layer 117. The active layer pattern T21 of the write transistor T2 includes a source region T21c of the write transistor T2, a drain region T21b of the write transistor T2, and a channel region T21a of the write transistor T2 located between the source region T21c and the drain region T21b of the write transistor T2.

[0387] In this embodiment, the sensing transistor T3 may be a bottom-gate transistor, including an active layer pattern T31 of the sensing transistor T3 and a bottom gate pattern T33 of the sensing transistor T3. The active layer pattern T31 of the sensing transistor T3 is disposed on the third active film layer 119, and the bottom gate pattern T33 of the sensing transistor T3 is disposed on the fourth gate film layer 112. The active layer pattern T31 of the sensing transistor T3 includes a source region T31c of the sensing transistor T3, a drain region T31b of the sensing transistor T3, and a channel region T31a of the sensing transistor T3 located between the source region T31c and the drain region T31b of the sensing transistor T3.

[0388] The first source / drain metal layer 109 includes a data signal line 1091 .

[0389] The first gate film layer 111 includes a second drain transfer pattern 1142 of the write transistor T2. It should be noted that, in this embodiment, the second gate film layer 114 serves as a first transfer gate film layer.

[0390] The second gate film layer 114 includes a source transfer pattern 1123 of the write transistor T2. It should be noted that, in this embodiment, the second gate film layer 114 serves as a second transfer gate film layer.

[0391] The fourth gate film layer 112 includes a first source transfer pattern 1121 of the driving transistor T1. It should be noted that, in this embodiment, the fourth gate film layer 112 serves as a third transfer gate film layer.

[0392] Compared to the embodiment shown in FIG5 , in which the source transfer pattern / drain transfer pattern of each transistor is disposed on the second source-drain metal layer 115 ′, in this embodiment, the fourth gate film layer 112 is used as the third transfer gate film layer for disposing the first source transfer pattern 1121 of the driving transistor T1, the second gate film layer 114 in the second sub-transistor distribution layer 22 is used as the second transfer gate film layer for disposing the source transfer pattern 1123 of the write transistor T2, and the first gate film layer 111 in the first sub-transistor distribution layer 21 is used as the first transfer gate film layer for disposing the second drain transfer pattern 1142 of the write transistor T2. This can reduce the wiring difficulty of other film layers (the second source-drain metal layer 115 ) in the array substrate 10, and is conducive to further improving the PPI (Pixels Per Inch) of the display panel 100.

[0393] The second source-drain metal layer 115 includes a first voltage signal line 1151 , an anode transfer pattern 1152 , and a first sensing signal line 1153 .

[0394] The active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. Specifically, the drain region T11b in the active layer pattern T11 of the driving transistor T1 is connected to the first voltage signal line 1151 through a via. The active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1. Specifically, the source region T11c in the active layer pattern T11 of the driving transistor T1 is connected to the anode switching pattern 1152 through a via and the first source switching pattern 1121 of the driving transistor T1.

[0395] The active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through a via and the second drain transfer pattern 1142 of the write transistor T2. Specifically, the drain region T21b in the active layer pattern T21 of the write transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain transfer pattern 1142 of the write transistor T2. The active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2. Specifically, the source region T21c in the active layer pattern T21 of the write transistor T2 is electrically connected to the gate pattern T12 of the drive transistor T1 through a via and the source transfer pattern 1123 of the write transistor T2.

[0396] The active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153. Specifically, the drain region T31b in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the first sensing signal line 1153. The active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. Specifically, the source region T31c in the active layer pattern T31 of the sensing transistor T3 is electrically connected to the anode transfer pattern 1152. The active layer pattern T31 of the sensing transistor T3 is directly electrically connected to the sensing signal line 1153 and the anode transfer pattern 1152, respectively, without the need for vias. This can reduce the number of vias on the second source-drain metal layer 115, further reduce the number of same-direction vias in the array substrate 10, and further reduce the area of ​​the sub-pixel area A1, which is beneficial to improving the PPI of the array substrate 10.

[0397] For example, along the Z direction, an overlapping region CC exists between the active layer pattern T21 of the write transistor T2 disposed in the first sub-transistor distribution layer 21 and the active layer pattern T31 of the sense transistor T3 disposed in the third sub-transistor distribution layer 23. That is, within a sub-pixel region A1, the write transistor T2 and the sense transistor T3 have an overlapping region CC. Providing the overlapping region CC can further reduce the area of ​​the sub-pixel region A1, thereby further improving the PPI of the array substrate 10.

[0398] The embodiment shown in FIG17 differs from the embodiment shown in FIG9A in that:

[0399] In the embodiment shown in FIG. 17 , the driving transistor T1 , the writing transistor T2 , and the sensing transistor T3 are all oxide transistors.

[0400] In the embodiment shown in FIG17 , the driving transistor T1 and the writing transistor T2 are both dual-gate transistors, and the sensing transistor T3 is a bottom-gate transistor. The bottom gate pattern T13 of the driving transistor T1 is disposed on the first gate film layer 111 , while the bottom gate pattern T13 of the sensing transistor T3 is disposed on the fourth gate film layer 112 .

[0401] In the embodiment shown in FIG. 17 , the driving transistor T1 is disposed in the second sub-transistor distribution layer 22 , and the writing transistor T2 is disposed in the first sub-transistor distribution layer 21 .

[0402] In the embodiment shown in Figure 17, the active layer pattern T11 of the driving transistor T1 is connected through the via and the first source switching pattern 1121 and the anode switching pattern 1152 of the driving transistor T1; the active layer pattern T21 of the writing transistor T2 is electrically connected to the data signal line 1091 through the via and the second drain switching pattern 1142 of the writing transistor T2.

[0403] In some embodiments, as shown in Figures 18A to 20B, Figures 18A to 20B are structural diagrams of the drain transfer pattern 1124 of the driving transistor T1 according to some embodiments of the present disclosure. The symbol "O" is used to represent a via. It should be noted that in order to clearly show the position and structure of the via in Figures 18A, 19A, and 20A, the drain transfer pattern 1124 of the driving transistor T1 is made transparent to expose the via located on the side of the drain transfer pattern 1124 of the driving transistor T1 close to the base substrate 101.

[0404] The drain T11 b of the driving transistor T1 is connected to the drain transfer pattern 1124 of the driving transistor T1 through a via.

[0405] For example, the drain transfer pattern 1124 of the driving transistor T1 may be a quadrilateral, an octagon, or any other shape with corners. FIG18A to FIG20B illustrate the drain transfer pattern 1124 of the driving transistor T1 as a quadrilateral.

[0406] When the drain transfer pattern 1124 of the driving transistor T1 is in a quadrilateral shape, the drain transfer pattern 1124 of the driving transistor T1 includes four boundaries: a first boundary L1, a second boundary L2, a third boundary L3, and a fourth boundary L4. The first boundary L1 and the third boundary L3 are arranged opposite each other, and the second boundary L2 and the fourth boundary are arranged opposite each other. As shown in Figures 18A and 18B, the spacing between each of the four boundaries of the drain transfer pattern 1124 of the driving transistor T1 and the boundary of the via hole can be the same, and are all d1. This increases the orthographic projection area of ​​the drain transfer pattern 1124 of the driving transistor T1 on the substrate 101, which helps to improve the connection stability between the drain transfer pattern 1124 of the driving transistor T1 and the first voltage signal line 1151 and the drain T11b of the driving transistor T1.

[0407] Alternatively, as shown in FIG. 19A , FIG. 19B , FIG. 20A , and FIG. 20B , the intervals between the four boundaries of the drain transfer pattern 1124 of the driving transistor T1 and the boundary of the via hole may also be different.

[0408] For example, as shown in Figures 19A and 19B, the spacing between the first boundary L1 of the drain switching pattern 1124 of the driving transistor T1 and the boundary of the via is equal to the spacing between the second boundary L2 and the boundary of the via, and both are d1, and the spacing between the third boundary L3 of the drain switching pattern 1124 of the driving transistor T1 and the boundary of the via is equal to the spacing between the fourth boundary L4 and the boundary of the via, and both are d2, wherein d1 and d2 are different, and d1 is greater than d2.

[0409] For another example, as shown in Figures 20A and 20B, the spacing between the first boundary L1 of the drain switching pattern 1124 of the driving transistor T1 and the boundary of the via is equal to the spacing between the third boundary L3 and the boundary of the via, and both are d1. The spacing between the second boundary L2 of the drain switching pattern 1124 of the driving transistor T1 and the boundary of the via is equal to the spacing between the fourth boundary L4 and the boundary of the via, and both are d2, wherein d1 and d2 are different, and d1 is greater than d2, which can ensure the spacing between the drain switching pattern 1124 of the driving transistor T1 and other switching patterns, signal lines or the first electrode plate C1 of the capacitor C on the fourth gate film layer 112, and avoid the short circuit caused by the small spacing between the drain switching pattern 1124 of the driving transistor T1 and other switching patterns, signal lines or the first electrode plate C1 of the capacitor C on the fourth gate film layer 112, thereby affecting the normal display of the array substrate 10.

[0410] It should be noted that the above-mentioned “boundary of the via hole” refers to the maximum boundary of the orthographic projection of the via hole on the drain transfer pattern 1124 of the driving transistor T1 .

[0411] 18A to 20B illustrate the relationship between the drain switching pattern 1124 of the driving transistor T1 and the via hole, taking the drain switching pattern 1124 of the driving transistor T1 as an example. Other switching patterns in the various embodiments of the present disclosure may also be configured as described above, such as the source switching pattern 1123 of the writing transistor T2 and the first source switching pattern 1121 of the driving transistor T1. Although some embodiments of the present application are described herein in conjunction with FIG. 6 to FIG. 17 , the above description is exemplary and not exhaustive, and is therefore not limited to the disclosed embodiments. Without departing from the scope of the above embodiments, many modifications and changes will be apparent to those skilled in the art.

[0412] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: a plurality of pixel driving circuits arranged in multiple rows and columns, each of the plurality of pixel driving circuits comprising a plurality of transistors, the plurality of transistors comprising at least a write transistor; The array substrate includes: substrate; A first source-drain metal layer is provided on one side of the base substrate, wherein the first source-drain metal layer includes a data signal line; a transistor distribution layer disposed on a side of the first source / drain metal layer away from the base substrate, the transistor distribution layer being provided with an active layer pattern of the write transistor, the active layer pattern of the write transistor being electrically connected to the data signal line; A second source-drain metal layer is provided on a side of the transistor distribution layer away from the base substrate, wherein the second source-drain metal layer includes an anode transfer pattern.

2. The array substrate according to claim 1, wherein: The transistor distribution layer includes at least two stacked sub-transistor distribution layers, each of the at least two sub-transistor distribution layers includes an active film layer and a gate film layer that are stacked; the active film layer includes an active layer pattern of the transistor, and the gate film layer includes a gate pattern of the transistor; the write transistor is located in one of the sub-transistor distribution layers; The active layer pattern of the write transistor is electrically connected to the data signal line through the drain transfer pattern of the write transistor; the drain transfer pattern of the write transistor is located in the first transfer gate film layer; The first transfer gate film layer is located in the sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers.

3. The array substrate according to claim 2, wherein: The active layer pattern of the write transistor is connected to the source switching pattern of the write transistor; Wherein, the source transfer pattern of the write transistor is located in the second transfer gate film layer; The second transfer gate film layer is located in the sub-transistor distribution layer or between two adjacent sub-transistor distribution layers.

4. The array substrate according to claim 2 or 3, wherein: The pixel circuit further includes a driving transistor and a sensing transistor, wherein the active layer pattern of the driving transistor is electrically connected to the anode switching pattern, and the active layer pattern of the sensing transistor is electrically connected to the anode switching pattern; The active layer pattern of the driving transistor is connected to the anode switching pattern through the source switching pattern of the driving transistor. The source switching pattern of the driving transistor is located in the third switching gate film layer. The third switching gate film layer is located in the sub-transistor distribution layer and / or between two adjacent sub-transistor distribution layers.

5. The array substrate according to any one of claims 2 to 4, wherein: The transistor distribution layer includes a first sub-transistor distribution layer and a second sub-transistor distribution layer that are stacked, and the first sub-transistor distribution layer is closer to the substrate than the second sub-transistor distribution layer; The transistor distribution layer further includes a fourth gate film layer located between the first sub-transistor distribution layer and the second sub-transistor distribution layer; The write transistor is located in the first sub-transistor distribution layer; The drain switching pattern and the source switching pattern of the write transistor are located in the fourth gate film layer.

6. The array substrate according to claim 5, wherein: The pixel driving circuit further includes a driving transistor; the driving transistor is located in the first sub-transistor distribution layer; The source transfer pattern of the driving transistor is located on the fourth gate film layer.

7. The array substrate according to claim 5 or 6, wherein: The pixel driving circuit further includes a sensing transistor, and the sensing transistor is located in the second sub-transistor distribution layer; The second source-drain metal layer further includes a first sensing signal line, and the active layer pattern of the sensing transistor is further connected to the first sensing signal line.

8. The array substrate according to any one of claims 5 to 7, wherein: The active film layer of the first sub-transistor distribution layer is a polysilicon active film layer, and the active film layers of the second sub-transistor distribution layer are all oxide active film layers.

9. The array substrate according to any one of claims 2 to 4, wherein: The transistor distribution layer includes a first sub-transistor distribution layer, a second sub-transistor distribution layer and a third sub-transistor distribution layer stacked in sequence, wherein the first sub-transistor distribution layer is closer to the base substrate than the second sub-transistor distribution layer; The transistor distribution layer further includes a fourth gate film layer located between the first sub-transistor distribution layer and the second sub-transistor distribution layer; The write transistor is located in the second sub-transistor distribution layer; The drain switching pattern of the write transistor includes a first drain switching pattern and a second drain switching pattern; The first drain switching pattern of the write transistor is located in the fourth gate film layer, the first drain switching pattern of the write transistor is connected to the second drain switching pattern of the write transistor, and is connected to the data signal line; The second drain switching pattern of the write transistor is located in the gate film layer of the second sub-transistor distribution layer, and the second drain switching pattern of the write transistor is connected to the active film layer of the write transistor; The source transfer pattern of the write transistor is located on the gate film layer of the second sub-transistor distribution layer.

10. The array substrate according to claim 9, wherein: The pixel driving circuit further includes a driving transistor and a sensing transistor; the driving transistor is located in the first sub-transistor distribution layer, and the sensing transistor is located in the third sub-transistor distribution layer.

11. The array substrate according to claim 10, wherein: The third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is closer to the base substrate relative to the third gate film layer; The source switching pattern of the driving transistor includes a first source switching pattern and a second source switching pattern; The first source switching pattern of the driving transistor is located on the fourth gate film layer, and the second source switching pattern of the driving transistor is located on the gate film layer of the second sub-transistor distribution layer; The first source switching pattern of the driving transistor is connected to the active layer pattern of the driving transistor, and the second source switching pattern of the driving transistor is connected to the first source switching pattern of the driving transistor and to the anode switching pattern.

12. The array substrate according to claim 10, wherein: The third sub-transistor distribution layer includes a third active film layer and a third gate film layer, and the third active film layer is farther away from the base substrate than the third gate film layer; The second sub-transistor distribution layer includes a second active film layer and a second gate film layer, and the second active film layer is closer to the base substrate than the second gate film layer; The third gate film layer and the second gate film layer are the same film layer; The source transfer pattern of the driving transistor is located on the fourth gate film layer.

13. The array substrate according to any one of claims 9 to 12, wherein: The second source-drain metal layer further includes a first voltage signal line; The active layer pattern of the driving transistor is connected to the first voltage signal line through the drain transfer pattern of the driving transistor; The drain transfer pattern of the driving transistor is located on the fourth gate film layer.

14. The array substrate according to claim 10, wherein: The array substrate also includes a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate; the second source-drain metal layer also includes a sensing pattern, and the active layer pattern of the sensing transistor is also connected to the sensing pattern. The third source-drain metal layer includes a first sensing signal line, and the first sensing signal line is connected to the sensing pattern.

15. The array substrate according to any one of claims 9 to 14, wherein: The active film layer of the first sub-transistor distribution layer is a polysilicon active film layer, and the active film layers of the second sub-transistor distribution layer and the third sub-transistor distribution layer are both oxide active film layers.

16. The array substrate according to any one of claims 2 to 4, wherein: The transistor distribution layer includes a first sub-transistor distribution layer, a second sub-transistor distribution layer and a third sub-transistor distribution layer which are stacked, and the first sub-transistor distribution layer is closer to the substrate than the second sub-transistor distribution layer; The write transistor is located in the first sub-transistor distribution layer; The drain transfer pattern of the write transistor is located in the gate film layer of the second sub-transistor distribution layer, or the drain transfer pattern of the write transistor is located in the gate film layer of the first sub-transistor distribution layer; The source transfer pattern of the write transistor is located on the gate film layer of the second sub-transistor distribution layer.

17. The array substrate according to claim 16, wherein: The pixel driving circuit further includes a driving transistor and a sensing transistor, wherein the driving transistor is located in the second sub-transistor distribution layer, and the sensing transistor is located in the third sub-transistor distribution layer; The second source-drain metal layer further includes a first sensing signal line, and the active layer pattern of the sensing transistor is further connected to the first sensing signal line.

18. The array substrate according to claim 17, wherein the third sub-transistor distribution layer comprises a third active film layer and a third gate film layer, and the third active film layer is closer to the base substrate than the third gate film layer; Alternatively, the third sub-transistor distribution layer includes a third active film layer and a third gate film layer, the third active film layer is farther away from the base substrate than the third gate film layer; the fourth gate film layer is located between the second sub-transistor distribution layer and the third active film layer; the fourth gate film layer and the third gate film layer are the same film layer; The source transfer pattern of the driving transistor is located on the fourth gate film layer. 19 . The array substrate according to claim 16 , wherein the active film layer of the first sub-transistor distribution layer, the active film layer of the second sub-transistor distribution layer, and the active film layer of the third sub-transistor distribution layer are all oxide active film layers.

20. The array substrate according to any one of claims 2 to 19, wherein: The array substrate further includes a light shielding layer located on one side of the array substrate; The light shielding layer is located on a side of the first source / drain metal layer close to the array substrate, or the light shielding layer is located on a side of the first source / drain metal layer away from the array substrate; At least one of the transistors disposed in the sub-transistor distribution layer closest to the array substrate is a dual-gate transistor; The gate film layer of the sub-transistor distribution layer closest to the array substrate is located on a side of the active film layer away from the array substrate, and the gate film layer includes a top gate pattern of a dual-gate transistor; The light shielding layer includes a bottom gate pattern of the dual-gate transistor.

21. A display panel comprising the array substrate according to any one of claims 1 to 20; An anode layer is provided on the array substrate, and the anode layer is connected to the anode switching pattern.

22. A display device comprising the display panel according to claim 21.

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