Memory management method and apparatus, and electronic device and readable storage medium

Abstract

A memory management method and apparatus, and an electronic device and a readable storage medium, which relate to the technical field of computers. The method comprises: when a first write instruction of a processor for a first memory and / or a second memory is received, synchronously writing into the first memory and the second memory data carried in the first write instruction (101); and when a memory access instruction of the processor for a target memory is received, if the target memory does not support instant interaction with the processor, sending the memory access instruction to a backup copy, so that the backup copy responds to the memory access instruction (102), wherein the first memory and the second memory are backup copies of each other.

Description

Memory management method, device, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 11, 2023, with application number 202311692024.3 and titled “A memory management method, device, electronic device and readable storage medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of computer technology, and in particular to a memory management method, device, electronic device, and readable storage medium. Background Art

[0004] When dynamic random access memory (DRAM) is operating, it requires additional background operations to ensure proper operation, such as signal integrity, stored data integrity, and stable read and write operations. While DRAM is performing background operations, it cannot exchange data with the central processing unit (CPU), resulting in additional memory access latency and becoming a performance bottleneck for the CPU. Furthermore, background operations also consume additional power. Existing solutions mostly use past DRAM access patterns to infer future access patterns and adjust the DRAM's background operation cycles accordingly to minimize the tail latency and power consumption encountered by the CPU during normal memory access. This solution does not effectively address tail latency. When the CPU encounters a DRAM background operation during an actual memory access, it still needs to wait for the DRAM to complete the background operation before data can be exchanged. Therefore, DRAM cannot be used in critical scenarios that are sensitive to tail latency, such as applications that require real-time network response (such as cloud gaming) or automotive chips that require real-time computing.

[0005] Summary of the Invention

[0006] Embodiments of the present invention provide a memory management method, device, electronic device, and readable storage medium, which can solve the problem in related technologies that DRAM cannot respond to the processor in a timely manner, easily causing tail delay.

[0007] In a first aspect, an embodiment of the present invention discloses a memory management method, which is applied to a memory controller, wherein the memory controller is used to control a first memory and a second memory; the method includes:

[0008] Upon receiving a first write instruction from the processor for the first memory and / or the second memory, synchronously writing the data carried in the first write instruction into the first memory and the second memory;

[0009] When receiving a memory access instruction from a processor for a target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to a backup copy so that the backup copy responds to the memory access instruction;

[0010] The first memory and the second memory are backup copies of each other. When the target memory is the first memory, the backup copy is the second memory; when the target memory is the second memory, the backup copy is the first memory.

[0011] Optionally, the memory access instruction includes a write instruction; and when receiving a memory access instruction from a processor for a target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to a backup copy so that the backup copy responds to the memory access instruction, comprising:

[0012] When receiving a write instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the write instruction to the backup copy so that the backup copy responds to the write instruction; the write instruction carries a memory access address;

[0013] Writing the memory access address into a write buffer corresponding to the target memory;

[0014] When the target memory satisfies the immediate interaction condition, reading the memory access address from the write buffer of the target memory;

[0015] The first target data corresponding to the memory access address is read from the backup copy according to the memory access address, and the first target data is written into the target memory.

[0016] Optionally, the memory access instruction includes a read instruction; and when receiving a memory access instruction from a processor for a target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to a backup copy so that the backup copy responds to the memory access instruction, comprising:

[0017] When receiving a read instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the read instruction to the backup copy so that the backup copy responds to the read instruction;

[0018] Acquire second target data matching the read instruction from the backup copy;

[0019] The second target data is sent to the processor.

[0020] Optionally, before writing the memory access address into a write buffer corresponding to the target memory, the method further includes:

[0021] Determining a buffer size required by the target memory according to an execution period of a periodic operation of the target memory;

[0022] A corresponding write buffer is allocated to the target memory according to the buffer size.

[0023] Optionally, the memory controller includes a storage module; before reading the first target data corresponding to the memory access address from the backup copy according to the memory access address and writing the first target data into the target memory, the method further includes:

[0024] If the write buffer corresponding to the target memory is full, writing the memory access address into the storage module;

[0025] When the target memory satisfies the immediate interaction condition, the memory access address is read from the storage module.

[0026] Optionally, the method further includes:

[0027] receiving a memory read / write request sent by the processor, wherein the memory read / write request carries a request address;

[0028] querying whether there is a data block matching the request address in the write buffer of each memory in the storage module and the memory controller;

[0029] If a data block matching the request address exists in the storage module, obtaining the data block matching the request address from the storage module;

[0030] If a data block matching the request address exists in the write buffer, obtaining the data block matching the request address from the write buffer;

[0031] The data block is sent to the processor.

[0032] Optionally, the target memory does not support real-time interaction with the processor, which includes: the target memory is executing a background operation; the background operation includes at least one of the following:

[0033] System memory refresh;

[0034] Periodic calibration;

[0035] Periodic read and write operations.

[0036] In a second aspect, an embodiment of the present invention discloses a memory management device, which is applied to a memory controller, wherein the memory controller is used to control a first memory and a second memory; the device includes:

[0037] a first control module, configured to, upon receiving a first write instruction from a processor for the first memory and / or the second memory, synchronously write data carried in the first write instruction into the first memory and the second memory;

[0038] a second control module, configured to, upon receiving a memory access instruction from the processor for a target memory, send the memory access instruction to a backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the memory access instruction;

[0039] The first memory and the second memory are backup copies of each other. When the target memory is the first memory, the backup copy is the second memory; when the target memory is the second memory, the backup copy is the first memory.

[0040] In a third aspect, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned memory management method.

[0041] In a fourth aspect, an embodiment of the present invention further discloses a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the aforementioned memory management method.

[0042] In a fifth aspect, an embodiment of the present invention further provides a computer program product (the computer program product is stored in a non-volatile storage medium), and the computer program product is executed by at least one processor to implement the method of the first aspect.

[0043] In a sixth aspect, an embodiment of the present invention further provides a memory management apparatus / device, including the apparatus / device (configured to) be used in the method of the first aspect.

[0044] The embodiments of the present invention include the following advantages:

[0045] An embodiment of the present invention provides a memory management method, which synchronously writes data carried in write instructions for a first memory and / or a second memory into the first memory and the second memory, so that the first memory and the second memory serve as backup copies of each other. Therefore, when a memory access instruction for a target memory is received and the target memory does not support instant interaction with a processor, the backup copy responds to the memory access instruction without waiting for the target memory to support instant interaction before responding to the memory access instruction, thereby saving the processor's memory access waiting time and avoiding tail delays caused by the target memory's inability to respond to the processor in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] FIG1 is a flowchart of a memory management method according to an embodiment of the present invention;

[0048] FIG2 is a schematic diagram of memory management of a memory controller of the present invention;

[0049] FIG3 is a schematic structural diagram of a memory management device of the present invention;

[0050] FIG4 is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0052] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0053] 1 , there is shown a flowchart of a memory management method according to an embodiment of the present invention. The method may specifically include the following steps:

[0054] Step 101: upon receiving a first write instruction from a processor for the first memory and / or the second memory, synchronously write data carried in the first write instruction into the first memory and the second memory.

[0055] Step 102: When a processor receives a memory access instruction for a target memory, if the target memory does not support real-time interaction with the processor, the memory access instruction is sent to a backup copy so that the backup copy responds to the memory access instruction.

[0056] The first memory and the second memory are backup copies of each other. When the target memory is the first memory, the backup copy is the second memory; when the target memory is the second memory, the backup copy is the first memory.

[0057] The memory management method provided in the embodiment of the present invention is applied to a memory controller, and the memory controller is used to control the first memory and the second memory. It can be understood that the first memory and the second memory are only used to distinguish different memories, and do not limit the number of memories connected to the memory controller. The memory in the embodiment of the present invention can be a memory bar, or a memory particle, or one or more rows of memory particles. The first memory and the second memory in the present invention can be DRAM, or a larger capacity static random access memory (SRAM). The access speed of SRAM is faster than that of DRAM, but according to capacity calculation, under the same memory capacity requirement, the cost of using SRAM is higher than the cost of using DRAM.

[0058] The processor in the embodiment of the present invention may be a CPU, a data processing unit (DPU), a field programmable gate array (FPGA), or a processing module or processing unit in an application specific integrated circuit (ASIC).

[0059] In an embodiment of the present invention, a memory controller can be connected to two or more memories, each of which has at least one corresponding backup copy, and any memory and its backup copy store the same data. Taking the first memory and the second memory as an example, as long as the memory controller receives a first write instruction from the processor for either the first memory or the second memory, it will synchronously write the data carried in the first write instruction to the first memory and the second memory. In this way, the first memory and the second memory will synchronously store the same data, achieving data redundancy between them. The first memory and the second memory storing the same data serve as backup copies of each other.

[0060] It can be understood that in order to ensure that the data in the received write instructions can be written synchronously into the first memory and the second memory, the model, storage capacity, etc. of the first memory and the second memory need to be the same, and the memory addresses that the processor can access correspond to the storage units on the first memory and the second memory that back up each other.

[0061] In the case where the first memory and the second memory serve as backup copies of each other, if a processor receives a memory access instruction for the target memory, and the target memory does not support real-time interaction with the processor, the memory access instruction can be sent to the backup copy, which responds to the memory access instruction. It should be noted that the target memory can be the first memory or the second memory. If the target memory is the first memory, the backup copy is the second memory; if the target memory is the second memory, the backup copy is the first memory.

[0062] The target memory does not support immediate interaction with the processor. This means that the target memory is currently performing other operations and cannot respond normally to the processor. Waiting for the target memory to respond to the processor will incur additional memory access latency. For example, the target memory may be performing background operations such as DRAM refresh, periodic calibration, or periodic read operations. During these operations, the target memory cannot exchange data with the processor, resulting in tail latency. Tail latency refers to high access latency that occurs infrequently but is significantly greater than the average latency. DRAM memory cells contain capacitors, which gradually lose charge over time, causing corruption of the information stored in the memory cell. Therefore, DRAM requires periodic refresh operations to ensure the integrity of stored information. During DRAM operation, temperature and voltage may fluctuate, requiring some parameters trained during the initialization phase to be retrained and updated. This typically involves periodic ZQ calibration and periodic read centering. Periodic ZQ Calibration Short (ZQCS) is used to periodically calibrate the 240 ohm resistor. Periodic read centering recalculates read latency and other related parameters. Memory controllers typically set a timer and perform periodic calibration after a timer expiration interrupt.

[0063] Optionally, the target memory does not support real-time interaction with the processor, which includes: the target memory is executing a background operation; the background operation includes at least one of the following:

[0064] System memory refresh;

[0065] Periodic calibration;

[0066] Periodic read and write operations.

[0067] In an embodiment of the present invention, if the target memory is executing background operations, such as system memory refresh, periodic calibration, periodic reading and writing, etc., it can be determined that the target memory does not support real-time interaction with the processor.

[0068] Of course, if the target memory cannot promptly serve the processor that sends the memory access instruction due to executing other operations or being occupied by other processors or tasks, it also belongs to the situation where real-time interaction with the processor is not supported, and the embodiment of the present invention does not make specific restrictions on this.

[0069] In an embodiment of the present invention, if the target memory does not support real-time interaction with the processor, the memory access instruction can be sent directly to the backup copy, and the backup copy responds to the memory access instruction without waiting for the target memory to respond to the memory access instruction, thereby saving the processor's memory access waiting time and avoiding the tail delay caused by the target memory's inability to respond to the processor in a timely manner.

[0070] The memory management method provided by the embodiment of the present invention can be applied to applications that require real-time network response (such as cloud games), or scenarios that are sensitive to tail delays, such as vehicle-mounted chips that require real-time calculations, to save the processor's memory access waiting time and avoid tail delays caused by the target memory's inability to respond to the processor in a timely manner. The memory management method provided by the embodiment of the present invention can also be applied to the memory access scenario of backbone network routers. The backbone network is a high-speed network used to connect multiple areas or regions. The packet forwarding of the backbone network router has very high requirements for memory access delay. Generally, only SRAM is used in the backbone network. The memory management method provided by the embodiment of the present invention can reduce memory access delay, so that low-cost storage devices such as DRAM can also be used in the backbone network, saving storage costs while ensuring memory access performance.

[0071] It should be noted that the memory access instructions in the embodiments of the present invention may include write instructions, read instructions, etc. For example, if a write instruction is received for a first memory, and the first memory is currently performing background operations and does not support real-time interaction with the processor, the write instruction can be sent to a second memory, which responds to the write instruction and performs a data write operation. If a read instruction is received for a first memory, and the first memory is currently performing background operations, the read instruction can be sent to the second memory, which responds to the write instruction and performs a data read operation.

[0072] In an optional embodiment of the present invention, the memory access instruction includes a write instruction; and in step 102, when the processor receives the memory access instruction for the target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to the backup copy so that the backup copy responds to the memory access instruction includes:

[0073] Step S11: upon receiving a write instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the write instruction to the backup copy so that the backup copy responds to the write instruction; the write instruction carries a memory access address;

[0074] Step S12: writing the memory access address into a write buffer corresponding to the target memory;

[0075] Step S13: when the target memory satisfies the instant interaction condition, reading the memory access address from the write buffer of the target memory;

[0076] Step S14: Read the first target data corresponding to the memory access address from the backup copy according to the memory access address, and write the first target data into the target memory.

[0077] In an embodiment of the present invention, a write buffer can be allocated for each memory to temporarily store relevant information, such as the memory access address, the channel number of the target memory, the channel number of the backup memory, etc., carried in the write instruction. If a write instruction is received for the target memory, but the target memory does not support real-time interaction with the processor, the write instruction can be sent to the backup copy, which responds to the write instruction by writing the first target data corresponding to the memory access address to the backup copy.

[0078] Furthermore, the memory access address carried in the write instruction can also be written into the write buffer corresponding to the target memory, so that when the target memory meets the immediate interaction condition, the temporarily stored memory access address is read from the write buffer of the target memory, and the first target data is obtained from the backup copy based on the memory access address and written into the target memory to ensure that the target memory and the backup copy write the same data. Among them, the target memory meets the immediate interaction condition, that is, the target memory is able to serve the processor at this time and respond to the write instruction. For example, if the target memory has completed the background operation, or the target memory has been released from the occupation of other tasks, it can be determined that the target memory meets the immediate interaction condition.

[0079] As an example, assume there are two DRAM banks, A and B, corresponding to two channels, controlled by the same memory controller. Memory banks A and B have data redundancy, meaning the same data exists in both banks. Each bank has a corresponding write buffer with sufficient depth. Now, data a needs to be read from bank A, but bank A is performing a background operation and cannot exchange data. If bank B is not performing a background operation, bank B can be accessed first to read data a without waiting for bank A to complete the background operation. Similarly, if data b needs to be written to DRAM, and bank A is performing a background operation while bank B is not, the access address can be written to write buffer 1 corresponding to bank A and, simultaneously, data b can be written to bank 2. After bank A completes the background operation, the memory controller reads the access address from write buffer 1 corresponding to bank A and, in the background, gradually transfers data b from bank B to bank A based on the access address without waiting for bank A to complete the background operation.

[0080] As another example, assume there are two banks of DRAM memory cells, C and D. Memory cells C and D serve as backup copies of each other. Bank C is currently performing background operations and is therefore unable to exchange data with the processor, while bank D is not performing any background operations. Banks C and D each have a corresponding write buffer with sufficient depth. When a read request is received for bank C, the required data can be read from bank D first, without waiting for bank C to complete the background operation. When a write request is received for bank C, the data can be written to the write buffer corresponding to bank C first, and then to bank D simultaneously. After waiting for bank C to complete the background operation, the memory controller gradually writes the data from the write buffer corresponding to bank C to the memory cells in bank C.

[0081] In an embodiment of the present invention, different memory banks can also be scheduled using multiple synchronously operating memory controllers. As an example, assume that two memory controllers E and F operate synchronously, each managing two memory banks. Memory controller E manages two memory banks, e1 and e2, and memory controller F manages two memory banks, f1 and f2. Each memory bank has a corresponding write buffer with sufficient depth. The memory banks managed by each memory controller perform background operations synchronously, but different memory controllers perform background operations in staggered order. That is, memory banks e1 and e2 perform background operations synchronously, memory banks f1 and f2 perform background operations synchronously, but memory banks e1 and f1 do not perform background operations synchronously. Correspondingly, memory banks e1 and f1 serve as backup copies of each other, and memory banks e2 and f2 serve as backup copies of each other. Assume that memory banks e1 and e2 are performing background operations and cannot exchange data with the processor. When a read command targeting memory bank e1 is received, the required data can be read from memory bank f1 first, without waiting for memory bank e1 to complete background operations. When a write request targeting memory bank e2 is received, the data can be written to the write buffer corresponding to memory bank e2 first, and then to memory bank f2 simultaneously. After waiting for background operations on memory bank e2 to complete, the memory controller gradually writes the data from the write buffer corresponding to memory bank e2 to memory bank e2.

[0082] Optionally, the memory controller includes a storage module; before reading the first target data corresponding to the memory access address from the backup copy according to the memory access address and writing the first target data into the target memory, the method further includes:

[0083] Step S21: If the write buffer corresponding to the target memory is full, the memory access address is written into the storage module;

[0084] Step S22: When the target memory satisfies the instant interaction condition, read the memory access address from the storage module.

[0085] In an embodiment of the present invention, a storage module may be added to the memory controller to store corresponding information when the write buffer of the memory corresponding to the memory access address in the write instruction is full. It is understood that the capacity of the storage module is much larger than the capacity of the write buffer corresponding to the memory.

[0086] In one possible implementation, the memory controller can set up a storage module in a distributed management manner, that is, the reserved area of ​​each memory bar connected to the memory controller is set as the storage module in the embodiment of the present invention. When the target memory does not support real-time interaction with the processor, the memory access address in the write instruction is stored in the reserved area of ​​the memory bar that supports real-time interaction with the processor and whose reserved area is free. Optionally, the storage module includes the reserved areas of each memory bar connected to the memory controller; the reserved area of ​​the third memory is determined as the storage module, and the third memory is the memory bar among the memory bars connected to the memory controller that supports real-time interaction with the processor and whose reserved area is free. In another possible implementation, a separate large-capacity storage device can also be used as the storage module in the embodiment of the present invention, and each memory connected to the memory controller shares the storage module.

[0087] If the memory controller receives a write instruction for the target memory, and the target memory does not support immediate interaction with the processor at this time, it can first query whether there is a free area in the write buffer corresponding to the target memory. If there is free data in the write buffer corresponding to the target memory, the memory access address will be temporarily stored in the write buffer, and the memory access address will be read from the write buffer after the target memory meets the immediate interaction conditions.

[0088] If the write buffer corresponding to the target memory is full, the memory access address can be temporarily stored in the storage module, and the memory access address can be read from the storage module after the target memory meets the immediate interaction condition.

[0089] Based on the memory access address, the first target data corresponding to the memory access address can be obtained from the backup copy, and the memory controller writes the first target data into the target memory during a time interval that does not interfere with other requests.

[0090] Optionally, before writing the memory access address into a write buffer corresponding to the target memory, the method further includes:

[0091] Step S31: determining a buffer size required by the target memory according to an execution period of a periodic operation of the target memory;

[0092] Step S32: Allocate a corresponding write buffer to the target memory according to the buffer size.

[0093] In embodiments of the present invention, the write buffer can be implemented in a variety of ways. As an example, a sufficiently large buffer depth, i.e., the required buffer size for the target memory, can be calculated based on the maximum latency of background operations of the target memory, i.e., the execution period of periodic operations, such as the maximum time interval of refresh operations and the read period of periodic read operations. Thus, a sufficiently large write buffer can be allocated to the target memory based on the buffer size.

[0094] Another implementation method is to use a smaller write buffer. When the write buffer is full, the memory controller writes the data to be written, including the memory access address carried in the write instruction, the channel number corresponding to the target memory, the channel number of the backup copy, etc., into a specific storage module. After the target memory meets the immediate interaction conditions, the memory controller checks the storage module. If the channel number matching the target memory is indexed, the first target data corresponding to the memory access address is read from the backup copy according to the memory access address corresponding to the channel number and the channel number of the backup copy, and the first target data is copied to the target memory.

[0095] In an optional embodiment of the present invention, the memory access instruction includes a read instruction; and in step 102, when the processor receives the memory access instruction for the target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to the backup copy so that the backup copy responds to the memory access instruction includes:

[0096] Step S41: when receiving a read instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the read instruction to the backup copy so that the backup copy responds to the read instruction;

[0097] Step S42: Acquire second target data matching the read instruction from the backup copy;

[0098] Step S43: Send the second target data to the processor.

[0099] In this embodiment of the present invention, if a memory controller receives a read instruction for a target memory that does not support real-time interaction with the processor, it can send the read instruction to a backup copy of the target memory, which responds to the read instruction. The memory controller then retrieves the read second target data from the backup copy and returns the second target data to the processor, avoiding tail latency.

[0100] Taking the first memory and the second memory as DRAM memory bars as an example, referring to FIG2 , a memory management schematic diagram of a memory controller provided by an embodiment of the present invention is shown. As shown in FIG2 , the memory controller includes a control module, a storage module, and a write buffer corresponding to all memory bars controlled by the memory controller. It is understandable that FIG2 only shows two memory bars: DRAM memory bar 1 and DRAM memory bar 1. In fact, the memory controller can access and control multiple memory bars at the same time. FIG2 is only an exemplary illustration of the present invention and does not constitute a limitation on the structure of the memory controller in the present invention and the number of memory bars connected.

[0101] Among them, the control module is used to track all memory sticks controlled by the memory controller, check whether the memory stick currently supports real-time interaction with the processor, and whether the write buffer corresponding to the memory stick is full. According to the tracking situation, while writing to the target memory, the same data and signals are sent to the backup copy, so that the backup copy and the target memory stick write the same data synchronously. When reading the target memory stick, if the target memory stick does not support real-time interaction with the processor, for example, the target memory stick is currently performing background operations, the read instruction is sent to the memory stick that is not performing background operations, that is, the backup copy of the target memory stick, so that the read data is obtained in time and returned to the CPU, avoiding tail delays.

[0102] The write buffer, with a certain depth, is used to store data and memory addresses that require delayed writes to the corresponding memory bank. When the memory bank meets the immediate interaction conditions, for example, after completing background operations, the memory controller gradually transfers the data to the corresponding memory bank in intervals that do not interfere with other requests.

[0103] The storage module is used to store the corresponding information when the write buffer of the memory bank corresponding to the memory access address is full. When the target memory bank meets the immediate interaction conditions, the memory controller queries the storage module to obtain the required information and then gradually transfers the required data from the backup copy to the target memory bank in the background.

[0104] Optionally, the method further includes:

[0105] Step S51: receiving a memory read / write request sent by the processor, wherein the memory read / write request carries a request address;

[0106] Step S52: query whether there is a data block matching the request address in the write buffer of each memory in the storage module and the memory controller;

[0107] Step S53: If a data block matching the request address exists in the storage module, obtain the data block matching the request address from the storage module;

[0108] Step S54: If a data block matching the request address exists in the write buffer, obtain the data block matching the request address from the write buffer;

[0109] Step S55: Send the data block to the processor.

[0110] In an embodiment of the present invention, if a memory controller (or the control module shown in FIG2 ) receives a memory read / write request, it may first query the write buffers and storage modules of each memory accessed by the memory controller to see whether there is a data block matching the request address in the memory read / write request. If a data block matching the request address exists in the write buffer, the data block is retrieved from the write buffer and fed back to the processor. If a data block matching the request address exists in the storage module, the data block is retrieved from the storage module and fed back to the processor.

[0111] Compared to querying memory, using data in memory to complete requests and obtaining data blocks from the write buffer or storage module can save query time and improve processing efficiency.

[0112] In summary, an embodiment of the present invention provides a memory management method, which synchronously writes the data carried in the write instructions for the first memory and / or the second memory into the first memory and the second memory, so that the first memory and the second memory serve as backup copies of each other, so that when a memory access instruction for the target memory is received and the target memory does not support instant interaction with the processor, the backup copy responds to the memory access instruction, and there is no need to wait for the target memory to support instant interaction before responding to the memory access instruction, thereby saving the processor's memory access waiting time, thereby avoiding tail delays caused by the target memory's inability to respond to the processor in a timely manner.

[0113] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0114] 3 , a structural block diagram of a memory management device according to the present invention is shown, which is applied to a memory controller, wherein the memory controller is used to control a first memory and a second memory; the device may specifically include:

[0115] A first control module 301 is configured to, upon receiving a first write instruction from a processor for the first memory and / or the second memory, synchronously write data carried in the first write instruction into the first memory and the second memory;

[0116] A second control module 302 is configured to, upon receiving a memory access instruction from a processor for a target memory, send the memory access instruction to a backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the memory access instruction;

[0117] The first memory and the second memory are backup copies of each other. When the target memory is the first memory, the backup copy is the second memory; when the target memory is the second memory, the backup copy is the first memory.

[0118] Optionally, the memory access instruction includes a write instruction; and the second control module includes:

[0119] a first sending submodule, configured to, upon receiving a write instruction from the processor for the target memory, send the write instruction to the backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the write instruction; the write instruction carries a memory access address;

[0120] A first processing submodule, configured to write the memory access address into a write buffer corresponding to the target memory;

[0121] A second processing submodule is configured to read the memory access address from the write buffer of the target memory when the target memory satisfies the instant interaction condition;

[0122] The third processing submodule is configured to read the first target data corresponding to the memory access address from the backup copy according to the memory access address, and write the first target data into the target memory.

[0123] Optionally, the memory access instruction includes a read instruction; and the second control module includes:

[0124] a second sending submodule, configured to, upon receiving a read instruction from the processor for the target memory, send the read instruction to the backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the read instruction;

[0125] a fourth processing submodule, configured to obtain second target data matching the read instruction from the backup copy;

[0126] The third sending submodule is configured to send the second target data to the processor.

[0127] Optionally, the device further comprises:

[0128] a buffer determination module, configured to determine a buffer size required by the target memory according to an execution cycle of a periodic operation of the target memory;

[0129] A buffer allocation module is used to allocate a corresponding write buffer to the target memory according to the buffer size.

[0130] Optionally, the memory controller includes a storage module; and the device further includes:

[0131] an address writing module, configured to write the memory access address into the storage module if the write buffer corresponding to the target memory is full;

[0132] The address reading module is used to read the memory access address from the storage module when the target memory meets the immediate interaction condition.

[0133] Optionally, the device further comprises:

[0134] A receiving module, configured to receive a memory read / write request sent by the processor, wherein the memory read / write request carries a request address;

[0135] A query module, configured to query whether there is a data block matching the request address in the write buffer of each memory in the storage module and the memory controller;

[0136] a first acquiring module, configured to acquire the data block matching the request address from the storage module if a data block matching the request address exists in the storage module;

[0137] a second acquiring module, configured to acquire the data block matching the request address from the write buffer if a data block matching the request address exists in the write buffer;

[0138] A data block sending module is used to send the data block to the processor.

[0139] Optionally, the target memory does not support real-time interaction with the processor, which includes: the target memory is executing a background operation; the background operation includes at least one of the following:

[0140] System memory refresh;

[0141] Periodic calibration;

[0142] Periodic read and write operations.

[0143] In summary, an embodiment of the present invention provides a memory management device, which synchronously writes the data carried in the write instructions for the first memory and / or the second memory into the first memory and the second memory, so that the first memory and the second memory serve as backup copies of each other. Therefore, when a memory access instruction for the target memory is received and the target memory does not support instant interaction with the processor, the backup copy responds to the memory access instruction without waiting for the target memory to support instant interaction before responding to the memory access instruction, thereby saving the processor's memory access waiting time and avoiding tail delays caused by the target memory's inability to respond to the processor in a timely manner.

[0144] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0147] Figure 4 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in Figure 4 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the memory management method according to the aforementioned embodiment.

[0148] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0149] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, an SDRAM (Synchronous Dynamic Random-Access Memory) bus, a DDR (Double Data Rate SDRAM) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG4 shows only one line, but this does not mean that there is only one bus or one type of bus.

[0150] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory) or the like.

[0151] An embodiment of the present invention further provides a non-transitory computer-readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute the memory management method shown in FIG1 .

[0152] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0153] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0155] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0157] It is understood that the embodiments described in the embodiments of the present invention can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and sub-units can be implemented in one or more ASICs, DSPs, digital signal processing devices (DSP devices, DSPDs), programmable logic devices (PLDs), FPGAs, general-purpose processors, controllers, microcontrollers, microprocessors, and other electronic units used to perform the functions described in the present invention, or a combination thereof.

[0158] For software implementation, the techniques described in the embodiments of the present invention can be implemented through modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present invention. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0159] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0160] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0161] The above is a detailed introduction to a memory management method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory management method, applied to a memory controller, wherein the memory controller is used to control a first memory and a second memory; the method comprises: When receiving a first write instruction from the processor for the first memory and / or the second memory, synchronously writing the data carried in the first write instruction into the first memory and the second memory; In the case of receiving a memory access instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to the backup copy so that the backup copy responds to the memory access instruction; The first memory and the second memory are backup copies of each other, and when the target memory is the first memory, the backup copy is the second memory; In the case where the target memory is the second memory, the backup copy is the first memory.

2. The method according to claim 1, wherein: The memory access instruction includes a write instruction; when receiving a memory access instruction from a processor for a target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to a backup copy so that the backup copy responds to the memory access instruction, including: In the case of receiving a write instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the write instruction to the backup copy so that the backup copy responds to the write instruction; the write instruction carries a memory access address; Writing the memory access address into a write buffer corresponding to the target memory; When the target memory satisfies the instant interaction condition, reading the memory access address from the write buffer of the target memory; The first target data corresponding to the memory access address is read from the backup copy according to the memory access address, and the first target data is written into the target memory.

3. The method according to claim 1, wherein: The memory access instruction includes a read instruction; when receiving a memory access instruction from a processor for a target memory, if the target memory does not support real-time interaction with the processor, sending the memory access instruction to a backup copy so that the backup copy responds to the memory access instruction, including: In the case of receiving a read instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the read instruction to the backup copy so that the backup copy responds to the read instruction; Acquire second target data matching the read instruction from the backup copy; The second target data is sent to the processor.

4. The method according to claim 2, wherein: Before writing the memory access address into a write buffer corresponding to the target memory, the method further includes: Determining a buffer size required for the target memory according to an execution period of a periodic operation of the target memory; A corresponding write buffer is allocated to the target memory according to the buffer size.

5. The method according to claim 2, wherein: The memory controller includes a storage module; before reading the first target data corresponding to the memory access address from the backup copy according to the memory access address and writing the first target data into the target memory, the method further includes: If the write buffer corresponding to the target memory is full, writing the memory access address into the storage module; When the target memory satisfies the immediate interaction condition, the memory access address is read from the storage module.

6. The method according to claim 5, wherein: The method further comprises: Receive a memory read / write request sent by the processor, wherein the memory read / write request carries a request address; Querying whether there is a data block matching the request address in the write buffer of each memory in the storage module and the memory controller; If a data block matching the request address exists in the storage module, obtaining the data block matching the request address from the storage module; If a data block matching the request address exists in the write buffer, obtaining the data block matching the request address from the write buffer; The data block is sent to the processor.

7. The method according to any one of claims 1 to 6, wherein: The target memory does not support real-time interaction with the processor, including: the target memory is executing a background operation; the background operation includes at least one of the following: System memory refresh; Periodic calibration; Periodic read and write operations.

8. A memory management device, applied to a memory controller, the memory controller being used to control a first memory and a second memory; the device comprising: A first control module is configured to synchronously write data carried in the first memory and the second memory upon receiving a first write instruction from a processor for the first memory and / or the second memory; A second control module is configured to, upon receiving a memory access instruction from a processor for a target memory, send the memory access instruction to a backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the memory access instruction; The first memory and the second memory are backup copies of each other, and when the target memory is the first memory, the backup copy is the second memory; In the case where the target memory is the second memory, the backup copy is the first memory.

9. The device according to claim 8, wherein: The memory access instruction includes a write instruction; the second control module includes: A first sending submodule is configured to, upon receiving a write instruction from a processor for the target memory, send the write instruction to the backup copy if the target memory does not support real-time interaction with the processor, so that the backup copy responds to the write instruction; the write instruction carries a memory access address; A first processing submodule, configured to write the memory access address into a write buffer corresponding to the target memory; A second processing submodule is used to read the memory access address from the write buffer of the target memory when the target memory meets the instant interaction condition; The third processing submodule is used to read the first target data corresponding to the memory access address from the backup copy according to the memory access address, and write the first target data into the target memory.

10. The device according to claim 8, wherein: The memory access instruction includes a read instruction; the second control module includes: A second sending submodule is used for, when receiving a read instruction from the processor for the target memory, if the target memory does not support real-time interaction with the processor, sending the read instruction to the backup copy so that the backup copy responds to the read instruction; a fourth processing submodule, configured to obtain second target data matching the read instruction from the backup copy; The third sending submodule is used to send the second target data to the processor.

11. The device according to claim 9, wherein: The device also includes: A buffer determination module, used to determine the buffer size required by the target memory according to the execution cycle of the periodic operation of the target memory; A buffer allocation module is used to allocate a corresponding write buffer to the target memory according to the buffer size.

12. The device according to claim 9, wherein: The memory controller includes a storage module; the device also includes: An address writing module, used for writing the memory access address into the storage module if the write buffer corresponding to the target memory is full; The address reading module is used to read the memory access address from the storage module when the target memory meets the instant interaction condition.

13. The device according to claim 12, wherein: The device also includes: A receiving module, used to receive a memory read / write request sent by the processor, wherein the memory read / write request carries a request address; A query module, used for querying whether there is a data block matching the request address in the write buffer of each memory in the storage module and the memory controller; a first acquisition module, configured to acquire the data block matching the request address from the storage module if the data block matching the request address exists in the storage module; A second acquisition module, configured to acquire the data block matching the request address from the write buffer if there is a data block matching the request address in the write buffer; A data block sending module is used to send the data block to the processor.

14. The device according to any one of claims 8 to 13, wherein: The target memory does not support real-time interaction with the processor, including: the target memory is executing a background operation; the background operation includes at least one of the following: System memory refresh; Periodic calibration; Periodic read and write operations.

15. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the memory management method as described in any one of claims 1 to 7. 16 . A readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the memory management method as claimed in any one of claims 1 to 7. 17 . A computer program product, the computer program product being stored in a non-transitory storage medium, the computer program product being executed by at least one processor to implement the method according to claim 1 .

18. A memory management apparatus / device, comprising the apparatus / device (configured to be) used in the method according to any one of claims 1 to 7.

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