Data processing method, device, and storage medium

Abstract

The present application relates to the technical field of solid state disks, and provides a data processing method, a device, and a storage medium. According to the method, a first data flushing instruction is received, a first data flushing range corresponding to a first data area is determined on the basis of the first data flushing instruction, and the position of a write pointer is updated on the basis of the first data flushing range, to form an area waiting for flushing, so that data in a specified flushing range in a ZRWA area is updated to the area waiting for flushing, the data in the specified flushing range in the ZRWA area is marked as data to be flushed, and then the data to be flushed can be flushed into a flash memory on the basis of the flushing instruction, so that the scenario requirements for multi-concurrent writing and random overwriting are satisfied, and the data written into the ZRWA area can be accurately flushed to the flash memory in sequence.

Description

Data processing method, device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 12, 2023, with application number 202311699841.1, entitled “Solid State Drive Data Processing Method, Device, Electronic Device and Storage Medium,” the entire contents of which are incorporated herein by reference, and claims priority to the Chinese patent application filed with the China Patent Office on December 12, 2023, with application number 202311696475.4, entitled “Data Storage Processing Method, Device, Equipment and Storage Medium,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solid-state hard disks, and more specifically, to a data processing method, device, and storage medium. Background Art

[0004] Zone Namespace Solid State Drive (ZNS SSD) is widely used in data storage due to its advantages such as reducing write amplification, increasing SSD lifespan, reducing over-provisioning (OP) space requirements, and reducing dynamic random access memory (DRAM) requirements.

[0005] Currently, when writing data, ZNSSSD strictly requires sequential writing within each zone, which cannot meet the requirements of multiple concurrent writes and local random overwrite writes within a specified space, resulting in a single application scenario for ZNSSSD.

[0006] Application Contents

[0007] The purpose of this application is to provide a data processing method, device and storage medium to address the deficiencies in the above-mentioned prior art, so as to facilitate random overwriting of data in a partitioned namespace solid-state drive and sequential flushing of written data.

[0008] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0009] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a partitioned namespace solid-state drive. The partitioned namespace solid-state drive includes: a first data area, where the starting address of the first data area coincides with the address of a write pointer. The method includes:

[0010] receiving a first data refresh instruction, and determining a first data refresh range corresponding to the first data area according to the first data refresh instruction;

[0011] Update the position of the write pointer according to the first data refresh range;

[0012] According to the updated position of the write pointer, the flush flag of the data in the address range between the start address and the write pointer in the first data area is updated.

[0013] In a second aspect, an embodiment of the present application provides a computer device, the computer device comprising: a memory and at least one processor, wherein instructions are stored in the memory;

[0014] At least one processor calls instructions in the memory to enable the computer device to execute the data processing method according to the first aspect.

[0015] In a third aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon, which, when executed by a processor, implement the data processing method of the first aspect.

[0016] The beneficial effects of this application are:

[0017] The present application provides a data processing method, device, and storage medium. The method performs random overwrite writing of data based on the ZRWA partition random write area in the partition namespace solid-state drive. At the same time as the data is written, the data written in the ZRWA area is explicitly flushed based on the data flush instruction. During the execution of the explicit flush, the position of the write pointer is updated to form a to-be-flushed area, thereby updating the data in the specified flush range in the ZRWA area to the to-be-flushed area, marking the data in the specified flush range in the ZRWA area as to-be-flushed data. Then, the to-be-flushed data can be flushed to the flash memory according to the flush instruction. This satisfies the requirements of multiple concurrent writes and random overwrite writes, and the data written in the ZRWA area can also be accurately and sequentially flushed to the flash memory.

[0018] Secondly, when performing an explicit or implicit flush, by checking the empty positions in the range to be flushed, the empty positions can be filled first, and then the flush is performed, thereby ensuring that the data in the flushable range complies with the ZNS protocol and is flushed to the flash memory according to the strict sequential write characteristics.

[0019] In addition, when the data to be flushed is flushed to the flash memory, the position of the data to be flushed can be dynamically adjusted according to the valid address range of the data to be flushed and the specified flush range to ensure that there is valid data in the currently selected flush range and it can be flushed normally, thereby ensuring the orderliness of the data when it is flushed to the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0021] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the dimensions in the drawings do not constitute proportional limitations.

[0022] FIG1 is a flow chart of a data processing method provided in an embodiment of the present application;

[0023] FIG2 is a schematic diagram of the structure of a partitioned namespace solid-state drive provided in an embodiment of the present application;

[0024] FIG3 is a schematic diagram of the structure of another partitioned namespace solid-state drive provided in an embodiment of the present application;

[0025] FIG4 is a schematic diagram of a structural change of a partition namespace solid-state drive before and after an explicit refresh provided by an embodiment of the present application;

[0026] FIG5 is a flow chart of another data processing method provided in an embodiment of the present application;

[0027] FIG6 is a schematic diagram of the structure of another partitioned namespace solid-state drive provided in an embodiment of the present application;

[0028] FIG7 is a schematic diagram of a structural change of a partition namespace solid-state drive before and after an implicit refresh provided by an embodiment of the present application;

[0029] FIG8 is a flow chart of another data processing method provided in an embodiment of the present application;

[0030] FIG9 is a flow chart of another data processing method provided in an embodiment of the present application;

[0031] FIG10 is a flow chart of another data processing method provided in an embodiment of the present application;

[0032] FIG11 is a schematic diagram of an embodiment of a data processing method provided in an embodiment of the present application;

[0033] FIG12 is a schematic diagram of an embodiment of a bitmap layout provided in an embodiment of the present application;

[0034] FIG13 is a schematic diagram of another embodiment of a bitmap layout provided in an embodiment of the present application;

[0035] FIG14 is another embodiment of the data processing method provided in the embodiment of the present application;

[0036] FIG15 is a schematic diagram of an embodiment of a one-dimensional array provided in an embodiment of the present application;

[0037] FIG16 is a schematic diagram of an embodiment of a two-dimensional array provided in an embodiment of the present application;

[0038] FIG17 is a schematic diagram of an embodiment of searching a bitmap for non-aligned data blocks provided by an embodiment of the present application;

[0039] FIG18 is a schematic structural diagram of a data processing device provided in an embodiment of the present application;

[0040] FIG19 is a schematic structural diagram of another data processing device provided in an embodiment of the present application;

[0041] FIG20 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application.

[0042] Description of reference numerals: DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0044] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0045] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0046] To facilitate understanding of this application, the technical terms involved in the embodiments are explained below.

[0047] SSD, short for Solid State Disk, solid state drive.

[0048] Zone refers to logical partition, which means dividing the solid-state drive into multiple independent logical areas.

[0049] ZNS, short for Zoned Namespaces, is a new feature of the NVMe protocol based on zone size management space. Each logical partition can be read in any order but must be written in sequence.

[0050] LBA, short for Logical Block Address, is a general mechanism for describing the blocks where data is located on computer storage devices. It can refer to the address of a data block or the data block pointed to by an address.

[0051] ZRWA, short for Zone Random Write Area, allows random writing and in-place overwriting of data in the SSD cache.

[0052] A data block is an area formed after data is written to a logical partition. A zone can contain one or more data blocks, and a data block can contain one or more LBAs. Aligned and non-aligned data blocks are two types of data blocks. For data blocks using 4K alignment, the difference lies in whether data is written according to the 4K sector rule, that is, 4096 bytes per sector. If the data block range is an integer multiple of 4K, it is a 4K-aligned data block; otherwise, it is a non-4K-aligned data block. The specific determination of whether a 4K-aligned or non-4K-aligned data block is generated is based on the write range.

[0053] FTL, short for Flash Translation Layer, is used to map the host's logical address space to the flash memory's physical address space. Each time the SSD writes user logical data to the flash memory address space, it records the mapping between the logical address and the physical address. When the host wants to read the data, the SSD uses this mapping to retrieve the data from the flash memory and return it to the user.

[0054] A Zone Namespace Solid State Drive (ZNS SSD) is a storage technology based on Zoned Namespaces. It uses a zoned storage model, where zones are linearly distributed within a namespace. All zones are written sequentially and must be reset before being written again.

[0055] In SSDs, a "zone" typically refers to the division of the SSD's storage space into multiple independent areas. Each area can be independently erased and programmed to improve SSD performance and lifespan. In ZNS SSDs, a "zone" is a portion of the namespace. Each "zone" has independent storage space and access rights, corresponding to different applications. By partitioning the namespace, ZNS SSDs can better manage data, improve storage efficiency, and increase lifespan.

[0056] Although ZNS SSD has the advantages of reducing write amplification, increasing SSD lifespan, reducing OP (Over Provisioning) space requirements, and reducing Dynamic Random Access Memory (DRAM), it strictly requires sequential writing within each zone and cannot meet the requirements of local random overwrite write scenarios within a specified space.

[0057] Based on this, the present application provides a data processing method, which realizes random writing of data in the ZRWA area based on the ZNS Zone Random Write Area (ZRWA) protocol. After the data is written, the explicit and implicit flushing of the data is also realized, and the data written in the ZRWA is identified as the data to be flushed, and in the process of data flushing, the empty positions in the ZRWA area are also filled to ensure that the data within the flushing range can comply with the ZNS protocol and be flushed to the NAND (flash memory) in strict order according to the write characteristics. When the data identified as to be flushed is flushed to the NAND, the position of the data block in the flushing linked list is dynamically adjusted to ensure the orderliness of the data flushing. In addition, according to the requirements of the ZRWA protocol, the data range before the write pointer cannot be overwritten, and it is flushed to the NAND in strict order.

[0058] FIG1 is a flow chart of a data processing method provided in an embodiment of the present application; FIG2 is a structural diagram of a partition namespace solid state drive provided in an embodiment of the present application. The execution subject of this method may be a computer device, and this method may be applied to a partition namespace solid state drive. As shown in FIG2 , the partition namespace solid state drive may include: a first data area; the starting address of the first data area coincides with the address of the write pointer. As shown in FIG1 , the method may include:

[0059] S101: Receive a first data refresh instruction, and determine a first data refresh range corresponding to a first data area according to the first data refresh instruction.

[0060] In this embodiment, the first data area may be a Zone Random Write Area (ZRWA) area, which has a data random write feature. In the first data area, data can be overwritten without being written in strict order.

[0061] Optionally, while writing data in the first data area, the data in the first data area may also be flushed to the NAND flash memory, and the data in the first data area may be stored in a cache before being flushed to the NAND.

[0062] This embodiment provides two data flushing methods. One is explicit flushing, which can be triggered by an external flush instruction. The ZRWA protocol stipulates that explicit flushing is implemented through the Zone Management Send command.

[0063] Optionally, the received first data flush instruction may include: a specified maximum logical block address (LBA) for explicit flushing, and the starting LBA of the explicit flushing is the address of the write pointer, so as to determine the first data flushing range corresponding to the first data area.

[0064] It is worth noting that the "first" here has no actual physical meaning, it is only used to distinguish different instructions and different data.

[0065] S102: Update the position of the write pointer according to the first data refresh range.

[0066] The explicit flush in this embodiment does not refer to executing an actual flush action, but rather marking the data in the first data flush range in the first data area as data to be flushed through the explicit flush.

[0067] FIG3 is a schematic diagram of the structure of another partition namespace solid-state drive provided by an embodiment of the present application. Optionally, in the initial state, that is, when no data to be flushed is marked, as shown in FIG2 , the position of the write pointer is at the starting position, and after determining the first data flush range in the first data area, the position of the write pointer can be updated accordingly, thereby forming an area to be flushed. As shown in FIG3 , the end address of the area to be flushed coincides with the address of the write pointer. The area to be flushed contains the data in the first data flush range in the first data area, thereby pushing the data in the first data flush range in the first data area into the area to be flushed, and then the data in the first data flush range in the first data area becomes the data to be flushed.

[0068] S103 : Update the flush flag of the data in the address range between the start address and the write pointer in the first data area according to the updated position of the write pointer.

[0069] FIG4 is a schematic diagram of the structural changes of a partition namespace solid-state drive before and after an explicit refresh provided by an embodiment of the present application.

[0070] FIG4 shows the update of the write pointer and the changes of the area to be flushed before and after the write pointer is updated when the area to be flushed already exists.

[0071] After determining the first data flush range corresponding to the first data area according to the first data flush instruction, the write pointer can be updated accordingly. The update of the write pointer is to move the write pointer from the current position to the end address of the first data flush range in the current first data area, thereby pushing the data in the first data flush range into the area to be flushed. That is, as can be seen from Figure 4, the position of the write pointer moves to the end address of the first data flush range, so that the data in the first data flush range in the first data area becomes the data in the area to be flushed, thereby realizing marking the data in the first data flush range in the first data area as data to be flushed.

[0072] In actual operation, the write pointer is updated by moving the write pointer from its current position by the length of the first flush range, thereby obtaining an updated position of the write pointer. The updated position is located at the end address of the first flush range, thereby completing the explicit flush of the data in the first data area.

[0073] In summary, the data processing method provided in this embodiment performs random overwrite writing of data based on the ZRWA partition random write area in the partition namespace solid-state drive. While writing data, the data written in the ZRWA area is explicitly flushed based on the data flush instruction. During the execution of the explicit flush, the position of the write pointer is updated to form a to-be-flushed area, thereby updating the data in the specified flush range in the ZRWA area to the to-be-flushed area, marking the data in the specified flush range in the ZRWA area as to-be-flushed data. Then, the to-be-flushed data can be flushed to the flash memory according to the flush instruction. This meets the requirements of multiple concurrent writes and random overwrite scenarios, and the data written in the ZRWA area can also be accurately and sequentially flushed to the flash memory.

[0074] FIG5 is a flow chart of another data processing method provided by an embodiment of the present application; optionally, the partition namespace solid state drive may further include: a second data area, the start address of the second data area coincides with the end address of the first data area. The method of the present application may further include:

[0075] S501: Determine the length of a second data refresh range according to the address of the data written into the second data area.

[0076] FIG6 is a schematic diagram of the structure of another partitioned namespace solid-state drive provided in an embodiment of the present application. As shown in FIG6 , in addition to the first data area, a second data area is also included. The starting address of the second data area coincides with the ending address of the first data area. The second data area can be an IZFR (implicit ZRWA flush range) area.

[0077] The ZRWA protocol specifies that implicit flushing is achieved by writing to the second data area in Figure 6. The starting address of the implicit flush is the starting address of the second data area, and the ending address of the implicit flush is the address where the data is written to the second data area. This determines the length of the second data flush range.

[0078] In some embodiments, implicit flushing does not need to be triggered by an instruction. Instead, when data writing is detected in the second data area, the second data flushing range is actively determined. The determined second data flushing range can be used to push the data in the corresponding range in the first data area into the area to be flushed, becoming the data to be flushed.

[0079] That is to say, although the second data flush range is determined based on the starting address of the second data area and the ending address of the data written in the second data area, the second data flush range is not used to mark the data within the second data range in the second data area as data to be flushed, but to mark the data within the length range indicated by the second data range in the first data area as data to be flushed, that is, the second data area is used to push the data in the first data area to become data to be flushed.

[0080] S502: Update the position of the write pointer according to the length of the second data refresh range and the starting position of the first data area.

[0081] Optionally, the length of the data in the first data area to be pushed into the area to be flushed can be determined based on the length of the second data flush range. As a result, the starting position of the first data area will change, and the starting position of the first data area can be moved backward from the current position by the length of the second data flush range. Since the starting address of the write pointer coincides with the starting address of the first data area, the position of the write pointer is updated.

[0082] S503: Update the flush flag of the data in the address range between the start address and the write pointer in the first data area according to the updated position of the write pointer.

[0083] Consistent with the implementation of step S103 above, due to the update of the write pointer position, the data in the address range between the starting position and the write pointer in the first data area is pushed into the area to be flushed, and this part of the data is marked as data to be flushed.

[0084] Figure 7 is a schematic diagram of the structural changes of a partitioned namespace solid-state drive before and after an implicit flush, according to an embodiment of the present application. As shown in Figure 7, based on the write end position of the data written to the second data area and the start position of the second data area, the second data flush range can be determined. Then, the data starting from the start position in the first data area and within the length range corresponding to the second data flush range can be determined as the data to be flushed. As a result, this portion of data in the first data area is pushed into the area to be flushed, becoming the data to be flushed.

[0085] Optionally, the method further includes: updating the address range of the first data area according to the updated position of the write pointer and the area length of the first data area.

[0086] In some embodiments, to ensure that the sizes of the first and second data regions remain unchanged, after the write pointer position is updated, the address range of the first data region may be updated based on the updated write pointer position and the set region length of the first data region, so that the length of the first data region remains unchanged. Since the starting address of the second data region coincides with the ending address of the first data region, the address range of the second data region may be correspondingly updated based on the update of the address range of the first data region and the preset region length of the second data region.

[0087] 4 or 7 , it can be seen that after the position of the write pointer is updated, the first data area and the second data area are subsequently shifted to corresponding positions, so that the lengths of the first data area and the second data area remain unchanged before and after explicit or implicit flushing.

[0088] Optionally, in step S101, according to the first data refresh instruction, the first data refresh range corresponding to the first data area is determined, including: according to the target address in the first data area indicated in the first data refresh instruction and the starting address of the first data area, determining the first data refresh range as the starting address to the target address.

[0089] This embodiment describes how to determine the first data refresh range during an explicit refresh. Since the ZRWA protocol specifies that explicit refreshes are implemented using the Zone Management Send command, the first data refresh instruction must specify the target address in the first data area. Based on the start address and target address of the first data area, the first data refresh range can be determined. The first data refresh range is the range between the start address of the first data area and the target address of the first data area.

[0090] FIG8 is a flow chart of another data processing method provided in an embodiment of the present application; optionally, in step S501, determining the length of the second data refresh range may include:

[0091] S801: Detect a data writing operation in a second data area.

[0092] This embodiment explains how to determine the second data refresh range during implicit refresh. The data write operation in the second data area can be monitored in real time. When data is written to the second data area, the write end address of the data currently written to the second data area is obtained.

[0093] S802: Determine the length of the second data refresh range according to the address of the data written into the second data area and the starting address of the second data area.

[0094] The ZRWA protocol stipulates that implicit flushing is achieved by writing into the second data area. The implicit flushing starting address is the starting address of the second data area, and the ending address is the write ending address of the data written into the second data area. From this, the length of the second data flushing range can be calculated.

[0095] Then, the length of the second data refresh range can be determined according to the write end address of the data currently written into the second data area and the start address of the second data area.

[0096] It is worth noting that, whether it is an explicit refresh or an implicit refresh, the starting address, end address of the first data area, the starting address, end address, target address of the second data area or the address to which data is written all refer to the LBA logical block address.

[0097] Optionally, in step S101, before receiving the first data flush instruction, it also includes: writing new data to a specified address range in the first data area according to a data write request, generating a valid address range for the new data, and updating the valid address range for the old data within the specified address range.

[0098] This embodiment illustrates the data writing process in the first data area. Data writing can be achieved by initiating a data write request. The data write request may include: data to be written and a specified address range. Thus, according to the data write request, the data to be written can be written into the specified address range in the first data area. Compared with the data already written, the data to be written is new data, that is, the new data is written into the specified address range in the first data area.

[0099] The designated address range here can be any range within the address range of the first data area, that is, data can be randomly overwritten in the first data area, and when new data is written within a certain address range, the previously written data will be replaced.

[0100] Optionally, if no data is written in the specified address range, new data can be written directly into the specified address range. If data has been written into the specified address range, an overwrite process needs to be performed to replace the old data with the new data.

[0101] FIG9 is a flow chart of another data processing method provided by an embodiment of the present application; optionally, in step S103, updating the flush flag of the data in the address range between the start address and the write pointer in the first data area may include:

[0102] S901: Determine whether there is empty data in the address range between the start address and the write pointer in the first data area.

[0103] In some embodiments, due to the random writing characteristics of data in the first data area, it is difficult to ensure that all LBAs in the first data area are written with data. The LBA positions where no data is written can be defined as empty positions. There is no data at the empty positions. Having an empty position means that there is empty data.

[0104] Optionally, when performing explicit and implicit refresh, based on the determined length of the first data refresh range and the second data refresh range, it is possible to first check whether there is empty data in the data within the first data refresh range in the first data area, or in the data within the range indicated by the length of the second data refresh range in the first data area.

[0105] S902: If it exists, fill the empty data with a preset value, and update the flush flag of the data in the address range between the start address and the write pointer to be flushed.

[0106] If empty data exists, it is necessary to process the empty data first to fill the empty position before performing an explicit or implicit flush. Optionally, the empty data can be filled with a preset value, such as 0. By filling the empty position, it is ensured that during an explicit or implicit flush, the data within the flush range complies with the ZNS protocol and is flushed to the NAND according to the strict sequential write characteristics.

[0107] FIG10 is a flow chart of another data processing method provided in an embodiment of the present application;

[0108] As shown in FIG10 , the method further includes:

[0109] S1001. Receive a second data flush instruction, where the second data flush instruction is used to instruct to flush data within a target address range to a flash memory; the second data flush instruction includes: a target address range.

[0110] Different from the above-mentioned explicit flush and implicit flush, which only mark the data in the first data area as data to be flushed without performing the actual flush operation, this embodiment actually flushes the data marked as to be flushed to the flash memory.

[0111] The second data flush instruction is used to instruct to flush the data in the target address range of the area to be flushed formed above to the flash memory.

[0112] S1002. Adjust the position of each data to be flushed according to the address information of the target data and the valid address range of each data to be flushed, and based on the adjusted position, flush the data within the target address range to the flash memory in sequence.

[0113] In order to ensure that the data is flushed to the flash memory strictly in sequence, it is necessary to dynamically adjust the position of each data in the area to be flushed to ensure that each data to be flushed can be flushed to the flash memory in the order of the valid address range.

[0114] The following describes the implementation of data writing, explicit flushing, and flushing data to the flash memory using a specific example:

[0115] Select an empty zone, the write pointer (WP) of this zone is 0, and write the first data in the address range of 0-31 in the ZRWA area of ​​this zone to generate data block 0. Then the properties of the first data written at this time (that is, data block 0) are as follows: the starting address is 0, the length is 32, the valid address range identifier fvalidbmp of the data is 0xffff, indicating valid data in the address range of 0-31, and the flush identifier flushbmp of the data is 0, indicating that data block 0 is still in the ZRWA area (after WP) and is not data to be flushed.

[0116] The second data in the address range of 16-23 is written in the ZRWA area to generate data block 1. Based on the random overwrite feature of data in the ZRWA area, the address range of the second data written (i.e., data block 1) overlaps with the address range of the first data written, and will overwrite the data in the address range of 16-23 in the first data. The properties of the second data are as follows: the starting address is 16, the length is 8, and the flushbmp is 0; if the second data overwrites part of the first data, the writing of the second data will cause the fvalidbmp of the first data to change.

[0117] It can be observed that the range of the second data and the first data overlap, and the overlapping address range is 16-23. Therefore, the second data is overwritten. The data in the address range of 16-23 of the second data will overwrite the data in the address range of 16-23 of the first data. Therefore, the fvalidbmp of the first data will change from 0xffff to 0xf0ff, indicating valid data in the address ranges of 0 to 15 and 24 to 31. The fvalidbmp of the second data is 0x0f00, indicating valid data in the address range of 16-23. The flushbmp of the second data is 0, indicating that the data is still in the ZRWA area (after WP) and is not data to be flushed.

[0118] Execute the explicit flush command. The flush range specified by the explicit flush command is 0-31 and the flush length is 32. Then the properties of the first and second data will change as follows:

[0119] (1) The write pointer of the zone changes from 0 to 32.

[0120] (2) The flushbmp of the first data will be assigned the value of the fvalidbmp of the first data, changing from 0 to 0xf0ff, indicating that the first data becomes the data to be flushed (before WP). The valid data range to be flushed is from address 0 to 15 and from address 24 to 31.

[0121] (3) The flushbmp of the second data will be assigned the value of the fvalidbmp of the second data, changing from 0 to 0x0f00, indicating that the second data becomes the data to be flushed (before WP). The valid data range to be flushed is address 16-23.

[0122] (4) Before executing the explicit flush command, the flushbmp of the first data and the second data are both 0, and neither of them belongs to the data to be flushed. After executing the explicit flush command, the flushbmp of the first data and the second data are both not 0, and the first data and the second data are both marked as data blocks to be flushed. Therefore, the length of the area to be flushed changes from 0 to 32, indicating that the total address range length of the data to be flushed is 32.

[0123] The dynamic management process for flushing data in the area to be flushed (before the write pointer) to the flash memory is as follows:

[0124] (1) According to the ZNS protocol requirements, the address range 0-15 is to be selected. When the flash starts, the first and second data are sequentially placed in the flash link list. The first data is selected first because the first data represents the address range 0-15 (the first data represents the address range 24-31, which is not important for the time being). The second data represents the address range 16-23.

[0125] (2) After the address range 0-15 is selected, the next step is to flash the first data in strict order according to the ZNS protocol requirements. Because it is observed that the address range represented by the first data is now 24-31, and the address range represented by the second data is 16-23, the positions of the second data and the first data in the flash list are swapped, with the second data in front and the first data in the back. In this way, the first data in the address range 0-15 can be flashed to the flash memory first, the second data in the address range 16-23 can be flashed to the flash memory, and finally the first data in the address range 24-31 can be flashed to the flash memory.

[0126] If the positions of the first data and the second data are not adjusted, an error will occur when the data is refreshed because there is no valid data in the address range 16-23 of the first data.

[0127] As shown in the above process, each time new data is selected, the downlink list needs to dynamically adjust the data position on the linked list in sequence according to the address range represented by each data to ensure orderliness.

[0128] Furthermore, each data block in the above-mentioned flush list uses the starting address plus data length to represent different address ranges. The data block is managed in units of 4k and is managed using a 32-bit flushbmp. The maximum data block managed does not exceed 32 units (4k), and the maximum managed data block is 128k.

[0129] In summary, the data processing method provided in this embodiment performs random overwrite writing of data based on the ZRWA partition random write area in the partition namespace solid-state drive. While writing data, the data written in the ZRWA area is explicitly flushed based on the data flush instruction. During the execution of the explicit flush, the position of the write pointer is updated to form a to-be-flushed area, thereby updating the data in the specified flush range in the ZRWA area to the to-be-flushed area, marking the data in the specified flush range in the ZRWA area as to-be-flushed data. Then, the to-be-flushed data can be flushed to the flash memory according to the flush instruction. This meets the requirements of multiple concurrent writes and random overwrite scenarios, and the data written in the ZRWA area can also be accurately and sequentially flushed to the flash memory.

[0130] Secondly, when performing an explicit or implicit flush, by checking the empty positions within the range to be flushed, the empty positions can be filled first, and then the flush is performed, thereby ensuring that the data within the flushable range complies with the ZNS protocol and is flushed to the flash memory according to the strict sequential write characteristics.

[0131] In addition, when the data to be flushed is flushed to the flash memory, the position of the data to be flushed can be dynamically adjusted according to the valid address range of the data to be flushed and the specified flush range to ensure that there is valid data in the currently selected flush range and it can be flushed normally, thereby ensuring the orderliness of the data when it is flushed to the flash memory.

[0132] Each partition of the partitioned namespace solid-state drive can be read in any order, but must be written in sequence. Therefore, there are no data holes when writing data based on ZNS technology. Although this method can reduce the write amplification and read-write latency inside the solid-state drive to a certain extent, it is not flexible enough. The partitioned random write area technology can solve the problem of inflexible data writing. The ZRWA area formed after the ZNS partition enables the ZRWA function can be randomly overwritten. Although this method improves the flexibility of data writing, this write feature does not strictly write data in sequence, which may cause data holes when writing data in the ZRWA area, thereby causing the data written in the ZRWA area to fail to meet the strict sequential write requirements of the ZNS partition and cannot be flushed to the flash memory. In order to avoid the data written in the ZRWA area from being unable to be normally flushed to the flash memory, the present application further identifies the location of the data hole when writing data in the ZRWA area and fills the data (fills with 0), so as to formally meet the ZNS sequential write requirements and the data written in the ZRWA area can be normally flushed to the flash memory.

[0133] Specifically, please refer to FIG11 , which is a schematic diagram of an embodiment of a data processing method provided in an embodiment of the present application;

[0134] As shown in FIG11 , the data processing method includes:

[0135] 101. When writing data in the first data area of ​​the memory space, scan the first address range corresponding to the data block in the linked table where the data is written;

[0136] Since the data written to the first data area of ​​the memory space (such as the ZRWA area) may contain data holes, this embodiment needs to first identify the data blocks with data holes and mark the locations of the data holes in the data blocks, so as to ensure that no holes appear when the data is refreshed to meet the ZNS sequential write requirements.

[0137] For the convenience of description, the following specific example uses the first data area as the ZRWA area and the linked list as the hash linked list. It should be noted that the first data area of ​​the present application can be other memory space data areas with data holes, and the linked list can also be other linked lists that can be used to store data block addresses.

[0138] In this embodiment, in order to facilitate the identification and recording of data holes in data blocks, it is necessary to identify data blocks of different address ranges in the first data area (such as the ZRWA area) and hang them on a linked list (such as a hash linked list) according to the address distribution. Each time data is written to the ZRWA area, the hash linked list needs to be updated accordingly. The address of the hash linked list refers to LMA, i.e., Logic Media Unit Address, which is in units of 4K. The address distribution also refers to the LMA address distribution. The data block address in the hash linked list is in LMA format, converted from LBA. For a 4K format SSD, LMA=LBA, and for a 512 format SSD, LMA=8LBA. It should be noted that only data blocks with written data will be hung in the linked list. Among them, using a hash linked list to store data block addresses can scatter many data blocks by hashing, and data blocks with the same hash result are hung on the same linked list, thereby avoiding the problem of low query efficiency caused by too many data block nodes on the linked list.

[0139] In this embodiment, it is necessary to first determine the scanning range in the hash chain table. Specifically, when refreshing the data written in the ZRWA area, the first address range corresponding to the ZRWA area data block to be scanned on the hash chain is determined according to the implicit or explicit refresh range. The first address range is the address range that needs to be scanned for the current refresh data.

[0140] 102. Determine whether the first address range is larger than the reference address range corresponding to the largest data block;

[0141] 103. If the first address range is larger than the reference address range, split the first address range into multiple second address ranges according to the reference address range;

[0142] In this embodiment, since the valid data bit identification method used is identified by a bitmap with a fixed number of bits, and the data block range identified by the bitmap is relatively small, in order to facilitate matching the data block scanning method with the valid data bit identification method and to facilitate data hole location identification, it is necessary to split the scanning range and then perform hole location identification on each of the split data blocks. This is equivalent to splitting a ZRWA area data block with a large address range into multiple data blocks with smaller address ranges. By identifying the data hole locations in each split data block, the data hole locations in the ZRWA area data block are indirectly obtained.

[0143] Since the data block structure is organized according to a maximum of 128K, that is, the address range represented by the largest data block is 128K, the address range identified by the largest data block is used as the basis for splitting, and the first address range to be scanned is split to obtain multiple second address ranges. If the first address range exceeds the address range of 128K represented by the largest data block, the first address range is split based on 128K as the base address range. If the first address range is smaller than the address range represented by the largest data block, no splitting is required. It should be noted that the scanning range can be an integer multiple of 128K or not. For example, if the scanning range is 300K, it can be split into two 128K data blocks and one 44K data block. In addition, data block management is strictly handled according to the address range, that is, the split data blocks need to meet the data block management requirements in the SSD. For example, taking a 4K format disk as an example, the address range corresponding to the data block range LBA 0-63 is 256K, and the data block can only be split into data blocks of LBA 0-31 and data blocks of LBA 32-63.

[0144] 104. Scan each second address range in sequence and determine whether a data block exists;

[0145] In this embodiment, if the data block address range is split, the second address ranges after the split are scanned. If the data block address range is not split, the first address range is scanned. Because the scanning method and data hole identification method corresponding to the two scenarios are the same, this embodiment only describes the scenario of splitting the data block address range.

[0146] In one embodiment, the following method is used to determine whether a data block exists within the second address range:

[0147] sequentially scanning data blocks within the second address range;

[0148] If the label value of the data block exists within the second address range, determining that the data block does not exist within the second address range;

[0149] If the label value of the data block does not exist within the second address range, it is determined that the data block exists within the second address range.

[0150] The scanning object of this embodiment is the address corresponding to the data block on the hash linked list. As long as the address of the data block corresponding to the written LBA is hung on the linked list. If there is no data block in a certain address range on the linked list, then the linked list in this address range is empty, and the label value of the corresponding read data block will be a special value: 0xFFFFUL, indicating that this address range belongs to the ZRWA area and no data has been written. The address space represented by all LBAs in this address range is a hole. If there is a data block in a certain address range on the linked list, the label value of the corresponding read data block is a non-special value 0xFFFFUL, which means that there is a data block in this range. Multiple data blocks exist in the form of a linked list. The address space represented by the LBA scanned in this address range is data written, and the address space represented by the LBA that has not been scanned is data not written, that is, data holes.

[0151] 105. If there are data blocks within the currently scanned second address range, update the values ​​of valid data bit identifiers corresponding to all data blocks within the second address range according to the third address range corresponding to each data block;

[0152] In this embodiment, if a data block is found within a second address range, it is necessary to further scan each data block within the second address range. Only by identifying the location of the data hole in each data block can the location of the data hole in the entire ZRWA area data block be determined. Specifically, based on the third address range corresponding to each data block, the value of the valid data bit identifier corresponding to all data blocks within the second address range is updated. The value of the valid data bit identifier is used to identify whether there is a data hole in the second address range and the location of the data hole. If no data block is found within a second address range, it is determined that the entire second address range being scanned is data holes.

[0153] In one embodiment, to facilitate the identification of data hole locations within the data block address range, a valid data bitmap is introduced to manage data blocks. This means that all data blocks containing data can be represented using the valid data bitmap. Given that both aligned and unaligned data blocks may contain data holes, two different variables can be used to identify them. For example, the variable fvalidbmp is used to identify data holes in aligned data blocks, while the variable uaBmp is used to identify data holes in unaligned data blocks.

[0154] The valid data bit identifier consists of multiple bits, each of which corresponds to a logical partition LBA within the data block address range. It should be noted that the bit order of the bitmap is consistent with the order of the LBAs within the corresponding data block address range. For example, bits 1-8 (from right to left) of a bitmap correspond to logical partitions LBA0-LBA7 of a data block, while bits 1-8 of another bitmap correspond to logical partitions LBA8-LBA15 of another data block.

[0155] The value of each bit indicates whether valid data exists in the logical partition LBA within the corresponding data block address range. For example, if data is written to an LBA, the corresponding bitmap bit is set to 1; otherwise, it is set to 0. The value of the valid data bit indicator (i.e., the bitmap value) is expressed in hexadecimal. Valid data specifically refers to the data written to the LBA based on a write command.

[0156] The number of bits used to identify valid data bits is related to the partition format of the ZNS SSD. For example, for a 4K-formatted disk, each LBA represents a size of 4K. If each data block can be managed using a U32-type parameter bitmap, such as using the variable fvalidbmp, with each bit representing 4K, then the address range of the largest data block that can be identified by fvalidbmp is 128KB. Of course, management can also be achieved through U8 or U16, but for 4K-formatted disks, the integer type is U32. Using U32 can reduce the number of data blocks on the linked list and increase the efficiency of batch processing. For a 512-formatted disk, each LBA represents a size of 512B. If each data block can be managed using a U8-type bitmap, such as using the variable uaBmp, with each bit representing 512B, then the address range of the largest data block that can be identified by uaBmp is 4KB.

[0157] Since the range size corresponding to the address unit used by the hash table (one LMA represents 4K) is the same as the range size corresponding to one LBA of a 4K format disk, 4K format disks generate aligned data blocks; while 512 format disks can generate either aligned data blocks or unaligned data blocks, depending on the data write range. If the write range is an integer multiple of 4K (for example, 8 LBAs), aligned data blocks will be generated. If the write range is not an integer multiple of 4K, unaligned data blocks will be generated.

[0158] For a 4K disk, assuming that the starting address of an aligned data block is 0 and its length is 32, that is, the address range corresponding to this data block is LBA0-LBA31, where the address range with valid data is LBA0-LBA7 and LBA24-LBA31. The valid data bit identification is represented by a bitmap as follows: bits 0-7 and bits 24-31 of written data are set to 1, and bits 8-23 of unwritten data are set to 0. That is, the bitmap value is represented in hexadecimal as 0xff0000ff. The valid data bit identification corresponding to this data block is shown in Figure 12. The numbers in the figure represent the address range LBA0-LBA31, and the dark areas LBA0-LBA7 and LBA24-LBA31 represent written data.

[0159] To facilitate understanding of ZRWA area partition random writing, the writing of the data block corresponding to Figure 12 is used as an example below.

[0160] Taking a 4K format disk as an example, assuming that the address range of the first write data is LBA0-LBA31, data block 1 is generated, and bits 0-bit 31 of the bitmap value corresponding to data block 1 are set to 1, that is, 0xffffffff. The address range of the second write data is LBA8-LBA23 (not starting from LBA32, that is, random partition write), generating data block 2, and bits 0-bit 7 of the bitmap value corresponding to data block 2 are set to 0, bits 8-bit 23 are set to 1, and bits 24-bit 31 are set to 0, that is, 0x00ffff00. Since the write range of data block 2 overlaps with that of data block 1, the address range 8-23 of data block 1 will be set to invalid (that is, invalid address) when data block 2 is generated. At this time, the bitmap value corresponding to data block 1 needs to be updated to 0xff0000ff. The bitmap layout corresponding to data block 1 is shown in Figure 12. It should be noted that the bitmap value 0xff0000ff corresponding to data block 1 does not mean that there is no write data in LBA8-LBA23, but that the write data of LBA8-LBA23 is located in data block 2, that is, each LBA of LBA0-LBA31 has valid data and there is no data hole.

[0161] For a 512-format disk, assuming that the starting address of a non-aligned data block is 0 and the length is 8, that is, the address range corresponding to the data block is LBA0-LBA7, among which the address range with valid data is LBA0-LBA1 and LBA5-LBA6, then the valid data bit identifier is represented by the bitmap as follows: bits 0-bit 1 and bits 5-bit 6 of written data are set to 1, and bits 2-4 and bit 7 of no written data are set to 0, that is, the bitmap value is represented by hexadecimal as 0x63. The valid data bit identifier corresponding to the data block is shown in Figure 13.

[0162] 106. Determine a location of a data hole in a second address range currently being scanned according to a value of a valid data bit identifier.

[0163] In this embodiment, the value of the valid flag bit calculated in step 105 is obtained based on the LBAs of the data written in all data blocks within the second address range. Therefore, the location of a data hole within the currently scanned second address range can be identified based on the value of the valid data flag bit. It should be noted that the valid data flag bit can also be used to identify whether there are data holes within the currently scanned second address range, that is, whether there are no data holes within the second address range.

[0164] The data block processing method of the ZRWA area provided in the embodiment of the present application can identify the data holes generated when the ZRWA area partitions randomly write data. The present application introduces a valid data bit identifier to identify the logical partitions that write data and the logical partitions that do not write data within the address range of each data block. When flushing the data written in the ZRWA area, in order to avoid data holes, it is necessary to first identify the location of the data hole in the data block to be flushed. The present application first determines the address range corresponding to the ZRWA area data block to be scanned on the hash chain; if the scanning range exceeds the address range represented by the largest data block, the scanning range is split according to the largest data block, and then the split address range is scanned to determine whether there is a data block. If there is a data block in the address range currently being scanned, the value of the valid data bit identifier corresponding to all data blocks in the address range currently being scanned is updated according to the address range corresponding to each data block; finally, according to the value of the updated valid data bit identifier, the location of the data hole in the address range currently being scanned is determined, which facilitates the subsequent processing of the data hole, thereby ensuring that the data written in the ZRWA area meets the requirements of sequential writing of the ZNS partition and can be successfully flushed to the flash memory.

[0165] In order to enable persons skilled in the art to better understand the present application solution, the specific implementation of steps 101-106 is further illustrated below based on the above description of the valid data bit identification.

[0166] (1) Assuming that a 4K format disk is used, first determine the scanning range of the hash linked table. For example, the address range of the scanned data block is LBA0-LBA63 (equivalent to the first address range). The address range is 256K, which is larger than the base address range of 128K. Therefore, it needs to be split into two address ranges: the first 128K corresponds to LBA0-LBA31 (equivalent to the second address range), and the second 128K corresponds to LBA32-LBA63 (equivalent to another second address range); then first scan whether there is a data block in the first 128K. Assuming that the aligned data block 1 is scanned first, the address range corresponding to the aligned data block 1 is LBA0-LBA7 and LBA24-LBA31 (equivalent to the third address range). There is valid data, then the value of the valid data bit identifier bitmap of all the data blocks currently being scanned (aligned data block 1) is updated to 0xff0000ff, and then continue to scan other data blocks within the first 128K range;

[0167] If another aligned data block 2 is subsequently scanned, and the address range LBA8-LBA23 corresponding to the aligned data block 2 (equivalent to another third address range) has valid data, then the value of the valid data bit identifier bitmap of all the data blocks currently being scanned (aligned data block 1 + aligned data block 2) is updated to 0xffffffff. When all the data blocks in the first 128K address range are scanned, the value of the current valid data bit identifier bitmap can be used to determine whether there is a data hole in the first 128K address range and the location of the data hole. Since the latest value of the valid data bit identifier bitmap corresponding to all data blocks in the first 128K is 0xffffffff, the corresponding first 128K address range is: LBA0-LBA31. If 0xffffffff is converted to binary, each binary bit is 1 and corresponds to LBA0-LBA31 respectively, that is, the valid data bit identifier 0xffffffff means that each LBA in LBA0-LBA31 has written data, which means that there is no data hole in the first 128K.

[0168] If no other data blocks are subsequently scanned, representing the address range LBA8-LBA23, it means that there is a data hole in the first 128K. The corresponding data hole position is LBA 8-LBA 23, and the value of the valid data bit identifier bitmap is 0xff0000ff. After the first 128K is scanned, the second 128K is scanned again. The specific processing method is the same as the first 128K. Assuming that the data block label read when scanning the second 128K is the special value 0xFFFFUL, it means that there is no data block in the second 128K address range, and the second 128K address range is entirely data holes.

[0169] (2) Assuming that a 512-format disk is used, first determine the scanning range of the hash table. For example, the scanning range is LBA0-LBA7 (equivalent to the first address range). The address range is 4K, which is smaller than the base address range of 128K. Therefore, there is no need to split the address range, and LBA0-LBA7 belongs to the first 128K range. First scan whether there is a data block in the first 128K range. Assume that the non-aligned data block 1 is scanned. The address range corresponding to the non-aligned data block 1 is LBA0-LBA1 and LBA5-LBA6. There is valid data, and there are no other data blocks in the first 128K address range. Then, the value of the valid data bit identifier corresponding to all data blocks in the first 128K address range is the bitmap value of the current non-aligned data block 1: 0x63. After inverting the bitmap value, the bitmap value of the data hole position in the scanning range LBA0-LBA7 can be obtained: 0x9C, that is, the scanning range LBA2-LBA4 and LBA7 are data holes.

[0170] In one embodiment, to ensure that the data written to the first area complies with the ZNS partition sequential write requirement and can be successfully flushed to the flash memory, after identifying the data hole location in the first area, the data hole needs to be further processed. The specific processing method is as follows:

[0171] When flushing the data written in the first data area, obtaining the value of the valid data bit identifier corresponding to the data block to be flushed;

[0172] According to the value of the valid data bit identifier corresponding to the data block to be flushed, the address space corresponding to the position of all data holes in the data block to be flushed is filled with 0 to obtain a new data block in the first data area;

[0173] Update the value of the valid data bit identifier corresponding to the new data block and add the new data block to the linked list.

[0174] In this embodiment, when refreshing data written in the first area, the value of the valid data bit identifier corresponding to the data block to be refreshed is first obtained, and the data hole position within the address range corresponding to the data block to be refreshed can be determined based on the value.

[0175] For example, through steps 101-106 in the above embodiment, the value of the valid data bit identifier corresponding to the data block to be flushed can be obtained, assuming it is 0xff0000ff. If the value is converted into binary representation, a bit position of 1 indicates that there is valid data in the corresponding LBA, and a bit position of 0 indicates that the corresponding LBA is a data hole. Assuming that the address range of the data block to be flushed is LAB0-LBA31, 0xff0000ff can be used to identify that there is a data hole in LBA8-LBA23.

[0176] In order to avoid data holes in the data blocks to be refreshed, it is necessary to fill the address space corresponding to the positions of all data holes in the data blocks to be refreshed with 0 in advance, so as to obtain a new data block in the first area. The new data block also needs to be hung in the hash linked list, and the corresponding valid data bit identifier of the data block is updated to: 0x00fffff00.

[0177] In this embodiment, after identifying the locations of all data holes within the address range of the data block to be flushed, these data holes are further filled with 0s, thereby making the data holes within the address range of the data block to be flushed become formally non-data holes, ensuring that the data written in the first area meets the requirements of ZNS partition sequential write and can be successfully flushed to the flash memory.

[0178] The random data write characteristics of the ZRWA area partition lead to data holes, which not only affect the flushing of data to the flash memory, but also generate misaligned data blocks, which in turn affect data recovery in power-off scenarios. In power-off scenarios, whether it is a normal power-off or an abnormal power-off, all data in the ZRWA area must be sent to the FTL module in multiples of 4KB before powering off so that it can be restored after power-on. Since the minimum unit of data managed by the FTL is LMA, which is also a minimum of 4KB, if misaligned data blocks are not processed before being sent to the FTL, the FTL module will mistake them for aligned data blocks. Therefore, for aligned data blocks, correct data recovery can be guaranteed, but for misaligned data blocks, since the misaligned data blocks before power-off will be mistakenly identified as aligned data blocks by the FTL module, correct recovery to misaligned data blocks after power-on cannot be guaranteed.

[0179] To address the problem that non-aligned data blocks cannot be correctly restored in power-off scenarios, this application pre-saves the bitmap of non-aligned data blocks before powering off, and also pads the non-aligned data blocks into aligned data blocks before sending them to the FTL module. After power-on, the non-aligned data blocks can be correctly restored based on the pre-saved bitmap.

[0180] Please refer to FIG. 14 , which is another embodiment of the data processing method provided in the embodiment of the present application. In this embodiment, the data processing method further includes:

[0181] 201. When a power failure event is detected, save the values ​​of valid data bit identifiers of all non-aligned data blocks in a first data area to a non-volatile readable storage medium;

[0182] This embodiment will detect power-off events in real time. In view of the problem that power-off and non-aligned data blocks cannot be correctly restored, when a power-off event is detected, it is necessary to first save the values ​​of the latest valid data bit identifiers of all non-aligned data blocks in the first data area (such as the ZRWA area) to a non-volatile readable storage medium (such as NANDFlash) to avoid power-off loss.

[0183] It should be noted that a normal power outage in an electronic device generally provides ample time for some transaction processing, such as saving cached data. An abnormal power outage also generally allows tens of milliseconds for some transaction processing, such as writing the relevant information of all non-aligned data blocks in the ZRWA area to the non-volatile readable storage medium upon power outage, and sending all data in the ZRWA area to the FTL module upon power outage. Therefore, there is no need to execute the above power-out processing logic in advance in either normal or abnormal power-out scenarios.

[0184] 202. Determine the logical partition corresponding to the non-aligned data block to which data is not written based on the value of the valid data bit identifier, add 0 to the memory address corresponding to the logical partition to which data is not written, and update the value of the valid data bit identifier corresponding to the non-aligned data block;

[0185] In this embodiment, before sending the unaligned data blocks to the FTL module, each unaligned data block needs to be padded to become an aligned data block. Specifically, the logical partitions contained in the unaligned data block are first determined based on the value of the valid data bit identifier bitmap of the unaligned data block. For example, assuming that before the power failure event occurs, the bitmap value of a certain unaligned data block A is 0x63, then the logical partitions contained in the unaligned data block A are LBA0-LBA1 and LBA5-LBA6. Correspondingly, the logical partitions missing from the aligned data block that the unaligned data block A lacks are LBA2-LBA4 and LBA7. If 0 is padded to the memory addresses corresponding to LBA2-LBA4 and LBA7, then LBA0-LBA7 will all belong to the unaligned data block A, and the bitmap value of the unaligned data block A will be updated to 0xff, thus completing the transition from unaligned data block to aligned data block.

[0186] 203. When a power-on event is detected, determining whether the currently recovered data block is an unaligned data block before power failure;

[0187] This embodiment also detects power-on events in real time. Since the non-aligned data blocks in the ZRWA area have already been converted to aligned data blocks when a power outage occurs, when restoring the data blocks upon power-on, the data blocks that were converted from non-aligned data blocks to aligned data blocks during the power outage must be restored to their original non-aligned state. Since all non-aligned data blocks sent to the FTL module are padded, it is not possible to determine whether the recovered data blocks were non-aligned before the power outage based on the data block size. It should also be noted that non-aligned data blocks do not exist on 4K format disks; only on 512 format disks.

[0188] In one embodiment, step 203 specifically includes: determining whether the currently recovered data block is a non-aligned data block before power failure based on pre-saved valid data bit identifiers of all data blocks and location information of each data block in the partition.

[0189] For 512-format disks, the valid data bit identifier bitmap value corresponding to the aligned data block is the same, specifically 0xff, and all values ​​other than 0xff correspond to unaligned data blocks. In the event of a power outage, the bitmaps of all data blocks and the location information of each data block in different zones are saved to a non-volatile readable storage medium. When powered on, the location information of each data block in the zone is first read, and the corresponding bitmap value is found based on the location information. Then, a check is made to see if it is 0xff. If it is 0xff, the currently recovered data block is determined to be an aligned data block, and if it is not 0xff, the currently recovered data block is determined to be an unaligned data block.

[0190] 204. If the currently recovered data block is a non-aligned data block before the power failure, update the value of the valid data bit identifier corresponding to the data block to the corresponding value before the power failure.

[0191] In this embodiment, when it is determined that the currently recovered data block is a non-aligned data block before power failure, in order to ensure that the non-aligned data block can be correctly recovered, it is necessary to update the value of the valid data bit identifier corresponding to the non-aligned data block to the corresponding value before power failure. The value of the valid data bit identifier corresponding to the power failure can be found through the position information of the data block in the zone, and the corresponding bitmap value is found according to the position information.

[0192] It should be noted that in step 202, the memory address corresponding to the logical partition where no data is written to the non-aligned data block is padded with 0, thereby formally completing the transformation from the non-aligned data block to the aligned data block. However, in step 204, the memory address corresponding to the logical partition originally padded with 0 can be cleared to zero or not cleared to zero. Not clearing the corresponding memory address will not affect the subsequent read and write operations on the non-aligned data block.

[0193] In one embodiment, to ensure that non-aligned data blocks can be correctly recovered in a power failure scenario, two types of data structures are used to manage non-aligned data blocks.

[0194] (1) A linked list for recording the index information of all misaligned data blocks. To facilitate the rapid and centralized retrieval of all misaligned data blocks in the event of an abnormal power outage, before power outage, whenever a new misaligned data block is generated in the ZRWA area, the index information of the misaligned data block is recorded in the linked list. Preferably, the subscript of the array storing the data block is used as the index information.

[0195] (2) An array used to record the bitmap of the non-aligned data block. When there are multiple first data areas of ZNS (such as ZRWA areas), in order to reduce the size of the array, a one-dimensional array is used to record only the partition ID of the partition where the writable ZRWA area is located. There are generally 16 writable ZRWA areas. A two-dimensional array is used to record the value of the valid data bit identifier of all non-aligned data blocks in each ZRWA area before power failure; the first column of the two-dimensional array is used to record the subscript of the one-dimensional array, and the first row of the two-dimensional array is used to record the offset of the ZRWA area in each partition relative to the write pointer. Generally, when writing data in the ZRWA area within the ZONE, there will be a write pointer as a mark bit after each sequential write is completed to record the logical block address position where the data has been written.

[0196] A one-dimensional array is used to record the ZoneIDs of the partitions corresponding to the ZRWA area containing unaligned data blocks. The size of this one-dimensional array represents the maximum number of zones that can be opened concurrently. As shown in Figures 15 and 17, a one-dimensional zone lookup table is formed. The first data point in the table is ZoneID 10, corresponding to the array index 0; the third data point is 13, corresponding to the array index 2.

[0197] The two-dimensional array is used to record the bitmap of the unaligned data block. The first column of the two-dimensional array is used to record the subscript of the one-dimensional array for ZoneID indexing. The first row of the two-dimensional array is used to record the offset of the ZRWA area relative to the write pointer within each partition. As shown in Figures 16 and 17, a two-dimensional bitmap lookup table is formed. For example, if the bitmap in the two-dimensional array is 0x04, based on the corresponding ZoneID index value of 2, the data with subscript 2 in the one-dimensional array is 13. The address offset relative to the write pointer is 1, and the bitmap value of 0x04 indicates that there is an unaligned data block in the zone with ZoneID 13. The address of this unaligned data block is the write pointer + address offset 1, and the bitmap of this unaligned data block is 0x04. In this embodiment, it is necessary to scan all non-aligned data blocks in each ZRWA area before power off, save the ZoneID of the partition corresponding to each ZRWA area into a one-dimensional array, write the address position of each non-aligned data block in the ZRWA area and the corresponding bitmap into a two-dimensional array, and save the one-dimensional array and the two-dimensional array to a storage medium that will not be lost during power off.

[0198] In order to enable persons skilled in the art to better understand the present application solution, the specific implementation of steps 201-204 is further illustrated below based on the above description of the one-dimensional array and the two-dimensional array.

[0199] (1) Whenever a new non-aligned data block is generated in the ZRWA area, the index information of the new non-aligned data block is recorded in the linked list. For example, the bitmap of non-aligned data block A is 0x04, and its subscript in the data block array (automatically generated by the system) is 3, then the array subscript index = 3 of non-aligned data block A is written into the linked list.

[0200] (2) When a power failure event is detected, the ZoneID corresponding to each ZRWA zone is written into a one-dimensional array. The valid data bitmap values ​​of all non-aligned data blocks in each ZRWA zone are written into a two-dimensional array. The subscript of the one-dimensional array is used as the index of the two-dimensional array. The bitmap values ​​of different non-aligned data blocks in the same ZRWA zone are distinguished based on the offset of the ZRWA zone relative to the write pointer. Finally, the one-dimensional array and the two-dimensional array are saved to a non-volatile readable storage medium.

[0201] Furthermore, to ensure correct recovery of misaligned data upon power-up, the type of recovered data blocks (aligned or misaligned) must be determined. In the event of a power outage, the bitmaps of all data blocks and their location information within different zones are saved to a non-volatile, readable storage medium. This location information includes the ZoneID of each data block, its LMA, and its corresponding write pointer.

[0202] (3) When power is lost, in order to comply with the data block format requirements of the FTL module, it is necessary to fill the non-aligned data block A with 0 and turn it into an aligned data block. Specifically, according to the bitmap of all data blocks saved in advance, the non-aligned data block is found and the memory address is filled with 0.

[0203] For example, before power failure, the bitmap of unaligned data block A is 0x04. When power failure occurs, the memory addresses corresponding to the logical partitions where unaligned data block A has not been written are first padded with 0, and then the bitmap is updated to 0xff. It should be noted that converting unaligned data block A to an aligned data block does not modify the data in the one-dimensional and two-dimensional arrays.

[0204] (4) When a power-on event is detected, since all data blocks are aligned, it is not possible to make a judgment based on the data block size. First, the location information of each data block in different zones is read, including the ZoneID of each data block, the LMA of each data block, and the write pointer WP corresponding to each data block. Then, based on the location information of each data block, the one-dimensional array and the two-dimensional array are queried.

[0205] For example, the ZoneID of data block A is 13, and the offset of non-aligned data block A in the zone is LMA-WP=1. ZoneID queries the one-dimensional array, and the array subscript corresponding to ZoneID 13 is 2. Then, using array subscript 2 + write pointer offset 1 as the query condition, query the two-dimensional array. If the corresponding value exists in the two-dimensional array, it is determined that data block A was an unaligned data block before power failure (the two-dimensional array only stores the bitmap of the non-aligned data block). If the corresponding value does not exist in the two-dimensional array, it is determined that data block A was an aligned data block before power failure.

[0206] (5) If the data block being restored was unaligned before the power failure, the bitmap value obtained by querying the two-dimensional array is directly used as the bitmap value of the data block after the power is restored. For example, the bitmap value of data block A before the power failure is 0x04. After the power failure, the bitmap value is updated to 0xff. When the power is restored again, the bitmap value is updated to 0x04 again.

[0207] The above detailed descriptions of various embodiments corresponding to the data processing method are based on this. This application also discloses a data processing device corresponding to the above data processing method. Figure 18 is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. The data processing device can be understood as the above-mentioned computer device. The data processing device can be applied to a partitioned namespace solid-state drive. The partitioned namespace solid-state drive includes: a first data area; the starting address of the first data area coincides with the address of the write pointer;

[0208] As shown in FIG18 , the data processing device includes: a determination module 110 and an update module 120;

[0209] The determining module 110 is configured to receive a first data refresh instruction and determine a first data refresh range corresponding to the first data region according to the first data refresh instruction;

[0210] An updating module 120 is configured to update a position of a write pointer according to a first data flush range;

[0211] The updating module 120 is configured to update the flush flag of the data in the address range between the start address and the write pointer in the first data area according to the updated position of the write pointer.

[0212] Optionally, the partition namespace solid state drive further includes: a second data area, wherein a start address of the second data area coincides with an end address of the first data area;

[0213] The determination module 110 is further configured to determine the length of the second data refresh range according to the address of the data written into the second data area;

[0214] The updating module 120 is further configured to update the position of the write pointer according to the length of the second data flush range and the starting position of the first data area;

[0215] The updating module 120 is further configured to update the flush flag of the data in the address range between the start address and the write pointer in the first data area according to the updated position of the write pointer.

[0216] Optionally, the updating module 120 is further configured to update the address range of the first data area according to the updated position of the write pointer and the area length of the first data area.

[0217] Optionally, the determination module 110 is specifically configured to determine the first data flush range as from the start address to the target address according to the target address in the first data area and the start address of the first data area indicated in the first data flush instruction.

[0218] Optionally, the determination module 110 is specifically configured to detect a data writing operation in the second data area;

[0219] The length of the second data refresh range is determined according to the address of the data written into the second data area and the start address of the second data area.

[0220] Optionally, it further includes: a writing module;

[0221] The writing module is used to write new data into a specified address range in the first data area according to a data writing request, generate a valid address range for the new data, and update the valid address range for the old data in the specified address range.

[0222] Optionally, the updating module 120 is specifically configured to determine whether there is empty data in an address range between a start address and a write pointer in the first data area;

[0223] If it exists, the empty data is filled with a preset value, and the flush flag of the data in the address range between the start address and the write pointer is updated to be flushed.

[0224] Optionally, it further includes: a lower brush module;

[0225] The flash module is configured to receive a second data flash instruction, wherein the second data flash instruction is configured to instruct to flash the data within a target address range to the flash memory; the second data flash instruction includes: a target address range;

[0226] According to the address information of the target data and the valid address range of each data to be flushed, the position of each data to be flushed is adjusted, and based on the adjusted position, the data within the target address range is flushed to the flash memory in sequence.

[0227] Please refer to FIG19 , which is a schematic diagram of the structure of another data processing device provided in an embodiment of the present application;

[0228] As shown in FIG19 , the data processing device includes:

[0229] The first scanning module 701 is used to determine a first address range corresponding to a data block of written data on a linked list when flushing data written to a first data area of ​​the memory space;

[0230] A determination module 702 is configured to determine whether the first address range is larger than a reference address range corresponding to the largest data block;

[0231] a splitting module 703, configured to split the first address range into a plurality of second address ranges according to the reference address range if the first address range is larger than the reference address range;

[0232] A second scanning module 704 is used to sequentially scan each second address range and determine whether a data block exists;

[0233] The identification module 705 is used to update the value of the valid data bit identifier corresponding to all data blocks in the second address range if there are data blocks in the second address range currently being scanned, based on the third address range corresponding to each data block; and determine the location of the data hole in the second address range currently being scanned based on the value of the valid data bit identifier.

[0234] In one embodiment, the identification module 705 is further configured to:

[0235] If there is no data block in the currently scanned second address range, it is determined that the currently scanned second address range is entirely data holes, and the value of the valid data bit flag corresponding to the currently scanned second address range is updated.

[0236] In one embodiment, the second scanning module 704 is specifically configured to:

[0237] sequentially scanning data blocks within the second address range;

[0238] If the label value of the data block exists within the second address range, determining that the data block does not exist within the second address range;

[0239] If the label value of the data block does not exist within the second address range, it is determined that the data block exists within the second address range.

[0240] In one embodiment, the valid data bit identifier consists of multiple bits, each bit corresponds to a logical partition within the data block address range, and the value of each bit represents whether valid data exists or not in the logical partition within the corresponding data block address range.

[0241] In one embodiment, the data block processing apparatus in the ZRWA region further includes:

[0242] The first zero-padding module 706 is used to obtain the value of the valid data bit identifier corresponding to the data block to be flushed when flushing the data written in the first data area; according to the value of the valid data bit identifier corresponding to the data block to be flushed, fill the address space corresponding to the positions of all data holes in the data block to be flushed with 0 to obtain a new data block in the first data area; update the value of the valid data bit identifier corresponding to the new data block, and hang the new data block in the linked list.

[0243] In one embodiment, the data block processing apparatus in the ZRWA region further includes:

[0244] A saving module 707 is configured to save the values ​​of valid data bit identifiers of all non-aligned data blocks in the first data area to a non-volatile readable storage medium when a power failure event is detected;

[0245] A second zero-padding module 708 is configured to determine the logical partitions in the non-aligned data block to which data has not been written based on the value of the valid data bit identifier, and to pad the memory addresses corresponding to the logical partitions to which data has not been written with zeros and update the value of the valid data bit identifier corresponding to the non-aligned data block;

[0246] The judging module 702 is further configured to: when a power-on event is detected, judge whether the currently recovered data block is an unaligned data block before power failure;

[0247] The recovery module 709 is used to clear the memory address corresponding to the logical partition of the data block filled with 0 and update the value of the valid data bit identifier corresponding to the data block if the currently recovered data block is an unaligned data block before power failure.

[0248] In one embodiment, a one-dimensional array is used to record the partition ID of the partition where each first data region is located, and a two-dimensional array is used to record the values ​​of valid data bit identifiers of all non-aligned data blocks in each first data region before power failure.

[0249] Since the embodiments of the device part correspond to the embodiments of the above method, please refer to the above method embodiments for the introduction of a data processing device provided by this application. This application will not go into details here. It has the same beneficial effects as the above data processing method.

[0250] 18 and 19 above describe in detail the data processing apparatus in the embodiment of the present application from the perspective of modular functional entities, and the following describes in detail the computer device in the embodiment of the present application from the perspective of hardware processing.

[0251] Figure 20 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. The computer device 500 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 510 (for example, one or more processors) and a memory 520, and one or more storage media 530 (for example, one or more mass storage devices) storing application programs 533 or data 532. Among them, the memory 520 and the storage medium 530 can be temporary storage or permanent storage. The program stored in the storage medium 530 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the computer device 500. Furthermore, the processor 510 can be configured to communicate with the storage medium 530 to execute a series of instruction operations in the storage medium 530 on the computer device 500.

[0252] The computer device 500 may further include one or more power supplies 540, one or more wired or wireless network interfaces 550, one or more input / output interfaces 560, and / or one or more operating systems 531, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will appreciate that the computer device structure shown in FIG20 does not limit the computer device, and the computer device may include more or fewer components than shown, or may combine certain components, or may have different component arrangements.

[0253] The present application also provides a computer device, which includes a memory and a processor. The memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes the steps of the data processing method in the above embodiments.

[0254] The present application also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to execute the steps of the data processing method.

[0255] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0256] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0257] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that: Applied to a partition namespace solid state drive, the partition namespace solid state drive comprises: a first data area, the start address of the first data area coincides with the address of the write pointer, the method comprises: receiving a first data refresh instruction, and determining a first data refresh range corresponding to the first data area according to the first data refresh instruction; According to the first data flushing range, updating the position of the write pointer; According to the updated position of the write pointer, the flush flag of the data in the address range between the start address and the write pointer in the first data area is updated.

2. The method according to claim 1, characterized in that: The partition namespace solid state drive further includes: a second data area, wherein the start address of the second data area coincides with the end address of the first data area; the method further includes: Determining the length of the second data refresh range according to the address of the data written into the second data area; updating the position of the write pointer according to the length of the second data flushing range and the starting position of the first data area; According to the updated position of the write pointer, the flush flag of the data in the address range between the start address and the write pointer in the first data area is updated.

3. The method according to claim 1, characterized in that The method further comprises: The address range of the first data area is updated according to the updated position of the write pointer and the area length of the first data area.

4. The method according to claim 1, characterized in that: The determining, according to the first data refresh instruction, a first data refresh range corresponding to the first data area includes: According to the target address in the first data area and the start address of the first data area indicated in the first data flush instruction, the first data flush range is determined to be from the start address to the target address.

5. The method according to claim 2, characterized in that: The determining the length of the second data refresh range includes: detecting a data writing operation in the second data area; The length of the second data refresh range is determined according to the address of the data written into the second data area and the starting address of the second data area.

6. The method according to claim 1, characterized in that Before receiving the first data refresh instruction, the method further includes: According to the data write request, new data is written into the specified address range in the first data area, Generate a valid address range for the new data, and update the valid address range for the old data within the specified address range.

7. The method according to claim 1, characterized in that The updating of the flush flag of the data in the address range between the start address and the write pointer in the first data area includes: Determine whether there is empty data in the address range between the start address and the write pointer in the first data area; If it exists, the empty data is filled with a preset value, and the flush flag of the data in the address range between the start address and the write pointer is updated to be flushed.

8. The method according to claim 1, characterized in that The method further comprises: Receive a second data flush instruction, the second data flush instruction is used to instruct to flush data within a target address range to a flash memory; the second data flush instruction includes: a target address range; According to the address information of the target data and the valid address range of each data to be flushed, the position of each data to be flushed is adjusted, and based on the adjusted position, the data within the target address range is flushed to the flash memory in sequence.

9. The method according to claim 1, characterized in that: The method further comprises: When the data written in the first data area is flushed, a first address range corresponding to the data block in which the data is written on the scan chain table is scanned; Determining whether the first address range is larger than a reference address range corresponding to a maximum data block; If the first address range is larger than the reference address range, the first address range is divided into a plurality of second address ranges according to the reference address range.

10. The method according to claim 9, characterized in that The method further comprises: Scan each of the second address ranges in sequence and determine whether a data block exists; If there are data blocks within the second address range currently being scanned, the values ​​of valid data bit identifiers corresponding to all data blocks within the second address range are updated according to the third address range corresponding to each of the data blocks.

11. The method according to claim 10, characterized in that The method further comprises: The location of the data hole in the second address range currently being scanned is determined according to the value of the valid data bit identifier.

12. The method according to claim 10, characterized in that After sequentially scanning each of the second address ranges and determining whether a data block exists, the method further includes: If there is no data block in the second address range currently being scanned, it is determined that the second address range currently being scanned is entirely data holes.

13. The method according to claim 10, characterized in that The sequentially scanning and determining whether there is a data block in each of the second address ranges includes: sequentially scanning data blocks within the second address range; If the label value of the data block exists within the second address range, determining that the data block does not exist within the second address range; If the label value of the data block does not exist in the second address range, it is determined that the data block exists in the second address range.

14. The method according to any one of claims 10 to 13, characterized in that: The valid data bit identifier is composed of multiple bits, each bit corresponds to a logical partition within the data block address range, and the value of each bit represents whether valid data exists or does not exist in the logical partition within the corresponding data block address range.

15. The method according to claim 9, characterized in that The method further comprises: When flushing the data written in the first data area, obtaining the value of the valid data bit identifier corresponding to the data block to be flushed; According to the value of the valid data bit identifier corresponding to the data block to be flushed, the address space corresponding to the position of all data holes of the data block to be flushed is filled with 0 to obtain a new data block in the first data area; The value of the valid data bit identifier corresponding to the new data block is updated, and the new data block is hung in the linked list.

16. The method according to claim 10, characterized in that The method further comprises: When a power failure event is detected, saving the values ​​of valid data bit identifiers of all non-aligned data blocks in the first data area to a non-volatile readable storage medium; According to the value of the valid data bit identifier, the logical partition in which data is not written in the corresponding non-aligned data block is determined, and 0 is added to the memory address corresponding to the logical partition in which data is not written, and the value of the valid data bit identifier corresponding to the non-aligned data block is updated.

17. The method according to claim 16, characterized in that The method further comprises: When a power-on event is detected, determining whether the currently recovered data block was a non-aligned data block before the power-off; If the currently restored data block is a non-aligned data block before power failure, the value of the valid data bit identifier corresponding to the data block is updated to the corresponding value before power failure.

18. The method according to claim 17, characterized in that A one-dimensional array is used to record the partition ID of the partition where each of the first data regions is located, and a two-dimensional array is used to record the value of the valid data bit identifier of all the non-aligned data blocks in each of the first data regions before power failure.

19. A computer device, characterized in that: The computer device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instructions in the memory to enable the computer device to execute the data processing method according to any one of claims 1 to 18.

20. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by a processor, the data processing method according to any one of claims 1 to 18 is implemented.

Images