Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel comprises a first substrate; the first substrate in a display area comprises a first base substrate, a first metal layer and a metal oxide semiconductor layer which are stacked; the first metal layer comprises data lines; transparent active layers of the metal oxide semiconductor layer each comprise a channel and, on both sides of the channel, a source region and a drain region, the source regions being electrically connected to the data lines, and all of the orthographic projections of the channels, the source regions and the drain regions on the first base substrate overlapping the orthographic projections of the data lines on the first base substrate.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311742449.0 filed on December 15, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display, and in particular to a display panel and a display device. Background Art

[0003] With the advancement of display technology, consumer electronics products that rely on display panels, such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, virtual reality (VR) display devices, and augmented reality (AR) display devices, have emerged in an endless stream. The rise of the "metaverse" concept has also attracted widespread consumer attention for VR / AR display devices, demonstrating their broad market application prospects.

[0004] VR / AR display devices are near-eye displays, placing high demands on the resolution of their display panels. For example, the pixel density (PPI) of these panels must be increased to over 1500. However, as the PPI increases, the spacing between adjacent active layers is compressed, resulting in the minimum spacing between the two adjacent active layers failing to meet design requirements.

[0005] Therefore, how to improve the product yield of display panels while taking into account high pixel resolution is a problem that those skilled in the art urgently need to solve. Summary of the Invention

[0006] The present application provides a display panel and a display device, which can effectively solve the problem that the display panels in existing VR / AR display devices cannot achieve both high resolution and product yield.

[0007] In a first aspect, the present application provides a display panel, which has a display area and includes a first substrate, wherein the first substrate of the display area includes: a first substrate; a first metal layer, arranged on one side of the first substrate, the first metal layer including a plurality of data lines arranged in sequence and spaced apart; a metal oxide semiconductor layer, arranged on a side of the first metal layer away from the first substrate, the metal oxide semiconductor layer including a plurality of transparent active layers, the transparent active layers including a channel and a source region and a drain region located on both sides of the channel, the source region being connected to the data line through a via; wherein the orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projections of the data line on the first substrate.

[0008] In a second aspect, the present application further proposes a display device, which includes a housing and the above-mentioned display panel. The housing has an accommodating space, and the display panel is arranged in the accommodating space. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic plan view of two adjacent transparent active layers in a display area according to an embodiment of the present application.

[0010] FIG2 is a schematic plan view of a display panel provided in some embodiments of the present application.

[0011] FIG3 is a schematic diagram of a film layer structure of a display panel provided in some embodiments of the present application.

[0012] FIG4 is a plan view schematically showing a plurality of adjacent transparent active layers in a first substrate of a display area provided in some embodiments of the present application.

[0013] FIG5 is a schematic diagram of a first film layer structure of a first substrate and a second substrate provided in an embodiment of the present application.

[0014] FIG6 a is a planar schematic diagram of a first transparent conductive portion provided in some embodiments of the present application.

[0015] FIG6 b is a planar schematic diagram of a first light shielding portion provided in some embodiments of the present application.

[0016] FIG6 c is a planar schematic diagram of a second transparent conductive portion provided in some embodiments of the present application.

[0017] FIG6 d is a planar schematic diagram of a stacked data line, a transparent active layer, a first transparent conductive portion, a first light shielding portion, and a second transparent conductive portion provided in some embodiments of the present application.

[0018] FIG7 is a plan view of a color filter unit provided in an embodiment of the present application.

[0019] FIG8 is a schematic diagram of a second film layer structure of the first substrate and the second substrate provided in an embodiment of the present application.

[0020] FIG9 is a schematic diagram of a third film layer structure of the first substrate and the second substrate provided in an embodiment of the present application.

[0021] FIG10 is a schematic diagram of a fourth film layer structure of the first substrate and the second substrate provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application and are not intended to limit the present application.

[0023] In the description of this application, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, and "at least one" means one, two, or more, unless otherwise specifically defined.

[0025] Please refer to Figure 1. Taking the 2000PPI display panel shown in Figure 1 as an example, the horizontal spacing a between two adjacent active layers is 4.2 microns, but the minimum spacing b between two adjacent active layers is only 2.95 microns, which cannot meet the design requirements and greatly reduces the product yield.

[0026] As shown in Figures 2 to 5, an embodiment of the present application provides a display panel 01. The display panel 01 can be used in a VR display device with high-resolution display requirements. The type of the display panel 01 can be a liquid crystal display panel.

[0027] In this embodiment, the display panel 01 has a display area AA, and the display panel 01 includes a first substrate 10. The first substrate 10 of the display area AA includes a first substrate 101, a first metal layer 102, and a metal oxide semiconductor layer 103, wherein the first metal layer 102 is arranged on one side of the first substrate 101, and the first metal layer 102 includes a plurality of data lines 1021 arranged in sequence and spaced apart; the metal oxide semiconductor layer 103 is arranged on a side of the first metal layer 102 away from the first substrate 101, and the metal oxide semiconductor layer 103 includes a plurality of transparent active layers 1031, and the transparent active layer 1031 includes a channel 1032 and a source region 1033 and a drain region 1034 located on both sides of the channel 1032, and the source region 1033 is electrically connected to the data line 1021 through a via; wherein the orthographic projections of the channel 1032, the source region 1033, and the drain region 1034 on the first substrate 101 all overlap with the orthographic projections of the data line 1021 on the first substrate 101.

[0028] In the display panel 01 provided in the embodiment of the present application, the orthographic projections of the channel 1032, the source region 1033, and the drain region 1034 in the transparent active layer 1031 on the first substrate 101 all overlap with the orthographic projections of the data line 1021 on the first substrate 101. Therefore, the overlapping area between the transparent active layer 1031 and the data line 1021 can be increased, thereby maximizing the use of the area above the data line 1021 to form the transparent active layer 1031. This reduces the area of ​​the transparent active layer 1031 between two adjacent data lines 1021, reduces the width of the transparent active layer 1031 in the arrangement direction of the data lines 1021, and minimizes or eliminates portions of the transparent active layer 1031 that are tilted relative to the data lines 1021. This allows the minimum spacing between two adjacent transparent active layers 1031 to be maximized while reducing the spacing between the two adjacent data lines 1021 and improving the resolution of the display panel 01, thereby improving the production yield of the display panel 01.

[0029] In some embodiments of the present application, the extending direction of the transparent active layer 1031 is the same as the extending direction of the data lines 1021. For example, the transparent active layer 1031 and the data lines 1021 are both long strips, and the extending directions of the transparent active layer 1031 and the data lines 1021 are both perpendicular to the arrangement direction of the data lines 1021.

[0030] It should be noted that the source region 1033 in the present application refers to the active material located in the source region 1033 , and the drain region 0134 refers to the active material located in the drain region 1034 .

[0031] 5 , in some embodiments of the present application, the first substrate 10 of the display area AA further includes at least one first insulating layer 104 , and the at least one first insulating layer 104 is disposed between the first metal layer 102 and the metal oxide semiconductor layer 103 ; wherein the source region 1033 is electrically connected to the data line 1021 through a first via hole H1 penetrating the at least one first insulating layer 104 .

[0032] In the display panel 01 provided in the embodiment of the present application, since the transparent active layer 1031 is arranged on the side of the data line 1021 facing away from the first substrate 101, and the orthographic projection of the source region 1033 of the transparent active layer 1031 on the first substrate 101 overlaps with the orthographic projection of the data line 1021 on the first substrate 101, the source region 1033 can be electrically connected to the data line 1021 through the first via hole H1 that penetrates at least one first insulating layer 104 by directly providing a via hole on the side of the source region 1033 facing the first substrate 101.

[0033] In some embodiments of the present application, the display panel 01 also has a non-display area NAA, and the first substrate 10 of the non-display area NAA includes: a first gate metal layer N11, including multiple first gates N111, and the first gate N111 is used as a gate of a low-temperature polycrystalline silicon thin film transistor arranged in the non-display area NAA; wherein the first gate metal layer N11 is arranged on the same layer as the first metal layer 102 and is made of the same material.

[0034] In the display panel 01 provided in the embodiment of the present application, the first substrate 10 of the display area AA includes a plurality of metal oxide thin film transistors, and the transparent active layer 1031 is used to set the semiconductor layer of the metal oxide thin film transistor in the display area AA; the first substrate 10 of the non-display area NAA includes a plurality of low-temperature polycrystalline silicon thin film transistors, and the first gate N111 in the first gate metal layer N11 is used as the gate of the low-temperature polycrystalline silicon thin film transistor set in the non-display area NAA.

[0035] In this embodiment, the first substrate 10 includes a metal oxide thin film transistor arranged in the display area AA and a low-temperature polysilicon thin film transistor arranged in the non-display area NAA, so that the display driving circuit in the first substrate 10 in the display area AA can fully utilize the characteristics of low off-state current of the metal oxide thin film transistor and the transparent active layer 1031 that does not reduce the aperture ratio, and the gate driving circuit in the first substrate 10 in the non-display area NAA can fully utilize the strong stability of the low-temperature polysilicon thin film transistor, thereby greatly improving the display performance of the display panel 01.

[0036] In addition, since the first gate metal layer N11 and the first metal layer 102 are provided on the same layer and made of the same material, the first gate metal layer N11 and the first metal layer 102 can be formed integrally, simplifying the film structure of the first substrate 10 and reducing manufacturing costs.

[0037] As shown in conjunction with Figure 5 and Figures 6a, 6b, 6c, and 6d, in some embodiments of the present application, the first substrate 10 of the display area AA further includes a first transparent conductive layer 107 and a second transparent conductive layer 108. The first transparent conductive layer 107 is arranged on a side of the metal oxide semiconductor layer 103 facing away from the first substrate 101, and the first transparent conductive layer 107 includes a plurality of first transparent conductive portions 1071. The first transparent conductive portion 1071 includes a first portion 1072 and a second portion 1073. The first portion 1072 is electrically connected to the drain region 1034 through a via. The second transparent conductive layer 108 is arranged on a side of the first transparent conductive layer 107 facing away from the first substrate 101. The second transparent conductive layer 108 includes a plurality of second transparent conductive portions 1081. The second transparent conductive portion 1081 is electrically connected to the second portion 1073 through a via. The second portion 1073 is located between two adjacent data lines 1021, and the distances between the second portion 1073 and the two adjacent data lines 1021 are different.

[0038] In some embodiments of the present application, the second portion 1073 of the first transparent conductive portion 1071, which is electrically connected to the second transparent conductive portion 1081 through a via, is often arranged in the middle area between two adjacent data lines 1021, and the first portion 1072 of the first transparent conductive portion 1071 is overlapped with the drain region 1034 and the data line 1021. This requires forming a connection portion 1074 with a larger inclination angle relative to the data line 1021 between the first portion 1072 and the second portion 1073. This will cause the spacing between the two adjacent first transparent conductive portions 1071 at the connection portion 1074 to be smaller and less than the safety threshold, thereby causing yield problems for the display panel 01.

[0039] The present application makes the distance between the second part 1073 and the two adjacent data lines 1021 different, so that the second part 1073 is no longer located in the middle area between the two adjacent data lines 1021. For example, each second part 1073 can be made closer to the data line 1021 on its left, or each second part 1073 can be made closer to the data line 1021 on its right, thereby reducing the inclination angle between the connecting portion 1074 between the first part 1072 and the second part 1073 and the data line 1021, thereby increasing the spacing distance between the two adjacent first transparent conductive portions 1071 at the connecting portion 1074, thereby improving the production yield of the display panel 01.

[0040] In some embodiments of the present application, the first transparent conductive portion 1071 further includes a connecting portion 1074 connecting the first portion 1072 and the second portion 1073, the connecting portion 1074 is inclined relative to the data line 1021, and the angle between the connecting portion 1074 and the data line 1021 is an acute angle, and the angle is less than or equal to 20°.

[0041] In the display panel 01 provided in the embodiment of the present application, since the angle between the connecting portion 1074 and the data line 1021 is an acute angle and the angle is less than or equal to 20°, the spacing distance between two adjacent first transparent conductive portions 1071 at the connecting portion 1074 can be effectively increased, thereby improving the production yield of the display panel 01.

[0042] In some embodiments of the present application, the first substrate 10 of the display area AA also includes a first light-shielding layer 109, which is arranged between the first transparent conductive layer 107 and the second transparent conductive layer 108. The first light-shielding layer 109 includes a plurality of first light-shielding portions 1091. The first light-shielding portion 1091 includes a first sub-light-shielding portion 1092, a second sub-light-shielding portion 1093 and a avoiding portion 1094. The first sub-light-shielding portion 1092 is arranged corresponding to the source region 1033, and the second sub-light-shielding portion 1093 is arranged corresponding to the drain region 1034. The avoiding portion 1094 connects the first sub-light-shielding portion 1092 and the second sub-light-shielding portion 1093; wherein, the avoiding portion 1094 is formed with a notch 1095 on the side close to the second portion 1073.

[0043] In the display panel 01 provided in the embodiment of the present application, the first light shielding portion 1091 is provided corresponding to the transparent active layer 1031 to shield the transparent active layer 1031 , thereby improving the device performance of the metal oxide thin film transistor including the transparent active layer 1031 .

[0044] In the display panel 01 provided in the embodiment of the present application, when the second portion 1073 is closer to the data line 1021 on its left side, the avoidance portion 1094 corresponding to the data line 1021 on the left side is formed with a notch 1095 on the side close to the second portion 1073, so as to avoid a short circuit problem between the first light-shielding portion 1091, the second portion 1073, and the second transparent conductive portion 1081 electrically connected to the second portion 1073, thereby improving the stability of the display panel 01.

[0045] In other embodiments of the present application, in the display panel 01 provided by the embodiments of the present application, when the second part 1073 is closer to the data line 1021 on its right side, the avoidance portion 1094 corresponding to the data line 1021 on the right side is formed with a notch 1095 on the side close to the second part 1073, so as to avoid a short circuit problem between the first light-shielding portion 1091 and the second part 1073 and the second transparent conductive portion 1081 electrically connected to the second part 1073, thereby improving the stability of the display panel 01.

[0046] In some embodiments of the present application, the display panel 01 also includes a second substrate 20 and a liquid crystal layer 30, the second substrate 20 is arranged opposite to the first substrate 10, and the liquid crystal layer 30 is arranged between the first substrate 10 and the second substrate 20: wherein, the second substrate 20 includes: a second substrate 201; a second shading layer 202, arranged on one side of the second substrate 201; wherein, the second shading layer 202 includes a plurality of second shading portions 2021, and the extension direction of the second shading portion 2021 is different from the extension direction of the first shading portion 1091.

[0047] In the display panel 01 provided in the embodiment of the present application, since the second substrate 20 includes a second light-shielding layer 202, and the extension direction of the second light-shielding portion 2021 in the second light-shielding layer 202 is different from the extension direction of the first light-shielding portion 1091, the first substrate 10 and the second substrate 20 are respectively provided with light-shielding portions with different extension directions, thereby avoiding the problem of greatly increased wiring difficulty caused by the need to form a grid-shaped light-shielding layer on the first substrate 10, and making the spacing distance between adjacent first light-shielding portions 1091 smaller, thereby improving the resolution of the display panel 01.

[0048] In combination with Figures 5 and 7, in some embodiments of the present application, the first substrate 10 of the display area AA further includes: a color filter layer 110, which is arranged between the first transparent conductive layer 107 and the first light-shielding layer 109, and the color filter layer 110 includes a plurality of color filter units 1101, each color filter unit 1101 includes a first filter unit 1102, a second filter unit 1103 and a third filter unit 1104, wherein two adjacent first filter units 1102 are arranged at intervals, two adjacent second filter units 1103 are arranged at intervals, and two adjacent third filter units 1104 are arranged at intervals.

[0049] In the display panel 01 provided in the embodiment of the present application, since the color filter layer 110 and the data line 1021 are both integrated on the first substrate 10, the pixel area between the color filter unit 1101 and the adjacent data line 1021 can be aligned during film formation, with higher alignment accuracy, thereby improving the display color deviation problem caused by the alignment accuracy problem of different substrates when the color filter unit 1101 and the data line 1021 are located on different substrates.

[0050] Furthermore, since the first substrate 10 is also provided with the first light shielding portion 1091, the color filter unit 1101 and the first light shielding portion 1091 can be aligned during film formation, achieving higher alignment accuracy. Furthermore, since two adjacent first filter units 1102 are spaced apart, two adjacent second filter units 1103 are spaced apart, and two adjacent third filter units 1104 are spaced apart, each color filter unit 1101 is independently disposed relative to its adjacent color filter unit 1101. This reduces the integration difficulty of the color filter layer 110 on the first substrate 10 and improves the production yield of the display panel 01. Optionally, the spacing between two adjacent color filter units 1101 is 4-5 microns to reduce the difficulty of planarizing the color filter layer 110.

[0051] In some embodiments of the present application, the first substrate 10 of the display area AA includes a composite functional layer M1, a first gate N111 insulating layer M2, a first metal layer 102, a first interlayer dielectric layer M3, a second interlayer dielectric layer M4, a second gate metal layer 111, a second gate insulating layer M5, a metal oxide semiconductor layer 103, a third gate insulating layer M6, a third gate metal layer 114, a third interlayer dielectric layer M7, a first blocking insulating layer M8, a first transparent conductive layer 107, and a second blocking insulating layer M9. , a color filter layer 110, a first flat layer M10, a first passivation layer M11, a first light-shielding layer 109, a second passivation layer M12, a second transparent conductive layer 108, a second flat layer M13, a third flat layer M14, a third transparent conductive layer 112, a third passivation layer M15, and a fourth transparent conductive layer 113, wherein at least one first insulating layer 104 includes a first interlayer dielectric layer M3, a second interlayer dielectric layer M4, and a second gate insulating layer M5, and a first via hole H1 penetrates the second gate insulating layer M5, the second interlayer dielectric layer M4, and the first interlayer dielectric layer M3.

[0052] 8 , an embodiment of the present application provides a display panel 01 . The structure of the display panel 01 provided in FIG8 is the same as or similar to the structure of the display panel 01 provided in FIG5 , and the same parts will not be described in detail in this embodiment.

[0053] In some embodiments of the present application, the display panel 01 also has a non-display area NAA, the first substrate 10 of the non-display area NAA includes a first gate metal layer N11, the first gate metal layer N11 includes multiple first gates N111, and the first gate N111 is used to set the gate of the low-temperature polycrystalline silicon thin film transistor in the non-display area NAA; the first gate metal layer N11 and the first metal layer 102 are set in different layers.

[0054] In some embodiments of the present application, the first metal layer 102 is disposed on a side of the first interlayer dielectric layer M3 facing away from the first gate metal layer N11. The first substrate 10 in the display area AA further includes at least one first insulating layer 104 disposed between the first metal layer 102 and the metal oxide semiconductor layer 103. The source region 1033 is electrically connected to the data line 1021 via a first via H1 penetrating the at least one first insulating layer 104. The at least one first insulating layer 104 includes a second interlayer dielectric layer M4 and a second gate insulating layer M5, and the first via H1 penetrates the second gate insulating layer M5 and the second interlayer dielectric layer M4.

[0055] In the display panel 01 provided in the embodiment of the present application, since the first metal layer 102 is arranged on the side of the first interlayer dielectric layer M3 away from the first gate metal layer N11, the first metal layer 102 can be made to have a larger distance from the first substrate 101 and a smaller distance from the metal oxide semiconductor layer 103 relative to the first gate metal layer N11, thereby reducing the number of film layers between the metal oxide semiconductor layer 103 and the first metal layer 102, that is, reducing the number of film layers of at least one first insulating layer 104, thereby reducing the difficulty of opening the first via H1.

[0056] 9 , an embodiment of the present application provides a display panel 01 . The structure of the display panel 01 provided in FIG. 9 is the same as or similar to the structure of the display panel 01 provided in FIG. 5 , and the same parts will not be described in detail in this embodiment.

[0057] In some embodiments of the present application, the first substrate 10 of the display area AA further includes: at least one first insulating layer 104, arranged between the first metal layer 102 and the metal oxide semiconductor layer 103; a second metal layer 105, arranged on the side of the metal oxide semiconductor layer 103 facing away from the first substrate 101; at least one second insulating layer 106, arranged between the metal oxide semiconductor layer 103 and the second metal layer 105; wherein the second metal layer 105 includes a plurality of bridging portions 1051, the bridging portions 1051 are electrically connected to the source region 1033 through second vias H2 passing through at least one second insulating layer 106, and the bridging portions 1051 are electrically connected to the data line 1021 through third vias H3 passing through at least one second insulating layer 106 and at least one first insulating layer 104.

[0058] In the display panel 01 provided in the embodiment of the present application, the provision of the bridge portion 1051 can effectively reduce the resistance of the data line 1021 and improve the transmission efficiency of the data signal.

[0059] In some embodiments of the present application, the display panel 01 further has a non-display area NAA. The first substrate 10 of the non-display area NAA includes: a first gate metal layer N11 including a plurality of first gate electrodes N111, the first gate electrodes N111 serving as gate electrodes of low-temperature polysilicon thin-film transistors disposed in the non-display area NAA; wherein the first gate metal layer N11 is disposed on the same layer and made of the same material as the first metal layer 102. At least one first insulating layer 104 includes a first interlayer dielectric layer M3, a second interlayer dielectric layer M4, and a second gate insulating layer M5; at least one second insulating layer 106 includes a third gate insulating layer M6 and a third interlayer dielectric layer M7; a second via H2 penetrates the third gate insulating layer M6 and the third interlayer dielectric layer M7; and a third via H3 penetrates the third gate insulating layer M6, the third interlayer dielectric layer M7, the second gate insulating layer M5, the second interlayer dielectric layer M4, and the first interlayer dielectric layer M3.

[0060] 10 , an embodiment of the present application provides a display panel 01 . The structure of the display panel 01 provided in FIG10 is the same as or similar to the structure of the display panel 01 provided in FIG9 , and the same parts will not be described in detail in this embodiment.

[0061] In some embodiments of the present application, the first metal layer 102 is arranged on the side of the first interlayer dielectric layer M3 away from the first gate metal layer N11, and the first substrate 10 of the display area AA also includes: at least one first insulating layer 104, arranged between the first metal layer 102 and the metal oxide semiconductor layer 103; a second metal layer 105, arranged on the side of the metal oxide semiconductor layer 103 away from the first substrate 101; at least one second insulating layer 106, arranged between the metal oxide semiconductor layer 103 and the second metal layer 105; wherein the second metal layer 105 includes a plurality of bridging portions 1051, the bridging portions 1051 are electrically connected to the source region 1033 through a second via H2 passing through at least one second insulating layer 106, and the bridging portions 1051 are electrically connected to the data line 1021 through a third via H3 passing through at least one second insulating layer 106 and at least one first insulating layer 104.

[0062] In the display panel 01 provided in the embodiment of the present application, since the first metal layer 102 is arranged on the side of the first interlayer dielectric layer M3 away from the first gate metal layer N11, the first metal layer 102 can be made to have a larger distance from the first substrate 101 and a smaller distance from the metal oxide semiconductor layer 103 relative to the first gate metal layer N11, thereby reducing the number of film layers between the metal oxide semiconductor layer 103 and the first metal layer 102, that is, reducing the number of film layers of at least one first insulating layer 104, thereby reducing the difficulty of opening the third via H3.

[0063] The present application further provides a display device, which includes a housing and a display panel 01 according to any one of the above embodiments. The housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0064] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The above is a detailed introduction to the technical solutions provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, wherein: The display panel has a display area, and the display panel includes a first substrate. The first substrate of the display area includes: a first substrate; A first metal layer is disposed on one side of the first substrate, the first metal layer comprising a plurality of data lines that are sequentially spaced apart; a metal oxide semiconductor layer, disposed on a side of the first metal layer away from the first substrate, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a channel and a source region and a drain region located on both sides of the channel, the source region being connected to the data line; The orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projection of the data line on the first substrate.

2. The display panel according to claim 1, wherein: The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; The source region is connected to the data line through a first via hole penetrating the at least one first insulating layer.

3. The display panel according to claim 1, wherein: The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; A second metal layer is disposed on a side of the metal oxide semiconductor layer away from the first substrate; at least one second insulating layer disposed between the metal oxide semiconductor layer and the second metal layer; The second metal layer includes a plurality of bridge portions, the bridge portions are connected to the source region through second via holes penetrating the at least one second insulating layer, and the bridge portions are connected to the data lines through third via holes penetrating the at least one second insulating layer and the at least one first insulating layer.

4. The display panel according to claim 2 or 3, wherein: The display panel further has a non-display area, and the first substrate of the non-display area includes: A first gate metal layer, comprising a plurality of first gates, wherein the first gates are used to be gates of low-temperature polysilicon thin film transistors disposed in the non-display area; Wherein, the first gate metal layer is arranged in the same layer as the first metal layer.

5. The display panel according to claim 4, wherein: The first gate metal layer is made of the same material as the first metal layer.

6. The display panel according to claim 1, wherein: The first substrate of the display area further comprises: A first transparent conductive layer is arranged on a side of the metal oxide semiconductor layer away from the first substrate, the first transparent conductive layer comprises a plurality of first transparent conductive portions, the first transparent conductive portions comprise a first portion and a second portion, and the first portion is connected to the drain region through a via hole; The second transparent conductive layer is arranged on a side of the first transparent conductive layer away from the first substrate, the second transparent conductive layer includes a plurality of second transparent conductive parts, and the second transparent conductive parts are connected to the second part through vias.

7. The display panel according to claim 6, wherein: The second portion is located between two adjacent data lines, and the distances between the second portion and the two adjacent data lines are different.

8. The display panel according to claim 7, wherein: The first transparent conductive portion further includes a connecting portion connecting the first portion and the second portion, and the connecting portion is inclined relative to the data line.

9. The display panel according to claim 8, wherein: An angle between the connecting portion and the data line is an acute angle, and the angle is less than or equal to 20°.

10. The display panel according to claim 7, wherein: The first substrate of the display area further comprises: A first light-shielding layer is arranged between the first transparent conductive layer and the second transparent conductive layer, the first light-shielding layer includes a plurality of first light-shielding portions, the first light-shielding portion includes a first sub-light-shielding portion, a second sub-light-shielding portion and an avoiding portion, the first sub-light-shielding portion is arranged corresponding to the source region, the second sub-light-shielding portion is arranged corresponding to the drain region, and the avoiding portion connects the first sub-light-shielding portion and the second sub-light-shielding portion.

11. The display panel according to claim 10, wherein: The avoidance portion is formed with a notch on one side close to the second portion.

12. The display panel according to claim 10, wherein: The display panel further includes a second substrate and a liquid crystal layer, wherein the second substrate is arranged opposite to the first substrate, and the liquid crystal layer is arranged between the first substrate and the second substrate: wherein the second substrate includes: a second substrate; A second light shielding layer is disposed on one side of the second substrate; The second light-shielding layer includes a plurality of second light-shielding portions, and an extending direction of the second light-shielding portions is different from an extending direction of the first light-shielding portions.

13. The display panel according to claim 10, wherein: The first substrate of the display area further comprises: The color filter layer is arranged between the first transparent conductive layer and the first light shielding layer. The color filter layer includes a plurality of color filter units. Each color filter unit includes a first filter unit, a second filter unit and a third filter unit.

14. The display panel according to claim 13, wherein: Two adjacent first filter units are arranged at intervals, two adjacent second filter units are arranged at intervals, and two adjacent third filter units are arranged at intervals.

15. The display panel according to claim 1, wherein: The display panel further has a non-display area, and the first substrate of the non-display area includes: A first gate metal layer, comprising a plurality of first gates, wherein the first gates are used to be gates of low-temperature polysilicon thin film transistors disposed in the non-display area; Wherein, the first gate metal layer and the first metal layer are arranged in different layers.

16. The display panel according to claim 1, wherein: An extending direction of the transparent active layer is the same as an extending direction of the data line.

17. The display panel according to claim 16, wherein: The transparent active layer and the data lines are both in the shape of long strips.

18. A display device, wherein: The display device comprises a housing and a display panel, wherein the housing has a containing space, and the display panel is arranged in the containing space; wherein the display panel has a display area, and the display panel comprises a first substrate, and the first substrate of the display area comprises: a first substrate; A first metal layer is disposed on one side of the first substrate, the first metal layer comprising a plurality of data lines that are sequentially spaced apart; a metal oxide semiconductor layer, disposed on a side of the first metal layer away from the first substrate, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a channel and a source region and a drain region located on both sides of the channel, the source region being connected to the data line; The orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projection of the data line on the first substrate.

19. The display device according to claim 18, wherein: The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; The source region is connected to the data line through a first via hole penetrating the at least one first insulating layer.

20. The display device according to claim 18, wherein: The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; A second metal layer is disposed on a side of the metal oxide semiconductor layer away from the first substrate; at least one second insulating layer disposed between the metal oxide semiconductor layer and the second metal layer; The second metal layer includes a plurality of bridge portions, the bridge portions are connected to the source region through second via holes penetrating the at least one second insulating layer, and the bridge portions are connected to the data lines through third via holes penetrating the at least one second insulating layer and the at least one first insulating layer.

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