Semiconductor structure and manufacturing method therefor

Abstract

A semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a first substrate and a semiconductor device located in the first substrate; a plurality of first conductive pads connected to the semiconductor device; a plurality of second conductive pads, at least one first conductive pad and at least one second conductive pad being electrically connected by means of a first conductive interconnection structure extending in a direction perpendicular to the first substrate; and a filling layer surrounding each first conductive pad, the first conductive interconnection structure and each second conductive pad, wherein the first conductive interconnection structure has a surface buried by the filling layer between adjacent second conductive pads. The semiconductor structure is at least beneficial to improving electrical performance.

Description

Semiconductor structure and method for manufacturing the same

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on December 14, 2023, with application number 202311728460.1 and invention name “Semiconductor structure and manufacturing method thereof”, the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0003] With technological advancements, the integration and convergence of semiconductor packaging are gradually increasing. Electronic devices are moving towards miniaturization, high speed, high reliability, low cost, and low power consumption. HBM (High Bandwidth Memory) products are in short supply. To achieve high-capacity HBM, wafer-on-wafer (WoW) or chip-on-chip (CoC) packaging technologies are required.

[0004] However, in semiconductor packaging technology, secondary processing is required after wafer-level testing. To ensure a flat bonding interface, it is often necessary to deposit thick dielectric layers multiple times and perform chemical mechanical polishing to achieve the goal of flatness. On this basis, the dielectric layer is subjected to deep hole etching or Damascus process. The process flow is relatively complicated, and deep hole etching can easily lead to poor metal contact caused by excessive by-products.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0007] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a semiconductor structure, including: a first substrate and a semiconductor device located in the first substrate; a plurality of first conductive pads, connecting the semiconductor devices; a plurality of second conductive pads, at least one of the first conductive pads and at least one of the second conductive pads being electrically connected via a first conductive interconnect structure extending in a direction perpendicular to the first substrate; a filling layer, the filling layer filling the periphery of each of the first conductive pads, the first conductive interconnect structure and the second conductive pads; wherein the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

[0008] In some embodiments, the filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer covers the first conductive pad, the third dielectric layer covers the sidewall of the second conductive pad, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the first preset height difference ranges from 0nm to 50nm.

[0009] In some embodiments, the first dielectric layer and the second dielectric layer constitute a sub-filling layer; the filling layer further includes a fourth dielectric layer, and the fourth dielectric layer is located between the sub-filling layer and the first conductive interconnect structure.

[0010] In some embodiments, at least one of the second conductive pads is located on a top surface of the second dielectric layer.

[0011] In some embodiments, the second conductive pad located on the top surface of the second dielectric layer is not electrically connected to the first conductive pad, and the second conductive pad is in direct contact with the top surface of the second dielectric layer.

[0012] In some embodiments, the first conductive pad electrically contacting the first conductive interconnect structure includes a first portion and a second portion, wherein the second portion is in direct contact with the first conductive interconnect structure, the first portion is not in direct contact with the first conductive interconnect structure, and a surface of the second portion in direct contact with the first conductive interconnect structure has a portion lower than a surface of the first portion.

[0013] In some embodiments, orthographic projections of at least two of the first conductive pads on the first substrate overlap with an orthographic projection of one of the first conductive interconnect structures on the first substrate.

[0014] In some embodiments, the filling layer includes a first bonding layer, the second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the second predetermined height difference ranges from 0nm to 50nm.

[0015] In some embodiments, the semiconductor structure further includes: a second bonding layer and a third conductive pad located in the second bonding layer, the second bonding layer is directly bonded to the first bonding layer, and the third conductive pad is directly bonded to the second conductive pad.

[0016] In some embodiments, the semiconductor structure further includes an isolation layer located in the filling layer between adjacent first conducting pads.

[0017] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: providing a first substrate, wherein the first substrate has a semiconductor device; forming a plurality of first conductive pads connecting the semiconductor devices; forming a first opening, wherein the first opening exposes the surface of at least one of the first conductive pads; forming a first conductive interconnect structure filling the first opening; forming a plurality of second conductive pads on the first conductive interconnect structure, so that at least one first conductive pad and at least one second conductive pad are electrically connected through the first conductive interconnect structure; wherein a filling layer is formed on the periphery of each of the first conductive pads, each of the second conductive pads and the first conductive interconnect structure, and the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

[0018] In some embodiments, the filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first conductive pad is formed in the first dielectric layer, the second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed before forming the first opening. The first opening is formed in the first dielectric layer and the second dielectric layer. After forming the first conductive interconnect structure in the first opening, the surface of the first conductive interconnect structure is planarized so that a first preset height difference exists between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure. The first preset height difference ranges from 0 nm to 50 nm. After forming the first conductive interconnect structure, the third dielectric layer is formed, and the second conductive pad electrically connected to the first conductive interconnect structure is formed in the third dielectric layer.

[0019] In some embodiments, the filling layer further includes a fourth dielectric layer, which is formed after forming the first opening and before forming the first conductive interconnect structure, such that the fourth dielectric layer is located between the first conductive interconnect structure and the first and second dielectric layers.

[0020] In some embodiments, the step of forming the fourth dielectric layer includes: forming an initial fourth dielectric layer, the initial fourth dielectric layer conformally covering the surface of the first opening and the top surface of the second dielectric layer, and etching back the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the top surface of the second dielectric layer and the bottom surface of the first opening, with the remaining initial fourth dielectric layer being the fourth dielectric layer; wherein, in the step of etching back the initial fourth dielectric layer, a portion of the thickness of the first conductive pad exposed by the first opening is etched away.

[0021] In some embodiments, the filling layer also includes a first bonding layer, the second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the second predetermined height difference ranges from 0nm to 50nm; after forming the second conductive pad, it also includes forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pad.

[0022] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0023] The electrical signal in the semiconductor device is transmitted to other electrical devices via the first conductive pad, the first conductive interconnect structure, and the second conductive pad, or the electrical signal in other electrical devices is transmitted to the semiconductor device via the second conductive pad, the first conductive interconnect structure, and the first conductive pad. Therefore, the first conductive pad is primarily used to achieve electrical connection with the semiconductor device, the second conductive pad is primarily used to achieve electrical connection with other electrical devices, and the first conductive interconnect structure is primarily used to achieve electrical connection between the first conductive pad and the second conductive pad.

[0024] On this basis, the first conductive interconnect structure is provided with a surface buried by the filling layer of the adjacent second conductive pad. In other words, the orthographic projections of at least two second conductive pads on the first substrate are designed to overlap with the orthographic projection of one first conductive interconnect structure on the first substrate, so that one first conductive interconnect structure is in electrical contact with at least two second conductive pads. On the one hand, this is beneficial to improving the transmission efficiency of the electrical signal among the first conductive pad, the first conductive interconnect structure, and the second conductive pad. On the other hand, in the horizontal direction, the length of the first conductive interconnect structure is greater than the length of the second conductive pad, which is beneficial to improving the alignment accuracy between the second conductive pad and the first conductive interconnect structure, thereby facilitating an increase in the contact area between the second conductive pad and the first conductive interconnect structure to reduce the contact resistance between the two, thereby further improving the transmission efficiency of the electrical signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] FIG1 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] FIG2 is a schematic cross-sectional view of a first conductive interconnect structure and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0028] FIG3 is another schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure;

[0029] FIG4 is a schematic diagram of another cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0030] FIG5 is a schematic diagram of another cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0031] FIG6 is a schematic cross-sectional view of a second conductive pad and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0032] FIG7 is a schematic diagram of another cross-sectional structure of a second conductive pad and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0033] FIG8 is a schematic diagram of another cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0034] FIG9 is a schematic cross-sectional view of each step in a method for manufacturing a semiconductor structure;

[0035] FIG10 is a schematic flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

[0036] 11 to 27 are schematic cross-sectional structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] As known from the background art, the electrical performance of semiconductor structures needs to be improved.

[0038] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein a first conductive pad is primarily used to electrically connect to a semiconductor device, a second conductive pad is primarily used to electrically connect to other electrical devices, and a first conductive interconnect structure is primarily used to electrically connect the first conductive pad and the second conductive pad. On this basis, the first conductive interconnect structure has a surface buried by a filling layer of an adjacent second conductive pad. In other words, the orthographic projections of at least two second conductive pads on a first substrate overlap with the orthographic projection of a first conductive interconnect structure on the first substrate, so that one first conductive interconnect structure is in electrical contact with at least two second conductive pads. This, on the one hand, is advantageously used to improve the transmission efficiency of electrical signals among the first conductive pad, the first conductive interconnect structure, and the second conductive pad. On the other hand, in the horizontal direction, the length of the first conductive interconnect structure is greater than the length of the second conductive pad, which is advantageously used to improve the alignment accuracy between the second conductive pad and the first conductive interconnect structure, thereby facilitating an increase in the contact area between the second conductive pad and the first conductive interconnect structure to reduce the contact resistance therebetween, thereby further improving the transmission efficiency of electrical signals.

[0039] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0040] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, for ease of description and to clearly illustrate the characteristics of the semiconductor structure, Figures 1 to 8 in an embodiment of the present disclosure are schematic diagrams of partial structures of the semiconductor structure.

[0041] Referring to FIG1 , FIG1 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure includes: a first substrate 100 and a semiconductor device (not shown) located in the first substrate 100; a plurality of first conductive pads 101 connecting the semiconductor devices; a plurality of second conductive pads 105, wherein at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected via a first conductive interconnect structure 103 extending in a direction X perpendicular to the first substrate 100; and a filling layer 142, wherein the filling layer 142 fills the periphery of each first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105. The first conductive interconnect structure 103 has a surface 103b buried by the filling layer 142 between adjacent second conductive pads 105. In some cases, electrical signals in the semiconductor device are transmitted to other electrical devices via the first conductive pads 101, the first conductive interconnect structure 103, and the second conductive pad 105, or electrical signals in other electrical devices are transmitted to the semiconductor device via the second conductive pads 105, the first conductive interconnect structure 103, and the first conductive pad 101. Based on this, the first conductive pad 101 is mainly used to achieve electrical connection with the semiconductor device, the second conductive pad 105 is mainly used to achieve electrical connection with other electrical devices, and the first conductive interconnect structure 103 is mainly used to achieve electrical connection between the first conductive pad 101 and the second conductive pad 105.

[0042] In addition, the first conductive interconnect structure 103 has a surface 103b buried by the filling layer 142 between adjacent second conductive pads 105, which is conducive to overlapping the orthographic projections of at least two second conductive pads 105 on the first substrate 100 with the orthographic projection of the same first conductive interconnect structure 103 on the first substrate 100, so that one first conductive interconnect structure 103 is in electrical contact with at least two second conductive pads 105. On this basis, a first conductive interconnect structure 103 is designed to simultaneously connect at least two adjacent second conductive pads 105. On the one hand, such a design is conducive to improving the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105. On the other hand, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive pad 105, which is conducive to improving the alignment accuracy between the second conductive pad 105 and the first conductive interconnect structure 103, and is more conducive to the electrical contact between the entire single second conductive pad 105 and the first conductive interconnect structure 103, thereby facilitating the increase of the contact area between the second conductive pad 105 and the first conductive interconnect structure 103 to reduce the contact resistance between the two, thereby further improving the transmission efficiency of electrical signals.

[0043] It should be noted that, referring to FIG1 , the direction perpendicular to the first substrate 100 is the vertical direction X. In some cases, the vertical direction X may also be the direction from the first conductive pad 101 to the second conductive pad 105; the horizontal direction Y may be perpendicular to the vertical direction X. Furthermore, FIG1 illustrates an example in which one first conductive interconnect structure 103 is in electrical contact with three second conductive pads 105, two of the three second conductive pads 105 are in entirety in electrical contact with the first conductive interconnect structure 103, and a portion of the remaining second conductive pad 105 is in electrical contact with the first conductive interconnect structure 103. In practical applications, firstly, for any second conductive pad 105 electrically contacting the first conductive interconnect structure 103, there is no limit on the contact area between the second conductive pad 105 and the first conductive interconnect structure 103. That is, the entire area of ​​the second conductive pad 105 can be electrically contacted with the first conductive interconnect structure 103, or a partial area of ​​the second conductive pad 105 can be electrically contacted with the first conductive interconnect structure 103. Secondly, there is no limit on the number of second conductive pads 105 electrically contacting the same first conductive interconnect structure 103; it only needs to be at least two.

[0044] In some embodiments, referring to FIG1 , the semiconductor structure may further include an isolation layer 151, at least a portion of which is located in the filling layer 142 between adjacent first conductive pads 101. This facilitates improving the insulation between adjacent first conductive pads 101 by utilizing the isolation layer 151, which has a lower dielectric constant than the filling layer 142, thereby preventing crosstalk between signals on adjacent first conductive pads 101.

[0045] In some embodiments, the isolation layer 151 may be an air gap.

[0046] In some embodiments, referring to Figures 1 and 2, the filling layer 142 includes a first dielectric layer 122, a second dielectric layer 132, and a third dielectric layer 124. The first dielectric layer 122 covers the first conductive pad 101, and the third dielectric layer 124 at least wraps the sidewall of the second conductive pad 105. The second dielectric layer 132 is located between the first dielectric layer 122 and the third dielectric layer 124. A first predetermined height difference H1 is defined between a top surface 132a of the second dielectric layer 132 and a top surface 103a of the first conductive interconnect structure 103. The first predetermined height difference H1 ranges from 0 nm to 50 nm.

[0047] 2 is a schematic cross-sectional view of a first conductive interconnect structure and a filling layer in a semiconductor structure provided by an embodiment of the present disclosure. In some cases, referring to FIG1 , the first predetermined height difference H1 can be 0 nm, that is, the top surface 132 a of the second dielectric layer 132 is flush with the top surface 103 a of the first conductive interconnect structure 103; in other cases, referring to FIG2 , the top surface 103 a of the first conductive interconnect structure 103 is a concave surface that is concave toward the first substrate 100 (refer to FIG1 ), in which case the first predetermined height difference H1 is greater than 0 and less than or equal to 50 nm; in other cases, the top surface of the first conductive interconnect structure can also be a convex surface that is convex toward the direction away from the first substrate, in which case the first predetermined height difference H1 is greater than 0 and less than or equal to 50 nm.

[0048] It should be noted that, in one embodiment of the present disclosure, only a first preset height difference H1 is defined between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103. However, based on the first substrate 100, there is no restriction on which of the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103 is higher, and the difference can be adjusted according to actual conditions.

[0049] 2 , a first predetermined height difference H1 between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103 is defined as the maximum vertical distance between each point on the top surface 132a of the second dielectric layer 132 and each point on the top surface 103a of the first conductive interconnect structure 103 along the vertical direction X. Furthermore, the surface 103b of the first conductive interconnect structure 103 that is buried by the filling layer 142 between adjacent second conductive pads 105 is a portion of the top surface 103a of the first conductive interconnect structure 103.

[0050] In some embodiments, referring to FIG1 , filling layer 142 includes a first dielectric layer 122 covering first conductive pad 101, a third dielectric layer 124 covering the sidewalls of second conductive pad 105, and a second dielectric layer 132 located between first dielectric layer 122 and third dielectric layer 124. Accordingly, isolation layer 151 is located within first dielectric layer 122. In other words, first dielectric layer 122 includes isolation layer 151. It should be noted that in practical applications, the isolation layer may also be located within the second dielectric layer.

[0051] In some embodiments, referring to FIG. 1 , the first dielectric layer 122 and the second dielectric layer 132 constitute a sub-filling layer 102 ; the filling layer 142 may further include a fourth dielectric layer 106 located between the sub-filling layer 102 and the first conductive interconnect structure 103 .

[0052] In some cases, in the step of forming the first conductive interconnect structure 103, it is necessary to form a first opening in the sub-filling layer 102 to accommodate the first conductive interconnect structure 103, and use the fourth dielectric layer 106 to protect the sidewalls of the first opening to prevent the sub-filling layer 102 constituting the sidewalls of the first opening from being etched, so that the sidewalls of the first opening have a relatively flat interface, which facilitates the subsequent formation of the first conductive interconnect structure 103 with regular dimensions.

[0053] In some embodiments, referring to FIG3 , which is another schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure, at least one second conductive pad 105 is located on the top surface 132a of the second dielectric layer 132. In some examples, the at least one second conductive pad 105 may be in contact with the top surface 132a of the second dielectric layer 132; in other embodiments, the at least one second conductive pad 105 may not be in direct contact with the top surface 132a of the second dielectric layer 132.

[0054] It should be noted that the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 will not be electrically connected to the first conductive pad 101. Furthermore, the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 may not be electrically connected to the semiconductor device. In other words, no electrical signal may be transmitted on the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132.

[0055] In this case, on the one hand, if an external film structure is bonded to the second conductive pad 105, the external film structure contains other conductive pads, and signals are transmitted between some of the other conductive pads and the second conductive pad 105 that is in electrical contact with the first conductive interconnect structure 103, but other conductive pads still exist in the external film structure. Based on this, designing the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132 is conducive to balancing the distribution density of the conductive pads in the external film structure with the distribution density of the second conductive pads 105 in the third dielectric layer 124, so that when the second conductive pad 105 and the external film structure are bonded to each other, the two bonding interfaces between the two are affected by thermal expansion to a similar degree, thereby facilitating improving the bonding strength between the second conductive pad 105 and the external film structure, thereby improving the contact performance between the second conductive pad 105 and the external film structure.

[0056] On the other hand, if an external film structure is bonded to the second conductive pad 105, the thermal expansion coefficient of the external film structure itself differs from the thermal expansion coefficient of the second conductive pad 105 and the third dielectric layer 124 as a whole. By designing the second conductive pad 105 in contact with the top surface 132a of the second dielectric layer 132, it is also beneficial to adjust the distribution density of the second conductive pad 105 in the third dielectric layer 124 so that when the second conductive pad 105 and the external film structure are bonded to each other, the two bonding interfaces between the two are affected by thermal expansion to a similar degree, thereby improving the bonding strength between the second conductive pad 105 and the external film structure, thereby improving the contact performance between the second conductive pad 105 and the external film structure.

[0057] In some embodiments, referring to Figure 1, the first conductive pad 101 electrically contacting the first conductive interconnect structure 103 includes a first portion 111 and a second portion 121, the second portion 121 is in direct contact with the first conductive interconnect structure 103, the first portion 111 is not in direct contact with the first conductive interconnect structure 103, and a surface of the second portion 121 in direct contact with the first conductive interconnect structure 103 has a portion lower than the surface of the first portion 111.

[0058] In some cases, with the top surface 100 a of the first substrate 100 as a reference, the top surface 121 a of the second portion 121 is lower than the top surface 111 a of the first portion 111 .

[0059] The corresponding relationship between the first conductive pad 101 and the first conductive interconnect structure 103 includes at least the following two embodiments:

[0060] 1 or 3 , only the orthographic projection of one first conductive pad 101 on the first substrate 100 overlaps with the orthographic projection of one first conductive interconnect structure 103 on the first substrate 100 , that is, the first conductive pad 101 and the first conductive interconnect structure 103 are in a one-to-one relationship.

[0061] It should be noted that both FIG1 and FIG3 illustrate an example in which the length of the first conductive pad 101 along the horizontal direction Y is greater than the length of the first conductive pad 101 in electrical contact with the first conductive interconnect structure 103. In practical applications, when the first conductive pad 101 and the first conductive interconnect structure 103 have a one-to-one relationship, there is no restriction on the length relationship between the first conductive pad 101 and the first conductive interconnect structure 103 along the horizontal direction Y.

[0062] In some cases, when the first conductive pad 101 and the first conductive interconnect structure 103 are in a one-to-one relationship, the first conductive pad 101 may be a wiring layer, which may be located in a peripheral region of the semiconductor structure. Referring to FIG3 , the first conductive pad 101 includes a first wiring layer 131 and a second wiring layer 141. Along a length direction Y, a first length L1 of the first wiring layer 131 is greater than a second length L2 of the second wiring layer 141.

[0063] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be regarded as the same layer structure, that is, they are both located in the film layer interval where the first conductive pad 101 is located, but the first wiring layer 131 and the second wiring layer 141 can be insulated from each other to achieve electrical connection between different conductive structures. In addition, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive pad 101 can also include a third wiring layer, a fourth wiring layer or a fifth wiring layer, etc. Moreover, the first wiring layer 131 and the second wiring layer 141 can be an integrally formed structure, that is, the first wiring layer 131 and the second wiring layer 141 have different functions, such as being electrically connected to different semiconductor devices, and the film layer structure and material are the same. The first wiring layer 131 and the second wiring layer 141 are drawn using the same filling method in Figure 3.

[0064] In some embodiments, continuing to refer to Figure 3, along the horizontal direction Y, an isolation layer 151 may further be provided between the first wiring layer 131 and the second wiring layer 141. For example, the first dielectric layer 122 has an isolation layer 151, which is beneficial to improving the insulation effect between the first wiring layer 131 and the second wiring layer 141 through the isolation layer 151.

[0065] In some embodiments, referring to Figure 4, Figure 4 is another cross-sectional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. In some embodiments, the first conductive pad 101 includes a blocking layer 161 and a conductive layer 171. Along the vertical direction X, the conductive layer 171 has a first side and a second side relative to each other, and the blocking layer 161 covers at least the first side and the second side.

[0066] It can be understood that the blocking layer 161 is used to block the diffusion and migration of conductive ions in the conductive layer 171 into the sub-filling layer 102, thereby preventing the conductive layer 171 from reducing its own conductivity due to the diffusion and migration of conductive ions, and preventing the sub-filling layer 102 from reducing its own insulation performance due to the migration of conductive ions, which is beneficial to ensuring the higher conductivity of the conductive layer 171 itself and the higher insulation performance of the sub-filling layer 102 itself.

[0067] 3 and 4 , both the first wiring layer 131 and the second wiring layer 141 may include a barrier layer 161 and a conductive layer 171. In practical applications, the first conductive pad 101 may also include only the conductive layer 171.

[0068] In some embodiments, the barrier layer 161 is made of at least one of titanium and titanium nitride, and the conductive layer 171 is made of aluminum. Thus, the barrier layer 161 is helpful in preventing aluminum ions from electromigration.

[0069] In other embodiments, referring to FIG. 5 , which is a schematic cross-sectional view of another embodiment of a semiconductor structure according to the present disclosure, the orthographic projections of at least two first conductive pads 101 on the first substrate 100 overlap with the orthographic projection of a first conductive interconnect structure 103 on the first substrate 100. This allows one first conductive interconnect structure 103 to be in electrical contact with at least two first conductive pads 101. This improves the transmission efficiency of electrical signals among the first conductive pads 101, the first conductive interconnect structure 103, and the second conductive pad 105. Furthermore, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single first conductive pad 101, which improves the alignment accuracy between the first conductive pad 101 and the first conductive interconnect structure 103 and further facilitates electrical contact between the entire first conductive pad 101 and the first conductive interconnect structure 103. This increases the contact area between the first conductive pad 101 and the first conductive interconnect structure 103, thereby reducing the contact resistance therebetween and further improving the transmission efficiency of electrical signals.

[0070] In some other embodiments, one first conductive pad 101 is connected to one first conductive interconnect structure 103 , so that each first conductive pad 101 forms a separate connection path with the corresponding second conductive pad 105 .

[0071] In some cases, when the first conductive pad 101 and the first conductive interconnect structure 103 are many-to-one, the first conductive pad 101 can be a signal lead-out layer, for example, the signal lead-out layer can be an I / O signal lead-out layer or a power signal lead-out layer or other types of signal lead-out layers.

[0072] In some embodiments, in combination with reference Figures 1 and 6, or in combination with reference Figures 1 and 7, the filling layer 142 may further include a first bonding layer 134, the second conductive pad 105 has a top surface 105a exposed to the first bonding layer 134, and there is a second predetermined height difference H2 between the top surface 105a of the second conductive pad 105 exposed to the first bonding layer 134 and the top surface 134a of the first bonding layer 134, and the second predetermined height difference H2 ranges from 0nm to 50nm.

[0073] In some cases, the third dielectric layer 124 and the first bonding layer 134 together constitute the dielectric layer 104 , and the second conductive pad 105 penetrates the dielectric layer 104 along the vertical direction X.

[0074] In some cases, referring to the second conductive pad D in Figure 1 or 7, the second predetermined height difference H2 (refer to Figure 6) can be 0nm, that is, the top surface 134a of the first bonding layer 134 is flush with the top surface 105d of the second conductive pad D or the top surface 105a of the second conductive pad 105 in Figure 1; in other cases, referring to Figure 7, the top surface 105e of the second conductive pad E is a concave surface that is recessed in the direction toward the first substrate 100 (refer to Figure 1). In this case, the second predetermined height difference H2 (refer to Figure 6) is greater than 0 and less than or equal to 50nm; in some other cases, referring to the second conductive pad F in Figure 6 or 7, the top surface 105a of the second conductive pad 105 is a convex surface that is protruded in the direction away from the first substrate 100 (refer to Figure 1). In this case, the second predetermined height difference H2 (refer to Figure 6) is greater than 0 and less than or equal to 50nm.

[0075] It should be noted that FIG6 is a schematic cross-sectional view of a second conductive pad and a filling layer in a semiconductor structure according to an embodiment of the present disclosure; FIG7 is a schematic cross-sectional view of another cross-sectional view of a second conductive pad and a filling layer in a semiconductor structure according to an embodiment of the present disclosure. Furthermore, to distinguish the three different second conductive pads 105 in FIG7 , the three different second conductive pads 105 are labeled D, E, and F, respectively, and the top surfaces 105a of the three different second conductive pads 105 are labeled 105d, 105e, and 105f, respectively.

[0076] It should be noted that, in one embodiment of the present disclosure, only a second predetermined height difference H2 is limited between the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105. However, based on the first substrate 100, there is no restriction on which of the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105 is higher, and the difference can be adjusted according to actual conditions.

[0077] In addition, the second preset height difference H2 between the top surface 134a of the first bonding layer 134 and the top surface 105a of the second conductive pad 105 is defined in Figure 6 as: along the vertical direction X, the maximum vertical distance between each point in the top surface 134a of the first bonding layer 134 and each point in the top surface 105a of the second conductive pad 105.

[0078] It is worth noting that FIG7 only illustrates the different morphologies of the top surface 105 a of the second conductive pad 105 . The morphologies of the top surfaces 105 a of different second conductive pads 105 in the same semiconductor structure may be the same or different and may be adjusted according to actual conditions.

[0079] In some cases, when the first conductive pad 101 is an I / O signal lead-out layer, the spacing between adjacent first conductive pads 101 in the horizontal direction Y is small and the length of the first conductive pad 101 itself is small, so that the spacing between corresponding adjacent second conductive pads 105 is also small and the length of the second conductive pad 105 itself is also small. Based on this, by adjusting the process parameters for preparing the second conductive pad 105, the top surface 105a of the second conductive pad 105 is designed to be similar to that shown in FIG6, which is a convex surface protruding in the direction away from the first substrate 100 (refer to FIG1). This is beneficial for improving the alignment accuracy of the second conductive pad 105 when it is subsequently bonded to the conductive pad in the external film layer structure when the length of the second conductive pad 105 itself in the horizontal direction Y is small, and increasing the contact area between the second conductive pad 105 and the conductive pad in the external film layer structure, thereby improving the transmission efficiency of electrical signals between the two.

[0080] In some embodiments, referring to FIG4 , the filling layer 142 includes a first dielectric layer 122 and a second dielectric layer 132 , the first dielectric layer 122 and the second dielectric layer 132 forming a sub-filling layer 102 , the sub-filling layer 102 having a first opening wrapping the first conductive interconnect structure 103 ; the first conductive interconnect structure 103 includes: a first diffusion barrier layer 113 conformally covering the sidewalls and bottom surface of the first opening; a first seed layer 123 conformally covering the sidewalls and bottom surface of the first diffusion barrier layer 113 ; and a first electroplating layer 133 filling the remaining portion of the first opening.

[0081] It is worth noting that the first diffusion barrier layer 113 is used to prevent the conductive ions in the first seed crystal layer 123 and the first electroplating layer 133 from diffusing and migrating into the sub-filling layer 102, thereby preventing the first seed crystal layer 123 and the first electroplating layer 133 from reducing their own conductivity due to the diffusion and migration of conductive ions, and preventing the sub-filling layer 102 from reducing its own insulation performance due to the migration of conductive ions, which is beneficial to the higher conductivity of the first seed crystal layer 123 and the first electroplating layer 133 themselves and the higher insulation performance of the sub-filling layer 102 itself.

[0082] In some cases, the first diffusion barrier layer 113 is made of at least one of tantalum and tantalum nitride, and the first seed layer 123 and the first electroplating layer 133 are made of copper.

[0083] In some embodiments, with continued reference to FIG4 , the filling layer 142 includes a third dielectric layer 124 having a second opening wrapping the second conductive pad 105; the second conductive pad 105 includes: a second diffusion barrier layer 115 conformally covering the sidewalls and bottom surface of the second opening; a second seed layer 125 conformally covering the sidewalls and bottom surface of the second diffusion barrier layer 115; and a second electroplating layer 135 filling the remaining portion of the second opening.

[0084] It is worth noting that the second diffusion barrier layer 115 is used to prevent the conductive ions in the second seed crystal layer 125 and the second electroplating layer 135 from diffusing and migrating into the third dielectric layer 124, thereby preventing the second seed crystal layer 125 and the second electroplating layer 135 from having their own conductive properties reduced due to the diffusion and migration of the conductive ions, and preventing the third dielectric layer 124 from having its own insulation properties reduced due to the migration of the conductive ions, which is beneficial to the higher conductivity of the second seed crystal layer 125 and the second electroplating layer 135 themselves and the higher insulation properties of the third dielectric layer 124 themselves.

[0085] In some embodiments, the second diffusion barrier layer 115 is made of at least one of tantalum and tantalum nitride, and the second seed layer 125 and the second electroplating layer 135 are made of copper.

[0086] It should be noted that the same filling method is used to draw the first diffusion barrier layer 113 and the second diffusion barrier layer 115 in Figure 4. In practical applications, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 can be the same or different.

[0087] In some embodiments, referring to Figure 8, Figure 8 is another cross-sectional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure may further include: a second bonding layer 234 and a third conductive pad 205 located in the second bonding layer 234, the second bonding layer 234 is directly bonded to the first bonding layer 134, and the third conductive pad 205 is directly bonded to the second conductive pad 105.

[0088] It is worth noting that the second bonding layer 234 and the first bonding layer 134 are directly bonded without using an adhesive, and the third conducting pad 205 and the second conducting pad 105 are directly bonded to achieve electrical connection therebetween.

[0089] In some embodiments, the third conducting pad 205 and the second conducting pad 105 may correspond one to one.

[0090] It should be noted that FIG8 uses the example of the overlap of the orthographic projections of the third conductive pad 205 and the second conductive pad 105 on the first substrate 100. In actual applications, there is no limitation on the size relationship between the orthographic projections of the third conductive pad 205 and the second conductive pad 105 on the first substrate 100 and this can be adjusted according to actual needs. Furthermore, with reference to FIG4 , the film structure within the third conductive pad 205 is similar to that within the second conductive pad 105 and will not be further described here. In other words, the third conductive pad 205 also includes a diffusion barrier layer, a seed layer, and an electroplating layer.

[0091] In some embodiments, continuing to refer to Figure 8, the semiconductor structure may further include: a second conductive interconnect structure 203, at least one third conductive pad 205 electrically contacting the same second conductive interconnect structure 203; a second filling layer 242, the second filling layer 242 filling the periphery and gaps of each third conductive pad 205 and the second conductive interconnect structure 203; a second substrate 200, the second filling layer 242 is located in the second substrate 200.

[0092] It should be noted that FIG8 illustrates an example of three third conductive pads 205 electrically contacting the same second conductive interconnect structure 203. In practical applications, there is no limit on the number of third conductive pads 205 electrically contacting the same second conductive interconnect structure 203 and this number can be adjusted based on actual conditions. Furthermore, the third conductive pads 205 are the other conductive pads in the outer film layer structure described in the aforementioned embodiments.

[0093] In some cases, the first substrate 100, the filling layer 142 located in the first substrate 100, the first conductive pad 101, the first conductive interconnect structure 103 and the second conductive pad 105 located in the filling layer 142 are all components of the first semiconductor chip, the second substrate 200, the second filling layer 242 located in the second substrate 200, the second conductive interconnect structure 203 and the third conductive pad 205 located in the second filling layer 242 are all components of the second semiconductor chip, the first semiconductor chip and the second semiconductor chip are bonded at the first bonding layer 134, and electrical signal transmission is achieved through the bonding connection between the second conductive pad 105 and the third conductive pad 205.

[0094] It should be noted that, first, with reference to Figure 4, the film layer structure inside the second conductive interconnect structure 203 is similar to the film layer structure inside the first conductive interconnect structure 103, and will not be elaborated here. In other words, the second conductive interconnect structure 203 also includes a diffusion barrier layer, a seed layer and an electroplating layer; second, with reference to Figure 4, the film layer structure inside the second filling layer 242 is similar to the film layer structure inside the filling layer 142, and will not be elaborated here. In other words, the second filling layer 242 also includes a multi-layer dielectric layer; third, the semiconductor device included in the second substrate 200 and the semiconductor device included in the first substrate 100 can be the same or different. If the semiconductor device included in the second substrate 200 is the same as the semiconductor device included in the first substrate 100, the first semiconductor chip and the second semiconductor chip are chips of the same type; if the semiconductor device included in the second substrate 200 is different from the semiconductor device included in the first substrate 100, the first semiconductor chip and the second semiconductor chip are chips of different types.

[0095] In summary, the first conductive pad 101 is mainly used to achieve electrical connection with the semiconductor device, the second conductive pad 105 is mainly used to achieve electrical connection with other electrical devices, and the first conductive interconnect structure 103 is mainly used to achieve electrical connection between the first conductive pad 101 and the second conductive pad 105. On this basis, the orthographic projections of at least two second conductive pads 105 on the first substrate 100 are designed to overlap with the orthographic projection of one first conductive interconnect structure 103 on the first substrate 100, so that one first conductive interconnect structure 103 is in electrical contact with at least two second conductive pads 105. On the one hand, this is beneficial for improving the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105. On the other hand, along the horizontal direction Y, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive pad 105, which is beneficial for improving the alignment accuracy between the second conductive pad 105 and the first conductive interconnect structure 103, and is more conducive to the electrical contact between the entire second conductive pad 105 and the first conductive interconnect structure 103, thereby increasing the contact area between the second conductive pad 105 and the first conductive interconnect structure 103, thereby reducing the contact resistance therebetween, and further improving the transmission efficiency of electrical signals.

[0096] Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure described in the above embodiment. The following will describe in detail the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure in conjunction with the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the above embodiment will not be described in detail here. After analysis, it was found that, referring to 9a in Figure 9, in order to lead out the electrical connection layer 10 in the semiconductor structure, after forming the electrical connection layer 10 and the first isolation layer 11 that wraps the electrical connection layer 10, the first isolation layer 11 will be patterned to form an opening 12 exposing the electrical connection layer 10. In the step of this patterning process, it is easy to cause etching damage to the exposed surface of the electrical connection layer 10, affecting the subsequent electrical connection performance between the electrical connection layer 10 and the conductive column.

[0097] It should be noted that 9a to 9d in FIG. 9 are schematic cross-sectional structural diagrams corresponding to the steps in a method for manufacturing a semiconductor structure.

[0098] Referring to Figures 9a and 9b, a large block of the second isolation layer 13 is deposited in the opening 12. In this deposition step, due to the presence of the opening 12, there is a large height difference between the second isolation layer 13 formed on the top surface of the first isolation layer 11 and the second isolation layer 13 formed at the opening 12, namely, step high.

[0099] Referring to Figures 9b and 9c, chemical mechanical polishing (CMP) is performed on the second isolation layer 13. As shown in Figure 9b, there is a large height difference between different areas of the second isolation layer 13, which increases the difficulty of achieving surface flatness of the second isolation layer 13 by chemical mechanical polishing.

[0100] Referring to 9c in Figure 9, the second isolation layer 13 after chemical mechanical polishing is patterned to form a through hole 14 exposing the electrical connection layer 10. In order to expose the electrical connection layer 10, the depth and width of the through hole 14 are relatively large, so that in the step of etching the second isolation layer 13 to form the through hole 14, the etching by-products formed in the through hole 14 are not easy to remove, which easily results in etching residues in the through hole 14.

[0101] Referring to 9c and 9d in FIG9 , a conductive column 15 is formed in the through hole 14. The presence of etching residues can easily reduce the conductivity of the conductive column 15, that is, increase the overall resistance of the conductive column 15, and further easily cause poor contact between the conductive column 15 and the electrical connection layer 10.

[0102] Continuing to refer to 9 d in FIG. 9 , a third isolation layer 16 is formed, and a conductive layer 17 is formed in the third isolation layer 16 using a damascene process.

[0103] As can be seen from the above description, to create the electrical connection layer 10 in a semiconductor structure, multiple dielectric layer depositions (e.g., first isolation layer 11, second isolation layer 13, and third isolation layer 16) and chemical mechanical polishing are often required to achieve flatness. The difficulty of chemical mechanical polishing in this step depends on the uniformity of the resulting isolation layer. Furthermore, deep hole etching or Damascus etching of the isolation layer is a complex process, and deep hole etching can easily result in excessive byproducts, leading to poor contact between the electrical connection layer 10 and the conductive pillars 15.

[0104] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 10 is a flow chart corresponding to the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure; Figures 11 to 27 are schematic cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that, in order to facilitate description and clearly illustrate the steps of the semiconductor structure manufacturing method, Figures 11 to 27 in this embodiment are all schematic diagrams of the partial structure of the semiconductor structure.

[0105] 10 to 27 , the method for manufacturing a semiconductor structure includes the following steps: S101: providing a first substrate 100, wherein the first substrate 100 has a semiconductor device therein, and forming a plurality of first conductive pads 101 connecting the semiconductor devices; S102: forming a first opening 112, wherein the first opening 112 exposes a surface of at least one first conductive pad 101; S103: forming a first conductive interconnect structure 103 filling the first opening 112; S104: forming a plurality of second conductive pads 105 on the first conductive interconnect structure 103, such that at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected through the first conductive interconnect structure 103.

[0106] A filling layer 142 is formed around each first conductive pad 101 , each second conductive pad 105 and the first conductive interconnect structure 103 . The first conductive interconnect structure 103 has a surface 103 b buried by the filling layer 142 between adjacent second conductive pads 105 (see FIG. 1 ).

[0107] It can be understood that, firstly, after forming the first opening 112 to expose the first conductive pad 101, an isolation layer filling the first opening 112 is no longer formed, thereby avoiding the problem of step high in the subsequently formed isolation layer, further reducing one chemical mechanical polishing step, and thus simplifying the process steps for manufacturing the semiconductor structure. Secondly, the first conductive interconnect structure 103 can be formed in the first opening 112. On the one hand, it is beneficial to increase the contact area between the first conductive interconnect structure 103 and the first conductive pad 101, thereby reducing the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101. On the other hand, it is not necessary to form the first conductive interconnect structure 103 in contact with the first conductive pad 101 through deep hole etching, thereby avoiding etching byproducts remaining between the first conductive pad 101 and the first conductive interconnect structure 103 or remaining in the first conductive interconnect structure 103, thereby improving the conductivity of the first conductive interconnect structure 103 itself, reducing the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101, and avoiding poor contact between the first conductive interconnect structure 103 and the first conductive pad 101.

[0108] In some embodiments, with continued reference to Figures 10 to 27, filling layer 142 may include a first dielectric layer 122, a second dielectric layer 132, and a third dielectric layer 124. First conductive pad 101 is formed in first dielectric layer 122, and second dielectric layer 132 is formed on first dielectric layer 122. First dielectric layer 122 and second dielectric layer 132 are formed before first opening 112 is formed. First opening 112 is formed in first dielectric layer 122 and second dielectric layer 132. How to form first conductive pad 101 will be described in detail later.

[0109] The following describes in more detail the steps of the manufacturing method provided in one embodiment of the present disclosure, with reference to the accompanying drawings. Referring to Figures 11 to 18 , S101 : Providing a first substrate 100 having semiconductor devices therein, and forming a plurality of first conductive pads 101 connected to the semiconductor devices. S102 : Forming a first opening 112 , exposing the surface of at least one first conductive pad 101.

[0110] In some embodiments, the filling layer 142 includes a sub-filling layer 102 wrapping the first conducting pad 101 , and the sub-filling layer 102 has a first opening 112 exposing at least a portion of the top surface of the first conducting pad 101 .

[0111] In some embodiments, forming the sub-filling layer 102 having the first opening 112 includes the following steps:

[0112] 11 to 14 , a first substrate 100 without a first opening 112 (see FIG15 ) includes a first conductive pad 101 and a sub-filling layer 102 that wraps around the first conductive pad 101. It is noteworthy that the sub-filling layer 102 shown in FIG11 to 14 seals and wraps around each surface of the first conductive pad 101, and the first opening 112 will be formed inside the sub-filling layer 102 later. For ease of description, the reference numerals of the sub-filling layer after the first opening 112 is formed in FIG12 to 14 and in the subsequent FIG15 to 27 are not distinguished.

[0113] In some embodiments, referring to FIG12 , the sub-filling layer 102 includes a first dielectric layer 122 and a second dielectric layer 132 stacked along a vertical direction X, and the first dielectric layer 122 wraps the first conductive pad 101. It is noteworthy that the first dielectric layer 122 and the second dielectric layer 132 in FIG12 and the subsequent FIG13 and FIG14 are the first dielectric layer and the second dielectric layer before the first opening 112 is formed. For ease of description, the reference numerals of the first dielectric layer and the second dielectric layer after the first opening 112 is formed in FIG12 to FIG14 and the subsequent FIG15 to FIG27 are not distinguished.

[0114] It can be understood that in addition to the first conductive pad 101, the semiconductor structure also has other semiconductor devices, such as transistor structures, word lines, bit lines and capacitor structures, and the first dielectric layer 122 and the second dielectric layer 132 jointly achieve electrical insulation between the first conductive pad 101 and other semiconductor devices in the semiconductor structure.

[0115] In some embodiments, the material of the first dielectric layer 122 is silicon oxide, and the material of the second dielectric layer 132 is silicon nitride. This is beneficial for utilizing silicon oxide to improve the electrical insulation performance between the first conductive pad 101 and other conductive structures in the semiconductor structure, while utilizing silicon nitride to improve the hardness of the sub-filling layer 102 wrapping the first conductive pad 101, that is, to improve the overall structural stability of the sub-filling layer 102.

[0116] In some embodiments, referring to Figure 13, the first conductive pad 101 may include a first wiring layer 131 and a second wiring layer 141. Along the horizontal direction Y, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141. The subsequently formed first opening 112 exposes a portion of the surface of the first conductive pad 101, including: the first opening 112 exposes a portion of the surface of the first wiring layer 131.

[0117] In some cases, the first conductive pad 101 may be a wiring layer, which may be located in a peripheral region of the semiconductor structure. In one example, the wiring layer includes the aforementioned first wiring layer 131 and second wiring layer 141. Based on this, the subsequently formed first conductive pad 101 and the first conductive interconnect structure 103 have a one-to-one relationship.

[0118] It is understood that the subsequently formed first opening 112 exposes the first wiring layer 131 for subsequent contact and connection with the electrical connection layer in another semiconductor structure to achieve electrical connection between the two semiconductor structures. The second wiring layer 141 located in the sub-fill layer 102 can be used to achieve electrical connection between two conductive structures in the same semiconductor structure. In addition, along the horizontal direction Y, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141, which facilitates the subsequent formation of a larger first opening 112 to expose a larger area of ​​the first wiring layer 131.

[0119] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be regarded as the same layer structure, that is, they are both located in the film layer interval where the first conductive pad 101 is located, but the first wiring layer 131 and the second wiring layer 141 can be insulated from each other to achieve electrical connection between different conductive structures. In addition, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive pad 101 can also include a third wiring layer, a fourth wiring layer or a fifth wiring layer, etc. Moreover, the first wiring layer 131 and the second wiring layer 141 can be an integrally formed structure, that is, the first wiring layer 131 and the second wiring layer 141 have the same film layer structure and material except that they have different functions. The first wiring layer 131 and the second wiring layer 141 are drawn in the same filling method in Figure 5.

[0120] In some embodiments, continuing to refer to Figure 13, in the horizontal direction Y, an isolation layer 151 may further be provided between the first wiring layer 131 and the second wiring layer 141. For example, the first dielectric layer 122 has an isolation layer 151, which is beneficial to improving the insulation effect between the first wiring layer 131 and the second wiring layer 141 through the isolation layer 151.

[0121] In some embodiments, the isolation layer 151 may be an air gap.

[0122] In some embodiments, referring to FIG. 14 , the first conductive pad 101 may include a barrier layer 161 and a conductive layer 171 , wherein the conductive layer 171 has a first side and a second side opposite each other along the vertical direction X, and the barrier layer 161 covers at least the first side and the second side. It will be appreciated that the barrier layer 161 is used to prevent the diffusion and migration of conductive ions in the conductive layer 171 into the sub-filling layer 102 , thereby preventing the conductive layer 171 from decreasing its own conductivity due to the diffusion and migration of conductive ions, and preventing the sub-filling layer 102 from decreasing its own insulation due to the migration of conductive ions. This helps ensure both the high conductivity of the conductive layer 171 and the high insulation of the sub-filling layer 102 .

[0123] It should be noted that, referring to Figures 13 and 14 , both the first wiring layer 131 and the second wiring layer 141 may include a barrier layer 161 and a conductive layer 171. The semiconductor structure shown in Figure 14 is used as an example to describe subsequent steps. In practical applications, the first conductive pad 101 may also include only the conductive layer 171.

[0124] In some embodiments, the barrier layer 161 is made of at least one of titanium and titanium nitride, and the conductive layer 171 is made of aluminum. Thus, the barrier layer 161 is helpful in preventing aluminum ions from electromigration.

[0125] 14 and 15 , the sub-filling layer 102 is patterned to form a first opening 112 . The first opening 112 exposes a portion of the surface of the first conducting pad 101 .

[0126] In some embodiments, referring to FIG14 , the sub-filling layer 102 includes a first dielectric layer 122 and a second dielectric layer 132 stacked along a vertical direction X. After the first opening 112 is formed, the first opening 112 is surrounded by the remaining first dielectric layer 122 and the remaining second dielectric layer 132. It will be understood that in the step of patterning the sub-filling layer 102, both the first dielectric layer 122 and the second dielectric layer 132 are patterned.

[0127] In some embodiments, referring to FIG. 15 , a portion of the exposed surface of the first conducting pad 101 has damage 107 .

[0128] In some embodiments, the damage 107 on the surface of the first conductive pad 101 includes etching damage and probe contact damage. Etching damage can be caused by etching damage to the surface of the first conductive pad 101 during the etching process when patterning the first dielectric layer 122 to form the first opening 112. Probe contact damage can be caused by physical contact between a test probe and the first conductive pad 101 after the surface of the first conductive pad 101 is exposed through the first opening 112. When the semiconductor structure is tested using the exposed first conductive pad 101, the probe mark left behind by the test probe causes damage to the surface of the first conductive pad 101, for example, causing a bulge on the surface of the first conductive pad 101. It is understood that whether it is etching damage or probe contact damage, the damage 107 will affect the electrical contact performance between the first conductive interconnect structure 103 (see FIG. 21 ) subsequently formed in the first opening 112 and the first conductive pad 101.

[0129] It should be noted that FIG15 illustrates two lesions 107 on the first conductive pad 101. In practice, the number of lesions 107 on the first conductive pad 101 may vary depending on the actual situation and is not limited in another embodiment of the present disclosure. Furthermore, the shape of the lesions 107 in FIG15 is merely an example and is not limited in one embodiment of the present disclosure.

[0130] In some embodiments, continuing to refer to Figure 15, on the basis of the first conductive pad 101 including the barrier layer 161 and the conductive layer 171, in the step of patterning the sub-filling layer 102 to form the first opening 112, the first opening 112 is also etched to expose a layer of the barrier layer 161, that is, the first opening 112 exposes the barrier layer 161, so that the subsequently formed first conductive interconnect structure 103 is directly in contact with the conductive layer 171.

[0131] In some embodiments, referring to Figures 15 to 22, the filling layer 142 may further include a fourth dielectric layer 106. The fourth dielectric layer 106 is formed after the first opening 112 is formed and before the first conductive interconnect structure 103 is formed, so that the fourth dielectric layer 106 is located between the first conductive interconnect structure 103 and the first dielectric layer 122 and the second dielectric layer 132.

[0132] The steps of forming the fourth dielectric layer 106 are described in detail below.

[0133] 15 to 22 , after forming the first opening 112 and before forming the first conductive interconnect structure 103 , the manufacturing method may further include the following steps: forming a fourth dielectric layer 106 and removing at least a portion of the damage 107 on the first conductive pad 101 , the fourth dielectric layer 106 being located on the sidewalls of the first opening 112 .

[0134] It should be noted that FIG18 takes the example of removing all the damage 107 on the first conductive pad 101 . In actual applications, due to limitations of the etching process or other requirements, a small amount of damage 107 may be retained on the first conductive pad 101 .

[0135] Forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 on the first conducting pad 101 include at least the following two embodiments.

[0136] In some embodiments, referring to Figure 16, a first opening 112 exposes a portion of the top surface of a first conductive pad 101, the thickness of the first conductive pad 101 whose top surface is exposed by the first opening 112 is a first thickness D1, and the thickness of the first conductive pad 101 whose top surface is not exposed by the first opening 112 is a second thickness D2, and the first thickness D1 is less than the second thickness D2.

[0137] It can be understood that the first conductive pad 101 whose top surface is exposed by the first opening 112 is the second portion 121, and the first thickness D1 is the thickness of the second portion 121. The first conductive pad 101 whose top surface is not exposed by the first opening 112 is the first portion 111, and the second thickness D2 is the thickness of the first portion 111. Because a portion of the second portion 121 is also etched during the step of forming the first opening 112, the first thickness D1 is less than the second thickness D2. Therefore, with the top surface 100a of the first substrate 100 as a reference, the top surface 121a of the second portion 121 is lower than the top surface 111a of the first portion 111.

[0138] In other embodiments, taking the formation of the semiconductor structure shown in FIG. 5 as an example, the same first opening 112 exposes the top surfaces of multiple first conducting pads 101. Thus, the orthographic projections of at least two first conducting pads 101 on the first substrate 100 overlap with the orthographic projection of a first conductive interconnect structure 103 subsequently formed in one first opening 112 on the first substrate 100, such that the number of first conducting pads 101 and first conductive interconnect structures 103 is many-to-one.

[0139] In some embodiments, the steps of forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 on the first conductive pad 101 may include: with reference to FIG16 and FIG17 , forming an initial fourth dielectric layer 116, wherein the initial fourth dielectric layer 116 conformally covers the surface of the first opening 112 and the top surface 102a of the sub-filling layer 102. It will be understood that the initial fourth dielectric layer 116 covers the damage 107, and the top surface 102a of the sub-filling layer 102 is the top surface 132a of the second dielectric layer 132 (see FIG2 ).

[0140] It should be noted that when the first conductive pad 101 includes the first wiring layer 131 and the second wiring layer 141 , the exposed wiring layer is the first wiring layer 131 .

[0141] 17 and 18 , the initial fourth dielectric layer 116 is etched back to remove the initial fourth dielectric layer 116 located on the top surface 102a of the sub-filling layer 102 and the bottom surface of the first opening 112, and the remaining initial fourth dielectric layer 116 is the fourth dielectric layer 106; wherein, in the step of etching back the initial fourth dielectric layer 116, a portion of the thickness of the first conductive pad 101 exposed by the first opening 112 is also etched along the vertical direction X. In other words, a portion of the thickness of the first conductive pad 101 exposed by the first opening 112 is etched away.

[0142] It is understood that during the step of etching back the initial fourth dielectric layer 116 to form the fourth dielectric layer 106, the etching process, while removing the initial fourth dielectric layer 116 located at the bottom surface of the first opening 112, also removes the damage 107 covered by the initial fourth dielectric layer 116, i.e., etches the second portion 121, thereby achieving the purpose of removing at least a portion of the damage 107. Simultaneously, the fourth dielectric layer 106 located at the sidewalls of the first opening 112 is utilized to prevent the sub-filling layer 102 forming the sidewalls of the first opening 112 from being etched. Furthermore, the steps of forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 can be performed simultaneously. This facilitates utilizing the fourth dielectric layer 106 to protect the sidewalls of the first opening 112 during the step of etching the damage 107, preventing the first dielectric layer 122 forming the sidewalls of the first opening 112 from being etched, thereby providing the sidewalls of the first opening 112 with a relatively smooth interface, facilitating the subsequent formation of a first conductive interconnect structure 103 with uniform dimensions. Furthermore, during the step of etching the damage 107 , possible contaminants on the surface of the first conductive pad 101 may be removed by etching, thereby further reducing the contact resistance between the subsequently formed first conductive interconnect structure 103 and the first conductive pad 101 .

[0143] In practical applications, the thickness of the etched second portion 121 is adjusted according to the adjustment of the etching process parameters to ensure that the damage 107 is completely removed.

[0144] In some embodiments, with continued reference to FIG. 18 , in the step of etching back the initial fourth dielectric layer 116 to form the fourth dielectric layer 106 based on the conductive layer 171 exposed by the first opening 112, the etching process may also etch a portion of the thickness of the conductive layer 171 along the vertical direction X, that is, etching at least a portion of the thickness of the second portion 121. In practical applications, the first opening may expose a barrier layer. In the step of etching back the initial fourth dielectric layer to form the fourth dielectric layer, the etching process will at least remove the barrier layer exposed by the first opening, so that the subsequently formed first conductive interconnect structure is directly in contact with and connected to the conductive layer.

[0145] It should be noted that the first portion 111 and the second portion 121 are divided by thick dashed lines in FIG. 16 to FIG. 18 . The division of the first portion 111 and the second portion 121 in the first conductive pad 101 depends on the area of ​​the first conductive pad 101 exposed by the first opening 112 .

[0146] In other embodiments, referring to Figure 16, the first conductive pad 101 whose top surface is exposed by the first opening 112 is the second portion 121, the first conductive pad 101 whose top surface is not exposed by the first opening 112 is the first portion 111, and the surface exposed by the second portion 121 has damage 107; the steps of forming the fourth dielectric layer 106 and removing at least part of the damage 107 on the first conductive pad 101 may include: in combination with reference to Figure 16 and Figure 19, forming a mask layer 108, the mask layer 108 being located on the sidewalls of the first opening 112 and the top surface 102a of the sub-filling layer 102, the mask layer 108 exposing the portion of the top surface of the first conductive pad 101 exposed by the remaining first opening 112, that is, the portion of the top surface of the second portion 121.

[0147] 19 and 20 , the damage 107 is etched using the mask layer 108 as a mask, so as to etch a portion of the thickness of the first conductive pad 101 exposed by the first opening 112 along the vertical direction X. This facilitates protecting the sub-filling layer 102 through the mask layer 108 during the step of etching the damage 107 .

[0148] 20 and 18 , the mask layer 108 is removed and the fourth dielectric layer 106 is formed.

[0149] It should be noted that the manufacturing method provided in another embodiment of the present disclosure does not limit the method for forming the fourth dielectric layer 106 after removing the mask layer 108. In some embodiments, the step of forming the fourth dielectric layer 106 may include: first forming a protective film that conformally covers the first opening after the mask layer is removed and the second top surface of the first dielectric layer, and then etching back the protective film to form the fourth dielectric layer 106.

[0150] It can be understood that after removing the damage 107, the fourth dielectric layer 106 is formed to avoid the protective film used for the next fourth dielectric layer 106 being exposed to the etching environment for too long, which is beneficial to improving the film uniformity of the formed fourth dielectric layer 106 and enhancing the fourth dielectric layer 106's blocking effect on the diffusion and migration of conductive ions in the subsequently formed first conductive interconnect structure 103.

[0151] S103: Forming a first conductive interconnect structure 103 filling the first opening 112. In some embodiments, referring to FIG15 and FIG21 , the fourth dielectric layer is not formed on the sidewalls of the sub-filling layer 102, and the first conductive interconnect structure 103 is formed directly in the first opening 112. In practical applications, if the first conductive pad 101 has a damage 107, the first conductive interconnect structure 103 covers the damage 107.

[0152] In other embodiments, referring to FIG. 18 and FIG. 22 , after the fourth dielectric layer 106 is formed, that is, after the damage 107 (see FIG. 16 ) is removed, the step of filling the first opening 112 with the first conductive interconnect structure 103 includes: the first conductive interconnect structure 103 fills the remaining portion of the first opening 112. It is understood that the fourth dielectric layer 106 and the first conductive interconnect structure 103 together completely fill the first opening 112.

[0153] It should be noted that the formation of the first conductive interconnect structure 103 and the second conductive pad 105 will be described in detail later using the semiconductor structure shown in FIG. 18 .

[0154] In some embodiments, in combination with reference to Figures 18 and 23, the step of forming the first conductive interconnect structure 103 may include: forming a first diffusion barrier layer 113, the first diffusion barrier layer 113 conformally covering the inner wall of the first opening 112 and the top surface 102a of the sub-filling layer 102; forming a first seed layer 123, the first seed layer 123 conformally covering the surface of the first diffusion barrier layer 113; forming a first electroplating layer 133, the first electroplating layer 133 fills the remaining portion of the first opening 112 and is located on the first seed layer 123 away from the top surface 123a of the sub-filling layer 102.

[0155] 23 and 24 , the first diffusion barrier layer 113 , the first seed layer 123 and the first electroplating layer 133 are planarized until the top surface 102 a of the sub-filling layer 102 is exposed, and the remaining first diffusion barrier layer 113 , the remaining first seed layer 123 and the remaining first electroplating layer 133 constitute the first conductive interconnect structure 103 .

[0156] It is understood that forming the first electroplating layer 133 based on the first seed layer 123 using an electroplating process is beneficial to improving the conductivity of the first electroplating layer 133, thereby further improving the overall conductivity of the first conductive interconnect structure 103. In addition, the first diffusion barrier layer 113 is used to prevent the diffusion and migration of conductive ions in the first seed layer 123 and the first electroplating layer 133 into the sub-filling layer 102, thereby preventing the first seed layer 123 and the first electroplating layer 133 from being degraded in conductivity due to the diffusion and migration of conductive ions, and preventing the sub-filling layer 102 from being degraded in insulation due to the migration of conductive ions. This is beneficial to the higher conductivity of the first seed layer 123 and the first electroplating layer 133 and the higher insulation performance of the sub-filling layer 102.

[0157] In some embodiments, the first diffusion barrier layer 113 is made of at least one of tantalum and tantalum nitride, and the first seed layer 123 and the first electroplating layer 133 are made of copper.

[0158] In some embodiments, after the first conductive interconnect structure 103 is formed in the first opening 112, the surface of the first conductive interconnect structure 103 is planarized. Referring to FIG. 2 , a first preset height difference H1 is provided between the top surface 132a of the second dielectric layer 132 and the top surface 103a of the first conductive interconnect structure 103. The first preset height difference H1 is in the range of 0 nm to 50 nm.

[0159] In some embodiments, referring to FIG. 24 to FIG. 27 , S104 : forming a plurality of second conductive pads 105 on the first conductive interconnect structure 103 , such that at least one first conductive pad 101 and at least one second conductive pad 105 are electrically connected through the first conductive interconnect structure 103 .

[0160] In some embodiments, referring to FIG. 24 to FIG. 27 , after forming the first conductive interconnect structure 103 , a dielectric layer 104 is formed, and a second conductive pad 105 electrically connected to the first conductive interconnect structure 103 is formed in the third dielectric layer 104 .

[0161] In some embodiments, referring to FIG27 , the step of forming the second conductive pad 105 may include forming at least two second conductive pads 105 that are in contact with and connected to a top surface 103a of a first conductive interconnect structure 103 that is away from the first conductive pad 101. It will be appreciated that the contact connection between a first conductive interconnect structure 103 and at least two second conductive pads 105 is beneficial for improving the transmission efficiency of electrical signals among the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105.

[0162] It should be noted that FIG27 takes a first conductive interconnect structure 103 being in contact with three second conductive pads 105 as an example. In actual applications, the number of second conductive pads 105 in contact with the same first conductive interconnect structure 103 can be determined according to actual needs, for example, it can be 1, 2, 4 or 5.

[0163] In some embodiments, forming at least two second conducting pads 105 may include the following steps:

[0164] 25 , a dielectric layer 104 is formed on the top surface formed by the sub-filling layer 102 and the first conductive interconnect structure 103 .

[0165] 25 , a third dielectric layer 124 and a first bonding layer 134 are stacked on top of the second dielectric layer 132. The third dielectric layer 124 and the first bonding layer 134 constitute the dielectric layer 104. It will be appreciated that the third dielectric layer 124 and the first bonding layer 134 together provide electrical insulation between the second conductive pad 105 subsequently formed in the dielectric layer 104 and other conductive structures in the semiconductor structure.

[0166] In some embodiments, the material of the third dielectric layer 124 is silicon oxide, and the material of the first bonding layer 134 is silicon nitride. This is beneficial for utilizing silicon oxide to improve the electrical insulation performance between the second conductive pad 105 subsequently formed in the third dielectric layer 124 and other conductive structures in the semiconductor structure, while utilizing silicon nitride to improve the hardness of the dielectric layer 104, that is, to improve the mechanical stability of the overall structure.

[0167] 25 and 26 , the dielectric layer 104 is patterned to form a plurality of second openings 114 spaced apart from each other, wherein at least two second openings 114 expose different regions of the top surface 103a of the same first conductive interconnect structure 103, and other portions of the second openings 114 expose the top surface 102a of the sub-filling layer 102 in the filling layer 142.

[0168] It can be understood that the first conductive interconnect structure 103 that is in contact with the second conductive pad 105 has already been formed in the sub-filling layer 102. It is only necessary to form the second opening 114 in the dielectric layer 104 and subsequently form the second conductive pad 105 that fills the second opening 114. In this way, the depth of the second opening 114 used to form the second conductive pad 105 is only related to the thickness of the dielectric layer 104. Even if the width of the second opening 114 in the horizontal direction Y is smaller than the width of the first conductive interconnect structure 103 in the horizontal direction Y, the aspect ratio of the second opening 114 will not be very large, and it is unlikely that etching by-products will remain at the contact point between the first conductive interconnect structure 103 and the second conductive pad 105. The etching by-products here mainly come from the step of patterning the dielectric layer 104.

[0169] 26 and 27 , a second diffusion barrier layer 115 is formed, conformally covering the inner wall of the second opening 114 ; a second seed layer 125 is formed, conformally covering the surface of the second diffusion barrier layer 115 ; a second electroplating layer 135 is formed, filling the remaining portion of the second opening 114 ; the second diffusion barrier layer 115 , the second seed layer 125 , and the second electroplating layer 135 constitute a second conductive pad 105 .

[0170] It is understood that forming the second electroplating layer 135 based on the second seed layer 125 using an electroplating process is beneficial for improving the conductivity of the second electroplating layer 135, thereby further improving the overall conductivity of the second conductive pad 105. In addition, the second diffusion barrier layer 115 is used to prevent the diffusion and migration of conductive ions in the second seed layer 125 and the second electroplating layer 135 into the dielectric layer 104, thereby preventing the second seed layer 125 and the second electroplating layer 135 from being degraded in conductivity due to the diffusion and migration of conductive ions, and preventing the dielectric layer 104 from being degraded in insulation due to the migration of conductive ions. This facilitates the higher conductivity of the second seed layer 125 and the second electroplating layer 135 and the higher insulation performance of the dielectric layer 104.

[0171] In some embodiments, the second diffusion barrier layer 115 is made of at least one of tantalum and tantalum nitride, and the second seed layer 125 and the second electroplating layer 135 are made of copper.

[0172] It should be noted that the same filling method is used to draw the first diffusion barrier layer 113 and the second diffusion barrier layer 115 in Figure 27. In practical applications, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 can be the same or different.

[0173] In some embodiments, referring to Figure 8, the filling layer may further include a first bonding layer 134, the second conductive pad 105 has a top surface exposed to the first bonding layer 134, and there is a second predetermined height difference H2 between the top surface of the second conductive pad 105 exposed to the first bonding layer 134 and the top surface of the first bonding layer 134, and the second predetermined height difference H2 ranges from 0nm to 50nm; after forming the second conductive pad 105, the manufacturing method may further include: forming a second bonding layer 234 directly bonded to the first bonding layer 134 and a third conductive pad 205 directly bonded to the second conductive pad 105.

[0174] It should be noted that the steps of forming the third conducting pad 205 are similar to the steps of forming the second conducting pad 105 , and are not described in detail here.

[0175] In summary, after forming the first opening 112 exposing the first conductive pad 101, the first conductive interconnect structure 103 is formed in the first opening 112, thereby reducing the steps of forming an isolation layer that fills the first opening 112 and forming a through hole in the isolation layer for forming a conductive column, which is conducive to simplifying the process steps of preparing the semiconductor structure; moreover, forming the first conductive interconnect structure 103 in the first opening 112 is conducive to increasing the contact area between the first conductive interconnect structure 103 and the first conductive pad 101, thereby reducing the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101, and on the other hand In terms of the present invention, there is no need to form the first conductive interconnect structure 103 in contact with the first conductive pad 101 by deep hole etching, that is, to avoid the generation of etching by-products that are difficult to remove, so as to avoid the etching by-products remaining between the first conductive pad 101 and the first conductive interconnect structure 103 or remaining in the first conductive interconnect structure 103, thereby facilitating the improvement of the conductivity of the first conductive interconnect structure 103 itself, and reducing the contact resistance between the first conductive interconnect structure 103 and the first conductive pad 101, thereby avoiding poor contact between the first conductive interconnect structure 103 and the first conductive pad 101, and improving the electrical performance of the semiconductor structure.

[0176] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first substrate (100) and a semiconductor device located in the first substrate (100); A plurality of first conductive pads (101), connected to the semiconductor device; a plurality of second conductive pads (105), at least one of the first conductive pads (101) and at least one of the second conductive pads (105) being electrically connected via a first conductive interconnect structure (103) extending in a direction perpendicular to the first substrate (100); A filling layer (142), the filling layer (142) filling the periphery of each of the first conductive pads (101), the first conductive interconnect structure (103) and each of the second conductive pads (105); wherein the first conductive interconnect structure (103) has a surface (103b) buried by the filling layer (142) between adjacent second conductive pads (105).

2. The semiconductor structure according to claim 1, characterized in that: The filling layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer covers the first conductive pad, the third dielectric layer covers the side wall of the second conductive pad, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and there is a first preset height difference between the top surface of the second dielectric layer and the top surface of the first conductive interconnect structure, and the first preset height difference ranges from 0nm to 50nm.

3. The semiconductor structure according to claim 2, characterized in that: The first dielectric layer and the second dielectric layer constitute a sub-filling layer; the filling layer further comprises a fourth dielectric layer, and the fourth dielectric layer is located between the sub-filling layer and the first conductive interconnect structure.

4. The semiconductor structure according to claim 2, characterized in that: At least one of the second conductive pads is located on the top surface of the second dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that: The second conductive pad located on the top surface of the second dielectric layer is not electrically connected to the first conductive pad, and the second conductive pad is in direct contact with the top surface of the second dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that The first conductive pad electrically contacting the first conductive interconnect structure includes a first part and a second part, wherein the second part is in direct contact with the first conductive interconnect structure, the first part is not in direct contact with the first conductive interconnect structure, and a surface of the second part in direct contact with the first conductive interconnect structure is lower than a surface of the first part.

7. The semiconductor structure according to claim 1, characterized in that: Orthographic projections of at least two of the first conductive pads on the first substrate overlap with an orthographic projection of one of the first conductive interconnect structures on the first substrate.

8. The semiconductor structure according to claim 1, characterized in that: The filling layer includes a first bonding layer, the second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the second predetermined height difference ranges from 0nm to 50nm.

9. The semiconductor structure according to claim 8, characterized in that: Also includes: A second bonding layer and a third conductive pad located in the second bonding layer, the second bonding layer is directly bonded to the first bonding layer, and the third conductive pad is directly bonded to the second conductive pad.

10. The semiconductor structure according to claim 1, wherein: Also includes: An isolation layer is located in the filling layer between adjacent first conductive pads.

11. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first substrate, wherein the first substrate has a semiconductor device; forming a plurality of first conductive pads connected to the semiconductor device; forming a first opening, wherein the first opening exposes a surface of at least one of the first conductive pads; forming a first conductive interconnect structure filling the first opening; forming a plurality of second conductive pads on the first conductive interconnect structure, so that at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through the first conductive interconnect structure; A filling layer is formed around the periphery of each of the first conductive pads, each of the second conductive pads, and the first conductive interconnect structure, and the first conductive interconnect structure has a surface buried by the filling layer between adjacent second conductive pads.

12. The manufacturing method according to claim 11, characterized in that: The filling layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first conductive pad is formed in the first dielectric layer, the second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed before forming the first opening, and the first opening is formed in the first dielectric layer and the second dielectric layer; After forming the first conductive interconnect structure in the first opening, planarizing the surface of the first conductive interconnect structure so that a first preset height difference exists between a top surface of the second dielectric layer and a top surface of the first conductive interconnect structure, and the first preset height difference ranges from 0 nm to 50 nm; After forming the first conductive interconnect structure, the third dielectric layer is formed, and the second conductive pad electrically connected to the first conductive interconnect structure is formed in the third dielectric layer.

13. The manufacturing method according to claim 12, characterized in that: The filling layer further includes a fourth dielectric layer, which is formed after forming the first opening and before forming the first conductive interconnect structure, so that the fourth dielectric layer is located between the first conductive interconnect structure and the first dielectric layer and the second dielectric layer.

14. The manufacturing method according to claim 13, characterized in that: The step of forming the fourth dielectric layer includes: forming an initial fourth dielectric layer, the initial fourth dielectric layer conformally covering the surface of the first opening and the top surface of the second dielectric layer, and etching back the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the top surface of the second dielectric layer and the bottom surface of the first opening, and the remaining initial fourth dielectric layer is the fourth dielectric layer; wherein, in the step of etching back the initial fourth dielectric layer, part of the thickness of the first conductive pad exposed by the first opening is etched away.

15. The manufacturing method according to claim 11, characterized in that: The filling layer also includes a first bonding layer, the second conductive pad has a top surface exposed to the first bonding layer, and there is a second predetermined height difference between the top surface of the second conductive pad exposed to the first bonding layer and the top surface of the first bonding layer, and the second predetermined height difference ranges from 0nm to 50nm; after forming the second conductive pad, it also includes forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pad.

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