Wiring substrate and manufacturing method therefor, light-emitting substrate, and display device

Abstract

A wiring substrate. The wiring substrate comprises: a substrate, having a first surface; and a plurality of signal lines, located on the first surface, wherein the plurality of signal lines comprise at least one target signal line, the target signal line comprises at least one comb-shaped portion, the comb-shaped portion is provided with a comb handle portion and a plurality of comb tooth portions, the same ends of the plurality of comb tooth portions are connected to the comb handle portion, and a first gap is formed between any two adjacent comb tooth portions.

Description

Wiring substrate and manufacturing method thereof, light-emitting substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate and a preparation method thereof, a light-emitting substrate, and a display device. Background Art

[0002] Light-emitting diodes (LEDs), submillimeter light-emitting diodes (Mini LEDs), or micro light-emitting diodes (Micro LEDs) are self-luminous components. Mini LEDs range in size from approximately 80μm to 500μm, while Micro LEDs are smaller than 80μm.

[0003] The above-mentioned types of LEDs can be used in the backlight module of a display device, or form the pixels of a display device and then be used in the display device. When used in the backlight module, by arranging a larger number of LEDs with a higher density, regional dimming within a smaller range can be achieved. Compared with the design of traditional backlight modules, it can achieve better brightness uniformity and higher color contrast within a smaller mixing distance, thereby realizing the ultra-thin, high color rendering, and power-saving design of terminal products such as display devices.

[0004] Summary of the Invention

[0005] In one aspect, a wiring substrate is provided, comprising: a substrate and a plurality of signal lines. The substrate has a first surface. The plurality of signal lines are located on the first surface; the plurality of signal lines include at least one target signal line, and the target signal line includes at least one comb-shaped portion; the comb-shaped portion includes a handle and a plurality of comb teeth, wherein the same end of the plurality of comb teeth is connected to the handle, and a first gap is defined between any two adjacent comb teeth.

[0006] In some embodiments, the target signal line further includes: a connecting portion; the connecting portion is connected to the comb handle.

[0007] In some embodiments, the sum of the widths of the plurality of comb teeth of the comb-shaped portion is equal to or approximately equal to the width of the connecting portion.

[0008] In some embodiments, in the same comb-shaped portion, the width of each comb tooth portion is equal or approximately equal.

[0009] In some embodiments, in the same comb-shaped portion, the widths of the first gaps between any two adjacent comb-tooth portions are equal or substantially equal.

[0010] In some embodiments, the wiring substrate further comprises: at least one dummy conductive pattern located on the first surface; the dummy conductive pattern is located on one side of one of the signal lines and is disposed on the same layer as the signal line; and the dummy conductive pattern is insulated from the signal line.

[0011] In some embodiments, a plurality of the dummy conductive patterns are provided on the same side of the signal line, and / or at least one dummy conductive pattern is provided on both sides of the signal line.

[0012] In some embodiments, a width of the dummy conductive pattern is equal to or substantially equal to a width of the comb-tooth portion.

[0013] In some embodiments, a second gap is provided between the signal line and the adjacent dummy conductive pattern, and a width of the second gap is equal to or substantially equal to a width of the first gap.

[0014] In some embodiments, a plurality of the dummy conductive patterns are provided on the same side of the signal line, a third gap is provided between any two adjacent dummy conductive patterns, and a width of the second gap is equal to or approximately equal to a width of the third gap.

[0015] In some embodiments, the dummy conductive pattern includes a first type dummy conductive pattern. The wiring substrate further includes a plurality of first type pad units and a plurality of second type pad units located on the first surface; the second type pad units include a plurality of device pad groups.

[0016] The multiple signal lines include: multiple first-class signal lines, multiple second-class signal lines and multiple third-class signal lines. Two first-class signal lines are respectively located on opposite sides of the second-class pad unit. A first-class pad unit is electrically connected to at least one second-class pad unit through the second-class signal line; multiple device pad groups within the same second-class pad unit are connected through the second-class signal line; the second-class pad unit is connected to the adjacent first-class signal line through the second-class signal line. The first-class pad unit is connected to the adjacent first-class signal line through the second-class signal line, and the multiple first-class pad units are connected through the multiple third-class signal lines. The first-class virtual conductive pattern extends at least along the overall direction of multiple device pad groups in the same second-class pad unit and the multiple second-class signal lines connected to the multiple device pad groups.

[0017] In some embodiments, when the wiring substrate includes a plurality of first-type dummy conductive patterns, at least two of the first-type dummy conductive patterns are respectively arranged on opposite sides along an extending direction perpendicular to the second-type signal line.

[0018] In some embodiments, when the first type of pad unit is connected to multiple second type of pad units, and two first type of virtual conductive patterns are respectively arranged on opposite sides along the extension direction perpendicular to the second type of signal line, multiple second type of pad units are arranged in a column, and the two first type of virtual conductive patterns located between any two adjacent second type of pad units are connected to each other.

[0019] In some embodiments, the dummy conductive pattern includes a second-type dummy conductive pattern extending at least along the overall direction of two adjacent first-type pad units and a plurality of the third-type signal lines and the second-type signal lines connected thereto.

[0020] In some embodiments, when the wiring substrate includes multiple second-type dummy conductive patterns, at least two of the second-type dummy conductive patterns are respectively arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines and on opposite sides along the direction perpendicular to the second-type signal lines.

[0021] In some embodiments, when the dummy conductive pattern includes a first-type dummy conductive pattern, the second-type dummy conductive pattern located on one side of the plurality of third-type signal lines and adjacent to the second-type signal lines is connected to the adjacent first-type dummy conductive pattern.

[0022] In some embodiments, the second type of signal line includes a cascade line or a connecting line; and / or, the third type of signal line includes at least one of a first voltage line, a data line and an addressing line; and / or, the first type of signal line includes at least one of a ground line and a second voltage line.

[0023] In another aspect, a method for preparing a wiring substrate is provided, wherein the method comprises: providing a substrate having a first surface; forming a plurality of signal lines on the first surface; the plurality of signal lines including at least one target signal line, the target signal line including at least one comb-shaped portion; the comb-shaped portion including a handle and a plurality of comb teeth, the plurality of comb teeth being connected to the handle at a common end, and a first gap being defined between any two adjacent comb teeth.

[0024] In some embodiments, forming multiple signal lines on the first surface includes: using the same composition process to simultaneously form multiple signal lines and at least one dummy conductive pattern on the first surface; the dummy conductive pattern is located on one side of one of the signal lines and is arranged on the same layer as the signal line; the dummy conductive pattern and the signal line are insulated.

[0025] In some embodiments, the simultaneous formation of the plurality of signal lines and at least one dummy conductive pattern on the first surface using the same patterning process includes: forming a seed layer on the first surface; forming a photoresist layer on the seed layer; the photoresist layer having a plurality of first openings and a plurality of second openings, the first openings corresponding to the signal lines to be formed, and the second openings corresponding to the dummy conductive patterns to be formed; and using an electroplating process to form the signal lines within the first openings and simultaneously form the dummy conductive patterns within the second openings.

[0026] On the other hand, a light-emitting substrate is provided, comprising: a wiring substrate as described in any one of the above embodiments and a plurality of light-emitting devices, wherein the plurality of light-emitting devices are arranged on the wiring substrate.

[0027] In another aspect, a display device is provided, comprising: the light-emitting substrate according to any one of the above embodiments, and a display panel, wherein the display panel is located on the light-emitting side of the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of the present disclosure.

[0029] FIG1 is a schematic diagram of a display device according to some embodiments of the present disclosure;

[0030] FIG2 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0031] FIG3 is a structural diagram of another display device according to some embodiments of the present disclosure;

[0032] FIG4 is a structural diagram of a light-emitting substrate according to some embodiments of the present disclosure;

[0033] FIG5 is a structural diagram of another light-emitting substrate according to some embodiments of the present disclosure;

[0034] FIG6A is a structural diagram of a light-emitting substrate according to some embodiments of the present disclosure;

[0035] FIG6B is a structural diagram of another light-emitting substrate according to some embodiments of the present disclosure;

[0036] FIG7 is a structural diagram of an electroplating device according to some embodiments of the present disclosure;

[0037] FIG8 is a structural diagram of a wiring substrate according to some embodiments of the present disclosure;

[0038] FIG9 is a partially enlarged structural diagram of the AA region of the wiring substrate in FIG8 ;

[0039] FIG10 is a partially enlarged structural diagram of a signal line according to some embodiments of the present disclosure;

[0040] FIG11 is a partially enlarged structural diagram of the BB region of the wiring substrate in FIG8 ;

[0041] FIG12 is a structural diagram of another wiring substrate according to some embodiments of the present disclosure;

[0042] FIG13A is a partially enlarged structural diagram of the CC region of the wiring substrate in FIG12;

[0043] FIG13B is a partially enlarged structural diagram of a wiring substrate according to FIG12;

[0044] FIG14 is a partially enlarged structural diagram of the DD region of the wiring substrate in FIG12;

[0045] FIG15 is a diagram illustrating thickness representations of a plurality of wiring patterns within a region on a substrate according to some embodiments of the present disclosure;

[0046] FIG16 is a flow chart of a method for preparing a wiring substrate according to some embodiments of the present disclosure;

[0047] FIG17 is a structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0048] FIG18 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0049] FIG19 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0050] FIG20 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0051] FIG21 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0052] FIG22 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0053] FIG23 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure;

[0054] FIG. 24 is another structural diagram of a wiring substrate during preparation according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0056] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0057] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0060] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0062] As used herein, "perpendicular" and "equal" include the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either.

[0063] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0065] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1. The display device 1 can be any display device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of jewelry), etc.

[0066] Illustratively, the display device 1 includes: a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0067] In some embodiments, the display device 1 further includes a light-emitting substrate 2. The light-emitting substrate 2 can be used directly for displaying images. In this case, the display device 1 is an active light-emitting display device. Since the light-emitting substrate 2 can emit light on its own, there is no need for a separate backlight module.

[0068] Exemplarily, the light-emitting substrate 2 includes a light-emitting device, such as an LED (Light Emitting Diode).

[0069] In some other embodiments, as shown in FIG. 2 , the display device 1 further includes a display panel 3 .

[0070] In some examples, the display panel 3 may be a liquid crystal display (LCD) display panel.

[0071] Exemplarily, the display panel 3 may be driven by a passive matrix (PM) driving mode or an active matrix (AM) driving mode. When the display panel 3 is driven by an active matrix driving mode, the display panel 3 may be, for example, a thin film transistor liquid crystal display (TFT-LCD) panel.

[0072] For example, as shown in FIG. 2 , the display panel 3 may include an array substrate 31 , a liquid crystal layer 32 , and a color filter substrate 33 , which are stacked in sequence.

[0073] For example, the array substrate 31 may include: a plurality of pixel electrodes 311 and a plurality of pixel driving circuits 312. The plurality of pixel electrodes 311 are electrically connected to the plurality of pixel driving circuits 312 in a one-to-one correspondence, and the pixel driving circuits 312 provide pixel voltages to the corresponding pixel electrodes 311.

[0074] Exemplarily, the display panel 3 further includes: a common electrode.

[0075] The setting position of the common electrode is related to the display type of the display panel 3. In the embodiment of the present disclosure, the display type of the display panel 3 can be ADS (Advanced Super Dimension Switch) display type, IPS (In-Plane Switching) display type, VA (Vertical Alignment) display type, FFS (Fringe Field Switching) display type, TN (Twisted Nematic) display type, etc. Therefore, there are multiple setting positions of the common electrode in the embodiment of the present disclosure.

[0076] For example, when the display panel 3 is an IPS display type, the common electrode can be set on the array substrate 31 and set on the same layer as the pixel electrode 311. Thus, the common electrode and the pixel electrode 311 can be formed simultaneously in one composition process, thereby simplifying the preparation process of the display panel 3.

[0077] For another example, when the display panel 3 is of the FFS display type or the ADS display type, the common electrode can be provided on the array substrate 31 and located on a different layer from the pixel electrode 311. This can prevent interference between the pixel voltage signal on the pixel electrode 311 and the common voltage on the common electrode, thereby improving the signal accuracy of the pixel voltage signal and the common voltage.

[0078] For another example, when the display panel 3 is of TN display type or VA display type, the common electrode can be provided on the color filter substrate 33 .

[0079] For example, the liquid crystal layer 32 includes a plurality of liquid crystal molecules. For example, if the display panel 3 is a TN display type, an electric field may be formed between the pixel electrode 311 and the common electrode, and the liquid crystal molecules between the pixel electrode 310 and the common electrode may be deflected under the action of the electric field.

[0080] Exemplarily, the color filter substrate 33 includes multiple color filters. For example, when the light incident on the color filter is white light, the color filters may include a red filter, a green filter, and a blue filter. For example, the red filter only transmits the red light in the incident light, the green filter only transmits the green light in the incident light, and the blue filter only transmits the blue light in the incident light.

[0081] The color filter substrate 33 also includes a black matrix, which can be used to prevent light mixing.

[0082] In this embodiment, as shown in Figure 3, the display device 1 further includes a light-emitting substrate 2. The light-emitting substrate 2 functions as a backlight module, providing backlight for a display panel 3. The display panel 3 is located on the light-emitting side of the light-emitting substrate 2. The light-emitting side of the light-emitting substrate 2 refers to the side from which light is emitted.

[0083] It is understood that the backlight provided by the light-emitting substrate 2 can pass through the array substrate 31 and be incident on the liquid crystal molecules in the liquid crystal layer 32. Under the influence of the electric field formed between the pixel electrode 311 and the common electrode, the liquid crystal molecules undergo a certain degree of flipping, thereby changing the polarization direction of the light passing through the liquid crystal molecules. This light passes through the different color filters in the color filter substrate 33 and then exits. This exiting light includes light of various colors, such as red, green, and blue. The various colors of light interact with each other to enable the display device 1 to achieve color display.

[0084] Exemplarily, the light emitting substrate 2 can be used as a direct-type backlight module or an edge-type backlight module. FIG. 4 shows the basic structure of the edge-type backlight module, and FIG. 5 shows the basic structure of the direct-type backlight module.

[0085] As shown in Figures 4 and 5, edge-lit backlight modules are generally thinner and lighter than direct-lit backlight modules. Direct-lit backlight modules can independently control the brightness of different areas, thereby providing localized backlighting and ultra-high contrast backlighting.

[0086] The following describes the light-emitting substrate 2 using the light-emitting substrate 2 as a direct-lit backlight module as an example. Of course, the light-emitting substrate 2 described in the following embodiments of the present disclosure can also be directly used as a display panel for displaying images.

[0087] As shown in FIG. 6A and FIG. 6B , the light emitting substrate 2 includes a wiring substrate 22 and a plurality of light emitting devices 21 provided on the wiring substrate 22 .

[0088] Exemplarily, the light emitting device 21 may be an LED light emitting device, for example, a sub-millimeter LED with a size of 100 μm to 500 μm, or a micro LED with a size less than 100 μm, or an LED with a larger size.

[0089] In some examples, as shown in FIG6A and FIG6B , the light emitting substrate 2 further includes a plurality of chips 23 disposed on a wiring substrate 22 . The plurality of chips 23 may be arranged in multiple rows and columns. One chip 23 is electrically connected to at least one light emitting device 21 .

[0090] For example, as shown in FIG6B , one chip 23 is electrically connected to one light emitting device 21. One chip 23 controls the operating state of one light emitting device 21 electrically connected thereto.

[0091] 6A , one chip 23 is electrically connected to a plurality of light emitting devices 21. One chip 23 controls the working states of the plurality of light emitting devices 21 electrically connected thereto.

[0092] It is understandable that each chip 23 works independently, so that different light-emitting devices 21 electrically connected to different chips 23 can be controlled to have different working states.

[0093] For example, when a chip 23 is electrically connected to multiple light-emitting devices 21 , there are multiple ways to electrically connect the multiple light-emitting devices 21 to the chip 23 , which can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0094] For example, the plurality of light-emitting devices 21 are electrically connected directly to the same chip 23 .

[0095] For another example, as shown in FIG6A , at least two light-emitting devices 21 are connected in series to form a light-emitting device group 21A, and at least one light-emitting device group 21A is electrically connected to a chip 23 .

[0096] By adopting the above-mentioned setting, the chip 23 in the light-emitting substrate 2 can be used to control the light emission of multiple light-emitting devices 21, so that the light-emitting substrate 2 can conveniently control the light-emitting devices 21, ensuring that the light-emitting substrate 2 can provide backlight or partial backlight for the display panel 3.

[0097] In the case where the light-emitting substrate 2 is used to provide backlight, the light-emitting substrate 2 may further include: an optical film group located on one side of the light-emitting device 21 .

[0098] Exemplarily, the optical film assembly includes: a diffusion plate, a quantum dot film, a diffusion sheet, and a composite film, etc., which are sequentially stacked on one side of the light emitting device 21 .

[0099] For example, the diffusion plate and the diffusion sheet are used to eliminate lamp shadows and to homogenize the light emitted by the light emitting device 21 , thereby improving the light uniformity of the light emitting substrate 2 .

[0100] For example, the quantum dot film is used to convert the light emitted by the light emitting device 21. Alternatively, when the light emitted by the light emitting device 21 is blue light, the quantum dot film can convert the blue light into white light and improve the purity of the white light.

[0101] For example, the composite film is used to increase the brightness of light emitted by the light emitting device 21 .

[0102] It can be understood that the brightness of the light emitted by the light emitting device 21 after entering the above-mentioned optical film group is enhanced, and the purity and uniformity of the emitted light are higher.

[0103] In some examples, the light-emitting substrate 2 further includes a support column disposed between the light-emitting device 21 and the diffusion plate of the optical film assembly.

[0104] For example, the support column can be fixed to the wiring substrate 22 by glue. The support column can be used to support the optical film group and make the light emitted by the light emitting device 21 obtain a certain light mixing distance, thereby further eliminating the lamp shadow and improving the uniformity of the light.

[0105] The wiring substrate 22 includes multiple signal lines 221, which are used to establish electrical connections between the multiple light-emitting devices 21, between the light-emitting devices 21 and the chip 23, and between the multiple chips 23. The signal lines 221 can be made of a conductive material, specifically a metal such as copper. Copper, as a material for the signal lines 221, has advantages such as high electrical conductivity, good thermal conductivity, low thermal expansion coefficient, and a high melting point. It also offers excellent high-frequency performance and resistance to electromigration.

[0106] Specifically, as shown in FIG6A , the signal lines 221 may include a first voltage line VCC, a data line DL, an addressing line AL, a second voltage line VLED, a ground line GND, a connecting line CL, and a cascade line JL. The connecting lines CL interconnect the multiple light-emitting devices (or the pads corresponding to each light-emitting device) in a light-emitting device group 21A, thereby enabling series connection between the multiple light-emitting devices. The cascade line JL connects a light-emitting device group 21A to the corresponding second voltage signal line VLED to transmit the electrical signal transmitted by the second voltage signal line VLED to the light-emitting device. The cascade line JL also connects the chip (or the pad corresponding to each chip) to the corresponding ground line GND. The first voltage line VCC, the data line DL, and the addressing line AL are used to interconnect the individual chips (or the pads corresponding to each chip) in a column of chips.

[0107] It is understandable that the signal line 221 can be formed by a variety of different processes.

[0108] In some embodiments, the process of forming the signal line 221 is as follows: first, a first conductive layer is formed on a substrate by a vacuum sputtering process, and then a photoresist material is coated on the first conductive layer to form a first photoresist film. Then, the first photoresist film is exposed and developed to form a plurality of openings in the first photoresist film to form a first photoresist layer. Then, the first photoresist layer is used as a mask to etch the first conductive layer to remove the portion of the first conductive layer opposite the opening to form the signal line 221. The thickness of the signal line 221 prepared by the vacuum sputtering process is generally less than or equal to 3.6 μm. When the thickness of the signal line 221 exceeds 3.6 μm, in the wiring substrate 22 formed by this preparation process, the signal line 221 located in the edge area of ​​the wiring substrate 22 or in the area adjacent to the edge area is prone to peeling, thereby affecting the signal transmitted by the signal line 221, resulting in the wiring substrate 22 being unable to perform normal functions.

[0109] In other embodiments, the process of forming the signal lines includes: forming a seed layer on a substrate; forming a photoresist layer on the seed layer, wherein the photoresist layer includes a plurality of openings; and forming the signal lines within the openings using an electroplating process, using the photoresist layer as a mask. The electroplating process utilizes the migration of metal ions in an electrolyte solution containing metal ions under the action of an external electric field, resulting in a reduction reaction of the metal ions at a cathode, thereby forming a metal coating on the substrate.

[0110] Taking the case where the metal ions in the electrolyte solution are copper ions as an example, the metal coating obtained by the above method is a copper film layer. Specifically, with reference to the simplified structural diagram of the electroplating equipment 100 shown in Figure 7, the electroplating equipment 100 includes an anode 110, a holding tank 120, etc. The electrolyte solution is stored in the holding tank 120 of the electroplating equipment 100, and the anode 110 is also arranged in the holding tank 120. In the process of carrying out the electroplating process, a seed layer and a photoresist layer are first formed on the substrate to be plated 2', the substrate to be plated 2' is mounted on a carrier, and then the carrier is placed in the holding tank 120, and the carrier and the anode 110 are arranged relative to each other. The carrier and the seed layer of the substrate to be plated 2' (here, the part of the seed layer exposed by the opening of the photoresist layer) are connected to the negative output terminal of the external power supply, and the anode 110 is connected to the positive output terminal of the external power supply. When the external power supply is turned on, an electric field is formed between the anode and the seed layer of the substrate to be plated 2'. Under the action of the electric field, the metal ions in the electrolyte solution in the receiving tank 120 move to the seed layer of the substrate 2 ′ to be plated and are deposited on the seed layer to form a metal plating layer and signal lines of a preset thickness.

[0111] It is understandable that the size and distribution of the openings in the above-mentioned photoresist layer are related to the size and distribution of the signal lines 221 to be formed. The arrangement density, arrangement position, and size of the various signal lines 221 in the wiring substrate 22 are all different, which makes the distribution density, size, and distribution of the openings in the photoresist layer different, and the openings in the photoresist layer are diverse. For example, in some areas of the substrate 2' to be plated, the sizes of the various signal lines to be formed, such as width, vary greatly, the distribution of the signal lines is uneven, and the distribution is relatively dispersed. Then, during the electroplating process, the number of metal ions corresponding to the larger openings is greater, and the number of metal ions corresponding to the smaller openings is less. The number of metal ions in the electrolyte solution deposited on the seed layer corresponding to each opening varies greatly, the current density formed by the movement of the metal ions corresponding to each opening also varies greatly, and the electroplating efficiency corresponding to each opening varies greatly. Therefore, within the same electroplating time, the thickness uniformity of the metal plating layer formed in each opening is poor, and it is difficult to reach the preset thickness of the signal line 221. It is also easy to cause the resistance value of the signal line 221 to differ greatly from the preset resistance value, affecting the accuracy of the electrical signal transmitted by the signal line 221, which is not conducive to improving the luminous brightness and luminous efficiency of the light-emitting substrate 2.

[0112] Based on this, some embodiments of the present disclosure provide a wiring substrate 22 applied to the above-mentioned light-emitting substrate 2 . As shown in FIG8 , the wiring substrate 22 includes: a plurality of signal lines 221 and a substrate 222 .

[0113] In some examples, the substrate 222 may be made of an inorganic material or an organic material, or may be a composite of an organic material and an inorganic material.

[0114] For example, the material of the substrate 222 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, or nickel.

[0115] Exemplarily, the material of the substrate 222 may also be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0116] The substrate 222 has a first surface 222A, which is, for example, a substantially flat surface. The plurality of signal lines 221 are located on the first surface 222A. The plurality of signal lines 221 are used to connect to other functional devices such as the chip 23 or the light-emitting device 21 and transmit corresponding electrical signals.

[0117] As shown in FIG. 8 and FIG. 9 , the plurality of signal lines 221 include at least one target signal line 221A. The target signal line 221A includes at least one comb-shaped portion 2211 .

[0118] Exemplarily, the target signal line 221A can be any signal line among the multiple signal lines 221, for example, the target signal line 221A can be the first voltage line VCC, the data line DL, the address line AL, the second voltage line VLED, the ground line GND, the connection line CL or the cascade line JL.

[0119] For example, the plurality of signal lines 221 include one or more target signal lines 221A, for example, at least one of the first voltage line VCC, the data line DL, the address line AL, the second voltage line VLED, the ground line GND, the connection line CL and the cascade line JL is the target signal line 221A.

[0120] For example, the target signal line 221A includes one or more comb-shaped parts 2211. When the plurality of signal lines 221 include a plurality of target signal lines 221A, the number of comb-shaped parts 2211 included in the plurality of target signal lines 221A may be equal or unequal.

[0121] For another example, as shown in FIG11 , the target signal line 221A is entirely formed into a comb-shaped portion 2211 .

[0122] Continuing to refer to Figure 9, the comb-shaped portion 2211 has a comb handle portion 2212 and a plurality of comb teeth portions 2213. The comb teeth portion 2213 has a certain thickness, and the shape of the comb teeth portion 2213 in a top view can be roughly strip-shaped. The shape of the comb teeth portion 2213 in a top view can also be roughly broken line-shaped, such as an "L" shape. The size differences of the plurality of comb teeth portions 2213 are small. As shown in Figure 10, the same end of the plurality of comb teeth portions 2213 is connected to the comb handle portion 2212. There is a first gap G1 between any two adjacent comb teeth portions 2213. Thus, any two adjacent comb teeth portions 2213 are independent, and the plurality of comb teeth portions 2213 in the same comb-shaped portion 2211 are arranged at intervals. The plurality of comb teeth portions 2213 are not connected to each other.

[0123] The multiple comb-teeth 2213 in the target signal line 221A break up at least a portion of the target signal line 221A into smaller pieces. The width of the comb-teeth 2213 is smaller than that of the comb handle 2212. This allows the distribution of multiple wiring patterns (here, the wiring patterns primarily comprise the comb-teeth 2213) to be relatively uniform in the region of the substrate 222 where the comb-shaped portion 2211 of the target signal line 221A is located, with minimal differences in the dimensions, such as width, of the multiple wiring patterns. Consequently, during electroplating to form the signal line 221, the concentration of copper ions moving corresponding to each opening in the region where the comb-shaped portion 2211 is to be formed tends to be equal, or the concentration of copper ions moving due to each wiring pattern tends to be equal, resulting in a roughly equal current density generated by the copper ion movement corresponding to each wiring pattern. Therefore, in this area, the efficiency of each wiring pattern (or comb tooth portion 2213) formed by the electroplating process tends to be consistent, and within the same electroplating time, the thickness of the formed wiring pattern tends to be consistent, thereby improving the thickness uniformity of the multiple signal lines 221 in the local area to a certain extent, so that the resistance value of the multiple signal lines 221 is slightly different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0124] The embodiment of the present disclosure provides a wiring substrate 22, which includes: a substrate 222 and a plurality of signal lines 221, the substrate 222 having a first surface 222A, the plurality of signal lines 221 being located on the first surface 222A; the plurality of signal lines 221 including at least one target signal line 221A, the target signal line 221A including at least one comb-shaped portion 2211; the comb-shaped portion 2211 having a comb handle 2212 and a plurality of comb teeth 2213, the same end of the plurality of comb teeth 2213 being connected to the comb handle 2212, and a first gap G1 being provided between any two adjacent comb teeth 2213, thereby In a local area of ​​the first surface 222A of 2, the multiple comb-teeth portions 2213 in the target signal line 221A can be used to reduce the size differences of the multiple wiring patterns (herein, the wiring patterns are mainly the comb-teeth portions 2213), thereby improving the distribution uniformity of the multiple wiring patterns. In this way, in the process of forming the signal line 221 using the electroplating process, the thickness of the formed multiple wiring patterns can be made consistent, thereby improving the thickness uniformity of the multiple signal lines 221 in the local area to a certain extent, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, and facilitating the improvement of the luminous efficiency of the light-emitting substrate.

[0125] In some examples, as shown in FIG9 and FIG10 , the target signal line 221A further includes a connecting portion 2214 . The connecting portion 2214 is connected to the comb handle 2212 of the comb-shaped portion 2211 .

[0126] For example, the connecting portion 2214 and the comb-shaped portion 2211 are an integral structure.

[0127] It is understood that, as shown in Figures 9 and 10, due to the first gap G1 between any two adjacent comb-tooth portions 2213, the width W1 of the comb-shaped portion 2211 can be greater than or equal to the width W2 of the connecting portion 2214 connected thereto. Here, the width of the comb-shaped portion 2211 refers to the dimension of the comb-shaped portion 2211 as a whole along a direction perpendicular to the extension of the comb-tooth portions 2213, and the width of the connecting portion 2214 refers to the dimension of the connecting portion 2214 along its extension direction.

[0128] Therefore, the above-mentioned setting can make the size of the connecting portion 2214 of the same target signal line 221A relatively smaller than that of the comb-shaped portion 2211, thereby reducing the area and space occupied by the target signal line 221A on the substrate 222 to a certain extent, thereby helping to simplify the layout design of the signal line 221 on the substrate 222 and optimizing the layout design of the signal line 221.

[0129] In some examples, as shown in FIG10 , the sum of the widths W3 of the plurality of comb-tooth portions 2213 of the comb-shaped portion 2211 is equal to the width W2 of the connecting portion 2214. Here, the width of the comb-tooth portion 2213 refers to the dimension of the comb-tooth portion 2213 along a direction perpendicular to the extension of the comb-tooth portion 2213. It will be appreciated that in this case, since there is a first gap G1 between any two adjacent comb-tooth portions 2213, the width W1 of the comb-shaped portion 2211 is greater than the width W2 of the connecting portion 2214 to which it is connected.

[0130] In this way, the consistency of the electrical performance between the connecting part 2214 of the target signal line 221A and the comb-shaped part 2211 can be improved, and the accuracy of the electrical signal transmitted by the target signal line 221A can be improved, which is beneficial to improving the luminous efficiency of the light-emitting substrate 2, avoiding affecting the electrical performance such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0131] The width W2 of the connecting portion 2214 may be positively correlated with the number of comb teeth 2213 included in the comb-shaped portion 2211 to which it is connected. For example, the larger the width W2 of the connecting portion 2214, the greater the number of comb teeth 2213 included in the comb-shaped portion 2211 to which it is connected. The smaller the width W2 of the connecting portion 2214, the fewer the number of comb teeth 2213 included in the comb-shaped portion 2211 to which it is connected.

[0132] It is understandable that within the same comb-shaped portion 2211, the width of each comb-tooth portion 2213 may be equal or unequal, and the width of the first gap G1 between any two adjacent comb-tooth portions 2213 may be equal or unequal. The widths of the comb-tooth portions 2213 in different comb-shaped portions 2211 may be equal or unequal. The widths of the first gaps G1 in different comb-shaped portions 2211 may be equal or unequal. The embodiments of the present disclosure are not limited in this regard.

[0133] In some examples, as shown in FIG. 10 , the width W3 of each comb-tooth portion 2213 is equal.

[0134] For example, in the same comb-shaped portion 2211, the lengths of the comb teeth 2213 are equal or substantially equal. Here, the length of the comb teeth 2213 refers to the dimension of the comb teeth 2213 along its extension direction. Thus, in the same comb-shaped portion 2211, the areas of the comb teeth 2213 can be equal or substantially equal.

[0135] For another example, when the same target signal line 221A includes multiple comb-shaped portions 2211, the width value W3 of each comb tooth portion 2213 in the multiple comb-shaped portions 2211 is equal or approximately equal, and the lengths of the comb tooth portions 2213 of different comb-shaped portions 2211 may be equal or unequal.

[0136] For another example, when the wiring substrate 22 includes multiple target signal lines 221A, and each target signal line 221A includes one or more comb-shaped portions 2211, the widths W3 of the comb teeth 2213 in each comb-shaped portion 2211 are equal or substantially equal. The lengths of the comb teeth 2213 in each comb-shaped portion 2211 may be equal or unequal.

[0137] By adopting the above-mentioned setting, the sizes of multiple wiring patterns (the wiring pattern here can be the comb tooth portion 2213) in the area where the comb-shaped portion 2211 of the target signal line 221A is located on the substrate 222 can be similar, which is conducive to achieving uniform distribution of multiple wiring patterns. Therefore, in the process of forming the signal line 221 using the electroplating process, in this area, the concentration difference of copper ion movement caused by the above-mentioned multiple wiring patterns is small, and the current density formed by the copper ion movement corresponding to the multiple wiring patterns is roughly equal. The efficiency of the electroplating process to form each wiring pattern will also tend to be consistent. Within the same electroplating time, the thickness of each wiring pattern formed tends to be consistent, thereby improving the thickness uniformity of the multiple signal lines 221 to a certain extent, so that the resistance values ​​of the multiple signal lines 221 are slightly different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is conducive to improving the luminous efficiency of the light-emitting substrate 2, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0138] In some examples, as shown in Figures 9 and 10 , in the same comb-shaped portion 2211 , the widths of the first gaps G1 between any two adjacent comb-tooth portions 2213 are equal or substantially equal. The comb-tooth portions 2213 are arranged at equal intervals.

[0139] Here, the width of the first gap G1 refers to a dimension of the first gap G1 along a direction perpendicular to the extending direction of the comb-tooth portion 2213 .

[0140] Therefore, in the area where the comb-shaped portion 2211 of the target signal line 221A is located on the substrate 222, the distribution of multiple wiring patterns (the wiring pattern here can be the comb-tooth portion 2213) on the substrate 222 tends to be uniform or approximately uniform, and the current density corresponding to each wiring pattern tends to be equal, so that the thickness of the formed target signal line 221A is relatively uniform, and the thickness of the signal line 221 in at least a local area on the substrate 222 is relatively uniform, so that the resistance value of the signal line 221 is slightly different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0141] In some examples, as shown in Figures 12 to 14 , the wiring substrate 22 further includes at least one dummy conductive pattern 223 located on the first surface 222A. Each dummy conductive pattern 223 is located on one side of a signal line 221 and is disposed on the same layer as the signal line 221 .

[0142] For example, the wiring substrate 22 includes one or more dummy conductive patterns 223 .

[0143] For example, if multiple signal lines 221 are disposed in one region of the substrate 222 and one dummy conductive pattern 223 is located on one side of the signal line 221, then the dummy conductive pattern 223 is disposed on one side of the entirety formed by the multiple signal lines 221. If multiple signal lines 221 are disposed in another region of the substrate 222 and multiple dummy conductive patterns 223 are located on one side of the signal line 221, then the multiple dummy conductive patterns 223 are disposed on the same side of the entirety formed by the multiple signal lines 221, or the multiple dummy conductive patterns 223 are disposed on opposite sides of the entirety formed by the multiple signal lines 221. It can be considered that the dummy conductive patterns 223 are located outside the corresponding multiple signal lines 221.

[0144] The material of the dummy conductive pattern 223 and the signal line 221 can be the same, for example, copper. Thus, the dummy conductive pattern 223 and the signal line 221 can be formed simultaneously using a single electroplating process, which simplifies the manufacturing process of the wiring substrate 22 and the light-emitting substrate 2.

[0145] The dummy conductive pattern 223 is insulated from the signal line 221. For example, the dummy conductive pattern 223 is not connected to or in contact with the adjacent signal line 221. Of course, other suitable insulation methods are not excluded. The dummy conductive pattern 223 can be considered a sacrificial pattern and is not used for signal transmission. This prevents the dummy conductive pattern 223 from becoming a load on the signal line 221 and affecting the accuracy of signal transmission.

[0146] Through the above arrangement, during the process of forming the signal line 221 using the electroplating process, a dummy conductive pattern 223 is simultaneously formed. In the case where the spatial arrangement or spatial layout of multiple signal lines 221 to be plated on the wiring substrate 22 is different, by providing the dummy conductive pattern 223 on one side of the signal line 221, the dummy conductive pattern 223 is used to improve or adjust the distribution uniformity of the wiring pattern (herein, the wiring pattern includes the dummy conductive pattern 223 and the signal line 221) in the area where the signal line 221 is located, so that the distribution of multiple wiring patterns in the area tends to be uniform, the current density corresponding to the multiple wiring patterns is roughly equal, and the electroplating efficiency is close, thereby making the thickness of the signal line 221 formed in the area more uniform. The thickness of the signal line 221 in at least a partial area on the substrate 222 is more uniform, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and thus avoiding affecting the luminescence of the light-emitting device 21.

[0147] It is understandable that, as shown in Figure 7, during the electroplating process, an electric field is formed between the wiring substrate to be plated 2' and the anode 110, and the electric field strength is generally characterized by the number and density of electric field lines EFL. In the region of the wiring substrate to be plated 2' shown in Figure 7, the electric field lines EFL at the edge of the region are distributed more dispersedly, and the number of electric field lines is relatively large, while the electric field lines EFL at the middle part of the region are distributed more evenly, and the number of electric field lines is relatively small. The electric field strength is positively correlated with the migration rate of copper ions. The greater the electric field strength, the faster the copper ion migration rate caused by it, which can improve electroplating efficiency to a certain extent. Therefore, the thickness of the wiring pattern or signal line formed at the edge of the region is larger, but because the electric field lines are distributed more dispersedly, the thickness uniformity at different positions of the same wiring pattern is poor in the wiring pattern at the edge. The thickness of the wiring pattern or signal line in the middle part of this area is relatively small, but since the electric field lines are distributed more evenly, the thickness uniformity of the wiring pattern at different positions of the same wiring pattern in the middle part is better. Therefore, the thickness of each signal line at different positions of the wiring substrate, such as the edge and the middle part, varies greatly and has poor uniformity.

[0148] In the embodiment of the present disclosure, a dummy conductive pattern 223 is disposed on one side of a signal line 221. During the electroplating process, the signal line 221 to be plated can be disposed in the middle portion where the electric field lines are more evenly distributed and fewer electric field lines are present. This results in a more uniform thickness for the multiple signal lines 221 formed, and better thickness uniformity at different locations on the same signal line 221. The dummy conductive pattern 223 to be plated is located at the edge where the electric field lines are more dispersed and more electric field lines are present, resulting in a thicker dummy conductive pattern 223 formed, and poorer thickness uniformity across the same dummy conductive pattern 223. However, since the dummy conductive pattern 223 serves as a sacrificial pattern, the thickness uniformity of the dummy conductive pattern 223 itself does not need to be considered. Therefore, the embodiment of the present disclosure utilizes the dummy conductive pattern 223 to, to a certain extent, ensure the thickness uniformity of the signal line 221, thereby improving the accuracy of the electrical signal transmitted by the signal line 221 and facilitating improved luminous efficiency of the light-emitting substrate 2.

[0149] In the case where the wiring substrate 22 includes a plurality of dummy conductive patterns 223 , there are multiple ways to set the relative positional relationship between the plurality of dummy conductive patterns 223 and the corresponding signal lines 221 , which can be selected and set according to actual conditions.

[0150] 13A , multiple dummy conductive patterns 223 are provided on the same side of the signal line 221. Specifically, in FIG13A , multiple dummy conductive patterns 223 are provided on the left side of the connection line CL and multiple dummy conductive patterns 223 are provided on the right side of the address line AL.

[0151] In this way, the signal line 221 can be located relatively close to the middle among multiple wiring patterns (the wiring pattern here refers to the pattern of the signal line 221 and the virtual conductive pattern 223 located on the same side of the signal line 221) to a certain extent, so that the signal line 221 to be plated is located in an area where the electric field lines are more evenly distributed, so that the thickness of the formed signal line 221 is more uniform.

[0152] In other examples, at least one dummy conductive pattern 223 is provided on both sides of the signal line 221. Specifically, in FIG13A , multiple dummy conductive patterns 223 are provided on both upper and lower sides of the cascade line JL in the signal line 221. In FIG14 , multiple dummy conductive patterns 223 are provided on opposite sides of the connection line CL.

[0153] In this way, it can be ensured that the signal line 221 is located relatively close to the middle position among multiple wiring patterns (the wiring pattern here refers to the pattern of the signal line 221 and the virtual conductive pattern 223 located on both sides of the signal line 221), thereby ensuring that the signal line 221 to be plated is located in an area where the electric field lines are more evenly distributed, so that the thickness of the formed signal line 221 is more uniform.

[0154] In some other examples, multiple dummy conductive patterns 223 are provided on the same side of the signal line 221 , and at least one dummy conductive pattern 223 is provided on both sides of the signal line 221 . For example, two dummy conductive patterns 223 are provided on both sides of the signal line 221 .

[0155] In this way, it can be ensured that the signal line 221 is located near the middle of multiple wiring patterns (the wiring pattern here refers to the pattern of the signal line 221 and the virtual conductive pattern 223 located on both sides of the signal line 221), thereby ensuring that the signal line 221 to be plated is located in an area where the electric field lines are more evenly distributed, thereby ensuring the uniformity of the thickness of the formed signal line 221.

[0156] In some examples, as shown in FIG. 14 , a second gap G2 is formed between the signal line 221 and the adjacent dummy conductive pattern 223 .

[0157] The width of the second gap G2 is equal to or substantially equal to the width of the first gap G1. The width of the second gap G2 refers to the distance between the dummy conductive pattern 223 and the signal line 221 along the extending direction perpendicular to the dummy conductive pattern 223 or the adjacent signal line 221.

[0158] This is beneficial to improving the distribution uniformity of the wiring pattern on the substrate 222, and to a certain extent ensures the thickness uniformity of the signal line 221, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate.

[0159] In some examples, as shown in FIG14 , a plurality of dummy conductive patterns 223 are provided on the same side of the signal line 221 , a second gap G2 is provided between adjacent signal lines 221 and dummy conductive patterns 223 , and a third gap G3 is provided between any two adjacent dummy conductive patterns 223 .

[0160] For example, the width of the second gap G2 is equal to or substantially equal to the width of the third gap G3.

[0161] For another example, the width of the second gap G2 is equal to or substantially equal to the width of the first gap G1.

[0162] For another example, the width of the second gap G2 is equal to or substantially equal to the width of the third gap G3, and the width of the second gap G2 is equal to or substantially equal to the width of the first gap G1. When the plurality of comb-tooth portions 2213 are adjacent to the plurality of dummy conductive patterns 223, the plurality of comb-tooth portions 2213 and the plurality of dummy conductive patterns 223 are arranged at equal intervals.

[0163] In this way, the wiring pattern can be distributed more evenly on the substrate 222, and the thickness uniformity of the signal line 221 can be ensured to a certain extent, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate.

[0164] It can be understood that when the width values ​​of the first gap G1, the second gap G2, and the third gap G3 are equal or approximately equal, and the width value W4 of each dummy conductive pattern 223 is equal to the width value W3 of each adjacent comb-tooth portion 2213, the distribution of the multiple wiring patterns (herein, the wiring pattern refers to the aforementioned comb-tooth portions and each dummy conductive pattern) is relatively uniform, and the size differences of the multiple wiring patterns are relatively small. Therefore, during the electroplating process, the electroplating efficiency of each wiring pattern tends to be consistent, which is conducive to improving the thickness uniformity of the formed signal line. Moreover, because the extension direction of the dummy conductive pattern 223 and the adjacent comb-tooth portion 2213 is generally consistent, the multiple comb-tooth portions 2213 are located near the middle of the multiple wiring patterns. During the electroplating process, the thickness uniformity of the comb-tooth portion 2213 or the signal line 221 located in the middle can be further improved, which is conducive to improving the luminous brightness of the light-emitting substrate 2.

[0165] In some examples, as shown in FIG14 , the widths W4 of the plurality of dummy conductive patterns 223 can be substantially equal or equal. The widths W3 of the comb-tooth portions 2213 of different target signal lines 221A can be equal or substantially equal. The widths W4 of each dummy conductive pattern 223 are equal or substantially equal to the widths W3 of each comb-tooth portion 2213.

[0166] For example, the width W4 of the dummy conductive pattern 223 refers to the dimension of the dummy conductive pattern 223 along a direction perpendicular to the extension of the dummy conductive pattern 223. The extension direction of the dummy conductive pattern 223 is the same as or substantially the same as the extension direction of the adjacent signal line 221, and is also the same as or substantially the same as the extension direction of the comb-tooth portion 2213 of the adjacent target signal line 221A.

[0167] Therefore, when the length of each dummy conductive pattern 223 is equal to or approximately equal to the length of each comb tooth portion 2213, the area occupied by each dummy conductive pattern 223 on the substrate 222 is equal to or approximately equal to the area occupied by each comb tooth portion 2213 on the substrate 222, which is beneficial to improving the distribution uniformity of the wiring pattern on the substrate 222, so that the number of metal ions that migrate corresponding to each opening or each wiring pattern is approximately equal, and the current density corresponding to each wiring pattern is approximately equal, so that the electroplating efficiency of each wiring pattern tends to be equal, and then the thickness difference of each wiring pattern is relatively small, which ensures the thickness uniformity of the signal line 221 composed of each wiring pattern to a certain extent, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate 2.

[0168] 8 and 9 , the wiring substrate 22 further includes a plurality of first-type pad units 224 and a plurality of second-type pad units 225 located on the first surface 222A. The second-type pad units 225 include a plurality of device pad groups 226 .

[0169] 6A and 9 , the first-type pad unit 224 can be connected to the chip 23 (e.g., the pins of the chip), and can include a plurality of pads 227. The device pad group 226 of the second-type pad unit 225 can be connected to the light-emitting device 21 (e.g., the pins of the light-emitting device), and can also include a plurality of pads 227.

[0170] It is understandable that the wiring substrate 22 further includes: an insulating layer (not shown in FIG9 ) provided on the side of the signal line 221 away from the substrate. The insulating layer includes a plurality of vias. The orthographic projection of at least one via on the substrate is located within the orthographic projection of at least one signal line 221 on the substrate, and the via exposes the surface of a local area of ​​the signal line 221 away from the substrate. The exposed local area of ​​the surface of the signal line 221 constitutes the pad 227, that is, the pad 227 is part of the signal line 221. The position of the via can correspond to the end of the signal line 221. Soldering material (such as tin) and / or fluxing material can also be provided between the pad and the pin to which it is connected, which is not limited in the present disclosure.

[0171] As shown in FIG8 , the plurality of signal lines 221 include a plurality of first-type signal lines 2215, a plurality of second-type signal lines 2216, and a plurality of third-type signal lines 2217. The two first-type signal lines 2215 are located on opposite sides of the second-type pad unit 225. The plurality of second-type signal lines 2216 and the plurality of third-type signal lines 2217 are located between the two first-type signal lines 2215.

[0172] One first-type pad unit 224 is electrically connected to at least one second-type pad unit 225 via a second-type signal line 2216. For example, one first-type pad unit 224 is electrically connected to one second-type pad unit 225 via a second-type signal line 2216. For another example, multiple first-type pad units 224 are electrically connected to multiple second-type pad units 225 via multiple second-type signal lines 2216. Thus, control of the chip 23 and the corresponding light-emitting device 21 can be achieved.

[0173] The multiple device pad groups 226 within the same second-type pad unit 225 are connected via the second-type signal line 2216. The second-type pad unit 225 is connected to the adjacent first-type signal line 2215 via the second-type signal line 2216. As a result, the multiple device pad groups 226 within the same second-type pad unit 225 are connected in series, so that the same second-type pad unit 225 can be connected to the first-type pad unit 224 as a whole, thereby simplifying the design of the wiring substrate 22.

[0174] The first-class pad unit 224 is connected to the adjacent first-class signal line 2215 through the second-class signal line 2216. Multiple first-class pad units 224 are arranged into multiple columns. Multiple first-class pad units 224 located in the same column are connected through multiple third-class signal lines 2217. In this way, the connection between multiple first-class pad units 224 is achieved, which is conducive to simplifying the design of the wiring substrate 22.

[0175] In some examples, as shown in Figures 12 to 14, the dummy conductive pattern 223 includes a first-type dummy conductive pattern 2231. The first-type dummy conductive pattern 2231 extends at least along the overall direction of multiple device pad groups 226 in the same second-type pad unit 225 and multiple second-type signal lines 2216 connected to the multiple device pad groups 226.

[0176] Therefore, the direction of the first-class virtual conductive pattern 2231 is consistent or substantially consistent with the outline or direction of the multiple second-class signal lines 221 between the multiple device pad groups 226 in the corresponding same second-class pad unit 225, so that to a certain extent, the multiple second-class signal lines 221 can be located relatively close to the middle position in the multiple wiring patterns (the wiring pattern here refers to the pattern of the multiple second-class signal lines 221 and the first-class virtual conductive pattern 2231), thereby making the signal line 221 to be plated located in an area where the electric field line distribution is relatively uniform, so that the thickness of the formed signal line 221 is relatively uniform.

[0177] 13A to 14 , when the wiring substrate 22 includes a plurality of first-type dummy conductive patterns 2231 , at least two first-type dummy conductive patterns 2231 are respectively arranged on opposite sides along an extension direction perpendicular to the second-type signal line 2216 .

[0178] For example, two first-type dummy conductive patterns 2231 are respectively disposed on two opposite sides perpendicular to the extending direction of the second-type signal line 2216 .

[0179] For another example, two of the three first-type dummy conductive patterns 2231 are arranged on one side along the extension direction perpendicular to the second-type signal line 2216, and the other first-type dummy conductive pattern 2231 is arranged on the other side along the extension direction perpendicular to the second-type signal line 2216.

[0180] For another example, two of the four first-type dummy conductive patterns 2231 are arranged on one side along the extension direction perpendicular to the second-type signal line 2216, and the other two first-type dummy conductive patterns 2231 are arranged on the other side along the extension direction perpendicular to the second-type signal line 2216.

[0181] In this way, the multiple signal lines 221 can be located relatively close to the middle of the multiple wiring patterns (the wiring patterns here refer to the patterns of the multiple signal lines 221 and the first type of virtual conductive patterns 2231) to a certain extent, so that the signal lines 221 to be plated are located in an area where the electric field lines are more evenly distributed, so that the thickness of the formed signal lines 221 is more uniform.

[0182] The inventors conducted experiments on the uniformity of multiple wiring patterns formed on a substrate using an electroplating process. Specifically, an area on the substrate was selected, as shown in Figure 15. The horizontal axis in the figure represents the size of the substrate along the first direction X, and the vertical axis in the figure represents the size of the substrate along the second direction Y. Each rectangle in the figure represents a sub-area and the wiring pattern obtained by the electroplating process in the sub-area. There are five wiring patterns to be plated in the area. The two wiring patterns located on opposite sides of the five wiring patterns are dummy conductive patterns 223, and the three wiring patterns in the middle can be three comb teeth 2213. The sizes of the five wiring patterns are roughly equal, and any two adjacent wiring patterns are arranged at equal intervals. The thickness of each wiring pattern is measured using a film thickness meter, and different thickness values ​​are converted into different colors, and the graph is obtained as Figure 15.

[0183] In Figure 15, the different colors of the wiring pattern parts represent different thicknesses. Specifically, the redder part represents that the thickness of the wiring pattern part is greater, and the bluer part represents that the thickness of the wiring pattern part is smaller.

[0184] As shown in Figure 15 , the color of each dummy conductive pattern 223 transitions from red to blue, with the center portion of the dummy conductive pattern 223 approaching blue and the edge portion of the dummy conductive pattern 223 approaching red. There is a significant color difference between the center and edge portions of the dummy conductive pattern 223. The thickness of the dummy conductive pattern 223 fluctuates between approximately 4.9 mm and 5.4 mm, with a wide range of thickness fluctuations, resulting in poor thickness uniformity. The color of each comb-tooth portion 2213 is approximately blue, with minimal color difference between the edge and center portions of each comb-tooth portion 2213. The thickness of each comb-tooth portion 2213 fluctuates between approximately 4.7 mm and 4.9 mm, with a narrow range of thickness fluctuations, resulting in good thickness uniformity across the comb-tooth portions 2213. It can be seen that setting two dummy conductive patterns 223 respectively on opposite sides of the plurality of comb teeth 2213 or the signal line can improve the thickness uniformity of the signal line 221 to a certain extent, which is beneficial to improving the luminous brightness of the light-emitting substrate 2.

[0185] In some examples, as shown in Figures 12 and 13A, the first type of pad unit 224 is connected to multiple second type of pad units 225, and two first type of dummy conductive patterns 2231 are respectively arranged on opposite sides along the extension direction perpendicular to the second type of signal line 2216, and multiple second type of pad units 225 are arranged in a row, and the two first type of dummy conductive patterns 2231 located between any two adjacent second type of pad units 225 are connected to each other.

[0186] Therefore, it is easy to arrange the first type dummy conductive patterns 2231 , thereby reducing the difficulty of preparing the first type dummy conductive patterns 2231 and the wiring substrate 22 .

[0187] 13A , the dummy conductive pattern 223 includes a second-type dummy conductive pattern 2232. The second-type dummy conductive pattern 2232 extends along at least two adjacent first-type pad units 224 and the plurality of third-type signal lines 2217 and second-type signal lines 2216 connected thereto.

[0188] Therefore, the direction of the second-type virtual conductive pattern 2232 is consistent or substantially consistent with the overall direction of the above-mentioned third-type signal line 2217 and the second-type signal line 2216, so that to a certain extent, the multiple third-type signal lines 2217 and the second-type signal lines 2216 can be located relatively close to the middle position among the multiple wiring patterns (the wiring pattern here refers to the pattern of the multiple second-type signal lines 2216, the pattern of the multiple third-type signal lines 2217 and the second-type virtual conductive pattern 2232), thereby making the signal line 221 to be plated (here refers to the third-type signal line 2217 and the second-type signal line 2216 to be plated) located in an area where the electric field lines are more evenly distributed, so that the thickness of the formed signal line 221 is more uniform.

[0189] In some examples, as shown in Figure 13A, when the wiring substrate 22 includes multiple second-type dummy conductive patterns 2232, at least two second-type dummy conductive patterns 2232 are respectively arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines 2217 and on opposite sides along the direction perpendicular to the second-type signal line 2216.

[0190] For example, two second-type dummy conductive patterns 2232 are respectively disposed on two opposite sides along a direction perpendicular to the extension direction of the plurality of third-type signal lines 2217 and on two opposite sides along a direction perpendicular to the second-type signal lines 2216 .

[0191] For example, two of the three second-type dummy conductive patterns 2232 are arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines 2217 and on one side along the direction perpendicular to the second-type signal line 2216, and the other second-type dummy conductive pattern 2232 is arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines 2217 and on the other side along the direction perpendicular to the second-type signal line 2216.

[0192] For example, two of the four second-type dummy conductive patterns 2232 are arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines 2217 and on one side along the direction perpendicular to the second-type signal line 2216, and the other two second-type dummy conductive patterns 2232 are arranged on opposite sides along the extension direction perpendicular to the multiple third-type signal lines 2217 and on the other side along the direction perpendicular to the second-type signal line 2216.

[0193] In this way, the multiple signal lines 221 can be located relatively close to the middle of the multiple wiring patterns (the wiring patterns here refer to the patterns of the multiple second-type signal lines 2216 and the third-type signal lines 2217 and the second-type virtual conductive patterns 2232) to a certain extent, so that the signal lines 221 to be plated are located in an area where the electric field lines are more evenly distributed, so that the thickness of the formed signal lines 221 is more uniform.

[0194] In some examples, as shown in Figure 13B, when the dummy conductive pattern 223 includes a first-type dummy conductive pattern 2231, a second-type dummy conductive pattern 2232 located on one side of multiple third-type signal lines 2217 and adjacent to the second-type signal line 2216 is connected to the adjacent first-type dummy conductive pattern 2231.

[0195] Therefore, it is easy to arrange the first type dummy conductive patterns 2231 and the second type dummy conductive patterns 2232 , thereby reducing the difficulty of preparing the wiring substrate 22 .

[0196] There are many types of the signal lines 221 , which can be selected and set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0197] In some examples, as shown in FIG. 9 , FIG. 11 and FIG. 14 , the second-type signal line 2216 includes the cascade line JL or the connection line CL.

[0198] For example, when the second-type signal line 2216 includes a cascade line JL, the cascade line JL is used to connect the first-type pad unit 224 with the corresponding second-type signal line 2216. When the second-type signal line 2216 includes a connection line CL, the connection line CL is used to connect multiple device pad groups 226 in the same second-type pad unit 225, and to connect the second-type pad unit 225 with the first-type pad unit 224.

[0199] Therefore, when the cascade line JL or the connecting line CL is the target signal line 221A, the cascade line JL or the connecting line CL includes a comb-shaped portion 2211, so that the distribution of multiple wiring patterns in the area where the cascade line JL or the connecting line CL is located is relatively uniform, and the sizes of the multiple wiring patterns are relatively small. Therefore, in the process of forming the signal line 221 using the electroplating process, in the area where the comb-shaped portion 2211 is to be formed, the concentration of copper ion movement caused by multiple wiring patterns tends to be equal, so that the current density formed by the copper ion movement also tends to be roughly equal. Therefore, in this area, the efficiency of each wiring pattern formed by the electroplating process tends to be consistent, and within the same electroplating time, the thickness of each wiring pattern formed tends to be consistent, thereby improving the thickness uniformity of the connecting line CL (or cascade line JL) to a certain extent, so that the resistance value of the connecting line CL (or cascade line JL) is slightly different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0200] In addition, a dummy conductive pattern 223 is provided on one side of the cascading line JL or the connecting line CL, so that the cascading line JL or the connecting line CL is located in a relatively middle position among multiple wiring patterns, thereby further ensuring that the thickness of the cascading line JL or the connecting line CL is relatively uniform. To a certain extent, the thickness uniformity of the cascading line JL and the connecting line CL can be ensured, thereby improving the accuracy of the electrical signal transmitted by the cascading line JL and the connecting line CL, which is beneficial to improving the luminous efficiency of the light-emitting substrate 2.

[0201] In other examples, as shown in FIG. 8 , FIG. 9 and FIG. 13A , the third type signal line 2217 includes at least one of a first voltage line VCC, a data line DL and an address line AL.

[0202] For example, when the third-type signal line 2217 is a first voltage line VCC, the first voltage line VCC is used to electrically connect at least two first-type pad units 224 and to transmit a first voltage signal. When the third-type signal line 2217 is a data line DL, the data line DL is used to electrically connect at least two first-type pad units 224 and to transmit a data signal. When the third-type signal line 2217 is an address line AL, the address line AL is used to electrically connect at least two first-type pad units 224 and to transmit an address signal.

[0203] Taking the third-type signal line 2217 as the first voltage line VCC as an example, the first voltage line VCC can be the target signal line 221A. The first voltage line VCC includes a comb-shaped portion 2211, so that the distribution of multiple wiring patterns in the area where the first voltage line VCC is located is relatively uniform, and the sizes of the multiple wiring patterns, such as width, are relatively small. Therefore, in the process of forming the signal line 221 using the electroplating process, in the area where the comb-shaped portion 2211 is to be formed, the concentration of copper ion movement caused by the multiple wiring patterns tends to be equal, so that the current density formed by the copper ion movement also tends to be roughly equal. Therefore, in this area, the efficiency of the first voltage line VCC formed by the electroplating process tends to be consistent, and within the same electroplating time, the thicknesses of the multiple comb-tooth portions of the formed first voltage line VCC tend to be consistent, thereby improving the thickness uniformity of the first voltage line VCC to a certain extent, so that the resistance values ​​of the multiple first voltage lines VCC are less different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the first voltage line VCC, which is beneficial to improving the luminous efficiency of the light-emitting substrate 2, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0204] In addition, the routing of the first voltage line VCC, the data line DL and the addressing line AL is roughly the same. A dummy conductive pattern 223 is provided on one side of the whole formed by the first voltage line VCC, the data line DL and the addressing line AL, so that the first voltage line VCC, the data line DL and the addressing line AL are located in a relatively middle position of multiple wiring patterns, thereby ensuring the thickness uniformity of the first voltage line VCC, the data line DL and the addressing line AL to a certain extent, and improving the accuracy of the electrical signal transmitted by the first voltage line VCC, the data line DL and the addressing line AL, which is beneficial to improving the luminous efficiency of the light-emitting substrate 2.

[0205] In some other examples, as shown in FIG. 8 , FIG. 9 , FIG. 12 , and FIG. 13A , the first-type signal line 2215 includes at least one of a ground line GND and a second voltage line VLED.

[0206] For example, when the first-type signal line 2215 includes a ground line GND, the ground line GND is connected to the first-type pad unit 224 through the second-type signal line 2216 or the cascade line JL. When the first-type signal line 2215 includes a second voltage line VLED, the second voltage line VLED is connected to the second-type pad unit 225 through the second-type signal line 2216 or the cascade line JL.

[0207] For example, the ground line GND and the second voltage line VLED extend in substantially the same direction.

[0208] It can be understood that when the ground line GND or the second voltage line VLED is the target signal line 221A, the thickness uniformity of the first-type signal line 2215 can be improved to a certain extent, so that the resistance values ​​of multiple first-type signal lines 2215 are slightly different from the preset resistance values, thereby improving the accuracy of the electrical signal transmitted by the ground line GND or the second voltage line VLED.

[0209] In yet other examples, the second-type signal lines 2216 include cascade lines JL or connection lines CL, and the third-type signal lines 2217 include at least one of the first voltage lines VCC, the data lines DL, and the address lines AL. Furthermore, the first-type signal lines 2215 include at least one of the ground lines GND and the second voltage lines VLED. This can improve the thickness uniformity of the signal lines 221, thereby increasing the luminous efficiency of the light-emitting substrate.

[0210] On the other hand, the present disclosure further provides a method for preparing a wiring substrate 22, which is used to prepare the wiring substrate 22 described in any of the above embodiments. As shown in FIG16 , the preparation method includes S100 to S200.

[0211] S100 , as shown in FIG. 17 , provides a substrate 222 , wherein the substrate 222 has a first surface 222A.

[0212] The material of the substrate 222 can refer to the description in some of the above embodiments of the present disclosure, and will not be repeated here.

[0213] At step S200, as shown in FIG24 , a plurality of signal lines 221 are formed on the first surface 222A. The plurality of signal lines 221 include at least one target signal line 221A, which includes at least one comb-shaped portion 2211. The comb-shaped portion 2211 includes a handle 2212 and a plurality of comb teeth 2213. The plurality of comb teeth 2213 are connected to the handle 2212 at the same end, and a first gap G1 is defined between any two adjacent comb teeth 2213.

[0214] For example, the signal lines 221 may be made of a metal material, such as copper. The manufacturing process of the plurality of signal lines 221 may include an electroplating process.

[0215] The embodiment of the present disclosure provides a method for preparing a wiring substrate 22, wherein a plurality of signal lines 221 are formed on a first surface 222A of the substrate 222, wherein the plurality of signal lines 221 include at least one target signal line 221A, wherein the target signal line 221A includes at least one comb-shaped portion 2211, wherein the comb-shaped portion 2211 has a comb handle 2212 and a plurality of comb teeth 2213, wherein the same end of the plurality of comb teeth 2213 is connected to the comb handle 2212, and a first gap G1 is provided between any two adjacent comb teeth 2213. Thus, in a local area of ​​the first surface 222A of the substrate 222, the plurality of comb teeth 2213 in the target signal line 221A can be utilized to reduce the number of wiring patterns (here, the wiring pattern is mainly the comb teeth) 2213), the size differences of each wiring pattern improve the distribution uniformity of multiple wiring patterns. In this way, in the process of forming the signal line 221 using the electroplating process, the current density caused by each wiring pattern to be plated tends to be consistent, the electroplating efficiency tends to be consistent, and within the same electroplating time, the thickness of the multiple wiring patterns formed tends to be consistent, thereby improving the thickness uniformity of the multiple signal lines 221 in the local area to a certain extent, so that the resistance value of the multiple signal lines 221 is less different from the preset resistance value, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and further avoiding affecting the luminescence of the light-emitting device 21.

[0216] Regarding the structure of the comb-shaped portion 2211 , reference may be made to the description in some of the above embodiments of the present disclosure, which will not be repeated here.

[0217] In some examples, in the above S200 , forming a plurality of signal lines 221 on the first surface 222A includes: S210 .

[0218] S210, as shown in FIG24, uses the same patterning process to simultaneously form multiple signal lines 221 and at least one dummy conductive pattern 223 on the first surface 222A. The dummy conductive pattern 223 is located on one side of a signal line 221 and is disposed on the same layer as the signal line 221. The dummy conductive pattern 223 is insulated from the signal line 221.

[0219] Through the above-mentioned setting, the signal line 221 and the dummy conductive pattern 223 are formed synchronously in the same composition process. When there are differences in the spatial arrangement or spatial layout of multiple signal lines 221 to be plated on the wiring substrate 22, by setting the dummy conductive pattern 223 on one side of the signal line 221, the dummy conductive pattern 223 can be used to improve or adjust the distribution uniformity of the wiring pattern (the wiring pattern here includes the dummy conductive pattern 223 and the signal line 221) in the area where the signal line 221 is located, so that the distribution of multiple wiring patterns in the area tends to be uniform, the current density corresponding to the multiple wiring patterns is roughly equal, and the electroplating efficiency is close, so that the thickness of the signal line 221 formed in the area is relatively uniform, and the thickness of the signal line 221 in at least a local area on the substrate 222 is relatively uniform, thereby improving the accuracy of the electrical signal transmitted by the signal line 221, which is beneficial to improving the luminous efficiency of the light-emitting substrate, avoiding affecting the electrical properties such as the resistance of the signal line 221, and thus avoiding affecting the luminescence of the light-emitting device 21.

[0220] Furthermore, by placing the dummy conductive pattern 223 on one side of the signal line 221, during the electroplating process, the signal line 221 to be plated can be placed in the middle portion, where the electric field lines are more evenly distributed and fewer, thereby making the thickness of the multiple signal lines 221 more uniform. Furthermore, the thickness uniformity of the same signal line 221 at different locations is also better. This ensures the uniformity of the thickness of the signal line 221 to a certain extent, thereby improving the accuracy of the electrical signal transmitted by the signal line 221 and facilitating the improvement of the luminous efficiency of the light-emitting substrate 2.

[0221] Regarding the structure of the dummy conductive pattern 223 , reference may be made to the description in some of the above embodiments of the present disclosure, which will not be repeated here.

[0222] In some examples, in the above S210 , a same patterning process is used to simultaneously form a plurality of signal lines 221 and at least one dummy conductive pattern 223 on the first surface 222A, including: S211 to S213 .

[0223] S211 , as shown in FIG. 19 , a seed layer 228 is formed on the first surface 222A.

[0224] For example, as shown in FIG18 , before forming the seed layer 228 , a buffer layer 2281 can be formed on the first surface 222A. The material of the buffer layer 2281 can be silicon nitride. For example, the thickness of the buffer layer 2281 can be 0.5 μm. The buffer layer 2281 is used to alleviate or prevent warping of the substrate 222 . Then, the seed layer 228 is formed on the side of the buffer layer 2281 away from the substrate 222 .

[0225] Exemplarily, the seed layer 228 includes an auxiliary layer and a first conductive layer. Specifically, the auxiliary layer is located between the first conductive layer and the substrate 222 or the buffer layer 2281. Compared to the first conductive layer, the auxiliary layer has greater adhesion to the substrate 222 or the buffer layer 2281, and the auxiliary layer also has greater adhesion to the first conductive layer, thereby preventing delamination between the first conductive layer and the substrate 222 or the auxiliary layer.

[0226] The material of the auxiliary layer may be a molybdenum-niobium alloy, and the material of the first conductive layer may be copper.

[0227] The thickness of the auxiliary layer is approximately The thickness of the first conductive layer ranges from 0.3 μm to 1.0 μm. For example, the thickness of the first conductive layer may be 0.3 μm, 0.35 μm, 0.4 μm, 0.5 μm or 1.0 μm.

[0228] Exemplarily, both the auxiliary layer and the first conductive layer can be formed by a sputtering process.

[0229] 21 , a photoresist layer 229 is formed on the seed layer 228. The photoresist layer 229 has a plurality of first openings 2292 and a plurality of second openings 2293. The first openings 2292 correspond to the signal lines 221 to be formed, and the second openings 2293 correspond to the dummy conductive patterns 223 to be formed.

[0230] 20 , a photoresist material may be coated on the seed layer 228 by a coating process to form a photoresist film 2291. To increase the curing rate of the photoresist material, after coating the photoresist material, a baking process may be used to bake the photoresist material to form the photoresist film 2291.

[0231] The thickness of the photoresist film 2291 may be greater than or equal to 7 μm. For example, the thickness of the photoresist film 2291 may be 7 μm, 8.5 μm, 9 μm, etc.

[0232] Illustratively, after the photoresist film 2291 is formed, the photoresist film 2291 is patterned, for example, by exposing and developing the photoresist layer 229 using a mask, so as to form a plurality of first openings 2292 and a plurality of second openings 2293 on the photoresist film 2291 .

[0233] For example, the material of the photoresist layer 229 can be a positive photoresist or a negative photoresist. Among them, the positive photoresist can be dissolved during the process of contacting with the developer after exposure, while the negative photoresist will not be dissolved during the process of contacting with the developer after exposure.

[0234] S213 , as shown in FIG. 21 and FIG. 24 , uses an electroplating process to form a signal line 221 in the first opening 2292 , and simultaneously forms a dummy conductive pattern 223 in the second opening 2293 .

[0235] Exemplarily, the signal line 221 and the dummy conductive pattern 223 are made of the same material, such as copper. For example, the material of the signal line 221 is the same as the material of the first conductive layer.

[0236] Specifically, the above S213 includes S214 to S216.

[0237] S214 , as shown in FIG. 21 and FIG. 22 , uses an electroplating process to form a signal sub-line 2218 in the first opening 2292 , and simultaneously forms a companion plating sub-pattern 2233 in the second opening 2293 .

[0238] Exemplarily, the thickness of the signal sub-line 2218 is substantially equal to the thickness of the accompanying plating sub-pattern 2233. For example, the thickness of the signal sub-line 2218 may be 7 μm.

[0239] For example, the thickness of the photoresist film 2291 can be greater than or equal to the thickness of the signal sub-line 2218. The ratio of the thickness of the photoresist film 2291 to the thickness of the signal sub-line 2218 can be in the range of 1.5:1 to 1:1. This allows the photoresist layer 229 formed by the photoresist film 2291, which acts as a spacer, to be thicker, ensuring the growth thickness of the signal sub-line 2218 and ensuring that the formed signal line 221 has a certain thickness.

[0240] For example, the ratio of the thickness of the photoresist film 2291 to the thickness of the signal sub-line 2218 can be 1.5:1, 1.4:1, 1.3:1:1.1:1 or 1:1.

[0241] It is understood that signal sub-line 2218 is part of signal line 221, and the only difference between signal sub-line 2218 and signal line 221 is thickness. For example, the thickness of signal line 221 is slightly greater than that of signal sub-line 2218. Therefore, the structural features of signal sub-line 2218 can be referenced to the description of signal line 221 in some of the aforementioned embodiments of the present disclosure, and will not be repeated here. Similarly, accompanying plating sub-pattern 2233 is part of dummy conductive pattern 223, and the only difference between accompanying plating sub-pattern 2233 and dummy conductive pattern 223 is thickness. For example, the thickness of dummy conductive pattern 223 is slightly greater than that of accompanying plating sub-pattern 2233. Therefore, the structural features of accompanying plating sub-pattern 2233 can be referenced to the description of dummy conductive pattern 223 in some of the aforementioned embodiments of the present disclosure, and will not be repeated here.

[0242] S215 , as shown in FIG. 22 and FIG. 23 , the photoresist layer 229 is removed to expose the seed layer 228 at a position corresponding to the removed photoresist layer 229 .

[0243] For example, the photoresist layer 229 is stripped off, so that a portion of the surface of the seed layer 228 away from the substrate 222 is exposed.

[0244] S216 , as shown in FIG. 23 and FIG. 24 , based on the signal sub-line 2218 and the accompanying plating sub-pattern 2233 , the exposed portion of the seed layer 228 is removed to form the signal line 221 and the dummy conductive pattern 223 .

[0245] It can be understood that the signal sub-line 2218 and the portion of the seed layer 228 facing the signal sub-line 2218 constitute the signal line 221 , and the accompanying plating sub-pattern 2233 and the portion of the seed layer 228 facing the accompanying plating sub-pattern 2233 constitute the dummy conductive pattern 223 .

[0246] For example, the signal sub-line 2218 and the accompanying plating sub-pattern 2233 are used as masks and an etching process is adopted to etch the exposed seed layer 228 until a portion of the seed layer 228 exposes the substrate 222 or the buffer layer 2281 .

[0247] It should be noted that, during the process of etching the exposed seed layer 228 , the signal sub-line 2218 and the accompanying plating sub-pattern 2233 may be thinned simultaneously.

[0248] For example, in the process of etching the exposed seed layer 228, it is necessary to control the etching time. Generally, it is necessary to appropriately increase the etching time on the basis of the theoretical etching time as the actual etching time. Specifically, the actual etching time can be increased by 30% to 50% on the basis of the theoretical etching time. In this way, the seed layer 228 can be overetched to completely remove the seed layer 228 that needs to be removed, thereby improving the yield of the wiring substrate 22, thereby alleviating or avoiding the short circuit phenomenon between multiple signal lines 221 and between the signal line 221 and the dummy conductive pattern 223.

[0249] For example, when the thickness of the auxiliary layer is about When the thickness of the first conductive layer is 0.3 μm, the actual etching time can be set to about 60 seconds according to the selection of etching solution.

[0250] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A wiring substrate, wherein: The wiring substrate includes: a substrate having a first surface; A plurality of signal lines are located on the first surface; the plurality of signal lines include at least one target signal line, and the target signal line includes at least one comb-shaped portion; the comb-shaped portion has a comb handle portion and a plurality of comb teeth portions, the same end of the plurality of comb teeth portions is connected to the comb handle portion, and a first gap is provided between any two adjacent comb teeth portions.

2. The wiring substrate according to claim 1, wherein The target signal line further includes: a connecting portion; the connecting portion is connected to the comb handle.

3. The wiring substrate according to claim 2, wherein The sum of the widths of the plurality of comb teeth of the comb-shaped portion is equal to or substantially equal to the width of the connecting portion.

4. The wiring substrate according to any one of claims 1 to 3, wherein The width of each comb-tooth portion is equal or approximately equal.

5. The wiring substrate according to any one of claims 1 to 4, wherein In the same comb-shaped portion, the widths of the first gaps between any two adjacent comb-tooth portions are equal or approximately equal.

6. The wiring substrate according to any one of claims 1 to 5, wherein The wiring substrate further includes: at least one conductive dummy pattern located on the first surface; the dummy conductive pattern is located on one side of one of the signal lines and is arranged on the same layer as the signal line; the dummy conductive pattern is insulated from the signal line.

7. The wiring substrate according to claim 6, wherein A plurality of dummy conductive patterns are provided on the same side of the signal line; and / or, At least one dummy conductive pattern is provided on both sides of the signal line.

8. The wiring substrate according to claim 6 or 7, wherein: The width of the dummy conductive pattern is equal to or substantially equal to the width of the comb-tooth portion.

9. The wiring substrate according to any one of claims 6 to 8, wherein A second gap is provided between the signal line and the adjacent dummy conductive pattern, and a width of the second gap is equal to or substantially equal to a width of the first gap.

10. The wiring substrate according to claim 9, wherein A plurality of dummy conductive patterns are provided on the same side of the signal line, and a third gap exists between any two adjacent dummy conductive patterns; The width of the second gap is equal to or substantially equal to the width of the third gap.

11. The wiring substrate according to claim 7, wherein The dummy conductive pattern includes a first type of dummy conductive pattern; The wiring substrate further comprises a plurality of first-type pad units and a plurality of second-type pad units located on the first surface; the second-type pad units include a plurality of device pad groups; The plurality of signal lines include: a plurality of first-category signal lines, a plurality of second-category signal lines, and a plurality of third-category signal lines; Two first-type signal lines are respectively located on two opposite sides of the second-type pad unit; A first-type pad unit is electrically connected to at least one second-type pad unit via the second-type signal line; multiple device pad groups within the same second-type pad unit are connected via the second-type signal line; the second-type The pad unit is connected to the adjacent first-type signal line through the second-type signal line; The first-type pad unit is connected to the adjacent first-type signal line via the second-type signal line, and the plurality of first-type pad units are connected to each other via the plurality of third-type signal lines; The first-type dummy conductive pattern at least extends along the overall direction of multiple device pad groups in the same second-type pad unit and multiple second-type signal lines connected to the multiple device pad groups.

12. The wiring substrate according to claim 11, wherein The wiring substrate includes a plurality of first-type dummy conductive patterns, and at least two of the first-type dummy conductive patterns are respectively arranged on two opposite sides along an extending direction perpendicular to the second-type signal line.

13. The wiring substrate according to claim 12, wherein The first type of pad unit is connected to multiple second type of pad units, and two first type of dummy conductive patterns are respectively arranged on opposite sides along the extension direction perpendicular to the second type of signal line. Multiple second type of pad units are arranged in a column, and the two first type of dummy conductive patterns located between any two adjacent second type of pad units are connected to each other.

14. The wiring substrate according to any one of claims 11 to 13, wherein The dummy conductive pattern includes a second type of dummy conductive pattern; The second-type dummy conductive pattern extends at least along the overall direction of two adjacent first-type pad units and a plurality of the third-type signal lines and the second-type signal lines connected thereto.

15. The wiring substrate according to claim 14, wherein The wiring substrate includes multiple second-type dummy conductive patterns, and at least two of the second-type dummy conductive patterns are respectively arranged on opposite sides along an extension direction perpendicular to the multiple third-type signal lines and on opposite sides along a direction perpendicular to the second-type signal lines.

16. The wiring substrate according to claim 15, wherein The dummy conductive patterns include a first type dummy conductive pattern, a second type dummy conductive pattern located on one side of the plurality of third type signal lines and adjacent to the second type signal lines, and connected to the adjacent first type dummy conductive pattern.

17. The wiring substrate according to any one of claims 11 to 16, wherein The second type of signal line includes a cascade line or a connecting line; and / or, the third type of signal line includes at least one of a first voltage line, a data line and an addressing line; and / or, the first type of signal line includes at least one of a ground line and a second voltage line.

18. A method for preparing a wiring substrate, wherein: include: providing a substrate having a first surface; A plurality of signal lines are formed on the first surface; the plurality of signal lines include at least one target signal line, and the target signal line includes at least one comb-shaped portion; the comb-shaped portion has a comb handle portion and a plurality of comb teeth portions, the same end of the plurality of comb teeth portions is connected to the comb handle portion, and a first gap is provided between any two adjacent comb teeth portions.

19. The preparation method according to claim 18, wherein The forming of a plurality of signal lines on the first surface comprises: A plurality of signal lines and at least one dummy conductive pattern are formed on the first surface using the same patterning process; the dummy conductive pattern is located on one side of one signal line and is arranged on the same layer as the signal line; the dummy conductive pattern is insulated from the signal line.

20. The preparation method according to claim 19, wherein The method of forming a plurality of signal lines and at least one dummy conductive pattern on the first surface by using the same patterning process includes: forming a seed layer on the first surface; forming a photoresist layer on the seed layer; the photoresist layer having a plurality of first openings and a plurality of second openings, the first openings corresponding to the signal lines to be formed, and the second openings corresponding to the dummy conductive patterns to be formed; The signal line is formed in the first opening by adopting an electroplating process, and the dummy conductive pattern is formed in the second opening simultaneously.

21. A light-emitting substrate, comprising: A wiring substrate, the wiring substrate according to any one of claims 1 to 17; A plurality of light emitting devices are arranged on the wiring substrate.

22. A display device comprising: A light-emitting substrate, which is the light-emitting substrate according to claim 21; The display panel is located on the light-emitting side of the light-emitting substrate.

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