Method and apparatus for recording read-write operation, and computer system

Abstract

The present application relates to the technology of processors, and specifically relates to a method and apparatus for recording a read-write operation, and a computer system comprising the apparatus. The method for recording a read-write operation comprises: A, receiving a read-write operation command from a processor (210), wherein the read-write operation command comprises a destination address; B, on the basis of the destination address, determining an operation object regarding the read-write operation command; and C, when the operation object is a specified object, storing the destination address in a storage device (220), wherein, independent of direct transmission of the read-write operation command from the processor (210) to a bus (230), a hardware module (240) is used to execute steps A-C.

Description

Method, device and computer system for recording read and write operations Technical Field

[0001] The present application relates to processor technology, and more particularly to a method and device for recording read and write operations, and a computer system including the device. Background Art

[0002] System stability is a crucial design criterion in the development of autonomous driving systems. Stability testing involves locating faults, or identifying the software or hardware modules that cause system errors. Due to the complexity of autonomous driving systems and the random nature of faults, fault location is a labor-intensive and time-consuming task. With the increasing sophistication of autonomous driving features and the increasing number of software and hardware modules included in the system, the challenges in this area are becoming even more severe.

[0003] Summary of the Invention

[0004] An object of the present application is to provide a method and apparatus for recording register access operations, and a computer system comprising the apparatus, which can provide information associated with a fault source in a low-cost manner.

[0005] According to one aspect of the present application, a method for recording read and write operations is provided, comprising:

[0006] A. receiving a read / write operation command from a processor, wherein the read / write operation command includes a destination address;

[0007] B. determining an operation object of the read / write operation command based on the destination address; and

[0008] C. When the operation object is a specified object, the destination address is saved in a storage device.

[0009] Wherein, steps A to C are performed using a hardware module independently of the direct sending of the read and write operation commands from the processor to the bus.

[0010] Optionally, in the above method, the read and write operation commands further include an identifier associated with the processor.

[0011] Optionally, in the above method, the destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

[0012] Optionally, in the above method, in step C, the identifier is also saved in the storage device.

[0013] According to another aspect of the present application, there is provided an apparatus for recording read and write operations, the apparatus being configured to perform the following operations independently of an operation of directly sending the read and write operation commands from the processor to a bus:

[0014] A. receiving a read / write operation command from a processor, wherein the read / write operation command includes a destination address;

[0015] B. determining an operation object of the read / write operation command based on the destination address, independently of sending the read / write operation command directly from the processor to the bus; and

[0016] C. When the operation object is a specified object, the destination address is saved in a storage device.

[0017] Optionally, the above-mentioned device includes a logic circuit connected between the processor and the bus, which is configured to determine the operation object of the read and write operation command based on the destination address and save the destination address to the storage device when the operation object is the specified object.

[0018] Optionally, in the above device, the read and write operation commands further include an identifier associated with the processor.

[0019] Optionally, in the above device, the destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

[0020] Optionally, in the above device, the logic circuit includes an address comparator configured to perform the following operations:

[0021] B1. Determine whether the destination address is within a set address range;

[0022] B2. If it is within the address range, generate a flag signal indicating that the operation object is the specified object.

[0023] Optionally, in the above apparatus, in operation C, the identifier is further saved in the storage device.

[0024] According to another aspect of the present application, there is provided a computer system comprising:

[0025] one or more processors;

[0026] one or more registers;

[0027] bus; and

[0028] The apparatus for recording read and write operations is configured to perform the following operations independently of the operation of directly sending the read and write operation commands from the processor to the bus:

[0029] A. receiving a read / write operation command from the processor via the interface circuit, wherein the read / write operation command includes a destination address;

[0030] B. determining an operation object of the read / write operation command based on the destination address; and

[0031] C. When the operation object is a specified object, the destination address is saved in a storage device.

[0032] Optionally, the computer system includes:

[0033] a first channel configured to allow the read and write operation commands to be sent directly from the processor to the bus;

[0034] A second channel includes the device for recording read and write operations, and the device for recording read and write operations includes a logic circuit connected between the processor and the bus, and the logic circuit is configured to determine the operation object of the read and write operation command based on the destination address and save the destination address to the storage device when the operation object is the specified object.

[0035] Optionally, in the above computer system, the storage device is a non-volatile memory inside or outside the computer system.

[0036] Optionally, in the above computer system, the read and write operation commands further include an identifier associated with the processor.

[0037] Optionally, in the above-mentioned computer system, the destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

[0038] Optionally, in the above computer system, the logic circuit includes an address comparator configured to perform the following operations:

[0039] B1. Determine whether the destination address is within a set address range;

[0040] B2. If it is within the address range, generate a flag signal indicating that the operation object is the specified object.

[0041] Optionally, in the above computer system, in operation C, the identifier is further saved in the storage device.

[0042] In some embodiments of the application, hardware module is independent of the operation that the read-write operation command from processor is directly sent to bus, determines operation object based on the destination address in the command, and records this read-write operation when operation object is the object of appointment.Because the read-write operation command can remain unchanged in the process of being sent to bus from processor, thereby can not affect the operation of existing program on processor, also need not revise the communication protocol between processor and bus, this has alleviated development workload and has good adaptability with existing system.In addition, in some embodiments, when implementing hardware module with the form of logic circuit, can simplify hardware structure and control logic and reduce cost.Moreover, because all read-write operation commands from processor are also received by the hardware module that is connected with processor or accesses bus when directly sending to bus, therefore can guarantee that all read-write operations to designated object are all recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or other aspects and advantages of the present application will become clearer and easier to understand through the following description of various aspects in conjunction with the accompanying drawings, in which the same or similar elements are represented by the same reference numerals. The accompanying drawings include:

[0044] FIG1 is a flow chart of a method for recording register access operations using software.

[0045] FIG2 is a schematic diagram of a computer system according to an embodiment of the present application.

[0046] FIG3 is a schematic diagram of a device for recording read and write operations according to another embodiment of the present application.

[0047] FIG4 is a schematic diagram of a hardware circuit for implementing an address comparison function according to another embodiment of the present application.

[0048] FIG5 is a flowchart of a method for recording read and write operations according to another embodiment of the present application. DETAILED DESCRIPTION

[0049] The present application is described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments of the present application. However, the present application may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. The foregoing embodiments are provided to make the disclosure herein comprehensive and complete, so as to more fully convey the scope of protection of the present application to those skilled in the art.

[0050] In this specification, terms such as "comprise" and "include" indicate that in addition to the units and steps directly and clearly stated in the specification and claims, the technical solution of this application does not exclude the situation where it has other units and steps that are not directly or clearly stated.

[0051] In this specification, "connection" refers to an electrical connection for transmitting power or a communication connection for transmitting signals between two or more hardware entities, which includes situations where two hardware entities are directly connected, and also includes situations where two hardware entities are connected through other hardware entities.

[0052] In this specification, "processor" refers to any semiconductor device or chip used to execute computer program instructions, process data, and perform operations. Processor types include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), embedded processors, microcontrollers, and AI processors.

[0053] In this specification, to distinguish between registers inside the processor and registers outside the processor, the latter are also referred to as external registers or system registers. In the following description, unless otherwise specified, registers, external registers, and system registers refer to the same object and are used interchangeably.

[0054] In many cases, system instability manifests itself as the inability of processor instructions to execute properly. The causes of this situation are characterized by low reproducibility and complex interaction mechanisms. In a typical autonomous driving chip design, software is used to record processor accesses to external registers or system registers in memory for fault location and analysis.

[0055] FIG1 is a flow chart of a method for recording register access operations using software. As shown in FIG1 , in step 110, in response to a processor's read or write operation command or request for a register, the program running on the processor calls a register read and write operation recording function. The program then proceeds to step 120, where the function executes to record data related to the read and write operation (e.g., access address and write data) in memory (e.g., a designated cache area). After completing step 120, the program proceeds to step 130, where the program running on the processor performs a read or write operation on the register. When the system fails and restarts, the operation data stored in the designated cache area will be stored in a non-volatile memory (e.g., a magnetic disk, hard disk, or optical disk).

[0056] In the method shown in FIG1 , in order to be able to identify the read and write operation commands or requests for the registers and record the corresponding operation data, a unified calling interface needs to be provided in the processor core. This limitation reduces the convenience of development. In addition, in order to record the operation data, the software needs to provide a multi-core concurrent buffer write function, which increases the workload and difficulty of programming. In addition, in the above method, not only a unified calling interface is required, but also the register space mapped by the user space needs to be monitored, which is more likely to lead to the generation of monitoring blind spots. Furthermore, the software-based implementation will consume more resources (such as processor utilization and memory bandwidth, etc.) and will also have an adverse effect on the execution speed of the program.

[0057] In some embodiments of the present application, the read and write operations of a specified object (such as a register or a specified memory storage area) are recorded by adding a hardware module that can receive a read and write operation command. In particular, the setting of the hardware module does not change or affect the connection relationship and communication mode between the processor and the bus. The read and write operation command or request from the processor can still be sent to the bus to be received by the destination device according to the original signal logic and timing. On the other hand, when the read and write operation command is directly sent to the bus from the processor, it is also directed to the hardware module. Accordingly, the hardware module can be independent of the processor in sending the read and write operation command to the bus, determines whether the operation object is a specified object based on the destination address in the read and write operation command and saves the relevant operation data to the storage device when the judgment result is true. This means that the operation performed by the hardware module and the sending operation of the read and write operation command between the processor and the bus are not restricted in execution order (such as can be executed first and then, or can be executed in parallel), and the operation results are also independent of each other and do not affect each other. In the above-mentioned hardware implementation, the read and write operation commands can remain unchanged during the process of being sent from the processor to the bus, thereby not affecting the operation of the existing program on the processor, and there is no need to modify the communication protocol between the processor and the bus, thereby reducing the development workload and being able to better adapt to the existing system.

[0058] In some embodiments, the hardware modules are implemented in the form of logic circuits (eg, circuits including logic elements such as gate circuits, switches, and comparators), which simplifies the hardware structure and control logic and reduces costs.

[0059] In some embodiments, when it is necessary to record the read and write operations of multiple processors on registers, in addition to saving the destination address in the storage device, an identifier associated with the processor (eg, masterid) may also be written into the storage device.

[0060] In some embodiments, the hardware module is connected to a port of the processor for outputting read and write operation commands or is connected to a bus, so that all read and write operations on a specified object can be detected by the hardware module and saved.

[0061] In many cases, the inability of a processor instruction to be executed normally is strongly correlated with the operation of the hardware before the event occurs. After research, the inventors of the present application found that when locating a fault, the information value possessed by the type of register on which the read and write operations are performed is much higher than the value possessed by the data written to or read from the register. In addition, saving the read data or write data to the register will lead to the complication of the recording task (especially when different buses are used to transmit data and instructions respectively). In some embodiments of the present application, the recorded operation data only includes the address of the read and write operation object (hereinafter referred to as the destination address) or a combination of the destination address and the source address (such as the identifier of the processor).

[0062] FIG2 is a schematic diagram of a computer system according to an embodiment of the present application. The computer system 20 shown in FIG2 includes processors 210-1 to 210-n, a storage device 220, a bus 230, a hardware module 240, a register or register group 250, and other destination devices (e.g., dynamic random access memory) 260. Referring to FIG2 , the processors 210-1 to 210-n are connected to the bus 230, and the registers 250 and other destination devices 260 are connected to the bus 230. The processors 210-1 to 210-n can perform read and write operations on each destination device via the bus 230. In some specific implementations, the read and write operation commands or requests include the destination address of the object being operated (e.g., registers and other destination devices). Optionally, the read and write operation commands also include a source address (e.g., an identifier associated with the processor). In the computer system shown in FIG2 , the hardware module 240 is connected to the processors 210-1 to 210-n to receive the read and write operation commands and is connected to the storage device 220 to record the read and write operations of the specified object.

[0063] 2 , the hardware module 240 is configured to “identify” read and write operations on a specified object based on the destination address and record such read and write operations in the storage device 220. The structure and operating principle of the hardware module 240 will be further described below in conjunction with FIG3 and FIG4 .

[0064] In some specific implementations, the data of the read and write operations of a specified object will be written to a specified cache area on the storage device 220 in a first-in, first-out manner. In other specific implementations, to prevent the storage overflow of the cache area, the remaining capacity of the cache area can be monitored, and when the remaining capacity falls below a set level, the read and write operation data recorded therein can be copied to other storage areas or other storage devices.

[0065] It should be noted that although the embodiment shown in Figure 2 includes multiple processors, this is merely exemplary, and in variations of this embodiment, the computer system may also include only one processor. In addition, the architectures or types of the multiple processors may be the same or different.

[0066] It should also be noted that, although in the embodiment shown in FIG2 , the storage device 220 for recording read and write operations on a specified object constitutes a component unit of the computer system 20, this arrangement is not required, and the storage device 220 may alternatively serve as an external device of the computer system 20.

[0067] FIG3 is a schematic diagram of an apparatus for recording read and write operations according to another embodiment of the present application. The apparatus 30 shown in FIG3 can be used to implement the hardware module 240 in FIG2 .

[0068] As shown in FIG3 , in device 30, read and write operation commands from a processor (e.g., one of processors 210-1 to 210-n in FIG2 ) are directly sent to a bus (e.g., bus 230 in FIG2 ) via channel #1 external to device 30. Furthermore, these commands are also input to channel #2 internal to device 30. In the device shown in FIG3 , the sending of read and write operation commands via channel #1 and the determination of the operation target type within channel #2 can be performed independently or in parallel.

[0069] In the embodiment shown in FIG3 , due to the use of direct transmission, the read and write commands sent to the bus via channel #1 remain unchanged on the processor side. The processor side does not need to adjust the method and format of sending read and write commands due to the presence of device 30. Similarly, the bus side does not need to adjust or change the method of receiving read and write commands. This means that the addition of device 30 does not require adaptive modifications to the programs running on the processor.

[0070] Channel #2 may include an address comparator 310. For example, the address comparator 310 may include two inputs and one output, wherein the inputs are addresses to be compared (e.g., a destination address and a reference address corresponding to a specified object), and the output is a Boolean value or flag signal indicating whether the compared addresses match. In some complex applications, the address comparator may include more inputs and more complex comparison logic units to perform more complex address comparison operations.

[0071] In some specific implementations, when assigning consecutive addresses to designated objects (e.g., a group of registers) in a computer system, a simple hardware circuit can be used to implement the address comparison function. FIG4 is a schematic diagram of a hardware circuit for implementing the address comparison function according to another embodiment of the present application. The hardware circuit 40 may include address registers REG1 to REG3, comparators CMP1 and CMP2, an AND gate AND, and a switch S (e.g., a switching transistor or field-effect transistor). Referring to FIG4 , address registers REG1 and REG3 are connected to the input of comparator CMP1, and address registers REG2 and REG3 are connected to the input of comparator CMP2. The outputs of comparators CMP1 and CMP2 are connected to the input of the AND gate AND. The output of the AND gate AND is connected to the control terminal of the switch S. In addition, in addition to being written to the address register REG3, the destination address signal from the processor is also output to a storage device (e.g., the storage device 220 in FIG2 ) via the switch S.

[0072] In the example shown in FIG4 , the minimum value ADDR_MIN and the maximum value ADDR_MAX of the consecutive addresses are stored in address registers REG1 and REG2, respectively. When performing a comparison operation, the destination address ADDR_T to be compared is written into address register REG3, and comparators CMP1 and CMP2 compare the destination address ADDR_T with the minimum value ADDR_MIN and the maximum value ADDR_MAX of the consecutive addresses, respectively. If the destination address ADDR_T is less than the minimum value ADDR_MIN, comparator CMP1 outputs a signal FALSE1 indicating that the address is invalid; otherwise, it outputs a signal TRUE1 indicating that the address is valid. If the destination address ADDR_T is greater than the maximum value ADDR_MAX, comparator CMP2 outputs a signal FALSE2 indicating that the address is invalid; otherwise, it outputs a signal TRUE2 indicating that the address is valid. The comparison result signals of comparators CMP1 and CMP2 are output to an AND gate AND. Only when the destination address ADDR_T falls within the address range defined by the minimum value ADDR_MIN and the maximum value ADDR_MAX (i.e., when the output signals of comparators CMP1 and CMP2 both indicate a valid address) does the AND gate output a TRUE signal or a flag signal indicating that the destination address belongs to the specified object. This TRUE signal turns on switch S, allowing the processor's read and write commands to be recorded in the storage device.

[0073] It should be noted that the address comparator shown in FIG4 is merely exemplary and various modifications or variations may be made thereon. For example, the address comparator may further include a destination address extraction circuit to extract the destination address from the read / write operation command and write it into the address register REG3. For another example, when the register group is not assigned consecutive addresses, more address registers may be added to store the assigned register addresses, and correspondingly more comparators may be added to compare the destination address with the register address.

[0074] FIG5 is a flowchart of a method for recording register access operations according to another embodiment of the present application. By way of example, the following description is implemented using the computer system, apparatus, and hardware circuits shown in FIG2-4. However, it should be noted that this embodiment is not limiting, and the various steps or functions of the method shown in FIG5 may also be implemented using devices having other structures and principles.

[0075] It should be noted that each step of the method shown in FIG5 may be independent of the operation or process of sending the read and write operation commands from the processor to the bus.

[0076] The method shown in FIG5 begins at step 510. In this step, a device for recording read and write operations (e.g., the hardware module 240 in FIG2 or the device 30 in FIG3) receives a read and write operation command from a processor (e.g., one of the processors 210-1 to 210-n in FIG2). In some specific implementations, the read and write operation command from the processor may only include the destination address of the operation object, such as the address of a memory space or an external register or a system register. In the case where multiple processors share a hardware module, the read and write operation command may also include a source address. For example, the identifier of the processor that issued the read and write operation command may be used as the source address.

[0077] Referring to FIG. 5 , after executing step 510, the process shown in FIG. 5 proceeds to step 520. In this step, the apparatus for recording read / write operations determines whether the operation object of the read / write operation command is a specified object (e.g., an external register, a system register, or a specified memory area) based on the destination address included in the read / write operation command. If it is a specified object, the process proceeds to step 530; otherwise, the process proceeds to step 540.

[0078] In step 520, the hardware circuit 40 shown in FIG4 can be used to perform an address comparison function and determine the subsequent steps or the type of operation object based on the comparison result. Specifically, if the register addresses are continuously assigned, the destination address can be compared with the maximum and minimum values ​​of the continuous addresses to determine whether the destination address is the address of the specified object, and if the comparison result is true (TRUE), step 530 is executed. Alternatively, if the register addresses are non-continuously assigned, the destination address can be compared with each register address, and if the comparison result is true, step 530 is executed.

[0079] In step 530, the apparatus for recording read and write operations stores the target address in a storage device (e.g., storage device 220 in FIG. 2 ). Taking the hardware circuit 40 shown in FIG. 4 as an example, when the comparison result in step 520 is true, switch S is turned on, allowing the read and write operation commands from the processor to be written to the storage device.

[0080] In step 540 , the apparatus for recording read and write operations discards the read and write operation commands received in step 510 .

[0081] Those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described herein may be implemented as hardware, computer software, or a combination of both.

[0082] To illustrate the interchangeability between hardware and software, various schematic components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in a varying manner for specific specific applications, but such implementation decisions should not be interpreted as causing a departure from the scope of this application.

[0083] Although only some specific embodiments of the present application have been described, it should be understood by those skilled in the art that the present application may be implemented in many other forms without departing from its spirit and scope. Therefore, the examples and embodiments shown are to be considered illustrative rather than restrictive, and the present application may encompass various modifications and substitutions without departing from the spirit and scope of the present application as defined in the appended claims.

[0084] The embodiments and examples set forth herein are provided to best illustrate embodiments according to the present technology and its specific applications, and thereby enable those skilled in the art to make and use the present application. However, those skilled in the art will appreciate that the above description and examples are provided for ease of illustration and example only. The descriptions set forth are not intended to be exhaustive of all aspects of the present application or to limit the present application to the precise forms disclosed.

Claims

1. A method for recording read and write operations, comprising: A. receiving a read / write operation command from a processor, wherein the read / write operation command includes a destination address; B. determining an operation object of the read / write operation command based on the destination address; and C. When the operation object is a specified object, the destination address is saved in a storage device. in, Steps A to C are performed using a hardware module independently of sending the read and write operation commands directly from the processor to the bus.

2. The method of claim 1, wherein: The read and write operation commands also include an identifier associated with the processor.

3. The method according to claim 1 or 2, wherein: The destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

4. The method of claim 2, wherein: In step C, the identifier is also saved in the storage device.

5. A device for recording read and write operations, the device being configured to perform the following operations independently of the operation of sending the read and write operation commands directly from the processor to a bus: A. receiving a read / write operation command from a processor, wherein the read / write operation command includes a destination address; B. determining an operation object of the read / write operation command based on the destination address; and C. When the operation object is a specified object, the destination address is saved in a storage device.

6. The apparatus as claimed in claim 5 comprises a logic circuit connected between the processor and the bus, wherein the logic circuit is configured to determine the operation object of the read / write operation command based on the destination address and save the destination address to a storage device when the operation object is the designated object device.

7. The device according to claim 5 or 6, wherein: The read and write operation commands also include an identifier associated with the processor.

8. The device according to claim 5 or 6, wherein: The destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

9. The device according to claim 6, wherein: The logic circuit includes an address comparator configured to perform the following operations: B1. Determine whether the destination address is within a set address range; B2. If it is within the address range, generate a flag signal indicating that the operation object is the designated object.

10. The device according to claim 7, wherein: In operation C, the identifier is also saved in the storage device.

11. A computer system comprising: one or more processors; one or more registers; bus; as well as The device for recording read and write operations is configured to perform the following operations independently of the operation of sending the read and write operation commands directly from the processor to the bus: A. receiving a read / write operation command from the processor via the interface circuit, wherein the read / write operation command includes a destination address; B. determining an operation object of the read / write operation command based on the destination address; as well as C. When the operation object is a specified object, the destination address is saved in a storage device.

12. The computer system of claim 11, comprising: The first channel is configured to allow the read and write operation commands to be sent directly from the processor to the The bus; A second channel includes the device for recording read and write operations, and the device for recording read and write operations includes a logic circuit connected between the processor and the bus, and the logic circuit is configured to determine the operation object of the read and write operation command based on the destination address and save the destination address to the storage device when the operation object is the specified object.

13. The computer system of claim 11 or 12, wherein: The storage device is a non-volatile memory inside or outside the computer system.

14. The computer system according to claim 11 or 12, wherein: The read and write operation commands also include an identifier associated with the processor.

15. The computer system according to claim 11 or 12, wherein: The destination address includes a memory space address or a register address, and the specified object includes at least one of the following: a register and a set memory area.

16. The computer system of claim 12, wherein: The logic circuit includes an address comparator configured to perform the following operations: B1. Determine whether the destination address is within a set address range; B2. If it is within the address range, generate a flag signal indicating that the operation object is the designated object.

17. The computer system of claim 14, wherein: In operation C, the identifier is also saved in the storage device.

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