Solar cell and preparation method therefor

Abstract

The present invention relates to a solar cell and a preparation method therefor. According to the preparation method, a first doped polycrystalline silicon layer is formed on a first tunneling layer, a protective layer is formed on the first doped polycrystalline silicon layer, and a second doped polycrystalline silicon layer having the same doping type is further formed, wherein the doping concentration of the second doped polycrystalline silicon layer is higher than that of the first doped polycrystalline silicon layer. Due to different segregation coefficients of impurities at low and high doping concentrations, the impurities tend to aggregate in a high-concentration doping area, and during processing, the second doped polycrystalline silicon layer with higher doping concentration can attract impurities in a lower film layer and impurities introduced during processing into the second doped polycrystalline silicon layer. Impurities in the surface layer of the first doped polycrystalline silicon layer are more attracted to the second doped polycrystalline silicon layer.

Description

Solar cell and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 21, 2023, with application number 202311777833.4 and application name “Solar Cells and Their Preparation Methods”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of photovoltaic technology, in particular to a solar cell and a preparation method thereof. Background Art

[0003] A conventional method for preparing a solar cell comprises the following steps:

[0004] As shown in FIG1 , a tunneling layer 12 is formed on a substrate 11 , a doped polysilicon layer 13 is formed on the tunneling layer 12 by a CVD (chemical vapor deposition) process, and a doped oxide layer 14 is formed on the doped polysilicon layer 13 ;

[0005] As shown in FIG2 , laser etching is performed to form a first groove 21 in the laser-etched area. The first groove 21 penetrates the doped oxide layer 14 and extends into the doped polysilicon layer 13 below the doped oxide layer 14 .

[0006] As shown in FIG3 , the bottom material of the first groove 21 is further removed by alkaline polishing to form a second groove. The second groove penetrates the doped oxide layer 14 , the doped polysilicon layer 13 , the tunneling layer 12 and extends into the substrate 11 .

[0007] In the doped polysilicon layer, the doping concentration shows a clear increasing trend compared to the substrate. Due to the Fermi level effect and ion pairing, metal impurities tend to accumulate in the doped polysilicon layer and the doped oxide layer at high temperatures, resulting in a higher impurity content in the surface layer of the doped polysilicon layer. Furthermore, grain boundaries and dislocations within the doped polysilicon layer strongly segregate and precipitate impurities, especially metal impurities with faster diffusion rates. High levels of these impurities in the doped polysilicon film will undoubtedly affect the passivation performance of the battery.

[0008] The above-mentioned traditional preparation method forms a doped oxide layer 14 on the doped polysilicon layer 13. Although the doped oxide layer 14 can be used as a mask to block and protect the doped polysilicon layer 13 in the non-laser etched area during the alkali polishing process, this also results in the surface layer of the doped polysilicon layer 13 with a relatively high impurity content being unable to be removed, affecting the battery passivation effect.

[0009] Simply reducing the doping concentration of the doped polysilicon layer 13 to avoid the adsorption of impurities during the high-concentration diffusion process simply reduces the impact and does not fundamentally solve the problem. Furthermore, when the doping concentration is reduced, not only will the field passivation effect be affected, but the ohmic contact will also be affected to a certain extent.

[0010] Summary of the Invention

[0011] Based on this, it is necessary to provide a solar cell and a preparation method thereof to solve the problem of high impurity content in the surface layer of the doped polysilicon layer.

[0012] A method for preparing a solar cell, characterized in that it comprises the following steps:

[0013] forming a first tunneling layer on the substrate;

[0014] forming a first doped polysilicon layer on the first tunneling layer;

[0015] forming a protective layer on the first doped polysilicon layer;

[0016] forming a second doped polysilicon layer on the protective layer, wherein the first doped polysilicon layer and the second doped polysilicon layer have the same doping type, and the doping concentration of the second doped polysilicon layer is higher than the doping concentration of the first doped polysilicon layer, so that the second doped polysilicon layer attracts impurities in the first doped polysilicon layer during the process;

[0017] The second doped polysilicon layer is removed.

[0018] In one embodiment, the doping concentration of the second doped polysilicon layer is 3 to 10 times the doping concentration of the first doped polysilicon layer.

[0019] In one embodiment, the preparation process temperature of the second doped polysilicon layer is 300° C. to 1100° C.

[0020] In one embodiment, the first doped polysilicon layer and the second doped polysilicon layer are P-type doped, and the doping concentration of the first doped polysilicon layer is 1×10 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second doped polysilicon layer is 1×10 20 ~5×10 21 cm -3 .

[0021] In one embodiment, the first doped polysilicon layer and the second doped polysilicon layer are N-type doped, and the doping concentration of the first doped polysilicon layer is 1×1020 cm -3 ~1×10 21 cm -3 The doping concentration of the second doped polysilicon layer is 1×10 20 ~5×10 22 cm -3 .

[0022] In one embodiment, the first tunneling layer is formed by an LPCVD process or a PECVD process.

[0023] In one embodiment, the first doped polysilicon layer is formed by an LPCVD process or a PECVD process.

[0024] In one embodiment, the second doped polysilicon layer is formed by an LPCVD process or a PECVD process.

[0025] In one embodiment, after the step of forming the second doped polysilicon layer, the preparation method further includes the following steps:

[0026] The second doped polysilicon layer is annealed at a temperature of 600° C. to 1100° C.

[0027] In one embodiment, the thickness of the first tunneling layer is 0.5 nm to 2 nm.

[0028] In one embodiment, the thickness of the first doped polysilicon layer is 100 nm to 500 nm.

[0029] In one embodiment, the thickness of the second doped polysilicon layer is 10 nm to 80 nm.

[0030] In one embodiment, the thickness of the protective layer is 5 nm to 50 nm.

[0031] In one embodiment, the material of the protective layer is silicon oxide.

[0032] In one embodiment, the step of removing the second doped polysilicon layer includes:

[0033] The second doped polysilicon layer is subjected to an alkali polishing treatment.

[0034] In one embodiment, before the step of removing the second doped polysilicon layer, the preparation method further comprises the following steps:

[0035] A first groove is formed in the laser etching area by laser etching, wherein the first groove penetrates the second doped polysilicon layer and the protective layer and extends into the first doped polysilicon layer.

[0036] In one embodiment, after the laser etching step and before the step of removing the second doped polysilicon layer, the preparation method further includes the following steps:

[0037] removing the oxide film formed on the bottom of the first groove due to the laser etching process by acid etching;

[0038] The alkali polishing process deepens the first groove until a second groove is formed with the bottom thereof in the substrate.

[0039] In one embodiment, before the laser etching step, the preparation method further includes the following steps:

[0040] forming a doped oxide layer on the second doped polysilicon layer;

[0041] The doped oxide layer is removed during the acid etching process.

[0042] In one embodiment, the preparation method further comprises the following steps:

[0043] A second tunneling layer is formed on the bottom of the second groove.

[0044] In one embodiment, the preparation method further comprises the following steps:

[0045] A third doped polysilicon layer is formed on the second tunneling layer, wherein the doping type of the third doped polysilicon layer is opposite to the doping type of the first doped polysilicon layer.

[0046] In one embodiment, the preparation method further comprises the following steps:

[0047] The first doped polysilicon layer and the third doped polysilicon layer are insulated and isolated.

[0048] In one embodiment, the preparation method further comprises the following steps:

[0049] A first passivation film is formed on the first doped polysilicon layer, and a second passivation film is formed on the third doped polysilicon layer.

[0050] In one embodiment, the preparation method further comprises the following steps:

[0051] A first gate line is formed on the first passivation film, and a second gate line is formed on the second passivation film.

[0052] A solar cell is prepared by the preparation method described in any one of the above embodiments.

[0053] Compared with the traditional method, the above-mentioned solar cell preparation method has the following beneficial effects:

[0054] The above-mentioned solar cell fabrication method forms a first doped polysilicon layer on a first tunneling layer, forms a protective layer on the first doped polysilicon layer, and further forms a second doped polysilicon layer of the same doping type, wherein the doping concentration of the second doped polysilicon layer is higher than that of the first doped polysilicon layer. Because the segregation coefficients of impurities at low and high doping concentrations differ, impurities tend to accumulate in the high-concentration doping region. During the process, the second doped polysilicon layer with a higher doping concentration can attract impurities from the underlying film layer and impurities introduced during the process. For the first doped polysilicon layer, impurities in its surface layer are more attracted to the second doped polysilicon layer, thereby reducing the impurity content of the surface layer of the first doped polysilicon layer. The second doped polysilicon layer is subsequently removed to obtain a first doped polysilicon layer with a more uniform impurity content. The protective layer protects the first doped polysilicon layer from damage or even removal. The above-mentioned fabrication method does not require intentionally reducing the doping concentration of the first doped polysilicon layer, thereby improving the cell passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is a schematic diagram of forming a tunneling layer, a doped polysilicon layer, and a doped oxide layer on a substrate in a conventional preparation method;

[0056] FIG2 is a schematic diagram of forming a first groove in a conventional preparation method;

[0057] FIG3 is a schematic diagram of forming a second groove in a conventional preparation method;

[0058] FIG4 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present invention;

[0059] 5 is a schematic diagram of forming a first tunneling layer, a first doped polysilicon layer, a protective layer, a second doped polysilicon layer and a doped oxide layer on a substrate in a preparation method according to an embodiment;

[0060] FIG6 is a schematic diagram of forming a first groove by laser etching;

[0061] FIG7 is a schematic diagram of removing the oxide film at the bottom of the first groove by acid etching;

[0062] FIG8 is a schematic diagram of removing the second doped polysilicon layer and deepening the first groove to form a second groove by alkali polishing;

[0063] 9 is a schematic diagram of forming a second tunneling layer on the bottom of the second groove, forming a third doped polysilicon layer on the second tunneling layer, and forming a doped silicon oxide film layer on the third doped polysilicon layer;

[0064] FIG10 is a schematic diagram of removing a locally doped silicon oxide film layer;

[0065] 11 is a schematic diagram of forming an isolation spacer between the first doped polysilicon layer and the third doped polysilicon layer and forming a texture structure on the second side of the substrate;

[0066] 12 is a schematic diagram of forming a first passivation film on the first doped polysilicon layer, forming a second passivation film on the third doped polysilicon layer, and forming a third passivation film on the second side of the substrate;

[0067] FIG. 13 is a schematic diagram of forming a first gate line on a first passivation film and forming a second gate line on a second passivation film.

[0068] Description of reference numerals:

[0069] 110. Substrate; 120. First tunneling layer; 130. First doped polysilicon layer; 140. Protective layer; 150. Second doped polysilicon layer; 160. Doped oxide layer; 171. First groove; 172. Second groove; 180. Oxide film; 190. Second tunneling layer; 200. Third doped polysilicon layer; 210. Doped silicon oxide film layer; 220. Isolation groove; 230. Textured structure; 240. First passivation film; 250. Second passivation film; 260. Third passivation film; 270. First gate line; 280. Second gate line. DETAILED DESCRIPTION

[0070] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0071] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be an element centered thereon. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an element centered thereon. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementations.

[0072] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number or order of the indicated technical features.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0074] The invention provides a method for preparing a solar cell.

[0075] Referring to FIG. 4 , a method 10 for preparing a solar cell according to an embodiment includes the following steps:

[0076] In step S1 , as shown in FIG. 5 , a first tunneling layer 120 is formed on a substrate 110 .

[0077] Step S2 , forming a first doped polysilicon layer 130 on the first tunneling layer 120 .

[0078] Step S3 , forming a protection layer 140 on the first doped polysilicon layer 130 .

[0079] In step S4, a second doped polysilicon layer 150 is formed on the protective layer 140. The first doped polysilicon layer 130 and the second doped polysilicon layer 150 have the same doping type, and the doping concentration of the second doped polysilicon layer 150 is higher than the doping concentration of the first doped polysilicon layer 130, so that the second doped polysilicon layer attracts impurities in the first doped polysilicon layer during the process.

[0080] Step S5 , removing the second doped polysilicon layer 150 .

[0081] The above-described solar cell manufacturing method forms a first doped polysilicon layer 130 on a first tunneling layer 120, forms a protective layer 140 on the first doped polysilicon layer 130, and further forms a second doped polysilicon layer 150 of the same doping type, wherein the doping concentration of the second doped polysilicon layer 150 is higher than the doping concentration of the first doped polysilicon layer 130. Because the segregation coefficients of impurities at low and high doping concentrations are different, impurities tend to accumulate in the high-concentration doping area. During the process, the second doped polysilicon layer 150 with a higher doping concentration can attract impurities from the underlying film layer and impurities introduced during the process. For the first doped polysilicon layer 130, impurities in its surface layer (i.e., the portion close to the second doped polysilicon layer 150) are more attracted to the second doped polysilicon layer 150, thereby reducing the impurity content in the surface layer of the first doped polysilicon layer 130. The second doped polysilicon layer 150 is subsequently removed to obtain a first doped polysilicon layer 130 with a more uniform impurity content. Furthermore, the first doped polysilicon layer 130 is protected from damage or even removal by the protective layer 140. The above preparation method does not require intentionally reducing the doping concentration of the first doped polysilicon layer 130, and can improve the cell passivation effect.

[0082] In order to better enable the second doped polysilicon layer 150 to perform the gettering function, the doping concentration of the second doped polysilicon layer 150 is preferably significantly higher than the doping concentration of the first doped polysilicon layer 130. For example, the doping concentration of the second doped polysilicon layer 150 is 3 to 10 times the doping concentration of the first doped polysilicon layer 130.

[0083] In one example, the first doped polysilicon layer 130 and the second doped polysilicon layer 150 are P-type doped, such as boron doped, and the doping concentration of the first doped polysilicon layer 130 is 1×10 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second doped polysilicon layer 150 is 1×10 20 cm -3 ~5×10 21 cm -3 .

[0084] In one example, the first doped polysilicon layer 130 and the second doped polysilicon layer 150 are N-type doped, such as phosphorus doped, and the doping concentration of the first doped polysilicon layer 130 is 1×10 20 cm -3 ~1×10 21 cm -3 The doping concentration of the second doped polysilicon layer 150 is 1×10 20 cm -3 ~5×1022 cm -3 .

[0085] The substrate 110 may be, but is not limited to, a single crystal silicon wafer. The doping type of the substrate 110 is the same as the doping type of the first doped polysilicon layer 130 , which may be N-type doping or P-type doping.

[0086] The substrate 110 has a first side and a second side opposite to each other. The first tunneling layer 120, the first doped polysilicon layer 130 and the second doped polysilicon layer 150 are all formed on the first side, which serves as the back side of the solar cell, and the second side serves as the front side.

[0087] In one example, the resistivity of the substrate 110 is 1-7 Ω·cm.

[0088] In one example, the thickness of the substrate 110 is 120-200 μm.

[0089] In one example, before forming the first tunneling layer 120 , the substrate 110 is pre-cleaned to remove a mechanical damage layer and dirt.

[0090] The material of the first tunneling layer 120 may be, but is not limited to, silicon oxide.

[0091] The preparation process of the first tunneling layer 120 may be, but is not limited to, a CVD process, such as LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), and the like.

[0092] In one example, the LPCVD process parameters of the first tunneling layer 120 include:

[0093] The flow rate of the oxygen source is 10,000 to 50,000 sccm, the pressure is 100 to 1,000 Torr, and the temperature is 550 to 630°C.

[0094] In one example, the PECVD process parameters of the first tunneling layer 120 include:

[0095] The flow rate of the oxygen source (oxygen or nitrous oxide) is 5000-20000 sccm, the frequency of the radio frequency power supply is 40 kHz to 400 kHz, and the temperature is 100° C. to 500° C.

[0096] The thickness of the first tunneling layer 120 can be adjusted by controlling the deposition time. In one example, the thickness of the first tunneling layer 120 is 0.5-2 nm. Furthermore, the thickness of the first tunneling layer 120 is 1-2 nm.

[0097] The preparation process of the first doped polysilicon layer 130 may be, but is not limited to, a CVD process, such as LPCVD, PECVD, and the like.

[0098] In one example, the LPCVD process parameters of the first doped polysilicon layer 130 include:

[0099] Borane and silane gases are introduced, with a flow ratio of borane to silane of 1:(5-15), a pressure of 100-500 mTorr, and a temperature of 550-630°C.

[0100] In one example, the LPCVD process parameters of the first doped polysilicon layer 130 include:

[0101] Phosphine and silane gases are introduced, with a flow ratio of phosphine to silane of 1:(5-15), a pressure of 100-500 mTorr, and a temperature of 550-630°C.

[0102] In one example, the PECVD process parameters for the first doped polysilicon layer 130 include:

[0103] Borane, silane and hydrogen gases are introduced, with a flow ratio of borane to silane of 1:(1-5), a pressure of 1000-4000 mBar and a temperature of 400-500°C.

[0104] In one example, the PECVD process parameters for the first doped polysilicon layer 130 include:

[0105] Phosphine, silane and hydrogen gases are introduced, with a flow ratio of phosphine to silane of 1:(1-5), a pressure of 1000-4000 mBar and a temperature of 400-500°C.

[0106] The thickness of the first doped polysilicon layer 130 can be adjusted by controlling the deposition time. In one example, the thickness of the first doped polysilicon layer 130 is 100-500 nm. Furthermore, the thickness of the first doped polysilicon layer 130 is 200-400 nm.

[0107] The preparation process of the second doped polysilicon layer 150 may be, but is not limited to, a CVD process, such as LPCVD, PECVD, and the like.

[0108] In one example, the LPCVD process parameters for the second doped polysilicon layer 150 include:

[0109] Borane and silane gases are introduced, with a flow ratio of borane to silane of 1:(2-10), a pressure of 200-500 mTorr, and a temperature of 550-630°C.

[0110] In one example, the LPCVD process parameters for the second doped polysilicon layer 150 include:

[0111] Phosphine and silane gases are introduced, with a flow ratio of phosphine to silane of 1:(2-10), a pressure of 200-500 mTorr, and a temperature of 550-630°C.

[0112] In one example, the PECVD process parameters for the second doped polysilicon layer 150 include:

[0113] Borane, silane, and hydrogen are introduced, with a flow ratio of borane to silane of 1:3 to 3:1, and a flow ratio of silane to hydrogen of 1:2 to 1:10. The pressure is 2000 to 5000 mBar, and the temperature is 400 to 500°C.

[0114] In one example, the PECVD process parameters for the first doped polysilicon layer 130 include:

[0115] Phosphine, silane and hydrogen gases are introduced, with a flow ratio of phosphine to silane of 1:3 to 3:1, a flow ratio of silane to hydrogen of 1:2 to 1:10, a pressure of 2000 to 5000 mBar, and a temperature of 400 to 500°C.

[0116] The thickness of the second doped polysilicon layer 150 can be adjusted by controlling the deposition time. In one example, the thickness of the second doped polysilicon layer 150 is 10 to 80 nm. Furthermore, the thickness of the second doped polysilicon layer 150 is 20 to 70 nm.

[0117] In one exemplary preparation method, after the step of forming the second doped polysilicon layer 150 and before the step of removing the second doped polysilicon layer 150 , the following steps are further included:

[0118] A doped oxide layer 160 is formed on the second doped polysilicon layer 150 .

[0119] The doping type of the doped oxide layer 160 is the same as the doping type of the second doped polysilicon layer 150. If the second doped polysilicon layer 150 is boron-doped, the doped oxide layer 160 is a borosilicate glass layer (BSG layer). If the second doped polysilicon layer 150 is phosphorus-doped, the doped oxide layer 160 is a phosphorus-silicate glass layer (PSG layer).

[0120] In one example, the step of forming the doped oxide layer 160 includes:

[0121] Oxygen is introduced for oxidation, with an oxygen flow rate of 5000-20000 sccm and a temperature of 800-1000°C.

[0122] The thickness of the doped oxide layer 160 can be adjusted by controlling the reaction time. In one example, the thickness of the doped oxide layer 160 is 5 to 50 nm. Furthermore, the thickness of the doped oxide layer 160 is 10 to 40 nm.

[0123] In one example, the preparation method further includes the following steps after forming the second doped polysilicon layer 150 and before forming the doped oxide layer 160:

[0124] The second doped polysilicon layer 150 is annealed.

[0125] In one example, the annealing temperature is 600-1100° C., so that under high temperature process conditions, the second doped polysilicon layer 150 is conducive to attracting impurities from the underlying film layer and impurities introduced during the process into the layer.

[0126] During the annealing process, the gas atmosphere is nitrogen or an inert gas such as argon.

[0127] In one example, the step of removing the second doped polysilicon layer 150 includes:

[0128] The second doped polysilicon layer 150 is subjected to an alkali polishing treatment.

[0129] The alkali solution used in the alkali polishing treatment can be at least one of KOH and NaOH.

[0130] In one example, the alkali polishing process parameters include:

[0131] The concentration of the alkali solution is 2% to 50%, the temperature is 60 to 90° C., and the time is 100 to 700 seconds.

[0132] If the second doped polysilicon layer 150 is not formed, and the surface of the first doped polysilicon layer 130 is directly alkaline polished to remove the surface layer with a high impurity content, the integrity of the first doped polysilicon layer 130 will undoubtedly be damaged and the surface morphology will be destroyed, which is detrimental to battery performance. However, by forming a second doped polysilicon layer 150 with a high doping concentration, the first doped polysilicon layer 130 is gettered during the process to reduce the impurity content of the surface layer of the first doped polysilicon layer 130. Alkaline polishing of the second doped polysilicon layer 150 is then performed, rather than directly performing alkaline polishing on the first doped polysilicon layer 130. This helps reduce damage to the first doped polysilicon layer 130.

[0133] It is understood that when removing the second doped polysilicon layer 150, the ideal effect is to completely remove the second doped polysilicon layer 150 while leaving the first doped polysilicon layer 130 intact. However, controlling the depth of the alkaline polishing process is difficult and has poor precision. To ensure that the second doped polysilicon layer 150 is completely removed, excessive alkaline polishing may occur, resulting in damage to the integrity of the first doped polysilicon layer 130 and destruction of the surface morphology.

[0134] To solve the above problem, as shown in FIG5 , before forming the second doped polysilicon layer 150, a protective layer 140 is formed on the first doped polysilicon layer 130. The second doped polysilicon layer 150 is formed on the protective layer 140, that is, the protective layer 140 is located between the first doped polysilicon layer 130 and the second doped polysilicon layer 150.

[0135] The protective layer can be made of, but is not limited to, silicon oxide. Since silicon oxide is relatively difficult to etch with alkaline solutions, when the second doped polysilicon layer 150 is removed by alkaline polishing, the protective layer 140 can protect the underlying first doped polysilicon layer 130, preventing the first doped polysilicon layer 130 from being etched by the alkaline solution. This prevents damage to the integrity of the first doped polysilicon layer 130 and the surface morphology of the first doped polysilicon layer 130, thereby improving product yield.

[0136] Optionally, the protective layer 140 can be prepared by a dry oxygen method or a wet oxygen method, preferably a wet oxygen method, with a reaction temperature of 800-900°C.

[0137] A protective layer 140 of a certain thickness can provide more effective protection. The thickness of the protective layer 140 can be adjusted by controlling the reaction time. In one example, the thickness of the protective layer 140 is 5 to 50 nm. Furthermore, the thickness of the protective layer 140 is 5 to 15 nm.

[0138] As shown in FIG6 , in one example of the preparation method, before the step of removing the second doped polysilicon layer 150 , the following steps are further included:

[0139] Laser etching forms a first groove 171 in the laser-etched area. The first groove 171 penetrates the second doped polysilicon layer 150 and the protective layer 140 and extends into the first doped polysilicon layer 130 .

[0140] In the example where the doped oxide layer 160 is formed, the doped oxide layer 160 is also removed by laser etching.

[0141] During the laser etching process, the protective layer 140 can protect the first doped polysilicon layer 130 in the non-laser-etched area to prevent the first doped polysilicon layer 130 from being damaged by the laser. The protective layer 140 in the laser-etched area is removed by the laser etching, so that the first groove 171 can be further deepened when the second doped polysilicon layer 150 is subsequently removed by alkaline polishing.

[0142] When the first groove 171 is formed by laser etching, the laser's photothermal effect forms an oxide film 180 with a thickness of 1 to 2 nm at the bottom of the first groove 171, i.e., on the exposed portion of the first doped polysilicon layer 130. This oxide film 180 hinders further alkali polishing of the first groove 171.

[0143] To this end, as shown in FIG7 , after the laser etching step and before the step of removing the second doped polysilicon layer 150, an acid etching process is performed to remove the oxide film 180 formed at the bottom of the first groove 171 due to the laser etching process. The acid etching process can use hydrofluoric acid (HF) with a concentration of 0.01% to 2% and an etching time of 5 to 120 seconds. The acid etching method can be chain acid etching or tank acid etching.

[0144] As shown in FIG8 , the alkaline polishing process facilitates deepening the first groove 171 and extending it to form the second groove 172 with its bottom located in the substrate 110. In other words, the removal of the second doped polysilicon layer 150 and the deepening of the first groove 171 to form the second groove 172 can be completed simultaneously during the alkaline polishing process. For example, the two processes can be completed simultaneously by placing the silicon wafer in a single alkaline polishing tank. This simplifies the manufacturing process and improves production efficiency.

[0145] In one example, the depth of the second groove 172 is 1-10 μm.

[0146] In the example where the doped oxide layer 160 is formed, the doped oxide layer 160 is removed by the aforementioned acid etching process. That is, in the aforementioned preparation process, the laser etching process is performed first, followed by the acid etching process. On the one hand, the acid etching process can remove the oxide film 180 formed on the laser-etched area during the laser etching process, facilitating the subsequent alkaline polishing process. On the other hand, the acid etching process can remove the doped oxide layer 160, thereby enabling the subsequent alkaline polishing process to effectively remove the second doped polysilicon layer 150.

[0147] If the laser etching process is performed after removing the second doped polysilicon layer 150, two acid etching steps are required. Specifically, before removing the second doped polysilicon layer 150, the doped oxide layer 160 must be removed by acid etching. After the laser etching process, the oxide film 180 formed on the laser-etched area must be removed by acid etching again. Therefore, by performing the laser etching process first and then the acid etching process, only one acid etching process is required, simplifying the production process and improving production efficiency.

[0148] As shown in FIG9 , in one example, the method for preparing a solar cell further includes the following steps:

[0149] A second tunneling layer 190 is formed on the bottom of the second groove 172 .

[0150] The material of the second tunneling layer 190 may be, but is not limited to, silicon oxide.

[0151] In one example, the thickness of the second tunneling layer 190 is 1-2 nm.

[0152] As shown in FIG9 , in one example, the method for preparing a solar cell further includes the following steps:

[0153] A third doped polysilicon layer 200 is formed on the second tunneling layer 190 . The doping type of the third doped polysilicon layer 200 is opposite to that of the first doped polysilicon layer 130 .

[0154] In one example, the thickness of the third doped polysilicon layer 200 is 100-400 nm.

[0155] The preparation process of the second tunneling layer 190 and the third doped polysilicon layer 200 may be, but is not limited to, a CVD process, such as LPCVD, PECVD, and the like.

[0156] In one example, the step of forming the third doped polysilicon layer 200 includes:

[0157] forming an intrinsic polysilicon layer on the second tunneling layer 190;

[0158] The intrinsic polysilicon layer is doped to form a third doped polysilicon layer 200 .

[0159] In one example, the third doped polysilicon layer 200 is N-type doped, and the surface doping concentration is 1×10 20 cm -3 ~6×10 21 cm -3 .

[0160] In one example, the third doped polysilicon layer 200 is P-type doped, and the surface doping concentration is 1×10 19 cm -3 ~6×10 20 cm -3 .

[0161] As shown in FIG9 , in one example, the method for preparing a solar cell further includes the following steps:

[0162] A doped silicon oxide film layer 210 is formed on the third doped polysilicon layer 200 .

[0163] As shown in FIG10 , in one example, the method for preparing a solar cell further includes the following steps:

[0164] The doped silicon oxide film layer 210 is partially removed, and the doped silicon oxide film layer 210 corresponding to the position of the second tunneling layer 190 is retained.

[0165] As shown in FIG11 , in one example, the method for preparing a solar cell further includes the following steps:

[0166] Using the retained doped silicon oxide film 210 as a mask, the third doped polysilicon layer 200 outside the coverage of the doped silicon oxide film 210 is removed. The removal method may be alkaline etching.

[0167] In one example, the method for preparing a solar cell further includes the following steps:

[0168] The doped silicon oxide film layer 210 and the protective layer 140 used as a mask are removed by etching with hydrofluoric acid.

[0169] As shown in FIG11 , in one example, the method for preparing a solar cell further includes the following steps:

[0170] The first doped polysilicon layer 130 and the third doped polysilicon layer 200 are insulated and isolated.

[0171] For example, by laser etching, an isolation trench 220 is etched between the first doped polysilicon layer 130 and the third doped polysilicon layer 200 to achieve insulation isolation between the two.

[0172] In one example, the method for preparing a solar cell further includes the following steps:

[0173] The second side of the substrate 110 is cleaned and textured to form a textured structure 230 on the second side.

[0174] As shown in FIG12 , in one example, the method for preparing a solar cell further includes the following steps:

[0175] A first passivation film 240 is formed on the first doped polysilicon layer 130. The material of the first passivation film 240 may be, but is not limited to, aluminum oxide, silicon nitride, or the like.

[0176] As shown in FIG12 , in one example, the method for preparing a solar cell further includes the following steps:

[0177] A second passivation film 250 is formed on the third doped polysilicon layer 200. The material of the second passivation film 250 may be, but is not limited to, aluminum oxide, silicon nitride, or the like.

[0178] The first passivation film 240 and the second passivation film 250 can be prepared simultaneously. At the same time, a third passivation film 260 can also be formed on the front side of the battery.

[0179] As shown in FIG13 , in one example, the method for preparing a solar cell further includes the following steps:

[0180] The first gate line 270 is formed on the first passivation film 240. The first gate line 270 may be formed by screen printing a conductive paste and sintering it.

[0181] As shown in FIG13 , in one example, the method for preparing a solar cell further includes the following steps:

[0182] The second gate line 280 is formed on the second passivation film 250. The second gate line 280 may be formed by screen printing a conductive paste and sintering the paste.

[0183] In one example, a method for preparing a solar cell includes the following steps:

[0184] In step 1 , as shown in FIG. 5 , a first tunneling layer 120 is formed on a first side of a substrate 110 .

[0185] Step 2: forming a first doped polysilicon layer 130 on the first tunneling layer 120 .

[0186] Step 3: forming a protection layer 140 on the first doped polysilicon layer 130 .

[0187] Step 4: forming a second doped polysilicon layer 150 on the protection layer 140 . The doping concentration of the second doped polysilicon layer 150 is higher than the doping concentration of the first doped polysilicon layer 130 .

[0188] Step 5: forming a doped oxide layer 160 on the second doped polysilicon layer 150 .

[0189] In step 6, as shown in FIG6 , laser etching is performed to form a first groove 171 in the laser etched area. The first groove 171 penetrates the doped oxide layer 160 , the second doped polysilicon layer 150 and the protective layer 140 and extends into the first doped polysilicon layer 130 .

[0190] In step 7, as shown in FIG. 7 , an acid etching process is performed to remove the oxide film 180 formed on the bottom of the first groove 171 due to the laser etching process.

[0191] In step 8, as shown in FIG8 , an alkali polishing process is performed to remove the second doped polysilicon layer 150 and further deepen the first groove 171 until a second groove 172 is formed with its bottom located in the substrate 110 .

[0192] In step 9, as shown in FIG9 , a second tunneling layer 190 is formed on the bottom of the second groove 172 .

[0193] In step 10 , an intrinsic polysilicon layer is formed on the second tunneling layer 190 , and is doped to form a third doped polysilicon layer 200 .

[0194] In step 11 , as shown in FIG. 9 , a doped silicon oxide film layer 210 is formed on the third doped polysilicon layer 200 .

[0195] In step 12 , as shown in FIG. 10 , the doped silicon oxide film layer 210 is partially removed, and the doped silicon oxide film layer 210 corresponding to the position of the second tunneling layer 190 is retained.

[0196] In step 13, as shown in FIG. 11 , the third doped polysilicon layer 200 outside the coverage of the doped silicon oxide film layer 210 is removed by alkaline etching using the retained doped silicon oxide film layer 210 as a mask.

[0197] In step 14 , hydrofluoric acid etching is used to remove the doped silicon oxide film layer 210 and the protective layer 140 that serve as a mask.

[0198] In step 15 , as shown in FIG. 11 , an isolation trench 220 is etched between the first doped polysilicon layer 130 and the third doped polysilicon layer 200 by laser etching.

[0199] In step 16, the second side of the substrate 110 is cleaned and textured to form a textured structure 230 on the second side.

[0200] In step 17 , as shown in FIG. 12 , a first passivation film 240 is formed on the first doped polysilicon layer 130 , a second passivation film 250 is formed on the third doped polysilicon layer 200 , and a third passivation film 260 is formed on the second side of the substrate 110 .

[0201] In step 18 , as shown in FIG. 13 , a first gate line 270 is formed on the first passivation film 240 , and a second gate line 280 is formed on the second passivation film 250 .

[0202] The above-mentioned solar cell manufacturing method forms a first doped polysilicon layer 130 on the first tunneling layer 120, forms a protective layer 140 on the first doped polysilicon layer 130, and further forms a second doped polysilicon layer 150 of the same doping type, wherein the doping concentration of the second doped polysilicon layer 150 is higher than the doping concentration of the first doped polysilicon layer 130. Because the segregation coefficients of impurities at low and high doping concentrations are different, impurities tend to accumulate in high-concentration doping areas. During the process, the second doped polysilicon layer 150 with a higher doping concentration can attract impurities from the underlying film layer and impurities introduced during the process. For the first doped polysilicon layer 130, impurities in its surface layer (i.e., the portion close to the second doped polysilicon layer 150) are more attracted to the second doped polysilicon layer 150, thereby reducing the impurity content in the surface layer of the first doped polysilicon layer 130. The second doped polysilicon layer 150 is subsequently removed to obtain a first doped polysilicon layer 130 with a more uniform impurity content. Furthermore, the protective layer 140 protects the first doped polysilicon layer 130 from damage or even removal. This preparation method eliminates the need to intentionally reduce the doping concentration of the first doped polysilicon layer 130, thereby improving the cell passivation effect.

[0203] The above preparation method does not need to deliberately reduce the doping concentration of the first doped polysilicon layer 130 , and the doping concentration can be appropriately increased to optimize the field passivation effect and contact resistance.

[0204] Furthermore, the above preparation method forms the protective layer 140 on the first doped polysilicon layer 130 and the second doped polysilicon layer 150, which can prevent the first doped polysilicon layer 130 from being damaged during the laser etching and alkali polishing processes, thereby improving product yield.

[0205] Furthermore, the above preparation process does not require the use of special chemicals.

[0206] Furthermore, the present invention also provides a solar cell.

[0207] The solar cell according to an embodiment of the present invention is prepared by any of the above-mentioned preparation methods.

[0208] The present invention will be further described below with reference to specific examples and comparative examples, but the present invention is not limited to the following specific examples.

[0209] Example 1

[0210] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0211] In step 1, an N-type silicon wafer is used as the substrate 110 and the substrate 110 is pre-cleaned to remove the mechanical damage layer and dirt.

[0212] Step 2: Load substrate 110 into a quartz boat in the LPCVD equipment, with one or two substrates per tank. Oxygen is introduced at a flow rate of 40,000 sccm, a pressure of 760 Torr, and a temperature of 610°C to form a first tunneling layer 120 with a thickness of 1.4 nm on the first side of substrate 110.

[0213] In step 3, borane and silane are introduced as reaction gases with a flow ratio of 1:6, a pressure of 300 mTorr, and a temperature of 610° C. to form a first doped polysilicon layer 130 with a thickness of 300 nm by in-situ deposition on the first tunneling layer 120 .

[0214] In step 4, an oxidation process is performed at a temperature of 900° C. to form a protective layer 140 with a thickness of 20 nm on the first doped polysilicon layer 130 .

[0215] In step 5, borane and silane are introduced as reaction gases with a flow ratio of 1:3, a pressure of 300 mTorr, and a temperature of 630° C. to form a second doped polysilicon layer 150 with a thickness of 80 nm by in-situ deposition on the protective layer 140 .

[0216] Step 6: annealing treatment is performed at a temperature of 1000°C and a nitrogen atmosphere. Oxygen is introduced for oxidation at a flow rate of 20,000 sccm of oxygen (or nitrous oxide) and a temperature of 1000°C to form a doped oxide layer 160 with a thickness of 30 nm on the second doped polysilicon layer 150. After annealing, the doping concentration of the first doped polysilicon layer 130 is between 5×10 19 cm -3 The doping concentration of the second doped polysilicon layer 150 is 3×10 21 cm -3 .

[0217] In step 7 , laser etching is performed to form a first groove 171 in the laser-etched area. The first groove 171 penetrates the doped oxide layer 160 , the second doped polysilicon layer 150 and the protective layer 140 and extends into the first doped polysilicon layer 130 .

[0218] Step 8: Perform acid etching to remove the oxide film 180 formed on the bottom of the first groove 171 due to the laser etching.

[0219] In step 9, an alkali polishing process is performed to remove the second doped polysilicon layer 150 and further deepen the first groove 171 until a second groove 172 is formed with the bottom thereof located in the substrate 110 .

[0220] In step 10, a second tunneling layer 190 is formed on the bottom of the second groove 172 by an LPCVD process, with a thickness of 1.4 nm.

[0221] Step 11: Form an intrinsic polysilicon layer with a thickness of 300 nm on the second tunneling layer 190 by LPCVD process, and perform phosphorus diffusion process to form a third doped polysilicon layer 200, with a surface doping concentration of 4×10 20 cm -3 .

[0222] Step 12 : forming a doped silicon oxide film layer 210 on the third doped polysilicon layer 200 .

[0223] In step 13 , the doped silicon oxide film layer 210 is partially removed, and the doped silicon oxide film layer 210 corresponding to the position of the second tunneling layer 190 is retained.

[0224] In step 14 , the third doped polysilicon layer 200 outside the coverage of the doped silicon oxide film layer 210 is removed by alkaline etching using the retained doped silicon oxide film layer 210 as a mask.

[0225] In step 15 , hydrofluoric acid etching is used to remove the doped silicon oxide film layer 210 and the protective layer 140 that serve as a mask.

[0226] Step 16: etching an isolation trench 220 between the first doped polysilicon layer 130 and the third doped polysilicon layer 200 by laser etching.

[0227] In step 17 , the second side of the substrate 110 is cleaned and textured to form a textured structure 230 on the second side.

[0228] In step 18 , aluminum oxide and silicon nitride are sequentially deposited on the front and back surfaces to form a first passivation film 240 on the first doped polysilicon layer 130 , a second passivation film 250 on the third doped polysilicon layer 200 , and a third passivation film 260 on the second side of the substrate 110 .

[0229] In step 19, conductive paste is screen-printed on the first passivation film 240 and the second passivation film 250 respectively, and then sintered to form the first gate line 270 and the second gate line 280 .

[0230] Example 2

[0231] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0232] In step 1, an N-type silicon wafer is used as the substrate 110 and the substrate 110 is pre-cleaned to remove the mechanical damage layer and dirt.

[0233] In step 2, the substrate 110 is loaded into a quartz boat of the PECVD equipment, oxygen is introduced at a flow rate of 10,000 sccm, the RF power supply is a 100 kHz square wave or sine wave power supply, the temperature is 450°C, and a first tunneling layer 120 with a thickness of 1.4 nm is formed on the first side of the substrate 110.

[0234] In step 3, the reaction gases silane, hydrogen and borane are introduced, with a flow ratio of borane to silane of 1:2, a pressure of 3000 mBar and a temperature of 450° C. to form a first doped polysilicon layer 130 with a thickness of 300 nm on the first tunneling layer 120 .

[0235] Step 4: performing an oxidation process at a temperature of 500° C. to form a protective layer 140 with a thickness of 20 nm on the first doped polysilicon layer 130 .

[0236] In step 5, the reaction gases silane, hydrogen and borane are introduced, with a flow ratio of borane to silane of 2:1, a pressure of 3000 mBar and a temperature of 480° C. to form a second doped polysilicon layer 150 with a thickness of 80 nm on the protective layer 140 .

[0237] Steps 6 to 19 are the same as steps 6 to 19 in Example 1.

[0238] Example 3

[0239] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0240] In step 1, a P-type silicon wafer is used as the substrate 110 and the substrate 110 is pre-cleaned to remove the mechanical damage layer and dirt.

[0241] Step 2: Load substrate 110 into a quartz boat in the LPCVD equipment, with one or two substrates per tank. Oxygen is introduced at a flow rate of 30,000 sccm, a pressure of 760 Torr, and a temperature of 610°C to form a first tunneling layer 120 with a thickness of 1.4 nm on the first side of substrate 110.

[0242] In step 3, phosphine and silane are introduced as reaction gases with a flow ratio of 1:3, a pressure of 300 mTorr, and a temperature of 630° C. to form a first doped polysilicon layer 130 with a thickness of 300 nm by in-situ deposition on the first tunneling layer 120 .

[0243] In step 4, an oxidation process is performed at a temperature of 900° C. to form a protective layer 140 with a thickness of 20 nm on the first doped polysilicon layer 130 .

[0244] In step 5, phosphine and silane are introduced as reaction gases with a flow ratio of 1:1, a pressure of 300 mTorr, and a temperature of 630° C. to form a second doped polysilicon layer 150 with a thickness of 80 nm by in-situ deposition on the protective layer 140 .

[0245] Step 6: annealing treatment is performed at a temperature of 1000°C and a nitrogen atmosphere. Oxygen is introduced for oxidation at a flow rate of 20,000 sccm and a temperature of 1000°C to form a doped oxide layer 160 with a thickness of 30 nm on the second doped polysilicon layer 150. After annealing, the doping concentration of the first doped polysilicon layer 130 is 4×10 20 cm -3 The doping concentration of the second doped polysilicon layer 150 is 5×10 21 cm -3 .

[0246] Steps 7 to 10 are the same as steps 7 to 10 in Example 1.

[0247] Step 11: Form an intrinsic polysilicon layer with a thickness of 300 nm on the second tunneling layer 190 by LPCVD process, and perform a boron diffusion process to form a third doped polysilicon layer 200 with a surface doping concentration of 5×10 19 cm -3 .

[0248] Steps 12 to 19 are the same as steps 12 to 19 in Example 1.

[0249] Example 4

[0250] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0251] In step 1, a P-type silicon wafer is used as the substrate 110 and the substrate 110 is pre-cleaned to remove the mechanical damage layer and dirt.

[0252] In step 2, the substrate 110 is loaded into a quartz boat of the PECVD equipment, oxygen is introduced at a flow rate of 10,000 sccm, the RF power supply is a 100 kHz square wave or sine wave power supply, the temperature is 450°C, and a first tunneling layer 120 with a thickness of 1.4 nm is formed on the first side of the substrate 110.

[0253] In step 3, silane, hydrogen and phosphine are introduced as reaction gases, with a flow ratio of phosphine to silane of 1:(5-20), a pressure of 3000 mBar and a temperature of 450° C. to form a first doped polysilicon layer 130 with a thickness of 300 nm on the first tunneling layer 120 .

[0254] In step 4, an oxidation process is performed at a temperature of 450° C. to form a protective layer 140 with a thickness of 20 nm on the first doped polysilicon layer 130 .

[0255] In step 5, silane, hydrogen and phosphine are introduced as reaction gases with a flow ratio of phosphine to silane of 2:1, a pressure of 3000 mBar and a temperature of 450° C. to form a second doped polysilicon layer 150 with a thickness of 80 nm on the protective layer 140 .

[0256] Step 6: annealing treatment is performed at a temperature of 1000°C and a nitrogen atmosphere. Oxygen is introduced for oxidation at a flow rate of 20,000 sccm and a temperature of 1000°C to form a doped oxide layer 160 with a thickness of 5-50 nm on the second doped polysilicon layer 150. After annealing, the doping concentration of the first doped polysilicon layer 130 is between 4×10 20 cm -3 The doping concentration of the second doped polysilicon layer 150 is 5×10 21 cm -3 .

[0257] Steps 7 to 10 are the same as steps 7 to 10 in the embodiment.

[0258] Step 11: Form an intrinsic polysilicon layer with a thickness of 300 nm on the second tunneling layer 190 by LPCVD process, and perform a boron diffusion process to form a third doped polysilicon layer 200 with a surface doping concentration of 6×10 19 cm -3 .

[0259] Steps 12 to 19 are the same as steps 12 to 19 in Example 1.

[0260] Comparative Example 1

[0261] The difference between this comparative example and Example 1 is that no protective layer and second doped polysilicon layer are prepared.

[0262] The solar cells prepared by the preparation methods of Examples 1 to 4 and Comparative Example 1 were subjected to performance tests, and the test results are shown in Table 1.

[0263] Table 1 Performance test results of solar cells prepared by the preparation methods of Examples 1 to 4 and Comparative Example 1

[0264] Compared to Comparative Example 1, Example 1 further forms a second doped polysilicon layer with a higher doping concentration on the first doped polysilicon layer to attract impurities and reduce the impurity content on the surface of the first doped polysilicon layer. A protective layer is also formed on the first doped polysilicon layer and the second doped polysilicon layer to prevent damage to the first doped polysilicon layer during laser etching and alkaline polishing. The performance test results in Table 1 show that compared to Comparative Example 1, the conversion efficiency of the solar cells prepared in Examples 1 to 4 increased by approximately 0.2 percentage points, the open-circuit voltage, short-circuit current, and fill factor all increased, and the series resistance decreased. Furthermore, the product yield was significantly improved, from 53% to 85% to 89%.

[0265] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0266] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: The following steps are involved: forming a first tunneling layer on the substrate; forming a first doped polysilicon layer on the first tunneling layer; forming a protective layer on the first doped polysilicon layer; forming a second doped polysilicon layer on the protective layer, wherein the first doped polysilicon layer and the second doped polysilicon layer have the same doping type, and the doping concentration of the second doped polysilicon layer is higher than the doping concentration of the first doped polysilicon layer, so that the second doped polysilicon layer attracts impurities in the first doped polysilicon layer during the process; The second doped polysilicon layer is removed.

2. The preparation method according to claim 1, characterized in that The doping concentration of the second doped polysilicon layer is 3 to 10 times the doping concentration of the first doped polysilicon layer.

3. The preparation method according to claim 2, characterized in that: The first doped polysilicon layer and the second doped polysilicon layer are P-type doped, and the doping concentration of the first doped polysilicon layer is 1×10 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second doped polysilicon layer is 1×10 20 cm -3 ~5×10 21 cm -3 .

4. The preparation method according to claim 2, characterized in that: The first doped polysilicon layer and the second doped polysilicon layer are N-type doped, and the doping concentration of the first doped polysilicon layer is 1×10 20 cm -3 ~1×10 21 cm -3 The doping concentration of the second doped polysilicon layer is 1×10 20 cm -3 ~5×10 22 cm -3 .

5. The preparation method according to any one of claims 1 to 4, characterized in that: The first tunneling layer is formed by an LPCVD process or a PECVD process.

6. The preparation method according to any one of claims 1 to 5, characterized in that: The first doped polysilicon layer is formed by an LPCVD process or a PECVD process.

7. The preparation method according to any one of claims 1 to 6, characterized in that: The second doped polysilicon layer is formed by an LPCVD process or a PECVD process.

8. The preparation method according to any one of claims 1 to 7, characterized in that: After the step of forming the second doped polysilicon layer, the preparation method further comprises the following steps: The second doped polysilicon layer is annealed at a temperature of 600-1100°C.

9. The preparation method according to any one of claims 1 to 8, characterized in that: The thickness of the first tunneling layer is 0.5 nm to 2 nm.

10. The preparation method according to any one of claims 1 to 9, characterized in that: The thickness of the first doped polysilicon layer is 100 nm to 500 nm.

11. The preparation method according to any one of claims 1 to 10, characterized in that: The thickness of the second doped polysilicon layer is 10 nm to 80 nm.

12. The preparation method according to any one of claims 1 to 11, characterized in that: The thickness of the protective layer is 5nm-50nm.

13. The preparation method according to any one of claims 1 to 12, characterized in that: The material of the protection layer is silicon oxide.

14. The preparation method according to any one of claims 1 to 13, characterized in that: The step of removing the second doped polysilicon layer comprises: The second doped polysilicon layer is subjected to an alkali polishing treatment.

15. The preparation method according to claim 14, characterized in that: Before the step of removing the second doped polysilicon layer, the preparation method further comprises the following steps: A first groove is formed in the laser etching area through laser etching, and the first groove penetrates the second doped polysilicon layer and the protective layer and extends into the first doped polysilicon layer.

16. The preparation method according to claim 15, characterized in that: After the step of laser etching and before the step of removing the second doped polysilicon layer, the preparation method further comprises the following steps: Removing the oxide film formed at the bottom of the first groove due to the laser etching process by acid etching; The alkali polishing process deepens the first groove until a second groove with a bottom located in the substrate is formed.

17. The preparation method according to claim 16, characterized in that: Before the laser etching step, the preparation method further comprises the following steps: forming a doped oxide layer on the second doped polysilicon layer; The doped oxide layer is removed during the acid etching process.

18. The preparation method according to claim 16, characterized in that: The preparation method further comprises the following steps: A second tunneling layer is formed on the bottom of the second groove.

19. The preparation method according to claim 18, characterized in that: The preparation method further comprises the following steps: A third doped polysilicon layer is formed on the second tunneling layer, wherein the doping type of the third doped polysilicon layer is opposite to the doping type of the first doped polysilicon layer.

20. The preparation method according to claim 19, characterized in that: The preparation method further comprises the following steps: The first doped polysilicon layer is insulated and isolated from the third doped polysilicon layer.

21. The preparation method according to claim 20, characterized in that: The preparation method further comprises the following steps: A first passivation film is formed on the first doped polysilicon layer, and a second passivation film is formed on the third doped polysilicon layer.

22. The preparation method according to claim 21, characterized in that: The preparation method further comprises the following steps: A first gate line is formed on the first passivation film, and a second gate line is formed on the second passivation film.

23. A solar cell, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 22.

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