Multilayer ceramic capacitor

Abstract

The present invention addresses the problem of providing a multilayer ceramic capacitor having high moisture resistance by preventing infiltration of moisture from a gap between a laminate and an external electrode.　The present invention provides a multilayer ceramic capacitor 1 comprising: a laminate 10 having an inner layer part 100 in which internal electrode layers 30 and dielectric layers 20i are laminated, and side margin parts WG respectively arranged on both sides of the inner layer part 100 in the width direction W; and external electrodes 40 respectively arranged on end faces on both sides of the laminate 10 in the length direction L, wherein the laminate 10 has first glass layers arranged on both sides of the inner layer part 100 in the width direction W so as to extend along the end faces.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been widely used in a variety of electronic devices, including mobile terminal devices such as mobile phones and personal computers. However, with the recent development of electronic devices, there is a growing demand for further miniaturization, higher capacitance, and higher moisture resistance.

[0003] Generally, a multilayer ceramic capacitor has a structure including a laminate having an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and an outer layer portion formed by laminating dielectric layers on the upper and lower parts of the inner layer portion, and external electrodes on both longitudinal end surfaces of the laminate. In order to improve moisture resistance, for example, a SiO ２ A technique for blending different concentrations of these ingredients is known (Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2015-216337

[0005] However, the moisture resistance of a multilayer ceramic capacitor may be reduced if moisture penetrates through the gap between the laminate and the external electrodes and reaches the internal electrode layers exposed at the end faces of the laminate. Therefore, the dielectric layers constituting the inner layer portion and the dielectric layers constituting the outer layer portion are coated with SiO ２ Simply combining different concentrations of these ingredients will not be enough to achieve a satisfactory effect.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that is highly moisture resistant and prevents moisture from penetrating through gaps between the laminate and the external electrodes.

[0007] The inventors discovered that by arranging glass layers extending in the stacking direction along the end faces of the laminate on both widthwise sides of the inner layer portion of the laminate constituting the multilayer ceramic capacitor, it is possible to prevent moisture from penetrating through gaps between the laminate and the external electrodes, thereby achieving high moisture resistance, and thus completed the present invention.

[0008] That is, the present invention is a multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are stacked; side margin portions arranged on both sides of the inner layer portion in a width direction that intersects with the stacking direction; and external electrodes arranged on both end faces of the laminate in a length direction that intersects with the stacking direction and the width direction, wherein the laminate has first glass layers arranged on both sides of the inner layer portion in the width direction so as to follow the end faces.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is highly moisture resistant and that prevents moisture from penetrating through gaps between the laminate and the external electrodes.

[0010] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 1 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II; FIG. 2 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 2 taken along line III-III; FIG. 3 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 3 taken along line IV-IV; FIG. 4 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 3 taken along line V-V; FIG. 4 shows two internal electrode patterns formed on a dielectric sheet; FIG. 1 is a diagram illustrating a process for forming the multilayer ceramic capacitor shown in FIG. 1; FIG. 1 is a diagram illustrating a process for forming the multilayer ceramic capacitor shown in FIG.

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing a multilayer ceramic capacitor, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 2 taken along line III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 3 taken along line IV-IV. Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 3 taken along line V-V. The multilayer ceramic capacitor 1 shown in Figs. 1 to 5 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] 1 to 5 show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also called an LT cross section, the cross section shown in FIG. 3 is also called an LW cross section, and the cross sections shown in FIGS. 4 and 5 are also called WT cross sections.

[0014] The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape and has a first surface P1 and a second surface P2 that face each other in the stacking direction T, a third surface P3 and a fourth surface P4 that face each other in the width direction W, and a fifth surface P5 and a sixth surface P6 that face each other in the length direction L. The surfaces of each surface may be uneven or may be roughened.

[0016] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0017] 2 and 4, the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100 therebetween.

[0018] The internal layer portion 100 includes a plurality of dielectric layers 20i and a plurality of internal electrode layers 30. The internal layer portion 100 is a region in which the dielectric layers 20i and the internal electrode layers 30 are alternately stacked, and is sandwiched between the internal electrode layers 30 located at both ends in the stacking direction T. The internal layer portion 100 is a portion in which the plurality of internal electrode layers 30 are arranged opposite each other via the dielectric layers 20i, and generates electrostatic capacitance and essentially functions as a capacitor.

[0019] The first outer layer portion 201 is disposed on the first surface P1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second surface P2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first surface P1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first surface P1, and the second outer layer portion 202 is disposed between the second surface P2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second surface P2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0020] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 20.

[0021] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 to 2000. The number of dielectric layers 20 is the total number of the dielectric layers 20i of the inner layer portion 100 and the dielectric layers 20o of the outer layer portion 200.

[0022] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0023] The first internal electrode layer 31 includes a first opposing portion 311 and a first lead portion 312 , and the second internal electrode layer 32 includes a second opposing portion 321 and a second lead portion 322 .

[0024] The first facing portion 311 and the second facing portion 321 face each other via the dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the first facing portion 311 and the second facing portion 321 are not particularly limited and may be, for example, approximately rectangular. The first facing portion 311 and the second facing portion 321 are portions that generate electrostatic capacitance and essentially function as capacitors.

[0025] The first lead portion 312 extends from the first opposing portion 311 toward the fifth surface P5 of the laminate 10 and is exposed at the fifth surface P5. The second lead portion 322 extends from the second opposing portion 321 toward the sixth surface P6 of the laminate 10 and is exposed at the sixth surface P6. The lengths of the width direction W of the first opposing portion 311 and the first lead portion 312 may be the same or different. Furthermore, the lengths of these width directions W may gradually change toward the exposed fifth surface P5. The lengths of the width direction W of the second opposing portion 321 and the second lead portion 322 may be the same or different. Furthermore, the lengths of these width directions W may gradually change toward the exposed sixth surface P6.

[0026] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the sixth surface P6 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the fifth surface P5 of the laminate 10, i.e., the first external electrode 41.

[0027] The first internal electrode layer 31 and the second internal electrode layer 32 contain metallic Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0028] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably, 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 sheets or more and 1000 sheets or less.

[0029] The thicknesses of the dielectric layers 20i and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0030] As shown in FIG. 4 , the laminate 10 has, in the width direction W, an electrode facing portion W30 between which the internal electrode layers 30 face, and a first side margin portion WG1 and a second side margin portion WG2 arranged to sandwich the electrode facing portion W30. The first side margin portion WG1 is located between the electrode facing portion W30 and the third surface P3, and the second side margin portion WG2 is located between the electrode facing portion W30 and the fourth surface P4. More specifically, the first side margin portion WG1 is located between the end of the internal electrode layer 30 on the third surface P3 side and the third surface P3, and the second side margin portion WG2 is located between the end of the internal electrode layer 30 on the fourth surface P4 side and the fourth surface P4. The first side margin portion WG1 and the second side margin portion WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side margin portion WG1 and the second side margin portion WG2 are also called W gaps.

[0031] The first side margin portion WG1 and the second side margin portion WG2 may have Si segregation, which can improve the flexural strength of the multilayer ceramic capacitor.

[0032] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end margin LG1, and a second end margin LG2. The first end margin LG1 is located between the electrode facing portion L30 and the fifth plane P5, and the second end margin LG2 is located between the electrode facing portion L30 and the sixth plane P6. More specifically, the first end margin LG1 is located between the end of the second internal electrode layer 32 on the fifth plane P5 side and the fifth plane P5, and the second end margin LG2 is located between the end of the first internal electrode layer 31 on the sixth plane P6 side and the sixth plane P6.

[0033] The first end margin LG1 includes the first internal electrode layer 31 and the dielectric layer 20, but does not include the second internal electrode layer 32. Therefore, a dielectric layer 20z having a thickness equivalent to that of the second internal electrode layer 32 is disposed, thereby eliminating a step at the end of the second internal electrode layer 32 on the fifth surface P5 side. The second end margin LG2 includes the second internal electrode layer 32 and the dielectric layer 20, but does not include the first internal electrode layer 31. Therefore, a dielectric layer 20z having a thickness equivalent to that of the first internal electrode layer 31 is disposed, thereby eliminating a step at the end of the first internal electrode layer 31 on the sixth surface P6 side. Note that the dielectric layer 20z does not necessarily have to be disposed, and the laminate 10 may be formed without disposing the dielectric layer 20z.

[0034] The first end margin LG1 is a portion that functions as an extension electrode portion to the fifth surface P5 of the first internal electrode layer 31, and the second end margin LG2 is a portion that functions as an extension electrode portion to the sixth surface P6 of the second internal electrode layer 32. The first end margin LG1 and the second end margin LG2 are also referred to as an L gap.

[0035] The electrode opposing portion L30 is provided with the first opposing portion 311 of the first internal electrode layer 31 and the second opposing portion 321 of the second internal electrode layer 32. The first end margin portion LG1 is provided with the first lead portion 312 of the first internal electrode layer 31, and the second end margin portion LG2 is provided with the second lead portion 322 of the second internal electrode layer 32.

[0036] An example of a method for measuring the thickness of each portion of the laminate 10 is to observe, using a scanning electron microscope, an LT cross section near the center of the width direction of the laminate exposed by polishing, or a WT cross section near the center of the length direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the length or width direction. Similarly, an example of a method for measuring the length of each portion of the laminate 10 is to observe, using a scanning electron microscope, an LT cross section near the center of the width direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the stacking direction. Similarly, an example of a method for measuring the width of each portion of the laminate 10 is to observe, using a scanning electron microscope, a WT cross section near the center of the length direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the stacking direction.

[0037] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0038] The first external electrode 41 is disposed on the fifth surface P5 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the fifth surface P5 to a portion of the first surface P1 and a portion of the second surface P2. The first external electrode 41 may also extend from the fifth surface P5 to a portion of the third surface P3 and a portion of the fourth surface P4.

[0039] The second external electrode 42 is disposed on the sixth surface P6 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the sixth surface P6 to a portion of the first surface P1 and a portion of the second surface P2. The second external electrode 42 may also extend from the sixth surface P6 to a portion of the third surface P3 and a portion of the fourth surface P4.

[0040] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0041] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0042] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0043] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0044] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0045] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as the fired layer or resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0046] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0047] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0048] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The first plating layer 416 and the second plating layer 426 may each have a three-layer structure, for example, by stacking Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0049] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0050] (Glass Layer) A first glass layer G1 extending in the stacking direction T is arranged along the end face LS of the laminate 10 on both sides in the width direction W of the inner layer portion 100. By arranging the first glass layer G1 along the end face LS of the laminate 10 on both sides in the width direction W of the inner layer portion 100, it is possible to prevent moisture from penetrating through the gap between the laminate 10 and the external electrode 40, and to provide high moisture resistance.

[0051] In the embodiment shown in Figure 3, an example is shown in which the first glass layer G1 is arranged so as to be along the fifth surface P5 and the sixth surface P6, but this is not limited to this, and the first glass layer G1 may be arranged so as to be along either the fifth surface P5 or the sixth surface P6 of the laminate 10.

[0052] As shown in Figure 5, the first glass layer G1 extends from the first surface P1 to the second surface P2, but it does not necessarily have to be arranged continuously from the first surface P1 to the second surface P2. If it is arranged so that it extends in the stacking direction T on both sides of the width direction W of the inner layer portion 100, it is possible to prevent moisture that has penetrated through the gap between the laminate 10 and the external electrode 40 from reaching the internal electrode layer 30.

[0053] A second glass layer G2 extending in the stacking direction T is disposed inside the side margin portions WG on both sides in the width direction W of the inner layer portion 100 so as to follow the end faces LS of the laminate 10. By disposing the second glass layer G2 inside the side margin portions WG so as to follow the end faces LS of the laminate 10, it is possible to prevent moisture from penetrating through gaps between the laminate 10 and the external electrodes 40, thereby providing high moisture resistance.

[0054] The side margin portion WG is composed of an inner layer WGi and an outer layer WGo stacked in the width direction W, and the second glass layer G2 can be disposed between the inner layer WGi and the outer layer WGo. For example, a second glass paste GP2 for forming the second glass layer G2 can be applied to either the inner layer WGi or the outer layer WGo before firing, and the inner layer WGi and the outer layer WGo are stacked with the second glass paste GP2 sandwiched between them, and then fired, thereby disposing the second glass layer G2 inside the side margin portion WG.

[0055] In the embodiment shown in Figure 3, an example is shown in which the second glass layer G2 is arranged so as to be along the fifth surface P5 and the sixth surface P6 of the laminate 10, but this is not limited to this, and the second glass layer G2 may be arranged so as to be along either the fifth surface P5 or the sixth surface P6.

[0056] As shown in Figure 5, the second glass layer G2 extends from the first surface P1 to the second surface P2, but it does not necessarily have to be arranged continuously from the first surface P1 to the second surface P2. If the second glass layer G2 is arranged so that it extends inside the side margin portion WG in the stacking direction T on both sides of the width direction W of the inner layer portion 100, it is possible to prevent moisture that has penetrated through the gap between the laminate 10 and the external electrode 40 from reaching the internal electrode layer 30.

[0057] In this embodiment, an example of a multilayer ceramic capacitor 1 in which a first glass layer G1 and a second glass layer G2 are arranged is shown, but moisture resistance can also be improved by arranging only one of the first glass layer G1 and the second glass layer G2.

[0058] The length in the length direction L of the first glass layer G1 or the length in the length direction L of the second glass layer G2 arranged along the fifth surface P5 may be substantially the same as or shorter than the length in the length direction L of the first lead portion 312 of the first internal electrode layer 31. Furthermore, the length in the length direction L of the first glass layer G1 or the length in the length direction L of the second glass layer G2 arranged along the sixth surface P6 may be substantially the same as or shorter than the length in the length direction L of the second lead portion 322 of the second internal electrode layer 32. By arranging at least one of the first glass layer G1 and the second glass layer G2 having such a length, it is possible to sufficiently obtain the effect of improving moisture resistance.

[0059] Furthermore, in this embodiment, an example is shown in which the lengths in the longitudinal direction L of the first glass layer G1 and the second glass layer G2 are the same, but there may be a difference between the lengths in the longitudinal direction L of the first glass layer G1 and the second glass layer G2, and for example, the length in the longitudinal direction L of the first glass layer G1 may be shorter than the length in the longitudinal direction L of the second glass layer G2.

[0060] (Manufacturing Method) Next, an example of a manufacturing method for the above-mentioned multilayer ceramic capacitor 1 will be described. First, a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0061] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0062] In mass production, a dielectric sheet with two internal electrode patterns as shown in FIG. 6 can be prepared. The coated portions 30N coated with the conductive paste are arranged at intervals in the longitudinal direction L, and ceramic paste is applied between adjacent coated portions 30N to form height adjustment portions 20N. The height adjustment portions 20N are coated with the conductive paste to a thickness approximately equal to that of the coated portions 30N, thereby canceling out any unevenness on the dielectric sheet caused by the application of the conductive paste and smoothing the surface of the dielectric sheet coated with the conductive paste. As shown in FIG. 6, the two internal electrode layer patterns are printed with a shift in the longitudinal direction L. As described below, the dielectric sheets with the two internal electrode patterns are alternately stacked in the stacking direction T and cut along the cutting lines x and y in the stacking direction T to form the structure of the inner layer portion 100 of the laminate 10. In the laminate 10 after firing, the applied portion 30N to which the conductive paste is applied forms the first internal electrode layer 31 and the second internal electrode layer 32 in the inner layer portion 100, the height adjustment portion 20N forms the dielectric layer 20z of the inner layer portion 100, and the dielectric sheet forms the dielectric layer 20i of the inner layer portion 100.

[0063] To form the outer layer portion 200, a predetermined number of dielectric sheets for the second outer layer portion 202, on which no internal electrode patterns are printed, are stacked. Dielectric sheets for the inner layer portion 100, on which two internal electrode patterns are printed, are alternately stacked on top of these. A predetermined number of dielectric sheets for the first outer layer portion 201, on which no internal electrode patterns are printed, are stacked on top of these. This produces a laminated sheet.

[0064] Next, the laminated sheet is pressed in the stacking direction by means of a hydrostatic press or the like to produce a laminated block, which is then cut into a predetermined size in the stacking direction T along cutting lines x and y shown in Figure 6 to cut out laminate chips 10T.

[0065] As shown in Figure 7, the laminate chip 10T is formed in an approximately rectangular shape by alternately stacking multiple material sheets on the surface of the laminate ceramic green sheet 120, which becomes the dielectric layer 20, with a conductive pattern 131 that becomes the first internal electrode layer 31 printed on the surface and a conductive pattern 132 that becomes the second internal electrode layer 32 printed on the surface.

[0066] On one of the pair of end faces 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed, and on the other end face, a conductive pattern 132 is exposed.

[0067] On the third surface 10Tp3 of the laminate chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are arranged on the cut-out exposed third surface 10Tp3 along the lamination direction T. This allows the ends in the width direction W of the multiple internal electrode layers 30 on the third surface P3 side of the laminated ceramic capacitor 1 to be arranged so as to be aligned within a range of 5 μm in the width direction W.

[0068] Similarly, on the fourth surface 10Tp4 of the laminate chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are arranged on the cut-out exposed fourth surface 10Tp4 along the lamination direction T. This allows the ends in the width direction W of the multiple internal electrode layers 30 on the fourth surface P4 side of the laminated ceramic capacitor 1 to be arranged so as to be aligned within a range of 5 μm in the width direction W.

[0069] The third surface 10Tp3 and the fourth surface 10Tp4 of the laminated chip 10T are respectively covered with side covering portions SC for forming a first side margin portion WG1 and a second side margin portion WG2. Ceramic green sheets can be used as the side covering portions SC.

[0070] The side surface covering portion SC can be formed by a third surface covering portion SC1 and a fourth surface covering portion SC2. A first glass paste GP1 is applied to the surface of the third surface covering portion SC1 facing the laminate chip 10T in the stacking direction T so as to follow the end surface LS of the fired laminate 10. Furthermore, a second glass paste GP2 is applied to the surface of the fourth surface covering portion SC2 facing the laminate chip 10T in the stacking direction T so as to follow the end surface LS of the fired laminate 10.

[0071] The first glass paste GP1 can be applied to the third-surface covering portion SC1, and the second glass paste GP2 can be applied to the fourth-surface covering portion SC2 by, for example, screen printing or gravure printing. The thickness of the first glass paste and the second glass paste can be controlled by changing the thickness of the printing plate. Furthermore, the hardness of the first glass layer G1 and the second glass layer G2 after firing can be controlled by changing the glass composition ratio.

[0072] By arranging a third surface covering portion SC1 coated with a first glass paste GP1 and a fourth surface covering portion SC2 coated with a second glass paste GP2 on the third surface 10Tp3 and the fourth surface 10Tp4 of the laminate chip 10T, respectively, the laminate 10 after firing has a structure in which a first glass layer G1 extending in the stacking direction T so as to follow the end surface LS of the laminate 10 is arranged on both sides of the width direction W of the inner layer portion 100, and a second glass layer G2 extending in the stacking direction T so as to follow the end surface LS of the laminate 10 is arranged inside the side margin portion WG.

[0073] 7 illustrates a process of applying a first glass paste GP1 to the third surface covering portion SC1 and attaching the third surface covering portion SC1 coated with the first glass paste to the side surface of the laminated chip 10T, but is not limited to such a process. For example, the process may be a process of applying the first glass paste GP1 to the side surface of the laminated chip 10T and attaching the third surface covering portion SC1 thereon. Also, the process of applying a second glass paste GP2 to the fourth surface covering portion SC2 and attaching the fourth surface covering portion SC2 coated with the second glass paste GP2 to the third surface covering portion SC1, but is not limited to such a process. For example, the process may be a process of applying the second glass paste GP2 to the third surface covering portion SC1 and attaching the fourth surface covering portion SC2 thereon.

[0074] 7 shows an example in which the first glass paste GP1 is applied to the laminate 10 after firing so as to follow the fifth surface P5 and the sixth surface P6, but the present invention is not limited thereto, and the first glass paste GP1 can be applied to either the fifth surface P5 or the sixth surface P6. Similarly, the present invention shows an example in which the second glass paste GP2 is applied to the laminate 10 after firing so as to follow the fifth surface P5 and the sixth surface P6, but the present invention is not limited thereto, and the second glass paste GP2 can be applied to either the fifth surface P5 or the sixth surface P6.

[0075] As a result of the above, an unfired laminate chip 10T with a side covering portion SC coated with glass paste is formed, as shown in Fig. 8. Next, this laminate chip 10T is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0076] Next, the fifth surface P5 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the first base electrode layer 415 to the fifth surface P5. Similarly, the sixth surface P6 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the second base electrode layer 425 to the sixth surface P6. These conductive pastes are then fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0077] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then firing it, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0078] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

[0079] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention.

[0080] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 20i Dielectric layer 20o Dielectric layer 20z Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First opposing portion 312 First lead portion 32 Second internal electrode layer 321 Second opposing portion 322 Second lead portion 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Internal layer portion 200 External layer portion 201 First external layer portion 202 Second external layer portion L30 Electrode opposing portion LG1 First end margin portion LG2 Second end margin portion W30 Electrode opposing portion WG1 First side margin portion WG2 Second side margin L: Lengthwise direction T: Lamination direction W: Widthwise direction G1: First glass layer G2: Second glass layer P1: First surface P2: Second surface P3: Third surface P4: Fourth surface P5: Fifth surface P6: Sixth surface

Claims

1. A multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are laminated; a laminate having side margin portions arranged on both sides of the inner layer portion in a width direction that intersects with the lamination direction; and external electrodes arranged on both end faces of the laminate in a length direction that intersects with the lamination direction and the width direction, wherein the laminate has a first glass layer arranged on both sides of the width direction of the inner layer portion so as to follow the end faces.

2. A multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are laminated; side margin portions arranged on both sides of the inner layer portion in a width direction intersecting with the lamination direction; and external electrodes arranged on both end faces of the laminate in a length direction intersecting with the lamination direction and the width direction, wherein the laminate has a second glass layer arranged inside the side margin portions so as to follow the end faces of the laminate.

3. A multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are laminated; and side margin portions arranged on both sides of the inner layer portion in a width direction intersecting with the lamination direction; and external electrodes arranged on both end faces of the laminate in a length direction intersecting with the lamination direction and the width direction, wherein the laminate includes: a first glass layer arranged on both sides of the width direction of the inner layer portion so as to follow the end faces; and a second glass layer arranged inside the side margin portions so as to follow the end faces.

4. The multilayer ceramic capacitor according to claim 2 or 3, wherein the side margin portion includes an outer layer and an inner layer disposed on the inner layer side of the outer layer, and the second glass layer is disposed between the inner layer and the outer layer.

5. A method for manufacturing a multilayer ceramic capacitor as described in claim 1 or 3, comprising applying a glass paste for forming the first glass layer to at least one of the inner layer portion and the side margin portion before firing, attaching the unfired side margin portions to both sides of the inner layer portion in the width direction, and firing to form the laminate.

6. A method for manufacturing a multilayer ceramic capacitor as set forth in claim 4, comprising the steps of: applying a glass paste for forming the second glass layer to at least one of the unsintered inner layer and the unsintered outer layer; attaching the unsintered inner layer and the unsintered outer layer to both sides in the width direction of the inner layer portion before firing; and firing to form the laminate.

7. A multilayer ceramic capacitor comprising: a laminate in which internal electrodes and dielectric layers are laminated, the laminate having first and second surfaces opposing each other in a lamination direction, third and fourth surfaces opposing each other in a width direction intersecting the lamination direction, and fifth and sixth surfaces opposing each other in a length direction intersecting the lamination direction and the width direction; and external electrodes provided on the fifth and sixth surfaces of the laminate, the laminate including: an inner layer portion in which the internal electrodes are arranged to face each other in the lamination direction via the dielectric layer; and side margin portions arranged on the third and fourth surfaces of both sides of the width direction of the inner layer portion, and a glass layer is arranged on at least one of both sides of the width direction of the inner layer portion and inside the side margin portion so as to follow the fifth and sixth surfaces of the laminate.

8. A laminate in which internal electrodes and dielectric layers are laminated, the laminate having a first surface and a second surface opposing each other in a lamination direction, a third surface and a fourth surface opposing each other in a width direction intersecting the lamination direction, and a fifth surface and a sixth surface opposing each other in a length direction intersecting the lamination direction and the width direction, a first external electrode provided on the fifth surface side of the laminate, and a second external electrode provided on the sixth surface side of the laminate, the internal electrode including a first extension portion extended to the fifth surface side of the laminate so as to connect with the first external electrode, and a second extension portion extended to the sixth surface side of the laminate so as to connect with the second external electrode, the laminate comprising: an inner layer portion in which the internal electrodes are disposed to face each other in the lamination direction via the dielectric layer; side margin portions disposed on the third surface side and the fourth surface side from both sides in the width direction of the inner layer portion; a glass layer arranged along a fifth surface and a sixth surface of the laminate on at least one of both sides in the width direction of the inner layer portion and the inside of the side margin portion, the glass layer having a length approximately equal to or shorter than each of the first lead portion and the second lead portion in the longitudinal direction of the laminate.

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