Array substrate and manufacturing method therefor, display panel, and display device

Abstract

An array substrate and a manufacturing method therefor, a display panel, and a display device. The array substrate comprises: a base substrate; a gate insulating layer located on one side of the base substrate; a gate layer located on the side of the gate insulating layer away from the base substrate; an interlayer insulating layer located on the side of the gate layer away from the base substrate, wherein the interlayer insulating layer comprises a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer which are stacked, the first sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer close to the gate layer, the third sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer away from the base substrate, and the third sub-interlayer insulating layer overlaps with a source / drain layer; and the source / drain layer located on the side of the interlayer insulating layer away from the base substrate, wherein the source / drain layer is provided with a pattern area and an opening area surrounding the pattern area, and the film thickness of the part overlapping with the pattern area in the second sub-interlayer insulating layer is greater than the film thickness of the part overlapping with the opening area in the second sub-interlayer insulating layer.

Description

Array substrate and manufacturing method thereof, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] Currently, in array substrates manufactured using LTPS technology, the gate material of transistors is Mo (molybdenum). To improve the driving capability of transistors, MAM (MoALMo, molybdenum aluminum molybdenum) is used to replace the Mo originally used in the gate.

[0003] However, existing LTPS MAM products are prone to problems such as yellowish color coordinates and color shift.

[0004] Summary of the Invention

[0005] The embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a display panel, and a display device, so as to solve the problems of yellowish color coordinates and color shift in LTPS MAM products in the prior art.

[0006] In a first aspect, to solve the above technical problems, the present disclosure provides an array substrate, including:

[0007] substrate;

[0008] a gate insulating layer, located on one side of the base substrate;

[0009] a gate layer, located on a side of the gate insulating layer away from the substrate;

[0010] an interlayer insulating layer located on a side of the gate layer away from the base substrate; the interlayer insulating layer includes a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer stacked together, the first sub-interlayer insulating layer being located on a side of the second sub-interlayer insulating layer close to the gate layer, the third sub-interlayer insulating layer being located on a side of the second sub-interlayer insulating layer away from the base substrate, and the third sub-interlayer insulating layer overlapping the source and drain layers;

[0011] a source-drain electrode layer, located on a side of the interlayer insulating layer away from the base substrate; the source-drain electrode layer comprises a pattern area and an opening area surrounding the pattern area;

[0012] The thickness of a portion of the second interlayer insulating layer overlapping with the pattern area is greater than the thickness of a portion of the second interlayer insulating layer overlapping with the opening area.

[0013] In a possible implementation manner, the thickness of the third interlayer insulating layer is smaller than the thickness of the first interlayer insulating layer.

[0014] In a possible implementation manner, the thickness of the third sub-interlayer insulating layer is the minimum etching loss amount of the interlayer insulating layer when etching the source and drain electrode layer.

[0015] In a possible implementation manner, the gate insulating layer includes:

[0016] A first sub-gate insulating layer and a second sub-gate insulating layer, wherein the first sub-gate insulating layer is located on a side of the second sub-gate insulating layer close to the array substrate.

[0017] In a possible implementation manner, the array substrate has a plurality of pixel opening areas arranged in an array;

[0018] The interlayer insulating layer and the second sub-gate insulating layer have through holes penetrating the film layer in the pixel opening area, and the orthographic projection area of ​​the through holes on the base substrate is substantially the same as the orthographic projection area of ​​the pixel opening area on the base substrate.

[0019] In a possible implementation manner, a longitudinal section of the through hole includes an inverted trapezoidal shape.

[0020] In a possible implementation manner, the array substrate further includes:

[0021] a buffer layer, located between the base substrate and the gate insulating layer;

[0022] a planar layer, located on a side of the source and drain electrode layer away from the substrate;

[0023] a first electrode layer, located on a side of the planar layer away from the substrate;

[0024] a passivation layer, located on a side of the first electrode layer away from the substrate;

[0025] The second electrode layer is located on a side of the passivation layer away from the substrate.

[0026] In a possible implementation manner, the gate layer is made of a material including molybdenum-aluminum-molybdenum.

[0027] In a possible implementation manner, an etching selectivity ratio of the source-drain electrode layer to the first inter-sub-layer insulating layer is smaller than an etching selectivity ratio of the source-drain electrode layer to the second inter-sub-layer insulating layer.

[0028] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, comprising:

[0029] providing a substrate;

[0030] forming a gate insulating layer on one side of the base substrate;

[0031] forming a gate layer on a side of the gate insulating layer away from the substrate;

[0032] An interlayer dielectric layer is formed on a side of the gate layer away from the base substrate; the interlayer insulating layer includes a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer stacked together, wherein the first sub-interlayer insulating layer is located on a side of the second sub-interlayer insulating layer close to the gate layer, the third sub-interlayer insulating layer is located on a side of the second sub-interlayer insulating layer away from the base substrate, and the third sub-interlayer insulating layer overlaps with the source and drain layer;

[0033] A source-drain layer is formed on a side of the interlayer dielectric layer away from the substrate; an etching selectivity of the source-drain layer to the first sub-interlayer insulating layer is smaller than an etching selectivity of the source-drain layer to the second sub-interlayer insulating layer.

[0034] In one possible implementation, a gate layer is formed on a side of the gate insulating layer away from the substrate, including:

[0035] Depositing a molybdenum-aluminum-molybdenum layer on a side of the gate insulating layer away from the substrate;

[0036] forming a photoresist layer on a side of the molybdenum-aluminum-molybdenum layer away from the substrate;

[0037] Transferring the pattern of the mask to the photoresist layer to obtain a patterned photoresist layer;

[0038] The molybdenum-aluminum-molybdenum layer is etched by wet etching to transfer the pattern of the patterned photoresist layer to the molybdenum-aluminum-molybdenum layer to obtain the gate layer.

[0039] In one possible implementation manner, before forming the gate insulating layer on one side of the substrate, the method further includes:

[0040] forming a buffer layer on a side of the base substrate close to the gate insulating layer;

[0041] An active layer is formed between the buffer layer and the gate insulating layer.

[0042] In a possible implementation manner, after etching the molybdenum-aluminum-molybdenum layer using a wet etching method, the method further includes:

[0043] doping the active layer;

[0044] The patterned photoresist layer is removed.

[0045] In a possible implementation manner, an interlayer dielectric layer is formed on a side of the gate layer away from the substrate, including:

[0046] Depositing a first intersub-layer insulating layer on a side of the gate layer away from the substrate;

[0047] Depositing a second intersub-layer insulating layer on a side of the first intersub-layer insulating layer away from the substrate;

[0048] The third sub-interlayer insulating layer is deposited on a side of the second interlayer insulating layer away from the base substrate.

[0049] In one possible implementation, forming a gate insulating layer on one side of the substrate includes:

[0050] Depositing a first sub-gate insulating layer on a side of the active layer away from the substrate;

[0051] A second sub-gate insulating layer is deposited on a side of the first sub-gate insulating layer away from the substrate.

[0052] In a possible implementation manner, a source and drain layer is formed on a side of the interlayer dielectric layer away from the substrate, including:

[0053] Depositing a metal layer on a side of the interlayer dielectric layer away from the substrate;

[0054] The metal layer is patterned to expose the second inter-sub-layer insulating layer to obtain the source-drain electrode layer.

[0055] In a possible implementation manner, the array substrate includes a plurality of pixel opening areas, and after forming the source and drain electrode layers, further includes:

[0056] In the pixel opening area, the interlayer dielectric layer and the second sub-gate insulating layer are bored to form a through hole penetrating the interlayer dielectric layer and the second sub-gate insulating layer.

[0057] In a possible implementation manner, after forming a through hole penetrating the interlayer dielectric layer and the second sub-gate insulating layer, the method further includes:

[0058] forming a flat layer on a side of the source and drain electrode layer away from the base substrate; wherein the flat layer fills the through hole;

[0059] forming a first electrode layer on a side of the planar layer away from the base substrate;

[0060] forming a passivation layer on a side of the common electrode layer away from the base substrate;

[0061] A second electrode layer is formed on a side of the passivation layer away from the substrate.

[0062] In a third aspect, an embodiment of the present disclosure provides a display panel, including:

[0063] The array substrate according to the first aspect;

[0064] a counter substrate, arranged opposite to the array substrate;

[0065] The liquid crystal layer is located between the array substrate and the cell-matching substrate.

[0066] In a fourth aspect, an embodiment of the present disclosure provides a display device comprising the display panel as described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] FIG1 is a schematic diagram of a film layer model of an array substrate in the related art;

[0068] FIG2 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0069] FIG3 is a top view of a source and drain layer in an array substrate provided by an embodiment of the present disclosure;

[0070] FIG4 is a cross-sectional view taken along the AA′ direction in FIG3 provided by an embodiment of the present disclosure;

[0071] FIG5 is a diagram showing the etching depth distribution of the second interlayer insulating layer after forming the source and drain layers according to an embodiment of the present disclosure;

[0072] FIG6 is a schematic diagram showing the side etching of the source and drain layers according to an embodiment of the present disclosure;

[0073] FIG7 is a film thickness distribution diagram of the silicon nitride layer in the interlayer insulating layer after the source and drain layers are formed in the related art;

[0074] FIG8 is a film thickness distribution diagram of the first sub-interlayer insulating layer in the interlayer insulating layer after forming the source and drain electrode layers according to an embodiment of the present disclosure;

[0075] FIG9 is a schematic structural diagram of a gate insulating layer provided by an embodiment of the present disclosure;

[0076] FIG10 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0077] FIG11 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0078] FIG12 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0079] FIG13 is a schematic diagram of manufacturing an array substrate provided by an embodiment of the present disclosure;

[0080] FIG14 is a flow chart of forming a buffer layer and a source / drain layer according to an embodiment of the present disclosure;

[0081] FIG15 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0082] FIG16 is a schematic diagram of a process flow of a gate layer provided by an embodiment of the present disclosure;

[0083] FIG17 is a schematic diagram of another process flow of a gate layer provided by an embodiment of the present disclosure;

[0084] FIG18 is a flow chart of forming a source and drain layer according to an embodiment of the present disclosure;

[0085] FIG19 is a schematic diagram of etching loss of an interlayer insulating layer when etching a source / drain layer according to an embodiment of the present disclosure;

[0086] FIG20 is a schematic diagram of etching loss of an interlayer insulating layer when etching a source / drain layer according to another embodiment of the present disclosure;

[0087] FIG21 is a schematic diagram of a through hole forming a pixel opening area provided by an embodiment of the present disclosure;

[0088] FIG22 is a schematic diagram of manufacturing another array substrate provided by an embodiment of the present disclosure;

[0089] FIG23 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] The embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a display panel, and a display device, so as to solve the problem in the prior art that LTPS MAM products are prone to yellowish color coordinates.

[0091] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present disclosure are all explained using the accompanying drawings as examples, but changes can be made as needed, and all changes are included in the scope of protection of the present disclosure. The drawings of the present disclosure are only used to illustrate relative position relationships and do not represent true proportions.

[0092] It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present disclosure. However, the present disclosure can be implemented in a variety of ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present disclosure. Therefore, the present disclosure is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present disclosure, but the description is for the purpose of illustrating the general principles of the present disclosure and is not intended to limit the scope of the present disclosure. The scope of protection of the present disclosure shall be as defined by the appended claims.

[0093] Related technology introduction:

[0094] Please refer to FIG1 which is a schematic diagram of a film layer model of an array substrate in the related art.

[0095] The array substrate includes a base substrate 1', a buffer layer 2' located on one side of the base substrate, a gate insulating layer 3' located on the side of the buffer layer 2' away from the base substrate 1', and an interlayer insulating layer 4' located on the side of the gate insulating layer 3' away from the base substrate 1'.

[0096] The gate insulating layer 3' includes a silicon oxide layer (SiOx) 31' and a silicon nitride layer (SiNx) 32' on one side. The silicon oxide layer 31' is located on the side of the buffer layer 2' away from the base substrate 1', and the silicon nitride layer 32' is located on the side of the silicon oxide layer 2' away from the base substrate 1'.

[0097] The interlayer insulating layer 4' also includes a silicon oxide layer (SiOx) 41' and a silicon nitride layer (SiNx) 42'. The silicon oxide layer 41' is located on the side of the buffer layer 2' away from the substrate 1', and the silicon nitride layer 42' is located on the side of the silicon oxide layer 41' away from the substrate 1'.

[0098] In addition, the LTPS MAM display panel eliminates the dry etching process in the process of forming the gate, so there will be no etching loss of the gate insulation layer located below the gate (not shown in Figure 1, the gate is located between the gate insulation layer and the interlayer insulation layer).

[0099] An array substrate and a manufacturing method thereof, a display panel, and a display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0100] Referring to Figures 2-4, Figure 2 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure, Figure 3 is a top view of a source and drain layer in an array substrate provided in an embodiment of the present disclosure, and Figure 4 is a cross-sectional view taken along the AA' direction in Figure 3 provided in an embodiment of the present disclosure. The array substrate includes:

[0101] Base substrate 1;

[0102] A gate insulating layer 2 is located on one side of the substrate 1;

[0103] The gate layer 3 is located on a side of the gate insulating layer 2 away from the substrate 1;

[0104] The interlayer insulating layer 4 is located on the side of the gate layer 3 away from the substrate 1; the interlayer insulating layer 4 includes a first sub-interlayer insulating layer 41, a second sub-interlayer insulating layer 42, and a third sub-interlayer insulating layer 43 stacked together, the first sub-interlayer insulating layer 41 is located on the side of the second sub-interlayer insulating layer 42 close to the gate layer 3; the third sub-interlayer insulating layer 43 is located between the second sub-interlayer insulating layer 42 and the source and drain layer 5, and the third sub-interlayer insulating layer 43 overlaps with the source and drain layer 5

[0105] The source-drain electrode layer 5 is located on the side of the interlayer insulating layer 4 away from the base substrate 1; as shown in FIG3 and FIG4 , the source-drain electrode layer 5 has a pattern area A1 and an opening area A2 surrounding the pattern area A1;

[0106] The thickness of the portion of the second interlayer insulating layer 42 overlapping the pattern area A1 is greater than the thickness of the portion of the second interlayer insulating layer 42 overlapping the opening area A2 .

[0107] As shown in FIG3 , in the etching process of the source / drain layer 5, after the third sub-interlayer insulating layer 43 in the interlayer insulating layer 4 is completely etched, the second sub-interlayer insulating layer 42 is usually further etched. As shown in FIG4 , if the thickness of the third sub-interlayer insulating layer 43 is The thickness of the second interlayer insulating layer 42 is The thickness of the first interlayer insulating layer 41 is In the etching process of etching the source and drain layer 5, the etching loss is approximately The thickness of the portion of the second interlayer insulating layer 42 that overlaps with the opening A2 is (After considering the error, approx. ), the thickness of the portion of the second interlayer insulating layer 42 that overlaps with the pattern area A1 is Therefore, the thickness of the portion of the second interlayer insulating layer 42 that overlaps with the pattern area A1 is greater than the thickness of the portion of the second interlayer insulating layer 42 that overlaps with the opening area A2. An α-Step device can be used to measure the etch depth profile of the second interlayer insulating layer 42 after etching the source and drain layers. FIG5 shows an etch depth profile of the second interlayer insulating layer after forming the source and drain layers, as provided in an embodiment of the present disclosure.

[0108] In some embodiments, the etching selectivity of the source / drain layer 5 to the first interlayer insulating layer 41 is smaller than the etching selectivity of the source / drain layer 5 to the second interlayer insulating layer 42 .

[0109] In some embodiments, the material used for the first interlayer insulating layer 41 may be silicon nitride (SiNx), and the material used for the second interlayer insulating layer 42 may be silicon oxide (SiOx). Since the etching selectivity of the source and drain layer 5 to the silicon nitride in the interlayer insulating layer 4 is S SD / SiNx =E SD :E SiNx =1.73:1, and the etching selectivity of the source and drain layer 5 to the silicon oxide in the interlayer insulating layer 4 is S SD / SiOx =E SD :E SiOx =2.01:1, so the etching fluctuation of SiOx in the interlayer insulating layer 4 when etching the source and drain layers is smaller than that of SiNx; at the same time, the etching fluctuation of SiOx in the interlayer insulating layer 4 has little effect on optical color deviation, which can greatly improve optical stability.

[0110] In some embodiments, the third interlayer insulating layer 43 is used to improve the serration defects that may exist in the source / drain layer 5. The third interlayer insulating layer 43 and the first interlayer insulating layer 41 are made of the same material, such as silicon nitride (SiNx). The third interlayer insulating layer 43 and the first interlayer insulating layer 41 can also be made of different materials, such as an oxidation-resistant material.

[0111] If the second interlayer insulating layer 42 is the top film layer in the interlayer insulating layer 4, when etching the metal layer corresponding to the source and drain layer 5, a portion of the second interlayer insulating layer 42 will be etched, causing the oxygen in the second interlayer insulating layer 42 to overflow, resulting in the destruction of the side complex protection of the source and drain layer 5; the Cl2 used for etching further etches the side of the source and drain layer 5, and gathers into the source and drain layer 5 at the location where the complex is damaged in the form of a hole, resulting in severe local lateral etching of the source and drain layer 5, forming sawtooth. As shown in Figure 6, a schematic diagram of the side etching of the source and drain layer provided in an embodiment of the present disclosure is shown.

[0112] If a layer of silicon nitride is deposited on the side of the second interlayer insulating layer 42 away from the base substrate 1 as the third interlayer insulating layer 43, during the etching process of the source-drain layer 5, the oxygen overflow in the second interlayer insulating layer 42 can be reduced or even prevented, thereby improving the formation of serrations in the side walls of the source-drain layer 5 and improving the product yield; and, since the third interlayer insulating layer 43 overlaps with the source-drain layer 5 after the source-drain layer 5 is formed, the third interlayer insulating layer 43 does not affect the optical stability of the backlight passing through the array substrate.

[0113] It should be understood that, ideally, after the source and drain layer 5 is formed, the third interlayer insulating layer 43 overlaps with the pattern area A1 of the source and drain layer 5. However, in the silicon nitride coating process, due to coating fluctuations, the actual thickness of the third interlayer insulating layer 43 may vary, and there are also etching fluctuations when etching the source and drain layer 5, so that there may be some residue in the area of ​​the third interlayer insulating layer 43 at the location with thicker film thickness that is not covered by the pattern area A1 of the source and drain layer 5. However, the third interlayer insulating layer 43 in the area with thinner film thickness overlaps with the pattern area A1 of the source and drain layer 5. These situations should be regarded as the third interlayer insulating layer 43 overlapping with the pattern area A1 of the source and drain layer 5.

[0114] For example, in solution 1, an array substrate is prepared using the film layer solution in the related art in FIG. 1 , wherein the thickness of the silicon oxide layer 41 ′ at the bottom of the interlayer insulating layer 4 ′ is The thickness of the silicon nitride layer 42' on the top layer is When the source-drain electrode layer 5 is formed on the upper layer of the interlayer insulating layer 4', the etching loss of the interlayer insulating layer 4' is

[0115] Solution 2: An array substrate is prepared using the film solution in FIG. 2 of the present disclosure, wherein the thickness of the first sub-interlayer insulating layer 41 (SiNx) located at the bottom of the interlayer insulating layer 4 is The coating thickness of the second sub-layer insulating layer 42 (SiOx) located in the second layer is The thickness of the third interlayer insulating layer 43 (SiNx) located at the top layer is When the source-drain electrode layer 5 is formed on the upper layer of the interlayer insulating layer 4, the etching loss of the interlayer insulating layer 4 is Assume that the coating fluctuation of silicon nitride in the above two schemes is The etching fluctuation of silicon nitride is

[0116] In the first embodiment, the silicon nitride layer 42' is formed into a film with a thickness of Since the silicon nitride layer 42' is located on the top layer of the interlayer insulating layer 4', when etching the metal layer corresponding to the source and drain layer 5 on the interlayer insulating layer 4', a portion of the silicon nitride layer 42' will be etched. Specifically, At this time, the film thickness of the silicon nitride layer 42' (the portion not covered by the opening region A2 of the source / drain layer 5) becomes Since there is a film fluctuation when the silicon nitride layer 42' is formed by film deposition, When etching the silicon nitride layer 42', there is etching fluctuation. Therefore, the coating + etching fluctuation of the silicon nitride layer 42' in solution 1 is (about 14%). Please refer to FIG7 , which is a film thickness distribution diagram of the silicon nitride layer in the interlayer insulating layer after the source and drain layers are formed in the related art.

[0117] In solution 2, the first interlayer insulating layer 41 is formed by plating to a thickness of Since the first interlayer insulating layer 41 is located at the bottom of the interlayer insulating layer 4, when etching the metal layer corresponding to the source and drain electrode layer 5 on the upper layer of the interlayer insulating layer 4, the first interlayer insulating layer 41 will not be etched, but the second interlayer insulating layer 42 and the third interlayer insulating layer 43 located in the interlayer insulating layer 4 will be etched. Therefore, after the source and drain electrode layer 5 are formed, the film thickness of the first interlayer insulating layer 41 is still Since there is a coating fluctuation when the first interlayer insulating layer 41 is formed by coating, The first interlayer insulating layer 41 is not etched, and the third interlayer insulating layer 43 is completely etched away. Therefore, the coating fluctuation of the first interlayer insulating layer 41 in scheme 2 is Completely etching away the portion of the third interlayer insulating layer 43 located in the pixel area does not affect optical color shift and can also improve aliasing defects that may exist in the source and drain electrode layer 5. Figure 8 shows the thickness distribution of the first interlayer insulating layer in the interlayer insulating layer after forming the source and drain electrode layer according to an embodiment of the present disclosure.

[0118] Please refer to Table 1 for a comparison of factors affecting the film thickness of silicon nitride of the interlayer insulating layer 4 in the related art and silicon oxide in the present disclosure.

[0119] Table 1

[0120] Through the above analysis, it can be seen that by placing the first sub-interlayer insulating layer 41 at the bottom layer of the interlayer insulating layer 4 in the present disclosure, when forming the source and drain layer 5, even if a portion of the interlayer insulating layer 4 is etched, the etching loss is the second sub-interlayer insulating layer 42 and the third sub-interlayer insulating layer 43. Compared with silicon nitride, silicon oxide has almost no effect on optical color deviation. Therefore, the backlight will not produce color deviation when passing through the array substrate due to the large fluctuation in the film thickness of the second sub-interlayer insulating layer 42 and the third sub-interlayer insulating layer 43, thereby improving the problem of yellowish color coordinates and color deviation in the display product in the related technology, and can also improve the possible jaggedness of the source and drain layer 5.

[0121] In the embodiment provided by the present disclosure, the silicon oxide layer 41' and the silicon nitride layer 42' (as shown in FIG. 1 ) in the interlayer insulating layer 4' in the related art are inverted to form the first sub-interlayer insulating layer 41 and the second sub-interlayer insulating layer 42 of the interlayer insulating layer 4 in the present disclosure, so that the first sub-interlayer insulating layer 41 is located on the side of the second sub-interlayer insulating layer 42 close to the gate layer 3. As a result, compared with the related art (the silicon nitride layer 42' is located on the top of the interlayer insulating layer 4'), the first sub-interlayer insulating layer 41 is no longer affected by the original coating fluctuation and etching fluctuation (as shown in FIG. 6 ), but is only affected by the coating fluctuation. This reduces the film thickness fluctuation of the first sub-interlayer insulating layer 41 and improves the optical stability of the first silicon nitride film layer. Since silicon oxide has little effect on optics and the etching fluctuation of silicon oxide is smaller than that of silicon nitride, it can effectively improve the optical stability and effectively improve the yellowing of color coordinates and color cast problems of display products in the related art. In addition, since a third sub-layer interlayer insulating layer 43 is provided on the side of the second sub-layer interlayer insulating layer 42 away from the base substrate 1, the third sub-layer interlayer insulating layer 43 can be used to prevent oxygen from overflowing from the second sub-layer interlayer insulating layer 42 and to form a buffering effect on the source and drain layer 5 when etching the source and drain layer 5, thereby protecting the source and drain layer 5 from being oxidized during the etching process and preventing the source and drain layer 5 from having sawtooth defects.

[0122] In some embodiments, the gate layer 3 is made of molybdenum-aluminum-molybdenum.

[0123] In the embodiments provided herein, by using molybdenum-aluminum-molybdenum as the material for gate layer 3, the driving capability of the transistors in the array substrate can be further improved. Furthermore, since the dry etching process is eliminated during the process of forming gate layer 3 using molybdenum-aluminum-molybdenum, etching fluctuations of the silicon nitride in gate insulating layer 2 are eliminated during the process of forming gate layer 3. This can further improve the yellowish color coordinates and color shift problems that occur in display products in related technologies.

[0124] In some embodiments, the third interlayer insulating layer 43 has a film thickness smaller than that of the first interlayer insulating layer 41 .

[0125] In some embodiments, the thickness of the third interlayer insulating layer 43 ranges from

[0126] When the thickness of the third interlayer insulating layer 43 is When the thickness of the third interlayer insulating layer 43 is less than 0. When etching the source / drain layer 5, the third interlayer insulating layer 43 cannot be completely etched away. If the material used for the third interlayer insulating layer 43 is SiNx, some SiNx will remain, thereby causing color defects.

[0127] In other embodiments, the thickness of the third interlayer insulating layer 43 is the minimum etching loss of the interlayer insulating layer 4 when etching the source and drain electrode layer 5. For example, when etching the source and drain electrode layer 5, the minimum etching loss of the interlayer insulating layer 4 is The thickness of the third interlayer insulating layer 43 is set to

[0128] In the embodiment provided in the present disclosure, by setting the film thickness of the third interlayer insulating layer 43 to the minimum etching loss of the interlayer insulating layer 4 when etching the source and drain layer 5, the side walls of the source and drain layer 5 can be protected when forming the source and drain layer 5, and the third interlayer insulating layer 43 can be prevented from affecting the optical stability of the backlight passing through the array substrate.

[0129] FIG9 is a schematic structural diagram of a gate insulating layer according to an embodiment of the present disclosure. The gate insulating layer 2 includes:

[0130] A first sub-gate insulating layer 21 and a second sub-gate insulating layer 22 , wherein the first sub-gate insulating layer 21 is located on a side of the second sub-gate insulating layer 22 close to the array substrate.

[0131] When molybdenum-aluminum-molybdenum is used for the gate layer 3, since the dry etching process is eliminated in the process of forming the gate layer 3, it will not cause etching fluctuations to the second sub-gate insulation layer 22 located on the top layer in the gate insulation layer 2, and will not change the optical stability of the backlight passing through the array substrate.

[0132] Please refer to Figure 10 for a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure. The array substrate has a plurality of pixel opening areas arranged in an array;

[0133] The interlayer insulating layer 4 and the second sub-gate insulating layer 22 have a through hole H penetrating the film layer in the pixel opening area. The orthographic projection area of ​​the through hole H on the base substrate 1 is substantially the same as the orthographic projection area of ​​the pixel opening area on the base substrate 1 .

[0134] In the embodiment provided in the present disclosure, a through hole H penetrating the interlayer insulating layer 4 and the second sub-gate insulating layer 22 is provided in a pixel opening area, and the orthographic projection area of ​​the through hole H on the base substrate 1 is made to be roughly the same as the orthographic projection area of ​​the pixel opening area on the base substrate 1. The silicon nitride layer in the interlayer insulating layer 4 and the gate insulating layer 2 can be removed, thereby reducing the effect of the silicon nitride layer on the color deviation of the display product and improving the light transmittance.

[0135] As shown in FIG10 , the longitudinal section of the through hole H may be in the shape of an inverted trapezoid or a rectangle, without limitation.

[0136] Please refer to FIG11 for a structural diagram of another array substrate provided in an embodiment of the present disclosure. The array substrate further includes:

[0137] a buffer layer 6, located between the base substrate 1 and the gate insulating layer 2;

[0138] a planarization layer 7, located on a side of the source and drain electrode layer 5 away from the substrate 1;

[0139] The first electrode layer S1 is located on a side of the planar layer 7 away from the base substrate 1;

[0140] The passivation layer 8 is located on a side of the first electrode layer S1 away from the substrate 1;

[0141] The second electrode layer S2 is located on a side of the passivation layer 8 away from the base substrate 1 .

[0142] The first electrode layer S1 can be a common electrode, and the corresponding second electrode layer S2 can be a pixel electrode; the first electrode layer S1 can also be a pixel electrode, and the corresponding second electrode layer S2 can be a common electrode.

[0143] In some embodiments, the materials used for the buffer layer 6, the planarization layer 7, and the passivation layer 8 may be materials that do not contain silicon nitride, such as silicon oxide. This can further reduce the color deviation effect of the silicon nitride layer on the display product and improve light transmittance.

[0144] Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing an array substrate. FIG12 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure. The method includes:

[0145] Step 1201: providing a substrate;

[0146] Step 1202: forming a gate insulating layer on one side of the substrate;

[0147] Step 1203: forming a gate layer on a side of the gate insulation layer away from the substrate;

[0148] Step 1204: forming an interlayer dielectric layer on a side of the gate layer away from the substrate; the interlayer insulating layer includes a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer stacked together, wherein the first sub-interlayer insulating layer is located on a side of the second sub-interlayer insulating layer close to the gate layer, the third sub-interlayer insulating layer is located on a side of the second sub-interlayer insulating layer away from the substrate, and the third sub-interlayer insulating layer overlaps with the source and drain layers;

[0149] Step 1205: forming a source-drain layer on a side of the interlayer dielectric layer away from the substrate; the source-drain layer has a pattern area and an opening area surrounding the pattern area; the thickness of a portion of the second interlayer insulating layer overlapping with the pattern area is greater than the thickness of a portion of the second interlayer insulating layer overlapping with the opening area.

[0150] Please refer to FIG13 which is a schematic diagram of manufacturing an array substrate provided in an embodiment of the present disclosure.

[0151] S10: providing a substrate 1;

[0152] S11: forming a gate insulating layer 2 on one side of the base substrate 1;

[0153] S12: forming a gate layer 3 on a side of the gate insulating layer 2 away from the substrate 1;

[0154] S13: depositing a layer of silicon nitride on a side of the gate layer 3 away from the substrate 1 to obtain a first sub-layer insulating layer 41;

[0155] S14: depositing a layer of silicon oxide on a side of the first interlayer insulating layer 41 away from the base substrate 1 to obtain a second interlayer insulating layer 42;

[0156] S15: depositing a layer of silicon nitride on a side of the second interlayer insulating layer 41 away from the substrate 1;

[0157] S16: forming a source-drain layer 5 and a third interlayer insulating layer 43 on a side of the third interlayer insulating layer 43 away from the substrate 1; the first interlayer insulating layer 41, the second interlayer insulating layer 42 and the third interlayer insulating layer 43 constitute an interlayer insulating layer 4.

[0158] Since part of the second interlayer insulating layer 42 and the third interlayer insulating layer 43 will be etched completely when the source and drain layer 5 is formed, but the first interlayer insulating layer 41 located at the bottom layer of the interlayer insulating layer 4 will not be etched, the film thickness fluctuation factor of the first interlayer insulating layer 41 is only affected by the coating fluctuation of the first interlayer insulating layer 41. This makes it possible to reduce the influence of the first interlayer insulating layer 41 on the optical color deviation to a minimum even if the first interlayer insulating layer 41 has a greater influence on the optical color deviation, because the film thickness of the first interlayer insulating layer 41 changes little, and thus the color deviation of the display product is effectively improved; and, although the film thickness of the second interlayer insulating layer 42 located in the interlayer insulating layer 4 is affected by the coating and etching fluctuations, the etching fluctuation of the second interlayer insulating layer 42 is smaller than that of the first interlayer insulating layer 41, and the second interlayer insulating layer 42 has less optical influence than the first interlayer insulating layer 41, so that the optical stability can be greatly improved, and the color deviation of the display product can be further improved. Moreover, since the portion of the third interlayer insulating layer 43 located in the pixel area will be completely etched away when etching the source and drain layer 5, even if the third interlayer insulating layer 43 has an impact on optics, it will not cause color deviation in the display product. At the same time, the third interlayer insulating layer 43 improves the jaggedness of the source and drain layer 5.

[0159] Before forming the gate insulating layer on one side of the substrate, the method further includes:

[0160] forming a buffer layer on a side of the substrate close to the gate insulating layer;

[0161] An active layer is formed between the buffer layer and the gate insulating layer.

[0162] Please refer to FIG. 14 for a flow chart of forming a buffer layer and a source-drain layer according to an embodiment of the present disclosure.

[0163] S21: forming a buffer layer 6 on one side of the base substrate 1;

[0164] S22: forming an active layer 9 on a side of the buffer layer 6 away from the base substrate 1;

[0165] S23 : Patterning the active layer 9 .

[0166] Thereafter, S11 to S15 may be performed to form an array substrate as shown in FIG15 . FIG15 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure.

[0167] The transistors in the array substrate include a gate layer 3, a source / drain layer 5, and an active layer 9. The transistors can adopt either a bottom-gate or top-gate structure. When the transistors in the array substrate adopt a top-gate structure, the active layer 9 must be formed first, followed by the gate layer 3. When the transistors adopt a bottom-gate structure, the gate layer 3 must be formed first, followed by the active layer 9. The order of film formation can be adjusted based on the top-gate structure described above, and the details are not detailed here.

[0168] In some embodiments, the material used for the gate layer 3 can be molybdenum. In this case, the gate insulation layer 2 includes a silicon nitride layer and a silicon oxide layer. The silicon oxide layer is located on the side of the silicon nitride layer away from the substrate 1. That is, the setting method of the gate insulation layer 2 is the same as the setting method of the interlayer insulation layer 4.

[0169] When the material of the gate layer 3 is molybdenum, the corresponding process flow mainly includes a mask process, a wet etching process, a doping process, and a dry etching process. Please refer to Figure 16 for a schematic diagram of the process flow of a gate layer provided in an embodiment of the present disclosure.

[0170] A layer of molybdenum (molybdenum layer) is deposited on the side of the gate insulating layer 2 away from the substrate 1, and a layer of photoresist PR is formed on the side of the molybdenum layer away from the substrate 1. The pattern on the mask is transferred to the photoresist PR layer by photolithography, and then the molybdenum layer is etched in the following manner to obtain the gate layer 3:

[0171] S31: patterning the molybdenum layer using a wet etching method;

[0172] S32: doping the active layer 9 between the buffer layer 6 and the gate insulating layer 2;

[0173] S33: etching the patterned molybdenum layer again using a dry etching method to obtain a gate layer 3;

[0174] Since dry etching primarily involves vertical etching, and when molybdenum is used as the material for gate layer 3, the top layer of gate insulating layer 2 is a silicon oxide layer. However, silicon oxide exhibits less etch fluctuation than silicon nitride and has a lesser optical impact than silicon nitride, thereby improving optical stability and further improving color shift in display products. The silicon nitride layer, which has a greater impact on color shift, is located at the bottom of gate insulating layer 2. This layer is unaffected by etching, resulting in minimal thickness variation. This minimizes the impact of the silicon nitride layer on optical color shift, further improving color shift in display products.

[0175] S34: removing the photoresist PR on the gate layer 3.

[0176] In other embodiments, the material used for the gate layer may also be molybdenum-aluminum-molybdenum. The gate layer may be formed in the following manner:

[0177] Depositing a molybdenum-aluminum-molybdenum layer on a side of the gate insulating layer away from the substrate;

[0178] forming a photoresist layer on a side of the molybdenum-aluminum-molybdenum layer away from the substrate;

[0179] Transferring the pattern of the mask to the photoresist layer to obtain a patterned photoresist layer;

[0180] The MoAlMo layer is etched by wet etching to transfer the pattern of the patterned photoresist layer to the MoAlMo layer to obtain a gate layer.

[0181] In some embodiments, after etching the molybdenum-aluminum-molybdenum layer using a wet etching method, the method further includes:

[0182] doping the active layer;

[0183] The patterned photoresist layer is removed.

[0184] In some other embodiments, forming a gate insulating layer on one side of a substrate includes:

[0185] Depositing a first sub-gate insulating layer on a side of the active layer away from the substrate;

[0186] A second sub-gate insulating layer is deposited on a side of the first sub-gate insulating layer away from the substrate.

[0187] When the material of the gate layer is molybdenum-aluminum-molybdenum, the corresponding process flow mainly includes a mask process, a wet etching process, and a doping process. Please refer to Figure 17 for a schematic diagram of the process flow of another gate layer provided in an embodiment of the present disclosure.

[0188] A molybdenum-aluminum-molybdenum layer is deposited on the side of the gate insulating layer 2 away from the substrate 1, and a photoresist PR is formed on the side of the molybdenum-aluminum-molybdenum layer away from the substrate 1. The pattern on the mask is transferred to the photoresist PR layer by photolithography, and then the molybdenum-aluminum-molybdenum layer is etched in the following manner:

[0189] S41: patterning the molybdenum-aluminum-molybdenum layer by wet etching to obtain a gate layer 3;

[0190] S42: doping the active layer 9 between the buffer layer 6 and the gate insulating layer 2;

[0191] S43 : removing the photoresist PR on the gate layer 3 .

[0192] Since the gate layer 3 is made of molybdenum-aluminum-molybdenum, the dry etching method is eliminated in the process of forming the gate layer 3. Therefore, even if silicon nitride is located on the top layer of the gate layer 3, there will be no etching fluctuation, that is, it will not affect the color deviation.

[0193] An interlayer dielectric layer is formed on a side of the gate layer away from the substrate, including:

[0194] Depositing a first inter-sub-layer insulating layer on a side of the gate layer away from the substrate;

[0195] Depositing a second intersub-layer insulating layer on a side of the first intersub-layer insulating layer away from the substrate;

[0196] A third sub-interlayer insulating layer is deposited on a side of the second interlayer insulating layer away from the substrate.

[0197] By depositing a third interlayer insulating layer on the side of the second interlayer insulating layer away from the substrate, the side surfaces of the source and drain can be protected when the source and drain layers are formed, avoiding sawtooth defects on the side surfaces of the source and drain, and improving product yield.

[0198] A source and drain layer is formed on a side of the interlayer dielectric layer away from the substrate, including:

[0199] Depositing a metal layer on a side of the interlayer dielectric layer away from the substrate;

[0200] The metal layer is patterned to expose the second inter-sub-layer insulating layer to obtain a source-drain electrode layer.

[0201] Please refer to Figure 18 for a flow chart of forming a source and drain layer provided in an embodiment of the present disclosure.

[0202] S51: depositing a metal layer on a side of the third interlayer insulating layer 43 away from the substrate 1;

[0203] S52 : patterning the metal layer and exposing the second inter-sub-layer insulating layer 42 to obtain the source-drain electrode layer 5 .

[0204] If the third interlayer insulating layer 43 is not provided on the upper layer of the second interlayer insulating layer 42, more of the second interlayer insulating layer 42 will be etched when the metal layer is patterned, causing more oxygen to overflow from the second interlayer insulating layer 42, thereby causing the side of the source and drain layer 5 to be seriously damaged, forming sawtooth. Please refer to Figure 19 for a schematic diagram of the etching loss of the interlayer insulating layer when etching the source and drain layers provided in an embodiment of the present disclosure.

[0205] S61: Use wet etching process to etch the metal layer corresponding to the source and drain layer 5. At this time, about The film thickness of the second sub-layer insulating layer 42 is .

[0206] S62: Continue etching the metal layer corresponding to the source and drain using the dry etching process. At this time, approximately This will cause a large amount of oxygen to overflow from the second sub-interlayer insulating layer 42, thereby causing severe lateral etching of the source and drain electrode layer 5, forming saw teeth.

[0207] If a third interlayer insulating layer 43 is provided on the upper layer of the second interlayer insulating layer 42 , please refer to FIG. 20 , which is another schematic diagram of etching loss of the interlayer insulating layer when etching the source and drain layers according to an embodiment of the present disclosure.

[0208] S71: Use wet etching process to etch the metal layer corresponding to the source and drain. At this time, about The thickness of the third interlayer insulating layer 43 is After the wet etching process, the film thickness of the portion not covered by the source / drain layer 5 becomes approximately

[0209] S72: Continue etching the metal layer corresponding to the source and drain using the dry etching process. At this time, approximately The interlayer insulating layer 4, wherein the portion of the third interlayer insulating layer 43 not covered by the source and drain electrodes is completely etched away, and the thickness of the second interlayer insulating layer 42 is etched away. This will reduce the yield of oxygen overflow from the second interlayer insulating layer 42 , thereby improving the lateral etching of the source and drain layer 5 .

[0210] Therefore, when patterning the metal layer corresponding to the source and drain electrode layer 5 , the protection of the third interlayer insulating layer 43 can prevent sawtooth defects from occurring on the side surfaces of the source and drain electrode layer 5 , thereby improving product yield.

[0211] In some embodiments, the array substrate includes a plurality of pixel opening areas, and after forming the source and drain electrode layer 5, further includes:

[0212] In the pixel opening area, the interlayer dielectric layer and the second sub-gate insulating layer 22 are bored to form a through hole H penetrating the interlayer dielectric layer and the second sub-gate insulating layer 22 .

[0213] Please refer to Figure 21 for a schematic diagram of a through hole forming a pixel opening area provided in an embodiment of the present disclosure.

[0214] After forming the source and drain electrode layer 5, holes are dug in the interlayer dielectric layer and the second sub-gate insulating layer 22 in each pixel opening area to form a through hole H that penetrates the interlayer dielectric layer and the second sub-gate insulating layer 22. This can reduce the influence of the first sub-interlayer insulating layer 41 and the second sub-gate insulating layer 22 in the pixel opening area on the optical stability, further improve color deviation, and increase light transmittance.

[0215] In some embodiments, after forming a through hole penetrating the interlayer dielectric layer and the second sub-gate insulating layer, the method further includes:

[0216] forming a flat layer on a side of the source and drain electrode layer away from the substrate; wherein the flat layer fills the through hole;

[0217] forming a first electrode layer on a side of the planar layer away from the substrate;

[0218] forming a passivation layer on a side of the common electrode layer away from the substrate;

[0219] A second electrode layer is formed on a side of the passivation layer away from the substrate.

[0220] Please refer to FIG22 for a schematic diagram of manufacturing another array substrate provided in an embodiment of the present disclosure.

[0221] S81: forming a planarization layer 7 on the side of the source / drain layer 5 away from the base substrate 1 , so that the planarization layer 7 fills the through hole H, and the side of the planarization layer 7 away from the base substrate 1 is higher than the side of the source / drain layer 5 away from the base substrate 1 .

[0222] By arranging a flat layer 7 on the side of the source / drain layer 5 away from the base substrate 1 and allowing the flat layer 7 to fill the through hole H and the source / drain layer 5, the flatness of the electrode layer can be ensured when the electrode layer is subsequently formed, thereby improving the uniformity of the electric field.

[0223] S82 : forming a first electrode layer S1 on a side of the planar layer 7 away from the base substrate 1 .

[0224] The first electrode layer S1 in FIG22 is a common electrode layer, and can of course also be set as a pixel electrode layer.

[0225] S83 : forming a passivation layer 8 on a side of the first electrode layer S1 away from the base substrate 1 .

[0226] S84 : forming a second electrode layer S2 on a side of the passivation layer 8 away from the base substrate 1 .

[0227] In Figure 22, the second electrode layer S2 is a pixel electrode layer. The second electrode layer S2 can also be a common electrode layer, and the corresponding first electrode layer S1 is a pixel electrode layer. The first electrode layer S1 and the second electrode layer S2 can be transparent electrodes, such as indium tin oxide electrodes, which can improve light transmission.

[0228] Figure 22 shows a schematic diagram of fabricating an array substrate for a horizontal electric field. If a vertical electric field is used, only one electrode layer needs to be formed on the array substrate. For example, a first electrode layer S1 is formed on the array substrate, and a second electrode layer S2 is formed on a mating substrate that is mated with the array substrate.

[0229] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel. FIG23 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. The display panel includes:

[0230] The array substrate 100 as described above;

[0231] The cell substrate 200 is disposed opposite to the array substrate 100;

[0232] The liquid crystal layer 300 is located between the array substrate 100 and the cell substrate 200 .

[0233] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, which includes the display panel as described above.

[0234] The display device may be a liquid crystal display, a liquid crystal display screen, a liquid crystal television or other display device, or may be a mobile device such as a mobile phone, a tablet computer, or a notebook.

[0235] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0236] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. An array substrate, wherein, Comprising: A substrate; A gate insulating layer located on one side of the substrate; A gate layer located on the side of the gate insulating layer away from the substrate; An interlayer insulating layer located on the side of the gate layer away from the substrate; the interlayer insulating layer includes a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer stacked on top of each other. The first sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer closer to the gate layer, and the third sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer away from the substrate. The third sub-interlayer insulating layer coincides with the source-drain layer; A source-drain layer located on the side of the interlayer insulating layer away from the substrate; the source-drain layer has a pattern region and an opening region surrounding the pattern region; The film thickness of the part of the second sub-interlayer insulating layer that coincides with the pattern region is greater than the film thickness of the part of the second sub-interlayer insulating layer that coincides with the opening region.

2. The array substrate according to claim 1, wherein, The film thickness of the third sub-interlayer insulating layer is less than the film thickness of the first sub-interlayer insulating layer.

3. The array substrate according to claim 1, wherein, The film thickness of the third sub-interlayer insulating layer is the minimum etching loss amount of the interlayer insulating layer when etching the source-drain layer.

4. The array substrate according to any one of claims 1-3, wherein, The gate insulating layer includes: A first sub-gate insulating layer and a second sub-gate insulating layer. The first sub-gate insulating layer is located on the side of the second sub-gate insulating layer closer to the array substrate.

5. The array substrate according to claim 4, wherein, The array substrate has a plurality of pixel opening regions arranged in an array; The interlayer insulating layer and the second sub-gate insulating layer have a through hole penetrating the film layer in the pixel opening region. The orthographic projection region of the through hole on the substrate is substantially the same as the orthographic projection region of the pixel opening region on the substrate.

6. The array substrate according to claim 5, wherein, The longitudinal cross-sectional shape of the through hole includes an inverted trapezoid.

7. The array substrate according to any one of claims 1-6, wherein, The array substrate further includes: A buffer layer located between the substrate and the gate insulating layer; A planarization layer located on the side of the source-drain layer away from the substrate; A first electrode layer located on the side of the planarization layer away from the substrate; A passivation layer located on the side of the first electrode layer away from the substrate; A second electrode layer located on the side of the passivation layer away from the substrate.

8. The array substrate according to any one of claims 1-7, wherein, The material used for the gate layer includes molybdenum-aluminum-molybdenum.

9. The array substrate according to any one of claims 1-8, wherein, The etching selectivity of the source-drain layer to the first sub-interlayer insulating layer is less than the etching selectivity of the source-drain layer to the second sub-interlayer insulating layer.

10. A method for manufacturing an array substrate, wherein, Comprising: Providing a substrate; Forming a gate insulating layer on one side of the substrate; Forming a gate layer on the side of the gate insulating layer away from the substrate; Forming an interlayer dielectric layer on the side of the gate layer away from the substrate; the interlayer insulating layer includes a first sub-interlayer insulating layer, a second sub-interlayer insulating layer, and a third sub-interlayer insulating layer stacked on top of each other. The first sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer closer to the gate layer, and the third sub-interlayer insulating layer is located on the side of the second sub-interlayer insulating layer away from the substrate. The third sub-interlayer insulating layer coincides with the source-drain layer; On a side of the interlayer dielectric layer away from the substrate, a source-drain layer is formed; the source-drain layer has a patterned area and an opening area surrounding the patterned area; a film thickness of a portion of the second interlayer insulating layer that coincides with the patterned area is greater than a film thickness of a portion of the second interlayer insulating layer that coincides with the opening area.

11. The manufacturing method according to claim 10, wherein, On a side of the gate insulating layer away from the substrate, a gate layer is formed, including: On a side of the gate insulating layer away from the substrate, a molybdenum-aluminum-molybdenum layer is deposited; On a side of the molybdenum-aluminum-molybdenum layer away from the substrate, a photoresist layer is formed; The pattern of the mask is transferred to the photoresist layer to obtain a patterned photoresist layer; The molybdenum-aluminum-molybdenum layer is etched by wet etching to transfer the pattern of the patterned photoresist layer to the molybdenum-aluminum-molybdenum layer to obtain the gate layer.

12. The manufacturing method according to claim 11, wherein, Before forming the gate insulating layer on a side of the substrate, it further includes: On a side of the substrate close to the gate insulating layer, a buffer layer is formed; An active layer is formed between the buffer layer and the gate insulating layer.

13. The manufacturing method according to claim 11, wherein, After etching the molybdenum-aluminum-molybdenum layer by wet etching, it further includes: Doping the active layer; Removing the patterned photoresist layer.

14. The manufacturing method according to any one of claims 10-13, wherein, On a side of the gate layer away from the substrate, an interlayer dielectric layer is formed, including: On a side of the gate layer away from the substrate, a first interlayer insulating layer is deposited; On a side of the first interlayer insulating layer away from the substrate, a second interlayer insulating layer is deposited; On a side of the second interlayer insulating layer away from the substrate, the third interlayer insulating layer is deposited.

15. The manufacturing method according to claim 12 or 13, wherein, Forming a gate insulating layer on a side of the substrate, including: On a side of the active layer away from the substrate, a first sub-gate insulating layer is deposited; On a side of the first sub-gate insulating layer away from the substrate, a second sub-gate insulating layer is deposited.

16. The manufacturing method according to any one of claims 10-13, on a side of the interlayer dielectric layer away from the substrate, forming a source-drain layer, including: On a side of the interlayer dielectric layer away from the substrate, a metal layer is deposited; The metal layer is patterned to expose the second interlayer insulating layer to obtain the source-drain layer.

17. The manufacturing method according to claim 15, wherein the array substrate includes a plurality of pixel opening regions, and After forming the source-drain layer, it further includes: In the pixel opening area, the interlayer dielectric layer and the second sub-gate insulating layer are dug to form a through hole penetrating the interlayer dielectric layer and the second sub-gate insulating layer.

18. The manufacturing method according to claim 17, wherein, After forming the through hole penetrating the interlayer dielectric layer and the second sub-gate insulating layer, it further includes: On a side of the source-drain layer away from the substrate, a planarization layer is formed; wherein, the planarization layer fills the through hole; On a side of the planarization layer away from the substrate, a first electrode layer is formed; On a side of the common electrode layer away from the substrate, a passivation layer is formed; On a side of the passivation layer away from the substrate, a second electrode layer is formed.

19. A display panel, wherein, Including: The array substrate according to any one of claims 1-9; A counter substrate, disposed opposite to the array substrate; A liquid crystal layer, located between the array substrate and the counter substrate.

20. A display device, wherein, including the display panel as described in claim 19.

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