Array substrate, display panel and display device

Abstract

Disclosed are an array substrate, a display panel and a display device. The array substrate comprises: a first base substrate, comprising a first area and a fan-out area; and a fan-out line group, comprising m sub-groups, wherein each sub-group comprises a plurality of fan-out lines; each fan-out line in the (m-i)th sub-group comprises a first part, a second part and a third part; in a first direction, the first part is located on the side of the second part close to the first area, and the third part is located on the side of the second part away from the first area; the second part extends in the first direction, and the extension direction of the first part and the extension direction of the third part intersect with the first direction and a second direction; the (m-i)th subgroup comprises a plurality of first fan-out lines and a plurality of second fan-out lines; and in the second direction, a first part of each first fan-out line and a third part of the first fan-out line are respectively located on both sides of a second part of the first fan-out line, and a first part of each second fan-out line and a third part of the second fan-out line are located on the same side of a second part of the second fan-out line in the second direction.

Description

Array substrate, display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] In existing technology, when multiple driver chips (ICs) are bundled with a display panel, the conventional design is to evenly distribute the ICs relative to the display area, minimizing the resistance differences between signal lines electrically connected to the ICs in different areas. However, in designs where flexible printed circuits (FPCs) are used to electrically connect the ICs to printed circuit boards (PCBs), the length limitations of the PCB prevent even IC distribution. This results in significant resistance differences between signal lines, which can easily cause display artifacts such as noticeable split screens and vertical lines. This impacts the display quality and user experience.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides an array substrate, wherein the array substrate includes:

[0005] A first substrate; comprising: a first region, and a fan-out region located on one side of the first region in a first direction;

[0006] At least one fan-out line group is located on one side of the first substrate in the fan-out region; each fan-out line group includes m subgroups arranged along a second direction, each subgroup including a plurality of fan-out lines arranged along the second direction; the second direction intersects the first direction; the fan-out line of the mi-th subgroup among the m subgroups includes: a first portion, a second portion, and a third portion electrically connected in sequence; in the first direction, the first portion is located on a side of the second portion close to the first region, and the third portion is located on a side of the second portion away from the first region; the second portion extends along the first direction, and the extension directions of the first portion and the third portion intersect both the first direction and the second direction;

[0007] The mi-th subgroup includes: multiple first fan-out lines, and multiple second fan-out lines located on one side of the multiple first fan-out lines in the second direction; in the second direction, the first part of the first fan-out line and the third part of the first fan-out line are respectively located on both sides of the second part of the first fan-out line, and the first part of the second fan-out line and the third part of the second fan-out line are located on the same side of the second part of the second fan-out line in the second direction; wherein m is an integer greater than 2, and i is an integer greater than 0 and less than m-1.

[0008] In some embodiments, an extension direction of the first portion of the first fan-out line has a first angle with a positive direction of the second direction;

[0009] An extension direction of the first portion of the second fan-out line has a second angle with the positive direction of the second direction;

[0010] The extension direction of the third portion has a third angle with the positive direction of the second direction;

[0011] The first angle and the third angle are greater than 0° and less than 90°, and the second angle is greater than 90° and less than 180°; or, the first angle and the third angle are greater than 90° and less than 180°, and the second angle is greater than 0° and less than 90°.

[0012] In some embodiments, in the mi-th subgroup, the number of first fan-out lines is smaller than the number of second fan-out lines; and the total width of the second portions of the plurality of first fan-out lines is smaller than the total width of the second portions of the plurality of second fan-out lines.

[0013] In some embodiments, in the direction from the first fan-out line to the second fan-out line, the lengths of the first portions of the plurality of first fan-out lines in the extending direction gradually decrease, the lengths of the first portions of the plurality of second fan-out lines in the extending direction gradually increase, the lengths of the second portions of the plurality of first fan-out lines in the first direction gradually increase, the lengths of the second portions of the plurality of second fan-out lines in the first direction gradually decrease, and the lengths of the plurality of third portions in the extending direction are equal.

[0014] In some embodiments, the first fan-out line farthest from the second fan-out line is adjacent to the mi-1th subgroup among the m subgroups, and the second fan-out line farthest from the first fan-out line is adjacent to the m-i+1th subgroup among the m subgroups.

[0015] In some embodiments, the pattern of at least part of the second portion on the first base substrate includes a fold line extending along the first direction.

[0016] In some embodiments, the fan-out line of the (m-i+1)th subgroup among the m subgroups includes: a fourth portion, a fifth portion, and a sixth portion electrically connected in sequence;

[0017] In the first direction, the fourth portion is located on a side of the fifth portion close to the first area, and the sixth portion is located on a side of the fifth portion away from the first area;

[0018] The fourth portion and the sixth portion extend along the first direction, and the extending direction of the fifth portion intersects both the first direction and the second direction.

[0019] In some embodiments, in the second direction, the fourth portion is located on a side of the fifth portion away from the mi-th subgroup, and the sixth portion is located on a side of the fifth portion close to the mi-th subgroup.

[0020] In some embodiments, the pattern of at least part of the fourth portion on the first base substrate is a fold line extending along the first direction;

[0021] And / or, the pattern of at least part of the sixth portion on the first base substrate is a fold line extending along the first direction.

[0022] In some embodiments, the extension direction of the fifth portion of the (m-i+1)th subgroup has a fourth angle with the positive direction of the second direction;

[0023] The fourth angle and the second angle are both greater than 90° and less than 180°; or the fourth angle and the second angle are both greater than 0° and less than 90°.

[0024] In some embodiments, in two adjacent fan-out lines located in the mi-th subgroup and the m-i+1-th subgroup, respectively, the first portion is adjacent to the fifth portion; in the first direction, at least part of the fifth portion is located on a side of the first portion closest to the m-i+1-th subgroup away from the first region.

[0025] In some embodiments, the mi-1th subgroup among the m subgroups includes a plurality of third fan-out lines, and the third fan-out lines include a bending portion turning toward the mi-th subgroup among the m subgroups.

[0026] In some embodiments, in a direction from the mi-1th subgroup to the mith subgroup, the lengths of the multiple bending portions gradually increase.

[0027] In some embodiments, the bent portion includes: a seventh portion, an eighth portion, and a ninth portion electrically connected in sequence;

[0028] In the first direction, the seventh portion is located on a side of the eighth portion close to the first region, and the ninth portion is located on a side of the eighth portion away from the first region; in the second direction, the seventh portion and the ninth portion are located on the same side of the eighth portion;

[0029] The seventh portion and the ninth portion cross the first direction and the second direction, and the eighth portion extends along the first direction.

[0030] In some embodiments, third portions of the plurality of fan-out lines in the mi-th subgroup are parallel to each other;

[0031] The plurality of first portions included in the plurality of first fan-out lines are parallel to each other;

[0032] The plurality of first portions included in the plurality of second fan-out lines are parallel to each other;

[0033] The fan-out line of the m-i+1th subgroup includes a fifth portion, and the fifth portions of the plurality of fan-out lines in the m-i+1th subgroup are parallel to each other;

[0034] In the mi-1th subgroup, the multiple seventh portions are parallel to each other, and the multiple ninth portions are parallel to each other.

[0035] In some embodiments, in the first direction, the lengths of the plurality of eighth portions included in the plurality of third fan-out lines are substantially equal;

[0036] In the direction from the mi-1th subgroup to the mith subgroup, the lengths of the seventh portions of the third fan-out lines gradually increase in the extending direction, and the lengths of the ninth portions of the third fan-out lines gradually increase in the extending direction.

[0037] In some embodiments, the extension direction of the seventh portion has a fifth angle with the positive direction of the second direction;

[0038] The fifth angle and the first angle are both greater than 90° and less than 180°; or the fifth angle and the first angle are both greater than 0° and less than 90°.

[0039] In some embodiments, the first substrate further includes: a first binding region located on a side of the fan-out region away from the first region in the first direction;

[0040] The array substrate further includes: a plurality of first binding electrodes and dummy binding electrodes located in the first binding area; the fan-out line is electrically connected to the first binding electrode at one end thereof away from the first area;

[0041] In the second direction, a dummy binding electrode is included between two adjacent first binding electrodes electrically connected to the fan-out lines of the mi-1th subgroup and the mith subgroup respectively;

[0042] In the first direction, at least a portion of the bent portion is located between the dummy binding electrode and the first portion closest to the mi-1th subgroup.

[0043] In some embodiments, the third fan-out line also includes: a tenth portion located on the side of the bending portion toward the first zone in the first direction, an eleventh portion located on the side of the bending portion away from the first zone in the first direction, and a twelfth portion located on the side of the tenth portion toward the first zone in the first direction; the tenth portion and the eleventh portion extend along the first direction, and the twelfth portion is parallel to the first portion.

[0044] In some embodiments, a pattern of an orthographic projection of a portion of at least a portion of the fan-out lines in the mi-1th subgroup on the first base substrate is a fold line extending along the first direction.

[0045] In some embodiments, in at least some of the subgroups, a plurality of fan-out lines on at least one side edge of the subgroup are dummy fan-out lines;

[0046] At least some of the dummy fan-out lines include broken line regions.

[0047] In some embodiments, at least one side edge of at least some of the subgroups includes two dummy fan-out lines, and the two dummy fan-out lines are respectively located in the first conductive layer and the second conductive layer.

[0048] In some embodiments, in the dummy fan-out line of the mi-th subgroup, the broken line area is located in the second portion;

[0049] The bending portion includes an eighth portion; and in the dummy fan-out line of the mi-1th subgroup, the broken line area is located at the eighth portion.

[0050] In some embodiments, an angle between the extension direction of the plurality of fan-out lines in the first subgroup and the positive direction of the first direction is a sixth angle;

[0051] The sixth angle is greater than 90° and less than 180°, and the fourth angle is greater than 0° and less than 90°; or, the sixth angle is greater than 0° and less than 90°, and the fourth angle is greater than 90° and less than 180°.

[0052] In some embodiments, m=4, i=1;

[0053] Among the four subgroups, the number of fan-out lines included in the first subgroup and the second subgroup is equal to the number of fan-out lines included in the third subgroup and the fourth subgroup;

[0054] The number of fan-out lines included in the first subgroup is greater than the number of fan-out lines included in the second subgroup;

[0055] The number of fan-out lines included in the third sub-group is greater than the number of fan-out lines included in the fourth sub-group.

[0056] In some embodiments, the array substrate includes 2n fan-out line groups arranged along the second direction; wherein n is a positive integer;

[0057] The 2nth fan-out line group is symmetrically arranged with the 2n-1th fan-out line group.

[0058] In some embodiments, the substrate further includes 2n first binding regions;

[0059] In the second direction, the distance between adjacent first binding regions is not equal to the distance between any first binding region located at the edge and the edge of the first substrate.

[0060] In some embodiments, in the second direction, a distance between the 2nth first binding region and the 2n-1th first binding region is smaller than a distance between the 2n-1th first binding region and the 2n-2th first binding region;

[0061] In the second direction, the distance between the 2n-2 th first binding region and the 2n-3 th first binding region is smaller than the distance between the 2n-1 th first binding region and the 2n-2 th first binding region.

[0062] In some embodiments, the difference in resistance between any two adjacent fan-out lines is less than or equal to 5 ohms.

[0063] In some embodiments, any two adjacent fan-out lines are located in different conductive layers.

[0064] In some embodiments, the array substrate further includes:

[0065] Multiple dummy structures are located in the fan-out area; the orthographic projections of the dummy structures on the substrate 1 are located in the area between the orthographic projections of adjacent subgroups on the substrate, and / or the orthographic projections of the dummy structures on the substrate are located on the side of the edge subgroup away from the other subgroups within the orthographic projection of the substrate.

[0066] An embodiment of the present disclosure provides a display panel, comprising:

[0067] The array substrate provided by the embodiment of the present disclosure;

[0068] an opposite substrate, arranged opposite to the array substrate;

[0069] The liquid crystal layer is located between the array substrate and the opposite substrate.

[0070] In some embodiments, the base substrate further includes 2n first binding areas; the display panel further includes 2n driver chips; the orthographic projection of the driver chip on the first base substrate coincides with the first binding area;

[0071] In the second direction, the distance between the orthographic projections of adjacent driver chips on the first substrate is not equal to the distance between the orthographic projection of any driver chip located at the edge and the edge of the first substrate.

[0072] In some embodiments, in the second direction, a distance between an orthographic projection of the 2nth driver chip on the first substrate and an orthographic projection of the 2n-1th driver chip on the first substrate is smaller than a distance between an orthographic projection of the 2n-1th driver chip on the first substrate and an orthographic projection of the 2n-2th driver chip on the first substrate.

[0073] In the second direction, the distance between the orthographic projection of the 2n-3th driver chip on the first substrate and the orthographic projection of the 2n-2th driver chip on the first substrate is smaller than the distance between the orthographic projection of the 2n-1th driver chip on the first substrate and the orthographic projection of the 2n-2th driver chip on the first substrate.

[0074] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0076] FIG1 is a schematic structural diagram of a display panel provided by the related art;

[0077] FIG2 is a schematic structural diagram of another display panel provided by the related art;

[0078] FIG3 is a schematic structural diagram of an array substrate provided by related art;

[0079] FIG4 is a curve diagram of resistance variation of a fan-out line group provided by the related art;

[0080] FIG5 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0081] FIG6 is a schematic structural diagram of area B in FIG5 provided by an embodiment of the present disclosure;

[0082] FIG7 is a schematic structural diagram of the B1 area in FIG6 provided by an embodiment of the present disclosure;

[0083] FIG8 is a schematic structural diagram of the B2 area in FIG6 provided by an embodiment of the present disclosure;

[0084] FIG9 is a schematic structural diagram of the B3 area in FIG6 provided by an embodiment of the present disclosure;

[0085] FIG10 is a schematic structural diagram of the B4 area in FIG6 provided by an embodiment of the present disclosure;

[0086] FIG11 is a schematic structural diagram of the B5 area in FIG6 provided by an embodiment of the present disclosure;

[0087] FIG12 is a schematic diagram of a second structure provided by an embodiment of the present disclosure;

[0088] FIG13 is a schematic structural diagram of the D region in FIG5 provided by an embodiment of the present disclosure;

[0089] FIG14 is a schematic structural diagram of the E region in FIG5 provided by an embodiment of the present disclosure;

[0090] FIG15 is a schematic structural diagram of area C in FIG5 provided by an embodiment of the present disclosure;

[0091] FIG16 is a schematic structural diagram of the C1 region in FIG15 provided by an embodiment of the present disclosure;

[0092] FIG17 is a schematic structural diagram of the C2 region in FIG15 provided by an embodiment of the present disclosure;

[0093] FIG18 is a curve diagram showing a resistance change of a fan-out line group in an array substrate provided by an embodiment of the present disclosure;

[0094] FIG19 is a graph showing a resistance change curve that can be processed by a driver chip provided by an embodiment of the present disclosure;

[0095] FIG20 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0096] FIG21 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0097] FIG22 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0098] FIG23 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0099] FIG24 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0100] FIG25 is a schematic structural diagram of the F region in FIG23 and FIG24 provided by an embodiment of the present disclosure;

[0101] FIG26 is a schematic structural diagram of the G region in FIG23 and FIG24 provided by an embodiment of the present disclosure;

[0102] FIG27 is a schematic structural diagram of the J region in FIG23 and FIG24 provided by an embodiment of the present disclosure;

[0103] FIG28 is a schematic structural diagram of the K region in FIG23 and FIG24 provided by an embodiment of the present disclosure;

[0104] FIG29 is a schematic structural diagram of the M region in FIG23 and FIG24 provided by an embodiment of the present disclosure;

[0105] FIG30 is a schematic structural diagram of the Q region in FIG24 provided by an embodiment of the present disclosure;

[0106] FIG31 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0107] FIG32 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0108] FIG33 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0109] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0110] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0111] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0112] In the related art, as shown in FIG1 , taking a display device with four driver ICs as an example, when the length of the printed circuit board (PCB) meets the requirements, the four driver ICs are located in the first area AA, i.e., one side of the display area, in the first direction Y. The four driver ICs are arranged along the second direction and evenly distributed relative to the first area AA. That is, in the second direction X, the distance between two adjacent driver ICs is equal, i.e., H2 = H3 = H4. The distance H1 between the driver ICs IC1 and IC4 located at the edge and the edge of the first area AA is approximately equal to half the distance between any two adjacent driver ICs. However, when the PCB length cannot meet the requirements for even distribution of the driver ICs relative to the first area AA, compared to FIG1 , as shown in FIG2 , driver IC1 needs to be shifted to the right and driver IC4 needs to be shifted to the left, and the distances of the two shifts are the same, H1' being greater than H1. At the same time, to prevent resistance mutations between adjacent data lines, driver chip IC2 needs to be shifted leftward and driver chip IC3 needs to be shifted rightward accordingly. The distance they move must be consistent with the distances of driver chips IC1 and IC4. H2' is less than H2, H4' is less than H4, and H3' is greater than H3. If the pattern of the fan-out lines in the fan-out area is not changed, the pattern of the multiple fan-out lines 1 corresponding to some driver chips IC is as shown in FIG3 . In the fan-out area, the multiple fan-out lines 1 are divided into four subgroups: a first subgroup A1, a second subgroup A2, a third subgroup A3, and a fourth subgroup A4. The fan-out lines 1 in the first subgroup A1 intersect both the first direction Y and the second direction X. The fan-out lines 1 in the second subgroup A2, the third subgroup A3, and the fourth subgroup A4 are divided into two sections, one of which extends along the first direction Y, and the other section extends in a direction that intersects both the first direction Y and the second direction X. The fan-out lines corresponding to a driver chip IC have large differences in length between A1, A2, A3, and A4. As shown in Figure 4, the resistance differences between the fan-out lines of different fan-out line groups in A1, A2, A3, and A4 are large. In Figure 4, the horizontal axis represents the serial number of the fan-out line. On high refresh rate products, it is easy to have poor block division of the four-split screen due to insufficient charging rate. As shown in Figure 4, there will be a sudden change in the resistance of adjacent fan-out lines at the middle position of the driver chip IC, that is, A2 and A3, which is prone to vertical line defects when the product is displayed.

[0113] An embodiment of the present disclosure provides an array substrate, as shown in FIG5 , comprising:

[0114] The first substrate 2 comprises a first area AA and a fan-out area 201 located on one side of the first area AA in the first direction Y;

[0115] At least one fan-out line group 3 is located on one side of the first substrate 2 in the fan-out area 201; each fan-out line group 3 includes m subgroups A arranged along the second direction X, and the subgroup A includes multiple fan-out lines 1 arranged along the second direction X; the second direction X intersects the first direction Y, and the second direction X is perpendicular to the first direction Y in FIG5 ; the fan-out line 1 of the mi-th subgroup A(mi) among the m subgroups A includes: a first portion 101, a second portion 102, and a third portion 103 electrically connected in sequence; in the first direction Y, the first portion 101 is located on a side of the second portion 102 close to the first area AA, and the third portion 103 is located on a side of the second portion 102 away from the first area AA; the second portion 102 extends along the first direction Y, and the extension directions of the first portion 101 and the third portion 103 intersect both the first direction Y and the second direction X;

[0116] The fan-out lines 1 of the mi-th subgroup A(mi) include: a plurality of first fan-out lines 1-1, and a plurality of second fan-out lines 1-2 located on one side of the plurality of first fan-out lines 1-1 in the second direction X; for the convenience of distinction, the reference number 101 of the first part 101 of the first fan-out line 1-1 is 101-1, the reference number 102 of the second part 102 of the first fan-out line 1-1 is 102-1, and the reference number 103-1 of the third part of the first fan-out line 1-1, the reference number 101 of the first part 101 of the second fan-out line 1-2 is 101-2, the reference number 102 of the second fan-out line 1-2 is 102-2, and the reference number 103-1 of the second fan-out line 1-2 is 103-1. The figure mark of the third part 103 of 1-2 is 103-2; in the second direction X, the first part 101 / 101-1 of the first fan-out line 1-1 and the third part 103 / 103-1 of the first fan-out line 1-1 are respectively located on both sides of the second part 102 / 102-1 of the first fan-out line 1-1, and the first part 101 / 101-2 of the second fan-out line 1-2 and the third part 103 / 103-2 of the second fan-out line 1-2 are located on the same side of the second part 102 / 102-2 of the second fan-out line 1-2 in the second direction X; wherein m is an integer greater than 2, and i is an integer greater than 0 and less than m-1.

[0117] In the array substrate provided by the embodiment of the present disclosure, the fan-out lines in the mi-th subgroup include a first portion, a second portion, and a third portion, i.e., the fan-out lines in the subgroup are divided into at least three sections, and any two adjacent sections extend in different directions. Compared to the two-segment wiring of the fan-out lines in the related art, the length of the fan-out lines can be increased, and the resistance of the fan-out lines can be increased, which is beneficial for reducing the resistance difference between adjacent fan-out lines, avoiding poor display caused by a large resistance difference between adjacent fan-out lines, and improving the display effect. Furthermore, in the mi-th subgroup, the pattern of the first fan-out line is different from the pattern of the second fan-out line. Thus, the first and third portions of the first fan-out line on one side of the mi-th subgroup are located on different sides of the second portion in the second direction, i.e., the three portions of the first fan-out line are arranged sequentially in the second direction. In the second fan-out line on the other side of the mi-th subgroup, the first and third portions are located on the same side of the second portion in the second direction, i.e., the three portions of the second fan-out line form a groove area, which can increase the length and resistance of the fan-out lines while saving wiring space.

[0118] It should be noted that the array substrate also includes multiple scan lines and multiple data lines; the scan lines and data lines intersect each other; and the first region includes: the area enclosed by the intersection of the multiple scan lines and the multiple data lines, as well as the area where the scan lines and data lines are located in the intersection. When the array substrate is used in a display panel, the first region is the display area of ​​the display panel.

[0119] In some embodiments, as shown in FIG. 5 , the first substrate 2 includes a peripheral area NA surrounding the first area AA, and the fan-out area 201 is located in the peripheral area NA.

[0120] In some embodiments, as shown in FIG5 , the first substrate 2 further includes: a first binding region 202 located on a side of the fan-out region 201 away from the first region AA in the first direction Y, a first sub-peripheral region 203 located between the fan-out region 201 and the first region AA in the first direction Y, and a second binding region 204 located on a side of the first binding region 202 away from the first region AA;

[0121] The array substrate further includes: a plurality of first signal lines 6 extending along a first direction Y from the first region to the first sub-peripheral region 203 .

[0122] In a specific implementation, as shown in FIG5 , the fan-out line 1 extends to the first sub-peripheral area 203 , and the fan-out line 1 is electrically connected to the first signal line 6 in a one-to-one correspondence.

[0123] In a specific implementation, as shown in FIG5 , the first binding area 202 includes a plurality of first binding electrodes 401 and a plurality of second binding electrodes 402 , and the second binding area 204 includes a plurality of third binding electrodes 403 ; the first binding electrodes 401 are electrically connected to the fan-out line 1 , and the second binding electrodes 402 are electrically connected to the third binding electrodes 403 via the first connecting lead 5 ; the first binding electrodes 401 and the second binding electrodes 402 are used for binding to a driver chip (not shown), and the third binding electrode 403 is used for binding to a circuit board (not shown), such as a flexible printed circuit (FPC).

[0124] It should be noted that one end of the fan-out line in its extension direction is electrically connected to the first binding electrode, and the other end is electrically connected to the first signal line, that is, the fan-out line is led out from the first binding electrode toward the side of the first zone, extends toward the side of the first zone, and is electrically connected to the first signal line. The first part, second part, and third part of the fan-out line are line segments located at different positions in the extension direction of the fan-out line. The extension directions of different parts of the fan-out line are not exactly the same. This is equivalent to dividing the fan-out line into multiple segments, i.e., multiple parts, according to the change in extension direction. Among the first part, second part, and third part of the same fan-out line, the third part is the section closest to the first binding zone and electrically connected to the first binding electrode located in the first binding zone. On the side of the third part facing the first zone, the first fan-out line or the second fan-out line extends upward and the extension direction changes, which is the second part; the first part is the section closest to the first zone, i.e., the second part faces the side of the first zone, the first fan-out line or the second fan-out line extends upward and the extension direction changes, which is the first part, and the first part is electrically connected to the first signal line.

[0125] In a specific implementation, the first area includes a plurality of sub-pixel units arranged in an array, and the first signal line is, for example, a data line electrically connected to the sub-pixel unit, so that data signals can be provided to the driver chip, the fan-out line, and the data line to the sub-pixel unit through the FPC.

[0126] In some embodiments, as shown in FIG5 , m=4, i=1; the m subgroups A are the first subgroup A1 , the second subgroup A2 , the third subgroup A3 , and the fourth subgroup A4 ; the mi th subgroup A(mi) is the third subgroup A3 .

[0127] In some embodiments, as shown in FIG5 to FIG11 , the third portions 103 of the plurality of fan-out lines 1 in the mi-th subgroup A(mi), i.e., the third subgroup A3, are parallel to each other;

[0128] The plurality of first portions 101 / 101 - 1 of the plurality of first fan-out lines 1 - 1 are parallel to each other;

[0129] The plurality of first portions 101 / 101 - 2 of the plurality of second fan-out lines 1 - 2 are parallel to each other;

[0130] An extending direction of the first portion 101 / 101 - 1 of the first fan-out line 1 - 1 and an extending direction of the first portion 101 / 101 - 2 of the second fan-out line 1 - 2 intersect with each other.

[0131] That is, the embodiment of the present disclosure sets the first portions of the first fan-out line and the second fan-out line to extend in different directions so as to reasonably utilize the wiring space corresponding to the mi-th subgroup, i.e., the third subgroup, while increasing the length and resistance of the fan-out line.

[0132] It should be noted that Figure 6 is an enlarged schematic diagram of area B in Figure 5, Figure 7 is an enlarged schematic diagram of area B1 in Figure 6, Figure 8 is an enlarged schematic diagram of area B2 in Figure 6, Figure 9 is an enlarged schematic diagram of area B3 in Figure 6, Figure 10 is an enlarged schematic diagram of area B4 in Figure 6, and Figure 11 is an enlarged schematic diagram of area B5 in Figure 6.

[0133] In a specific implementation, in the same fan-out line, the angle between the first portion and the second portion is an obtuse angle, and the angle between the third portion and the second portion is an obtuse angle. For example, as shown in Figure 6, in the same fan-out line 1, the angle a8 between the first portion 101 and the second portion 102 is greater than 90° and less than or equal to 100°, and the angle a9 between the third portion 103 and the second portion 102 is greater than or equal to 100° and less than or equal to 110°. The angle a8 between the first portion 101 / 101-1 of the first fan-out line 1-1 and the second portion 102 / 101-2 of the first fan-out line 1-1 and the angle a8 between the first portion 101 / 101-2 of the second fan-out line 1-2 and the second portion 102 / 101-2 of the second fan-out line 1-2 can be the same or different.

[0134] In some embodiments, as shown in FIG6 , the extension direction of the first portion 101 / 101 - 1 of the first fan-out line 1 - 1 has a first angle a1 with the positive direction X+ of the second direction X;

[0135] An extension direction of the first portion 101 / 101 - 2 of the second fan-out line 1 - 2 forms a second angle a2 with the positive direction X+ of the second direction X;

[0136] The extending direction of the third portion 103 forms a third angle a3 with the positive direction X+ of the second direction X.

[0137] It should be noted that in FIG6 , the positive direction X+ of the second direction X is the direction extending to the right, the negative direction X- of the second direction X is the direction extending to the left, the positive direction Y+ of the first direction Y is the direction extending upward, and the negative direction Y- of the first direction Y is the direction extending downward. The angle between the extension direction of each part of the fan-out line and the positive direction X+ of the second direction X refers to the angle toward the positive direction Y+ of the first direction Y. When the angle between a part of the fan-out line and the positive direction X+ of the second direction X is greater than 0° and less than 90°, the extension direction of the part passes through the first quadrant and the third quadrant of the coordinate system composed of the first direction Y and the second direction X; when the angle between a part of the fan-out line and the positive direction X+ of the second direction X is greater than 90° and less than 180°, the extension direction of the part passes through the second quadrant and the fourth quadrant of the coordinate system composed of the first direction Y and the second direction X. In a specific implementation, in the first fan-out line, the extension direction of the first portion and the extension direction of the third portion pass through the same quadrant of the coordinate system formed by the first direction Y and the second direction X, while in the second fan-out line, the extension direction of the first portion and the extension direction of the third portion pass through different quadrants of the coordinate system formed by the first direction Y and the second direction X.

[0138] In some embodiments, as shown in Figure 5, the first fan-out line 1-1 farthest from the second fan-out line 1-2 is adjacent to the mi-1th subgroup A(mi-1) among the m subgroups A (i.e., the 2nd subgroup A2 in Figure 5), and the second fan-out line 1-2 farthest from the first fan-out line 1-1 is adjacent to the m-i+1th subgroup A(m-i+1) among the m subgroups A (i.e., the 4th subgroup A4 in Figure 5).

[0139] In some embodiments, as shown in FIG6 , the first angle a1 and the third angle a3 are greater than 90° and less than 180°, and the second angle a2 is greater than 0° and less than 90°.

[0140] In a specific implementation, as shown in FIG5 , when the first subgroup A1 to the mth subgroup Am in a fan-out line group 3 are arranged along the positive direction X+ of the second direction X, the first fan-out line 1-1 and the second fan-out line 1-2 are also arranged along the positive direction X+ of the second direction X. As shown in FIG6 , the first angle a1 and the third angle a3 are greater than 90° and less than 180°, and the second angle a2 is greater than 0° and less than 90°.

[0141] In a specific implementation, as shown in FIG6 , for example, the first angle a1 is greater than or equal to 170° and less than 180°, the third angle a3 is greater than or equal to 160° and less than or equal to 170°, and the second angle a2 is greater than 0° and less than or equal to 10°.

[0142] Alternatively, in some embodiments, the first angle a1 and the third angle a3 are greater than 0° and less than 90°, and the second angle a2 is greater than 90° and less than 180°.

[0143] In a specific implementation, when the first subgroup A1 to the mth subgroup Am in a fan-out line group 3 are arranged along the negative direction X- of the second direction X, the first fan-out line and the second fan-out line are also arranged along the negative direction X- of the second direction X, the first angle a1 and the third angle a3 are greater than 0° and less than 90°, and the second angle a2 is greater than 90° and less than 180°.

[0144] For example, the first angle a1 is greater than 0° and less than or equal to 10°, the third angle a3 is greater than or equal to 10° and less than or equal to 20°, and the second angle a2 is greater than 90° and less than or equal to 100°.

[0145] In some embodiments, as shown in FIG6 , in the direction from the first fan-out line 1-1 to the second fan-out line 1-2 (i.e., the positive direction X+ of the second direction X in FIG6 ), the lengths of the first portions 101 / 101-1 of the plurality of first fan-out lines 1-1 gradually decrease in their extending directions, and the lengths of the first portions 101 / 101-2 of the plurality of second fan-out lines 1-2 gradually increase in their extending directions.

[0146] 5 , the first portions 101 / 101 - 1 of the plurality of first fan-out lines 1 - 1 close to the first area AA are substantially located on a same straight line extending along the second direction X, which is the boundary between the first sub-region 203 and the fan-out area 201 . When the length of the first portion 101 / 101-1 of the first fan-out line 1-1 gradually decreases in the direction in which the first fan-out line 1-1 points to the second fan-out line 1-2, and the length of the first portion 101 / 101-2 of the second fan-out line 1-2 gradually increases in the direction in which the first fan-out line 1-1 extends, as shown in FIG6 , a line 13 connecting the ends of the first portions 101 / 101-1 of the plurality of first fan-out lines 1-1 away from the first area AA is approximately located in the same straight line, and the extending direction of the line 13 intersects both the first direction Y and the second direction X. A line 14 connecting the ends of the first portions 101 / 101-2 of the plurality of second fan-out lines 1-2 away from the first area AA is approximately located in the same straight line, and the extending direction of the line 14 intersects both the first direction Y and the second direction X. For example, an angle a11 between a line 13 of the first portion 101 / 101-1 of the plurality of first fan-out lines 1-1 away from the first area AA and a line 14 of the first portion 101 / 101-2 of the plurality of second fan-out lines 1-2 away from the first area AA is greater than 90° and less than 100°.

[0147] In some embodiments, as shown in FIG. 6 , the lengths of the plurality of third portions 103 in their extending directions are equal.

[0148] In a specific implementation, as shown in FIG6 , among the multiple fan-out lines 1 of the third subgroup, the line connecting the end of the third portion 103 away from the first region is approximately located on the same straight line extending along the second direction X, and the line connecting the end of the third portion 103 close to the first region is approximately located on the same straight line extending along the second direction X.

[0149] It should be noted that the lengths of the two third parts can be considered equal if the difference between their lengths is within a reasonable process error range.

[0150] In some embodiments, as shown in FIG6 , in the direction from the first fan-out line 1-1 to the second fan-out line 1-2 (i.e., the positive direction X+ of the second direction X in FIG6 ), the lengths of the second portions 102 / 102-1 of the plurality of first fan-out lines 1-1 in the first direction Y gradually increase, and the lengths of the second portions 102 / 102-2 of the plurality of second fan-out lines 1-2 in the first direction Y gradually decrease.

[0151] It should be noted that since the fan-out lines extend to the first sub-region and are electrically connected to the first signal line, and extend to the first binding area and are electrically connected to the first binding electrode, when the position of the first signal line and the position of the first binding electrode electrically connected to the fan-out line are determined, the maximum wiring space for the fan-out lines in the fan-out line group is also determined accordingly, and the starting position of the first portion and the ending position of the third portion in the fan-out area are also determined accordingly. In the array substrate provided by the disclosed embodiment, in the direction from the first fan-out line to the second fan-out line, the length of the first portion of the plurality of first fan-out lines gradually decreases in the direction of their extension, and the length of the second portion in the first direction Y gradually increases. The length of the first portion of the plurality of second fan-out lines gradually increases in the direction of their extension, and the length of the second portion in the first direction Y gradually decreases. The length of the third portions of the plurality of fan-out lines is equal. This facilitates the rational use of wiring space and increases the length of the fan-out lines when the first portions of the first and second fan-out lines extend in different directions, avoids display defects caused by a large difference in length between adjacent first and second fan-out lines, resulting in a sudden change in resistance, and thus improves display quality.

[0152] In some embodiments, as the first fan-out line points toward the second fan-out line, the length of the first fan-out line gradually decreases, while the length of the second fan-out line gradually increases. For adjacent second fan-out lines and first fan-out lines, the length of the second fan-out line is greater than or equal to the length of the first fan-out line. This facilitates the rational use of wiring space and avoids large length and resistance differences between adjacent fan-out lines in the mi-th subgroup, thereby improving display quality.

[0153] In some embodiments, as shown in FIG6 , in the mi-th subgroup A(mi) (ie, the third subgroup A3 in FIG6 ), the number of the first fan-out lines 1 - 1 is less than the number of the second fan-out lines 1 - 2 .

[0154] In a specific implementation, when the line widths of the second parts are equal and the spacing between two adjacent second parts is equal, as shown in Figure 6, in the second direction X, the total width L1 of the second parts 102 / 102-1 of the multiple first fan-out lines 1-1 is smaller than the total width L2 of the second parts 102 / 102-2 of the multiple second fan-out lines 1-2.

[0155] During specific implementation, the number of the first fan-out lines and the number of the second fan-out lines may be set according to the number of the mi-th subgroup, wiring space, and the resistance difference between adjacent fan-out lines.

[0156] It should be noted that Figures 5 and 6 illustrate the pattern of the first portion 101, the second portion 102, and the third portion 103 as straight lines extending along the first direction Y. In practice, if each portion is configured as a straight line, resistance can be increased and display defects caused by large resistance differences between adjacent fan-out lines can be avoided. This can save wiring space and simplify the process for easy implementation.

[0157] Alternatively, when there is sufficient wiring space, in some embodiments, at least part of the pattern of the second portion includes a fold line extending along the first direction Y. This can further increase the length of the fan-out line and increase the resistance of the fan-out line.

[0158] It should be noted that when at least part of the pattern of the second portion includes a zigzag line extending along the first direction Y, the patterns of the first and third portions remain linear. The second portion extends along the first direction, while the first and third portions extend in an oblique direction that intersects both the first and second directions. Compared to the second portion extending vertically, i.e., along the first direction, the first and third portions have less wiring space. By configuring only the second portion to extend as a zigzag line, the length and resistance of the fan-out lines can be increased while rationally utilizing the wiring space and avoiding increasing the difficulty of fan-out line production.

[0159] In some embodiments, as shown in FIG. 12 , the second portion 102 includes: a plurality of first sub-portions 1021 extending along the first direction Y and a plurality of second sub-portions 1022 extending along the second direction X, and the first sub-portions 1021 and the second sub-portions 1022 are alternately connected.

[0160] It should be noted that Figure 12 illustrates an example in which the length of the first subsection 1021 is smaller than the length of the second subsection 1022. In practice, the length and number of the first subsections and the length and number of the second subsections can be set as needed.

[0161] In some embodiments, any two adjacent fan-out lines are located in different conductive layers.

[0162] In the array substrate provided by the embodiment of the present disclosure, any two adjacent fan-out lines are located in different conductive layers. Even if the distance between the two adjacent fan-out lines is very small, no short circuit will occur between the two lines, thus saving wiring space.

[0163] In some embodiments, as shown in Figures 7 to 11, the array substrate includes: a first conductive layer 11 and a second conductive layer 12 located on the side of the first conductive layer 11 away from the first base substrate 2; among the multiple fan-out lines 1, some fan-out lines 1 are located in the first conductive layer 11, and the remaining fan-out lines 1 are located in the second conductive layer 12; and in the second direction X, the fan-out lines 1 located in the first conductive layer 11 and the fan-out lines 1 located in the second conductive layer 12 are alternately arranged.

[0164] In some embodiments, each sub-pixel includes a thin-film transistor and a pixel electrode located on a side of the thin-film transistor facing away from the first substrate. In a specific implementation, the first conductive layer also includes the gate of the thin-film transistor, and the second conductive layer also includes the source and drain of the thin-film transistor. That is, some of the multiple fan-out lines are arranged on the same layer as the gate of the thin-film transistor, while the remaining fan-out lines are arranged on the same layer as the source and drain of the thin-film transistor.

[0165] In a specific implementation, the thin film transistor has a top gate structure, that is, the gate is located on the side of the active layer away from the first substrate; or the thin film transistor has a bottom gate structure, that is, the gate is located on the side of the active layer toward the first substrate.

[0166] In some embodiments, the second conductive layer also includes a first signal line; when the electrically connected first signal line and the fan-out line are both located in the second conductive layer, the two are connected as a whole in the first sub-peripheral area; when the electrically connected first signal line and the fan-out line are both located in different conductive layers, in the first sub-peripheral area, the first signal line located in the second conductive layer is electrically connected to the fan-out line located in the first conductive layer through a via penetrating the insulating layer between the first conductive layer and the second conductive layer.

[0167] In some embodiments, the first binding electrode includes a first sub-electrode and a second sub-electrode that are stacked and electrically connected, the first conductive layer also includes the first sub-electrode, and the second conductive layer also includes the second sub-electrode; for the electrically connected first binding electrode and the fan-out line, when the fan-out line is located in the first conductive layer, the fan-out line is integrally connected to the first sub-electrode, and when the fan-out line is located in the second conductive layer, the fan-out line is integrally connected to the second sub-electrode.

[0168] In some embodiments, the line widths of the plurality of second portions are equal; as shown in FIG7 to FIG11 , the distance between the orthographic projections of two adjacent second portions 102 on the first substrate 2 is greater than 0, and the distance between the orthographic projections of any two adjacent second portions 102 on the first substrate 2 is equal.

[0169] During specific implementation, the line width of the second portion and the distance between orthographic projections of adjacent second portions on the first substrate can be set according to actual wiring space and the number of second portions.

[0170] In some embodiments, the first portions of the plurality of first fan-out lines have equal line widths. As shown in FIG7 and FIG11 , the orthographic projections of two adjacent first portions 101 on the first substrate 2 do not overlap, and the distance between the orthographic projections of two adjacent first portions 101 on the first substrate 2 is zero. That is, the orthographic projections of the first portions of the plurality of first fan-out lines on the first substrate are closely arranged, thereby saving wiring space. Furthermore, because the two adjacent first portions are located on different conductive layers, they will not interfere with each other even if the orthographic projections of the two adjacent first portions on the first substrate are zero.

[0171] During specific implementation, the line width of the first portion of the first fan-out line can be set according to actual wiring space and the number of the first portions.

[0172] In some embodiments, the first portions of the plurality of second fan-out lines have equal line widths. As shown in FIG9 and FIG11 , the orthographic projections of two adjacent first portions 101 on the first substrate 2 do not overlap, and the distance between the orthographic projections of two adjacent first portions 101 on the first substrate 2 is zero. That is, the orthographic projections of the first portions of the plurality of second fan-out lines on the first substrate are closely arranged, thereby saving wiring space. Furthermore, because the two adjacent first portions are located on different conductive layers, they will not interfere with each other even if the orthographic projections of the two adjacent first portions on the first substrate are zero.

[0173] During specific implementation, the line width of the first portion of the second fan-out line can be set according to the actual wiring space and the number of the first portions.

[0174] In some embodiments, as shown in FIG8 and FIG10 , the line widths of the plurality of third portions 103 are equal; the orthographic projections of two adjacent third portions 103 on the first substrate 2 do not overlap, and the distance between the orthographic projections of two adjacent third portions 103 on the first substrate 2 is zero. In other words, the orthographic projections of the plurality of third portions on the first substrate 2 are closely arranged, thereby saving wiring space. Furthermore, because two adjacent third portions are located on different conductive layers, they will not interfere with each other even if the distance between the orthographic projections of the two adjacent third portions on the first substrate is zero.

[0175] In a specific implementation, the line width of the third portion can be set according to the actual wiring space and the number of the first portions.

[0176] In some embodiments, as shown in FIG5 , the fan-out line 1 of the m-i+1th subgroup A(m-i+1) (i.e., the 4th subgroup A4 in FIG5 ) among the m subgroups A includes: a fourth portion 104 , a fifth portion 105 , and a sixth portion 106 that are electrically connected in sequence;

[0177] In the first direction Y, the fourth portion 104 is located on a side of the fifth portion 105 close to the first area AA, and the sixth portion 106 is located on a side of the fifth portion 105 away from the first area AA;

[0178] The fourth portion 104 and the sixth portion 106 extend along the first direction Y, and the extension direction of the fifth portion 105 intersects both the first direction Y and the second direction X.

[0179] In the array substrate provided by the embodiments of the present disclosure, the fan-out lines in the (m-i+1)th subgroup include a fourth portion, a fifth portion, and a sixth portion. This means that the fan-out lines in this subgroup are also divided into at least three segments, and any two adjacent segments extend in different directions. Compared to the two-segment wiring of fan-out lines in related art, the length of the fan-out lines can be increased, and the resistance of the fan-out lines can be increased, which helps reduce the resistance difference between adjacent fan-out lines. Furthermore, when the fan-out lines in both the (m-i+1)th and (m-i+1)th subgroups are divided into at least three segments, the resistance difference between adjacent fan-out sub-lines can be reduced, preventing the display effect from being affected by large differences in fan-out lines between different subgroups.

[0180] It should be noted that one end of the fan-out line in the (m-i+1)th subgroup is electrically connected to the first binding electrode, and the other end is electrically connected to the first signal line. That is, the fan-out line extends from the first binding electrode toward one side of the first zone, extends toward the first zone, and is electrically connected to the first signal line. The fourth, fifth, and sixth portions of the fan-out line in the (m-i+1)th subgroup are line segments located at different positions along the extension direction of the fan-out line in the (m-i+1)th subgroup. The extension directions of different portions of the fan-out line in the (m-i+1)th subgroup are not exactly the same. This is equivalent to dividing the fan-out line in the (m-i+1)th subgroup into multiple segments, or portions, based on the change in extension direction. Among the fourth, fifth, and sixth parts of the same first fan-out line or the second fan-out line, the sixth part is a section closest to the first binding area and electrically connected to the first binding electrode located in the first binding area; the sixth part is a section facing the side of the first area, and the fan-out line in the m-i+1th subgroup further extends upward, and the part where the extension direction changes is the fifth part; the fourth part is a section closest to the first area, that is, the fifth part is a section facing the side of the first area, and the fan-out line in the m-i+1th subgroup further extends upward, and the part where the extension direction changes is the fourth part, and the fourth part is electrically connected to the first signal line.

[0181] In some embodiments, as shown in FIG5 , in each fan-out line 1 in the (m-i+1)th subgroup A(m-i+1), in the second direction X, the fourth portion 104 is located on a side of the fifth portion 105 away from the (mi)th subgroup A(mi), and the sixth portion 106 is located on a side of the fifth portion 105 close to the (mi)th subgroup A(mi).

[0182] In some embodiments, as shown in FIG13 , at least a portion of the fourth portion 104 is patterned as a zigzag line extending along the first direction Y. This increases the length of the fourth portion compared to a straight line, thereby increasing the length and resistance of the fan-out line in the (m-i+1)th subgroup.

[0183] It should be noted that FIG13 is an enlarged schematic diagram of the D area in FIG5 .

[0184] In some embodiments, as shown in FIG. 13 , the fourth portion 104 includes a plurality of third sub-portions 1041 extending along the first direction Y and a plurality of fourth sub-portions 1042 extending along the second direction X. The third sub-portions 1041 and the fourth sub-portions 1042 are alternately connected.

[0185] It should be noted that FIG13 illustrates an example in which the length of the third subsection 1041 is smaller than the length of the fourth subsection 1042. In a specific implementation, as shown in FIG13 , the lengths of the multiple third subsections 1041 may not be exactly the same, and the lengths of the multiple fourth subsections 1042 may not be exactly the same. In a specific implementation, the length and number of the third subsections and the length and number of the fourth subsections may be set as needed.

[0186] In some embodiments, the lengths of the plurality of fourth portions are all equal, that is, each fourth portion is a fold line extending along the first direction Y. For example, in the (m-i+1)th subgroup, the patterns of the plurality of fourth portions are the same, the total lengths of the plurality of fourth portions are all equal, and the widths of the orthographic projections of the fourth portions on the first substrate in the first direction Y are all equal.

[0187] In a specific implementation, the ratio of the width of the fourth portion in the first direction Y of the orthographic projection of the first substrate to the distance between the edge of the fan-out region facing the first region and the first binding region is approximately 1 / 3.

[0188] In some embodiments, the pattern of the fifth portion is linear; and in the arrangement direction of the mi-th subgroup and the m-i+1-th subgroup, the lengths of the plurality of fifth portions gradually increase.

[0189] 14 , at least a portion of the sixth portion 106 is patterned as a zigzag line extending along the first direction Y. This increases the length of the sixth portion, thereby increasing the length and resistance of the fan-out line in the (m-i+1)th subgroup.

[0190] It should be noted that FIG14 is an enlarged schematic diagram of the E region in FIG5 .

[0191] In some embodiments, as shown in FIG. 14 , the sixth portion 106 includes a plurality of fifth sub-portions 1061 extending along the first direction Y and a plurality of sixth sub-portions 1062 extending along the second direction X, and the third sub-portions 1061 and the sixth sub-portions 1062 are alternately connected.

[0192] It should be noted that FIG14 illustrates an example in which the length of fifth subsection 1061 is smaller than the length of sixth subsection 1062. In a specific implementation, as shown in FIG14 , the lengths of multiple fifth subsections 1061 may not be exactly the same, and the lengths of multiple sixth subsections 1062 may not be exactly the same. In a specific implementation, the length and number of the fifth subsections and the length and number of the sixth subsections may be set as needed.

[0193] In some embodiments, in the arrangement direction of the mi-th subgroup and the (m-i+1)-th subgroup, lengths of at least some of the plurality of sixth portions gradually decrease.

[0194] In a specific implementation, when there is sufficient wiring space, each sixth portion can be a folded line extending along the first direction Y. Alternatively, based on the resistance difference requirement of the fan-out lines, as shown in FIG14 , in the (m-i+1)th subgroup, some sixth portions 106 are folded lines extending along the first direction Y, and the remaining sixth portions 106 are straight lines extending along the first direction Y.

[0195] In some embodiments, as shown in FIG. 14 , a plurality of zigzag-line sixth portions 106 are located on a side of the linear sixth portion 106 facing the mi-th subgroup A(mi).

[0196] It should be noted that, taking i=1 and m=4 as an example, that is, when the m-i+1th subgroup is the fourth subgroup, the wiring space in the area close to the third subgroup is small, while the wiring space in the area far from the third subgroup is relatively sufficient. Accordingly, the length of the fan-out line close to the third subgroup is shorter than the length of the fan-out line in the area far from the third subgroup. There may be a large difference in resistance between the fan-out line close to the third subgroup and the fan-out line in the area far from the third subgroup. Setting the sixth portion of the fan-out line close to the third subgroup to a broken line shape is beneficial to avoid the large resistance difference between adjacent fan-out lines affecting the display effect. In specific implementation, the number of broken line-shaped sixth portions and the number of straight line-shaped sixth portions can be specifically set according to the requirement for the resistance difference between adjacent fan-out lines.

[0197] In some embodiments, as shown in FIG14 , in the arrangement direction of the mi-th subgroup and the m-i+1-th subgroup (i.e., the positive direction X+ of the second direction X in FIG14 ), the length of the sixth portion 106 extending from the multiple broken lines gradually decreases.

[0198] In the array substrate provided by the embodiment of the present disclosure, the fourth part and the sixth part extend along the first direction, and the extension direction of the fifth part is an inclined direction intersecting with both the first direction and the second direction. Compared with the vertical extension, that is, the extension along the first direction, the wiring space of the fifth part is smaller. At least part of the fourth part and at least part of the sixth part are set to be a broken line extension, and the fifth part is set to be a straight line extension. This can increase the length of the fan-out line and increase the resistance of the fan-out line while reasonably utilizing the wiring space and avoiding increasing the difficulty of fan-out line production.

[0199] In some embodiments, as shown in FIG5 , FIG13 , and FIG14 , the fifth portions 105 of the plurality of fan-out lines 1 in the (m-i+1)th subgroup A(m-i+1) are parallel to each other.

[0200] In some embodiments, as shown in FIG. 13 , the extension direction of the fifth portion 105 of the (m-i+1)th subgroup A(m-i+1) has a fourth angle a4 with the positive direction X+ of the second direction X.

[0201] In some embodiments, as shown in FIG5 , when the first to mth subgroups A1 to Am in a fan-out line group 3 are arranged along the positive direction X+ of the second direction X, as shown in FIG6 and FIG13 , the fourth angle a4 and the second angle a2 are both greater than 0° and less than 90°. For example, the fourth angle a4 is greater than or equal to 5° and less than or equal to 10°.

[0202] Alternatively, in some embodiments, when the first to mth subgroups A1 to Am in a fan-out line group 3 are arranged along the negative direction X- of the second direction X, the fourth angle a4 and the second angle a2 are both greater than 90° and less than 180°. For example, the fourth angle a4 is greater than or equal to 170° and less than or equal to 175°.

[0203] In some embodiments, as shown in Figure 5, in two adjacent fan-out lines of the mi-th subgroup A(mi) and the m-i+1-th subgroup A(m-i+1), the first portion 101 is adjacent to the fifth portion 105; in the first direction Y, at least part of the fifth portion 105 is located on the side of the first portion 101 closest to the m-i+1-th subgroup A(m-i+1) away from the first area AA.

[0204] In the array substrate provided by the embodiments of the present disclosure, the extension direction of the first portion of the second fan-out line in the mi-th subgroup and the extension direction of the fifth portion in the m-i+1-th subgroup pass through the same quadrant of the coordinate system formed by the first direction Y and the second direction X, and the first portion and the fifth portion of two adjacent fan-out lines in the mi-th subgroup and the m-i+1-th subgroup are adjacent, which can match the patterns of the fan-out lines of adjacent subgroups, saving wiring space. In addition, the first portion and the third portion of the second fan-out line are located on the same side of the second portion in the second direction, so that the patterns of the first portion, the second portion, and the third portion have a groove area, which can match the pattern of the fan-out line including the fourth portion, the fifth portion, and the sixth portion in the m-i+1-th subgroup, which is conducive to reducing wiring space. It is possible to increase the length of the second fan-out line and the fan-out line in the m-i+1-th subgroup while fully utilizing the wiring space, thereby avoiding display defects caused by excessive resistance differences between adjacent fan-out lines located in the mi-th subgroup and the m-i+1-th subgroup.

[0205] In a specific implementation, in the mth subgroup, the fan-out lines located in the first conductive layer and the fan-out lines located in the second conductive layer are alternately arranged.

[0206] In some embodiments, in the mth subgroup, the line widths of the plurality of fifth portions are equal, the orthographic projections of adjacent fifth portions on the first substrate do not overlap, the distances between the orthographic projections of any adjacent fifth portions on the first substrate are equal, and the distances between the orthographic projections of adjacent fifth portions on the first substrate are greater than or equal to 0; in the fourth portion, the line widths of the plurality of third sub-portions are equal, the line widths of the plurality of fourth sub-portions are equal, the line widths of the third sub-portions are equal to the line widths of the fourth sub-portions, the orthographic projections of two adjacent fourth portions on the first substrate do not overlap, and the distance between the third sub-portions in the orthographic projections of any two adjacent fourth portions on the first substrate is greater than or equal to 0. The distances between the fifth sub-parts are equal; in the sixth part, the line widths of the plurality of fifth sub-parts are equal, the line widths of the plurality of sixth sub-parts are equal, the line widths of the fifth sub-part are equal to the line widths of the sixth sub-part, the orthographic projections of the two adjacent sixth parts on the first substrate substrate do not overlap with each other, and the distances between the fifth sub-parts in the orthographic projections of any two adjacent sixth parts on the first substrate substrate are equal; when the m-th sub-group includes a linear sixth part, the line widths of the plurality of linear sixth parts are equal, the distance between the orthographic projections of adjacent linear sixth parts on the first substrate substrate is greater than 0, and the distances between the orthographic projections of any adjacent linear sixth parts on the first substrate substrate are equal.

[0207] In a specific implementation, in the mth subgroup, the line width of each part of the fan-out line and the distance between the orthographic projections of adjacent fan-out lines on the first substrate can be set according to the actual wiring space and the number of fan-out lines.

[0208] In some embodiments, as shown in Figure 5, the mi-1th subgroup A(mi-1) among the m subgroups A (i.e., the 2nd subgroup A2 in Figure 5) includes multiple third fan-out lines 1-3; the third fan-out line 1-3 includes: a bending portion 1-3-1 that turns to the mi-th subgroup A(mi) among the m subgroups A (i.e., the 3rd subgroup A3 in Figure 5).

[0209] In the related art, as shown in FIG3 , in the fan-out area, the fan-out line 1 in the second subgroup A2 and the third subgroup A3 is divided into two parts: a part extending in an oblique direction and a part extending in a vertical direction, that is, the pattern of some fan-out lines in the second subgroup A2 and the third subgroup A3 is the same. However, due to the large blank area between the second subgroup A2 and the third subgroup A3 and above the dummy binding electrode, this will cause a large difference in length between the two adjacent fan-out lines respectively located in the second subgroup A2 and the third subgroup A3. This will in turn cause a large difference in resistance between the two adjacent fan-out lines respectively located in the second subgroup A2 and the third subgroup A3. As shown in FIG4 , there is a large jump in the resistance between the fan-out lines of the second subgroup A2 and the third subgroup A3, which will result in poor vertical lines on the display, seriously affecting the display effect.

[0210] In the array substrate provided by the embodiments of the present disclosure, the third fan-out line in the mi-1 subgroup includes a bend. Compared to the related art where the fan-out line does not have a bend, this increases the length of the third fan-out line and the resistance of the fan-out line. This helps reduce the resistance difference between adjacent fan-out lines, avoids resistance jumps between adjacent fan-out lines that can cause poor vertical line display, and improves display quality.

[0211] In some embodiments, as shown in FIG15 , in a direction from the mi-1th subgroup A(mi-1) to the mi-th subgroup A(mi), the lengths of the plurality of bending portions 1 - 3 - 1 gradually increase.

[0212] It should be noted that FIG15 is an enlarged schematic diagram of area C in FIG5 .

[0213] In some embodiments, as shown in FIG5 and FIG15 to FIG17 , the bending portion 1 - 3 - 1 includes: a seventh portion 107 , an eighth portion 108 , and a ninth portion 109 that are electrically connected in sequence;

[0214] In the first direction Y, the seventh portion 107 is located on a side of the eighth portion 108 close to the first area AA, and the ninth portion 109 is located on a side of the eighth portion 108 away from the first area AA. In the second direction X, the seventh portion 107 and the ninth portion 109 are located on the same side of the eighth portion 108.

[0215] The seventh portion 107 and the ninth portion 109 intersect the first direction Y and the second direction X, and the eighth portion 108 extends along the first direction Y.

[0216] It should be noted that FIG16 is an enlarged schematic diagram of the C1 region in FIG15 , and FIG17 is an enlarged schematic diagram of the C1 region in FIG15 .

[0217] In the array substrate provided by the embodiments of the present disclosure, the bend portion of the third fan-out line is also divided into at least three sections, with any two adjacent sections extending in different directions. Compared to the two-section fan-out line wiring in related art, this increases the length of the fan-out line and its resistance, facilitating a uniform change in fan-out line resistance and reducing resistance differences between adjacent fan-out lines. Furthermore, when the fan-out lines in the mi-1 subgroup and the m-i+ subgroup are both divided into at least three sections, resistance differences between adjacent fan-out sub-lines can be reduced, preventing significant differences in fan-out lines between different subgroups from affecting display quality.

[0218] It should be noted that the seventh part, the eighth part and the ninth part are line segments located at different positions in the bending portion, and the extension directions of different segments are different. The pattern of the positive projection of the seventh part, the eighth part and the ninth part connected in sequence on the first base substrate is a pattern with a turning point.

[0219] In some embodiments, as shown in FIG. 5 and FIG. 15 to FIG. 17 , in the mi-1th subgroup A(mi-1), the plurality of seventh portions 107 are parallel to each other, and the plurality of ninth portions 109 are parallel to each other.

[0220] In some embodiments, in the first direction Y, the lengths of the plurality of eighth portions 108 included in the plurality of third fan-out lines 1-3 are substantially equal;

[0221] In the direction from the mi-1th subgroup A(mi-1) to the mi-th subgroup A(mi), the lengths of the multiple seventh portions 107 included in the multiple third fan-out lines 1-3 gradually increase in the extending direction thereof, and the lengths of the multiple ninth portions 109 included in the multiple third fan-out lines 1-3 gradually increase in the extending direction thereof.

[0222] It should be noted that, in the first direction Y, if the difference between the lengths of the plurality of eighth portions is within a reasonable error range, the lengths of the plurality of eighth portions can be considered to be substantially equal.

[0223] In some embodiments, as shown in FIG. 5 and FIG. 15 , in the mi-1th subgroup A(mi-1), the length of the seventh portion 107 of the third fan-out line is substantially equal to the length of the ninth portion 109 .

[0224] It should be noted that if the difference between the length of the seventh portion and the length of the ninth portion is within a reasonable error range, it can be considered that the length of the seventh portion is approximately equal to the length of the ninth portion.

[0225] In some embodiments, as shown in FIG15 , the angle a12 between the seventh portion 107 and the eighth portion 108 is equal to the angle a13 between the ninth portion 109 and the eighth portion 108 ; a12 and a13 are greater than or equal to 95° and less than 100°.

[0226] 15 , the ends of the plurality of eighth portions 108 close to the first region are approximately located on the same straight line extending along the second direction X, and the ends of the plurality of eighth portions 108 away from the first region are approximately located on the same straight line extending along the second direction X. The ends of the plurality of seventh portions 107 proximate the first zone are approximately located on the same straight line, and the extension direction of the straight line 15 intersects both the first direction Y and the second direction X. The ends of the plurality of ninth portions 109 proximate the first zone are approximately located on the same straight line, and the extension direction of the straight line 16 intersects both the first direction Y and the second direction X. The angle between the extension direction of the straight line 15 and the second direction X is a14, and the angle between the extension direction of the straight line 16 and the second direction X is a16, where a14=a16, and a14 and a16 are greater than or equal to 95° and less than 100°. The angle between the extension direction of the line 15 and the seventh portion 107 is a15, and the angle between the extension direction of the straight line 16 and the ninth portion 109 is a17, where a15=a17, and a15 and a17 are greater than or equal to 95° and less than 100°.

[0227] In some embodiments, as shown in FIG15 , the extending direction of the seventh portion 107 and the positive direction X+ of the second direction X form a fifth angle a5; the extending direction of the ninth portion 109 and the positive direction X+ of the second direction X form a seventh angle a7;

[0228] In some embodiments, when the 1st subgroup A1 to the mth subgroup Am in a fan-out line group 3 are arranged along the positive direction X+ of the second direction X, as shown in FIG15 , the fifth angle a5 and the first angle a1 are both greater than 90° and less than 180°, and the seventh angle a7 is greater than 0° and less than 90°.

[0229] Alternatively, in some embodiments, when the 1st to mth subgroups A1 to Am in a fan-out line group 3 are arranged along the negative direction X- of the second direction X, the fifth angle a5 and the first angle a1 are both greater than 0° and less than 90°, and the seventh angle a7 is greater than 90° and less than 180°.

[0230] That is, in the array substrate provided by the embodiment of the present disclosure, the extension direction of the seventh portion of the third fan-out line and the extension direction of the first portion of the first fan-out line pass through the same quadrant of the coordinate system composed of the first direction Y and the second direction X, so that the patterns of the fan-out lines of adjacent subgroups can be matched, saving wiring space.

[0231] In some embodiments, as shown in FIG5 , the array substrate further includes: a dummy binding electrode 404 located in the first binding region 202 . In FIG5 , the first binding region 202 includes a plurality of dummy binding electrodes 404 .

[0232] It should be noted that FIG5 only illustrates one row of first binding electrodes 401 and one row of dummy binding electrodes 404 . In a specific implementation, multiple first binding electrodes may be arranged in multiple rows, and multiple dummy binding electrodes may be arranged in multiple rows.

[0233] In some embodiments, the array substrate further includes a driver chip; a plurality of first binding electrodes and a plurality of dummy binding electrodes located in the first binding region are bound to the driver chip. The area of ​​the first binding region shown in FIG5 coincides with the orthographic projection of the driver chip on the first base substrate, for example.

[0234] In a specific implementation, the dummy binding electrodes do not need to be electrically connected to the fan-out lines, and the provision of the dummy binding electrodes can ensure thickness uniformity and support strength of the first binding area.

[0235] In some embodiments, as shown in FIG5 and FIG15 , the fan-out line 1 extends to the first binding area 202 , that is, the fan-out line 1 is electrically connected to the first binding electrode 401 at one end thereof away from the first area AA;

[0236] In the second direction X, a dummy binding electrode 404 is included between two adjacent first binding electrodes 401 electrically connected to the fan-out lines 1 of the mi-1th subgroup A(mi-1) and the mi-th subgroup A(mi);

[0237] In the first direction Y, at least part of the bent portion 1 - 3 - 1 is located between the dummy binding electrode 404 and the first portion 101 closest to the mi-1th subgroup A(mi-1), ie, region C3 in FIG15 .

[0238] Specifically, in Figures 5 and 15, the first binding area 202 includes multiple dummy binding electrodes 404 as an example for illustration. In the second direction X, multiple dummy binding electrodes 404 are included between the first binding electrodes 401 that are electrically connected to the two adjacent fan-out lines 1 located in the mi-1th subgroup A (mi-1) and the mi-th subgroup A (mi); in the first direction Y, at least part of the bending portion 1-3-1 is located between the multiple dummy binding electrodes 404 and the first portion 101 closest to the mi-1th subgroup A (mi-1).

[0239] In the array substrate provided by the disclosed embodiments, the dummy binding electrodes do not need to be electrically connected to the fan-out lines, thus providing ample wiring space on the side of the dummy binding electrodes facing the first region. At least a portion of the bend portion of the third fan-out line is located between the multiple dummy binding electrodes and the first portion closest to the mi-1 subgroup. That is, at least a portion of the bend portion extends to the area above the multiple dummy binding electrodes and below the first portion closest to the mi-1 subgroup. This allows the fan-out lines of adjacent subgroups to match their patterns while fully utilizing the space on the side of the multiple dummy binding electrodes facing the first region. This increases the length and resistance of the third fan-out line, reduces resistance differences between adjacent fan-out sub-lines, and avoids significant differences in fan-out lines between different subgroups, resulting in vertical streaks that affect display quality.

[0240] In some embodiments, as shown in Figures 5 and 15, the third fan-out line 1-3 also includes: a tenth portion 1010 located on the side of the bending portion 1-3-1 toward the first area AA in the first direction Y, an eleventh portion 1011 located on the side of the bending portion 1-3-1 away from the first area AA in the first direction Y, and a twelfth portion 1012 located on the side of the tenth portion 1010 toward the first area AA in the first direction Y; the tenth portion 1010 and the eleventh portion 1011 extend along the first direction Y, and the twelfth portion 1012 is parallel to the first portion 101.

[0241] In some embodiments, as shown in FIG15 , the lengths of the plurality of tenth portions 1010 are substantially equal;

[0242] In the direction from the mi-1th subgroup A(mi-1) to the mi-th subgroup A(mi), the lengths of the plurality of eleventh portions 1011 gradually decrease, and the lengths of the plurality of twelfth portions 1012 gradually decrease.

[0243] In some embodiments, as shown in FIG15 , the mi-1th subgroup further includes a plurality of fourth fan-out lines 1-4, and the plurality of fourth fan-out lines 1-4 are located on a side of the plurality of third fan-out lines 1-3 away from the mi-th subgroup;

[0244] The fourth fan-out line 1-4 includes a thirteenth portion 1013 connected in sequence and a fourteenth portion 1014 located on a side of the thirteenth portion 1013 away from the first region;

[0245] The extending direction of the thirteenth portion 1013 intersects both the first direction Y and the second direction X, and the fourteenth portion 1014 extends along the first direction Y.

[0246] In some embodiments, as shown in FIG. 15 , the thirteenth portion 1013 is parallel to the twelfth portion 1012 .

[0247] In some embodiments, in a direction from the mi-1th subgroup to the mith subgroup, lengths of the plurality of thirteenth portions gradually decrease, and lengths of the plurality of fourteenth portions gradually increase.

[0248] In a specific implementation, if the second subgroup is a fan-out line pattern as shown in FIG3 in the related art, i.e., a fan-out line with two segments, the resistance of the fan-out line closest to the third subgroup in the second subgroup is M1. If the resistance of the first fan-out line closest to the second subgroup in the third subgroup provided by the embodiment of the present disclosure is M2, the number of third fan-out lines is set to N based on the requirement for the difference in resistance of adjacent fan-out lines, and |M2-M1| / N≤5 ohms is required to satisfy, so that the resistance difference can be evenly distributed in the third fan-out line, avoiding a resistance jump between the third fan-out line and the first fan-out line.

[0249] In some embodiments, a pattern of a portion of at least a portion of the fan-out lines 1 in the mi-1th subgroup is a fold line extending along the first direction Y. In a specific implementation, if wiring space permits and the fan-out line length needs to be further increased, at least a portion of the eighth portion, the tenth portion, the eleventh portion, and the fourteenth portion can be set to be a fold line extending along the first direction Y.

[0250] In some embodiments, the lengths of two adjacent fan-out lines 1 located in the mi-1th subgroup A(mi-1) and the mith subgroup A(mi) are substantially equal, thereby avoiding vertical line defects caused by large resistance differences between adjacent fan-out lines located in different subgroups.

[0251] In a specific implementation, in the mi-1 th subgroup, the fan-out lines located in the first conductive layer and the fan-out lines located in the second conductive layer are alternately arranged.

[0252] In some embodiments, as shown in Figures 16 and 17, the line widths of multiple eighth portions 108 are equal; the distance between the orthographic projections of two adjacent eighth portions 108 on the first substrate 2 is greater than 0, and the distance between the orthographic projections of any two adjacent eighth portions 108 on the first substrate 2 is equal.

[0253] During specific implementation, the line width of the eighth portion and the distance between orthographic projections of adjacent eighth portions on the first substrate can be set according to actual wiring space and the number of eighth portions.

[0254] In some embodiments, as shown in Figures 16 and 17 , the line widths of the plurality of seventh portions 107 are equal; the orthographic projections of two adjacent seventh portions 107 on the first substrate 2 do not overlap, and the distance between the orthographic projections of two adjacent seventh portions 107 on the first substrate 2 is zero. In other words, the orthographic projections of the plurality of third fan-out lines 107 on the first substrate 2 are closely arranged, thereby saving wiring space. Furthermore, because two adjacent seventh portions are located on different conductive layers, they will not interfere with each other even if the orthographic projections of the two adjacent seventh portions on the first substrate 2 are zero.

[0255] During specific implementation, the line width of the seventh portion in the third fan-out line can be set according to the actual wiring space and the number of the first portions.

[0256] In some embodiments, as shown in Figures 16 and 17 , the line widths of the plurality of ninth portions 109 are equal; the orthographic projections of two adjacent ninth portions 109 on the first substrate 2 do not overlap, and the distance between the orthographic projections of two adjacent ninth portions 109 on the first substrate 2 is zero. In other words, the orthographic projections of the ninth portions 109 of the plurality of third fan-out lines on the first substrate 2 are closely arranged, thereby saving wiring space. Furthermore, because the ninth portions are located on different conductive layers, they will not interfere with each other even if the orthographic projections of the ninth portions on the first substrate 2 are zero.

[0257] During specific implementation, the line width of the ninth portion in the third fan-out line can be set according to the actual wiring space and the number of the first portions.

[0258] In some embodiments, as shown in Figure 17, the line widths of multiple tenth portions 1010 are equal; the distance between the orthographic projections of two adjacent tenth portions 1010 on the first substrate 2 is greater than 0, and the distance between the orthographic projections of any two adjacent tenth portions 1010 on the first substrate 2 is equal.

[0259] In some embodiments, as shown in Figure 17, the line widths of multiple eleventh portions 1011 are equal; the distance between the orthographic projections of two adjacent eleventh portions 1011 on the first substrate 2 is greater than 0, and the distance between any two adjacent eleventh portions 1011 on the first substrate 2 is equal.

[0260] In some embodiments, as shown in Figure 17, the line widths of multiple fourteenth portions 1014 are equal; the distance between the orthographic projections of two adjacent fourteenth portions 1014 on the first substrate substrate 2 is greater than 0, and the distance between the orthographic projections of any two adjacent fourteenth portions 1014 on the first substrate substrate 2 is equal; the line width of the fourteenth portion 1014 is equal to the line widths of the tenth portion 1010 and the eleventh portion 1011; the distance between the orthographic projections of two adjacent fourteenth portions 1014 on the first substrate substrate 2, the distance between the orthographic projections of two adjacent tenth portions 1010 on the first substrate substrate 2, the distance between the orthographic projections of adjacent fourteenth portions 1014 and the tenth portion 1010 on the first substrate substrate 2, the distance between the orthographic projections of two adjacent eleventh portions 1011 on the first substrate substrate 2, and the distance between the orthographic projections of adjacent fourteenth portions 1014 and the eleventh portion 1011 on the first substrate substrate 2 are equal.

[0261] In specific implementation, the line width of the tenth part, the distance between the orthographic projections of adjacent tenth parts on the first substrate substrate, the line width of the eleventh part, the distance between the orthographic projections of adjacent eleventh parts on the first substrate substrate, the line width of the fourteenth part, and the distance between the orthographic projections of adjacent fourteenth parts on the first substrate substrate can be set according to the actual wiring space and the number of fourteenth parts.

[0262] In some embodiments, the line widths of the multiple twelfth portions and the line widths of the multiple thirteenth portions are equal; the orthographic projections of two adjacent twelfth portions on the first substrate substrate do not overlap with each other, the orthographic projections of two adjacent thirteenth portions on the first substrate substrate do not overlap with each other, the orthographic projections of adjacent twelfth portions and thirteenth portions on the first substrate substrate do not overlap with each other, and the distance between the orthographic projections of two adjacent twelfth portions on the first substrate substrate, the distance between the orthographic projections of two adjacent thirteenth portions on the first substrate substrate, and the distance between the orthographic projections of adjacent twelfth portions and thirteenth portions on the first substrate substrate are greater than or equal to 0.

[0263] In specific implementation, the line width of the twelfth part and the thirteenth part, the distance between the orthographic projections of two adjacent twelfth parts on the first substrate substrate, the distance between the orthographic projections of two adjacent thirteenth parts on the first substrate substrate, and the distance between the orthographic projections of adjacent twelfth and thirteenth parts on the first substrate substrate can be set according to the actual wiring space and the number of the twelfth part and the thirteenth part.

[0264] In some embodiments, as shown in FIG. 5 , in the fan-out region 201 , the extension direction of the fan-out line 1 in the first subgroup intersects both the first direction Y and the second direction X.

[0265] In some embodiments, the fan-out line in the first subset is parallel to the thirteenth portion.

[0266] In some embodiments, as shown in FIG. 5 , the angle between the extension direction of the plurality of fan-out lines 1 in the first subgroup A1 and the positive direction of the first direction Y is a sixth angle a6 .

[0267] In some embodiments, when the first to mth subgroups A1 to Am in a fan-out line group 3 are arranged along the positive direction X+ of the second direction X, the sixth angle a6 is greater than 90° and less than 180°, and the fourth angle a4 is greater than 0° and less than 90°.

[0268] Alternatively, in some embodiments, when the 1st to mth subgroups A1 to Am in a fan-out line group 3 are arranged along the negative direction X- of the second direction X, the sixth angle a6 is greater than 0° and less than 90°, and the fourth angle a4 is greater than 90° and less than 180°.

[0269] That is, the extension direction of the fan-out line in the first subgroup and the extension direction of the fifth portion in the mth subgroup pass through different quadrants of the coordinate system formed by the first direction Y and the second direction X.

[0270] In some embodiments, among the m subgroups, the maximum width of the mth subgroup is smaller than the maximum width of the first subgroup in the second direction X. When m=4, the maximum width of the fourth subgroup is smaller than the maximum width of the first subgroup.

[0271] The array substrate provided by the embodiments of the present disclosure is applicable when the driver chips are unevenly distributed relative to the first region, and the wiring spaces of the multiple subgroups in the fan-out line group are also different. The maximum width of the m-th subgroup is smaller than the maximum width of the first subgroup, that is, the wiring space in the area corresponding to the first subgroup is sufficient than the wiring space of the m-th subgroup.

[0272] It should be noted that in the related art, in the fan-out area, the fan-out lines in the first sub-group are not segmented and the fan-out lines of this sub-group are extended at an angle, and the fan-out lines of the fourth sub-group are wired in two segments. However, due to the large difference in wiring space, as shown in FIG4 , the difference between the maximum resistance of the first sub-group and the maximum resistance of the fourth sub-group is large.

[0273] The array substrate provided by the embodiment of the present disclosure has a fan-out line in the fourth subgroup including a fourth part, a fifth part, and a sixth part, that is, the fan-out line is divided into at least three sections. This can increase the length of the fan-out line in the fourth subgroup while reasonably utilizing the wiring space, thereby increasing the resistance of the fan-out line in the fourth subgroup, and reducing the difference between the maximum resistance of the first subgroup and the maximum resistance of the fourth subgroup, thereby avoiding excessive resistance differences between different subgroups that affect the display effect.

[0274] In some embodiments, when m=4, among the four subgroups, the number of fan-out lines included in the first subgroup A1 and the second subgroup A2 is equal to the number of fan-out lines included in the third subgroup A3 and the fourth subgroup A4.

[0275] In some embodiments, the number of fan-out lines included in the first subgroup A1 is greater than the number of fan-out lines included in the second subgroup A2;

[0276] The number of fan-out lines included in the third sub-group A3 is greater than the number of fan-out lines included in the fourth sub-group A4.

[0277] In some embodiments, a ratio of the number of fan-out lines included in the first subgroup A1 to the number of fan-out lines included in the second subgroup A2 is greater than or equal to 3 and less than or equal to 8;

[0278] A ratio of the number of fan-out lines 1 included in the third sub-group A3 to the number of fan-out lines 1 included in the fourth sub-group A4 is greater than or equal to 2 and less than or equal to 3.

[0279] Next, the resistance of the fan-out line group is taken as an example, where the number of fan-out lines included in the first subgroup A1 is 810, the number of fan-out lines included in the second subgroup A2 is 150, the number of fan-out lines 1 included in the third subgroup A3 is 609, and the number of fan-out lines included in the fourth subgroup A4 is 351. That is, the serial numbers of the fan-out lines included in the first subgroup A1 are 1 to 810, the serial numbers of the fan-out lines included in the second subgroup A2 are 811 to 960, the serial numbers of the fan-out lines included in the third subgroup A3 are 961 to 1569, and the serial numbers of the fan-out lines included in the second subgroup A 2 includes fan-out lines numbered 1570 to 1920. The pattern of the fan-out line group is shown in FIG5 . Accordingly, the resistance variation of multiple fan-out lines in the fan-out line group is shown in FIG18 . It can be seen that in the array substrate provided by the embodiment of the present disclosure, the third fan-out line of the second subgroup, the fan-out line of the third subgroup, and the fan-out line of the fourth subgroup all extend in at least three sections. This increases the length of the fan-out line, thereby increasing the resistance of the fan-out line, resulting in a uniform resistance variation between the fan-out lines. Compared with FIG4 , the maximum resistance of the fourth subgroup A4 increases, thereby reducing the resistance difference between the fourth subgroup A4 and the first subgroup A1, thereby avoiding screen segmentation defects. Furthermore, there is no resistance mutation between the second subgroup A2 and the third subgroup A3, thereby avoiding vertical streaks caused by excessive resistance differences.

[0280] It should be noted that the number of fan-out lines included in each subgroup of the above fan-out line group is only for illustrative purposes of the effect of reducing resistance differences in the embodiment of the present disclosure, and does not limit the present disclosure. In specific implementations, the number of fan-out lines included in the fan-out line group and the number of fan-out lines included in the subgroup can be set according to actual needs.

[0281] In a specific implementation, the fan-out line is electrically connected to the first binding electrode, which is bound to the driver chip. In the related art, one resistance compensation technique is to perform resistance compensation on the entire fan-out line group through an internal setting of the driver chip to further reduce the resistance difference between the fan-out lines. When compensating for the resistance change of the fan-out line group approximately as shown in the curve of Figure 19, it is necessary to make the driver chip channels corresponding to the inflection points P1 and P2 of the resistance change within the channel range shown in Table 1, and the channel number of the driver chip corresponds to the number of the fan-out line in the fan-out line group. In the related art, as shown in Figure 4, the fan-out line numbers corresponding to the inflection points of the resistance change are 960 and 1211, and the corresponding driver chip channels are 960 and 1211, which do not fall within the channel range for resistance compensation. Therefore, the driver chip cannot compensate for the resistance of the fan-out line group. The pattern of the fan-out line group provided in the embodiment of the present disclosure is designed for the patterns of the fan-out lines of the second sub-group, the third sub-group, and the fourth sub-group. As shown in Figure 18, the fan-out line numbers corresponding to the inflection points of the resistance change are 814 and 1137, and the corresponding driver chip channels are 814 and 1137, which fall within the channel range for resistance compensation. The driver chip can be used to perform resistance compensation on the entire fan-out line group to further reduce the resistance difference between the fan-out lines and improve the display effect.

[0282] Table 1

[0283] In some embodiments, as shown in FIG. 20 and FIG. 21 , the array substrate includes 2n fan-out line groups 3 arranged along the second direction X; wherein n is a positive integer;

[0284] The 2nth fan-out line group 3 is symmetrically arranged with respect to the 2n-1th fan-out line group.

[0285] In some embodiments, as shown in FIG20 , n=1. The array substrate includes two fan-out line groups 3 arranged along a second direction X, namely, a first fan-out line group 301 and a second fan-out line group 302 . Accordingly, the peripheral area includes two first binding areas 202 , namely, a first first binding area 202 - 1 corresponding to the first fan-out line group 301 and a second first binding area 202 - 2 corresponding to the second fan-out line group 302 .

[0286] In some embodiments, as shown in FIG21 , n=2. The array substrate includes four fan-out line groups 3 arranged along the second direction X, namely, a first fan-out line group 301, a second fan-out line group 302, a third fan-out line group 303, and a fourth fan-out line group 304. Accordingly, the peripheral area includes four first binding areas 202, namely, a first first binding area 202-1 corresponding to the first fan-out line group 301, a second first binding area 202-2 corresponding to the second fan-out line group 302, a third first binding area 202-3 corresponding to the third fan-out line group 303, and a fourth first binding area 202-4 corresponding to the fourth fan-out line group 304.

[0287] In a specific implementation, when the array substrate includes multiple fan-out line groups, the number of fan-out lines in the j-th subgroup in different fan-out line groups is exactly the same, where j is an integer greater than or equal to 1 and less than or equal to m. Furthermore, the patterns of the fan-out lines in the j-th subgroup in different fan-out line groups are symmetrical or identical.

[0288] In a specific implementation, taking m=4 as an example, as shown in Figure 20, the two fan-out line groups 3 are arranged in sequence along the positive direction X+ of the second direction X, the first subgroup A1 to the fourth subgroup A4 in the first fan-out line group 301 are arranged in sequence along the positive direction X+ of the second direction X, and the first subgroup A1 to the fourth subgroup A4 in the second fan-out line group 302 are arranged in sequence along the negative direction X- of the second direction X, and the fourth subgroup A4 of the first fan-out line group 301 is adjacent to the fourth subgroup A4 of the second fan-out line group 302. The pattern of the 4th subgroup A4 of the 1st fan-out line group 301 is symmetrical with the pattern of the 4th subgroup A4 of the 2nd fan-out line group 302, the pattern of the 3rd subgroup A3 of the 1st fan-out line group 301 is symmetrical with the pattern of the 3rd subgroup A3 of the 2nd fan-out line group 302, the pattern of the 2nd subgroup A2 of the 1st fan-out line group 301 is symmetrical with the pattern of the 2nd subgroup A2 of the 2nd fan-out line group 302, and the pattern of the 1st subgroup A1 of the 1st fan-out line group 301 is symmetrical with the pattern of the 1st subgroup A1 of the 2nd fan-out line group 302.

[0289] In a specific implementation, taking m=4 as an example, as shown in Figure 21, the four fan-out line groups 3 are arranged in sequence along the positive direction X+ of the second direction X, the first subgroup A1 to the fourth subgroup A4 in the first fan-out line group 301 and the third fan-out line group 303 are arranged in sequence along the positive direction X+ of the second direction X, and the first subgroup A1 to the fourth subgroup A4 in the second fan-out line group 302 and the fourth fan-out line group 304 are arranged in sequence along the negative direction X- of the second direction X, the fourth subgroup A4 of the first fan-out line group 301 is adjacent to the fourth subgroup A4 of the second fan-out line group 302, the first subgroup A1 of the second fan-out line group 302 is adjacent to the first subgroup A1 of the third fan-out line group 303, and the fourth subgroup A4 of the third fan-out line group 303 is adjacent to the fourth subgroup A4 of the fourth fan-out line group 304. The pattern of the 4th subgroup A4 of the 1st fan-out line group 301 is symmetrical with the pattern of the 4th subgroup A4 of the 2nd fan-out line group 302, the pattern of the 3rd subgroup A3 of the 1st fan-out line group 301 is symmetrical with the pattern of the 3rd subgroup A3 of the 2nd fan-out line group 302, the pattern of the 2nd subgroup A2 of the 1st fan-out line group 301 is symmetrical with the pattern of the 2nd subgroup A2 of the 2nd fan-out line group 302, and the pattern of the 1st subgroup A1 of the 1st fan-out line group 301 is symmetrical with the pattern of the 1st subgroup A1 of the 2nd fan-out line group 302. The pattern of the 4th subgroup A4 of the 3rd fan-out line group 303 is symmetrical with the pattern of the 4th subgroup A4 of the 4th fan-out line group 304, the pattern of the 3rd subgroup A3 of the 3rd fan-out line group 303 is symmetrical with the pattern of the 3rd subgroup A3 of the 4th fan-out line group 304, the pattern of the 2nd subgroup A2 of the 3rd fan-out line group 303 is symmetrical with the pattern of the 2nd subgroup A2 of the 4th fan-out line group 304, and the pattern of the 1st subgroup A1 of the 3rd fan-out line group 303 is symmetrical with the pattern of the 1st subgroup A1 of the 4th fan-out line group 304. The pattern of the first subgroup A1 of the first fan-out line group 301 is the same as the pattern of the first subgroup A1 of the third fan-out line group 303, the pattern of the second subgroup A2 of the first fan-out line group 301 is the same as the pattern of the second subgroup A2 of the third fan-out line group 303, the pattern of the third subgroup A3 of the first fan-out line group 301 is the same as the pattern of the third subgroup A3 of the third fan-out line group 303, and the pattern of the fourth subgroup A4 of the first fan-out line group 301 is the same as the pattern of the fourth subgroup A4 of the third fan-out line group 303. ; The pattern of the first sub-group A1 of the second fan-out line group 302 is the same as the pattern of the first sub-group A1 of the fourth fan-out line group 304, the pattern of the second sub-group A2 of the second fan-out line group 302 is the same as the pattern of the second sub-group A2 of the fourth fan-out line group 304, the pattern of the third sub-group A3 of the second fan-out line group 302 is the same as the pattern of the third sub-group A3 of the fourth fan-out line group 304, and the pattern of the fourth sub-group A4 of the second fan-out line group 302 is the same as the pattern of the fourth sub-group A4 of the fourth fan-out line group 304.

[0290] In some embodiments, the 2n fan-out line groups are divided into n units, that is, each unit includes 2 fan-out line groups, and any two adjacent units are symmetrically arranged.

[0291] In some embodiments, the substrate includes 2n first binding regions;

[0292] In the second direction, the distance between adjacent first binding regions is not equal to the distance between any first binding region located at the edge and the edge of the first substrate.

[0293] In specific implementation, one fan-out line group corresponds to one first binding area, and one first binding area corresponds to one driver chip, that is, one fan-out line group corresponds to one driver chip, and one fan-out line group is electrically connected to one driver chip through the first binding electrode located in the first binding area.

[0294] In some embodiments, in the second direction, the distance between the 2n-jth first binding area and the 2n-j-1th first binding area is not equal to the distance between the 2n-jth first binding area and the 2n-j+1th first binding area; j is an integer less than 2n, and 2n-j-1 is an integer greater than or equal to 1.

[0295] In some embodiments, in the second direction, a distance between the 2nth first binding region and the 2n-1th first binding region is smaller than a distance between the 2n-1th first binding region and the 2n-2th first binding region;

[0296] In the second direction, the distance between the 2n-2 th first binding region and the 2n-3 th first binding region is smaller than the distance between the 2n-1 th first binding region and the 2n-2 th first binding region.

[0297] That is, in some embodiments, among n units, the distance between two first binding areas corresponding to two adjacent fan-out line groups in each unit in the second direction X is smaller than the distance between two first binding areas corresponding to two adjacent fan-out line groups in the unit in the second direction X. Taking m=4 as an example, the distance between the first first binding area 202-1 and the second first binding area 202-2 in the second direction X, and the distance between the third first binding area 202-3 and the fourth first binding area 202-4 in the second direction X are smaller than the distance between the second first binding area 202-2 and the third first binding area 202-3 in the second direction X.

[0298] In some embodiments, as shown in FIG21 , n is greater than 1, and the 2n-th fan-out line group 3 and the 2n-1-th fan-out line group 3 are symmetrically arranged with the 2n-2-th fan-out line group 3 and the 2n-3-th fan-out line group 3. In FIG21 , the first fan-out line group 301 is symmetrically arranged with the second fan-out line group 302, the third fan-out line group 303 is symmetrically arranged with the fourth fan-out line group 304, and the first fan-out line group 301 and the second fan-out line group 302 are symmetrically arranged with the third fan-out line group 303 and the fourth fan-out line group 304 as a whole.

[0299] In some embodiments, taking m = 4 as an example, as shown in FIG. 21, H10 is the width of the first substrate 1 in the second direction X; H9 is the width of the second bonding region 204 in the second direction X, which is also the length of the FPC (not shown); H5 is the width of the first bonding region 202 in the second direction X, and is also the width of the driving chip (not shown); H6 is the distance between the edge of the first bonding region 202 and the edge of the first substrate 1; H7 is the distance between the first first bonding region 202-1 and the second first bonding region 202-2 in the second direction X and the distance between the third first bonding region 202-3 and the fourth first bonding region 202-4 in the second direction X; H8 is the distance between the second first bonding region 202-2 and the third first bonding region 202-3 in the second direction X, and H7 < H8; 4×H5 + 2×H7 + H8 < H9. In specific implementation, since the FPC needs to be bonded to the PCB, H9 needs to be less than or equal to the length of the PCB. In the second direction X, the width H10 of the first substrate is 348.4784 millimeters (mm), the total length of the PCB is 280 mm, the length H9 of the FPC (not shown) is 279.5668 mm, H5 = 30.34 mm, H6 = 34.8148 mm, H7 = 45.8296 mm, and H8 = 65.8296 mm.

[0300] For the array substrate provided by the embodiments of the present disclosure, the multiple first bonding regions are not evenly distributed relative to the first region, that is, H7 and H8 are not equal, and neither of them is a multiple relationship with H6. This can ensure that the width of the second bonding region is less than or equal to the length of the PCB. And on the premise of ensuring that the width of the second bonding region is less than or equal to the length of the PCB, the patterns of the fan-out lines in the second subgroup, the third subgroup, and the fourth subgroup in the fan-out line group are designed such that the third fan-out line in the second subgroup and the fan-out lines in the third subgroup and the fourth subgroup are each divided into at least three segments. Compared with the case where the fan-out lines in the related art are divided into two segments, the lengths of the fan-out lines in the second subgroup, the third subgroup, and the fourth subgroup can be increased, thereby increasing the resistance of the fan-out lines and making the resistance of the fan-out lines change uniformly, avoiding excessive differences in the fan-out lines between adjacent subgroups from affecting the display effect.

[0301] In some embodiments, the resistance difference between any two adjacent fan-out lines 1 is less than or equal to 5 ohms. Thereby, it is possible to avoid excessive resistance differences between adjacent fan-out lines from affecting the display effect.

[0302] In some embodiments, as shown in FIG. 22, the array substrate further includes:

[0303] Multiple dummy structures 17 are located in the fan-out area 201; the orthographic projections of the dummy structures 17 on the substrate 1 are located in the area between the orthographic projections of adjacent sub-groups A on the substrate 1, and / or the orthographic projections of the dummy structures 17 on the substrate 1 are located on the side of the edge sub-group A away from the other sub-groups A and within the orthographic projections of the substrate 1.

[0304] It should be noted that the areas between at least some adjacent subgroups and the areas on the side of the edge subgroup away from the other subgroups occupy a larger area. Since the distance between the fan-out lines in the subgroup is relatively close, that is, the fan-out lines in the area corresponding to the subgroup are arranged relatively densely. In the fan-out area, if there is a blank area with a large area and no metal pattern on one side of the fan-out line, it is easy to affect the etching uniformity of the fan-out line, resulting in large fluctuations in the line width of the fan-out line near the edge of the blank area, affecting the yield of the fan-out line production.

[0305] The array substrate provided by the embodiment of the present disclosure is further provided with a dummy structure in the area between at least some adjacent subgroups and the area on the side of the edge subgroup away from the other subgroups, so that the area between at least some adjacent subgroups and the area on the side of the edge subgroup away from the other subgroups is no longer a blank area without a metal pattern, which can improve the etching uniformity of the fan-out line.

[0306] In some embodiments, the material of the dummy structure includes metal.

[0307] In some embodiments, as shown in FIG. 22 , the orthographic projection of the dummy structure 17 on the base substrate 1 is in the shape of a strip extending along the second direction X.

[0308] In some embodiments, as shown in FIG22 , in the region between adjacent subgroups A, a plurality of dummy structures 17 are arranged along the first direction Y;

[0309] On a side of the edge subgroup A away from the other subgroups A, a plurality of dummy structures 17 are arranged along the first direction Y.

[0310] In some embodiments, as shown in FIG22 , a plurality of dummy structures 17 are provided on the side of the first subgroup A1 away from the second subgroup A2, on the side of the fourth subgroup A4 away from the third subgroup A3, and between the fourth subgroup A4 and the third subgroup A3; the area between the first subgroup A1 and the second subgroup A2 is relatively small, and no dummy structure 17 is required.

[0311] In some embodiments, some of the multiple dummy structures are located in the first conductive layer, and the remaining dummy structures are located in the second conductive layer. Alternatively, each dummy structure includes a first sub-dummy structure located in the first conductive layer, and a second sub-dummy structure located in the second conductive layer.

[0312] In some embodiments, as shown in FIG. 23 to FIG. 30 , in at least some subgroups A, the plurality of fan-out lines 1 on at least one side edge of the subgroup A are dummy fan-out lines 18 ;

[0313] At least part of the dummy fan-out line 18 includes a disconnection area 1801 ; that is, the dummy fan-out line 18 is divided into mutually disconnected parts by the disconnection area 1801 .

[0314] The array substrate provided by the present disclosure includes dummy fan-out lines on the edge of at least one side of the subgroup. These dummy fan-out lines do not need to transmit signals. This improves the etching uniformity of the fan-out lines and prevents line width fluctuations that affect signal transmission caused by fan-out lines that need to transmit signals being located at the edge. Furthermore, at least some of the dummy fan-out lines include breakout areas, which can prevent static electricity accumulation caused by long dummy fan-out lines.

[0315] It should be noted that Figure 25 is an enlarged schematic diagram of the F area in Figures 23 and 24, Figure 26 is an enlarged schematic diagram of the G area in Figures 23 and 24, Figure 27 is an enlarged schematic diagram of the J area in Figures 23 and 24, Figure 28 is an enlarged schematic diagram of the K area in Figures 23 and 24, Figure 29 is an enlarged schematic diagram of the M area in Figures 23 and 24, and Figure 30 is an enlarged schematic diagram of the Q area in Figure 24.

[0316] In some embodiments, as shown in FIG. 25 to FIG. 30 , at least one side edge of at least part of the subgroups A includes two dummy fan-out lines 18 , and the two dummy fan-out lines 18 are respectively located in the first conductive layer 11 and the second conductive layer 12 .

[0317] In the array substrate provided by the embodiment of the present disclosure, when any two adjacent fan-out lines are located in different conductive layers, the edge of at least one side of the subgroup includes two dummy fan-out lines located in different conductive layers, thereby improving the etching uniformity of each conductive layer.

[0318] In some embodiments, as shown in Figures 23 to 30, in some dummy fan-out lines 18, the break area 1801 is located in the area where the dummy fan-out line 18 extends along the second direction X; in some dummy fan-out lines 18, the extension directions of the portions of the dummy fan-out lines 18 located on both sides of the break area 1801 intersect with both the first direction Y and the second direction X.

[0319] In some embodiments, as shown in Figures 23 and 24, the two fan-out lines 1 on the edge of the first sub-group A1 away from the second sub-group A2 are virtual fan-out lines 18 including a broken line area 1801, and the extension directions of the portions of the virtual fan-out lines 18 located on both sides of the broken line area 1801 intersect with the first direction Y and the second direction X.

[0320] In a specific implementation, in the first subgroup, the extension direction of the fan-out line intersects with both the first direction and the second direction, and the length is relatively long. The virtual three of the first subgroup away from the second subgroup includes a broken line area, which can avoid the accumulation of static electricity caused by the long length of the obliquely extended fan-out line.

[0321] In a specific implementation, for the dummy fan-out lines included in the first subgroup, the lengths of the portions of the dummy fan-out lines located on both sides of the disconnection area can be substantially equal, thereby avoiding static electricity accumulation caused by a longer length of one portion.

[0322] In some embodiments, as shown in Figures 23 and 24, the two fan-out lines 1 of the second sub-group A2 away from the edge of one side of the first sub-group A1 are virtual fan-out lines 18 including a broken line area 1801, that is, the two third fan-out lines 1-3 farthest from the first sub-group A1 are virtual fan-out lines 18, and the broken line area 1801 is located in the eighth part 108 extending along the first direction Y.

[0323] In a specific implementation, the eighth portion of the third fan-out line extends along the first direction, and the eighth portion is roughly located in the middle section of the fan-out line, and the broken line area is located in the eighth portion, which can avoid a large difference in the length of the portions of the virtual fan-out line on both sides of the broken line area, and avoid the accumulation of static electricity due to the longer length of one side.

[0324] In some embodiments, as shown in Figures 23 and 24, the two fan-out lines 1 of the third sub-group A3 near the edge of one side of the second sub-group A2 are dummy fan-out lines 18 including a broken line area 1801, and the two fan-out lines 1 of the third sub-group A3 near the edge of one side of the fourth sub-group A4 are dummy fan-out lines 18 including a broken line area 1801; that is, the two first fan-out lines 1-1 near the edge of one side of the second sub-group A2 are dummy fan-out lines 18 including a broken line area 1801, and the two second fan-out lines 1-2 near the edge of one side of the fourth sub-group A4 are dummy fan-out lines 18 including a broken line area 1801; the broken line area 1801 is located in the second part 102 extending along the first direction Y.

[0325] In a specific implementation, the second parts of the first fan-out line and the second fan-out line extend along the first direction, and the second parts are roughly located in the middle of the fan-out line, and the broken line area is located in the second part, which can avoid a large difference in the length of the parts of the virtual fan-out line on both sides of the broken line area, and avoid the accumulation of static electricity due to the longer length of one side.

[0326] It should be noted that if the dummy fan-out line is short, a break region may not be provided on the dummy fan-out line. For example, in some embodiments, as shown in FIG23 , the two fan-out lines 1 on the edge of the fourth subgroup A4 away from the third subgroup A3 are dummy fan-out lines 18 including a break region 1801 , where the break region 1801 is located in the fifth portion 105 . The edge of the fourth subgroup A4 near the third subgroup A3 includes a dummy fan-out line 18 , but the dummy fan-out line 18 does not include a break region.

[0327] Alternatively, if the fourth sub-group A4 includes a dummy fan-out line 18 having a longer length at an edge close to one side of the third sub-group A3, as shown in FIG24 , the two fan-out lines 1 of the fourth sub-group A4 away from the edge of one side of the third sub-group A3 are dummy fan-out lines 18 including a broken line area 1801, and the two fan-out lines 1 of the fourth sub-group A4 close to the edge of one side of the third sub-group A3 are also dummy fan-out lines 18 including a broken line area 1801, and the broken line area 1801 is located in the fifth part 105.

[0328] In specific implementation, in the fourth subgroup A4, the extension direction of the fifth part of the fan-out line intersects with both the first direction and the second direction, and the length of the fifth part is longer. The broken line area is located in the fifth part, which can avoid static electricity accumulation caused by the longer length of one side of the broken line area.

[0329] In some embodiments, the lengths of the portions of the dummy fan-out line located on both sides of the disconnection area are substantially equal, thereby preventing static electricity accumulation caused by a portion being longer.

[0330] In some embodiments, as shown in FIG31 , the array substrate further includes a plurality of dummy structures 17 ;

[0331] The orthographic projection of part of the dummy structure 17 on the base substrate 1 is located in the area between the orthographic projections of two dummy fan-out lines 18 on the base substrate 1 , and the two dummy fan-out lines 18 are respectively located in adjacent subgroups A;

[0332] The orthographic projection of some dummy structures 17 on the substrate 1 is located on a side of the edge subgroup A away from the other subgroups A and within the orthographic projection of the substrate 1 .

[0333] The array substrate provided by the embodiment of the present disclosure simultaneously provides a dummy structure and a dummy fan-out line in the fan-out area, which can further improve the etching uniformity of the fan-out line.

[0334] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, as shown in FIG32 , comprising:

[0335] The array substrate 7 provided in the embodiment of the present disclosure;

[0336] an opposite substrate 8, arranged opposite to the array substrate 7;

[0337] The liquid crystal layer 9 is located between the array substrate 7 and the opposite substrate 8 .

[0338] In a specific implementation, an alignment layer is further provided on a side of the array substrate close to the liquid crystal layer and a side of the opposite substrate close to the liquid crystal layer.

[0339] In some embodiments, the counter substrate includes: a second base substrate, and a black matrix and color resists on a side of the second base substrate facing the liquid crystal layer. The black matrix has an opening area, and the color resists are located in the opening area.

[0340] In a specific implementation, the orthographic projection of the black matrix on the array substrate falls within the wiring area. The color resists correspond one-to-one with the sub-pixels, and the orthographic projection of the color resists on the array substrate falls within the sub-pixels. The sub-pixels include red, blue, and green sub-pixels. Accordingly, the color resists include a red resist corresponding to the red sub-pixel, a blue resist corresponding to the blue sub-pixel, and a green resist corresponding to the green sub-pixel.

[0341] In some embodiments, the base substrate further includes 2n first binding areas; the display panel further includes 2n driver chips; the orthographic projection of the driver chip on the first base substrate coincides with the first binding area;

[0342] In the second direction, the distance between the orthographic projections of adjacent driver chips on the first substrate is not equal to the distance between the orthographic projection of any driver chip located at the edge and the edge of the first substrate.

[0343] In a specific implementation, the driver chip is bound to the first binding electrode, the second binding electrode, and the dummy binding electrode of the first binding area. One fan-out line group corresponds to one first binding area, and one first binding area corresponds to one driver chip. That is, one fan-out line group corresponds to one driver chip, and one fan-out line group is electrically connected to one driver chip via the first binding electrode located in the first binding area.

[0344] In some embodiments, in the second direction, the distance between the orthographic projection of the 2n-j th driver chip on the first substrate and the orthographic projection of the 2n-j-1 th driver chip on the first substrate is not equal to the distance between the orthographic projection of the 2n-j th driver chip on the first substrate and the orthographic projection of the 2n-j+1 th driver chip on the first substrate; j is an integer less than 2n, and 2n-j-1 is an integer greater than or equal to 1.

[0345] In some embodiments, in the second direction, a distance between an orthographic projection of the 2nth driver chip on the first substrate and an orthographic projection of the 2n-1th driver chip on the first substrate is smaller than a distance between an orthographic projection of the 2n-1th driver chip on the first substrate and an orthographic projection of the 2n-2th driver chip on the first substrate.

[0346] In the second direction, the distance between the orthographic projection of the 2n-3th driver chip on the first substrate and the orthographic projection of the 2n-2th driver chip on the first substrate is smaller than the distance between the orthographic projection of the 2n-1th driver chip on the first substrate and the orthographic projection of the 2n-2th driver chip on the first substrate.

[0347] That is, in some embodiments, in n units, the distance in the second direction X between two adjacent driver chips among the multiple driver chips corresponding to each unit is smaller than the distance in the second direction X between two driver chips corresponding to two fan-out line groups of adjacent units.

[0348] In a specific implementation, taking m=4 as an example, the distance in the second direction X between the driver chip corresponding to the first first binding area and the driver chip corresponding to the second first binding area, and the distance in the second direction X between the driver chip corresponding to the third first binding area and the driver chip corresponding to the fourth first binding area are smaller than the distance in the second direction X between the driver chip corresponding to the second first binding area and the driver chip corresponding to the third first binding area.

[0349] An embodiment of the present disclosure provides a display device, as shown in FIG33 , which includes a display panel 10 provided in an embodiment of the present disclosure.

[0350] In some embodiments, the display device provided by the present disclosure may further include a backlight module 11 located on the light incident side of the array substrate 7, as shown in FIG33 . The backlight module may be a direct-lit backlight module or an edge-lit backlight module.

[0351] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0352] In some embodiments, the display device further includes: an FPC and a PCB; the FPC is bound to the second binding region of the array substrate and the PCB.

[0353] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the array substrate and display panel, and any repetitive details will not be repeated.

[0354] In summary, in the array substrate, display panel, and display device provided by the embodiments of the present disclosure, the fan-out lines in the mi-th subgroup include a first portion, a second portion, and a third portion, that is, the fan-out lines in the subgroup are divided into at least three sections, and any two adjacent sections extend in different directions. Compared to the two-section wiring of the fan-out lines in the related art, the length of the fan-out lines can be increased, the resistance of the fan-out lines can be increased, and the display effect can be prevented from being affected by large differences in fan-out lines between different subgroups. Furthermore, in the mi-th subgroup, the pattern of the first fan-out line is different from the pattern of the second fan-out line. Thus, the first and third portions of the first fan-out line on one side of the mi-th subgroup are located on different sides of the second portion in the second direction, that is, the three portions of the first fan-out line are arranged sequentially in the second direction, and the first and third portions of the second fan-out line on the other side of the mi-th subgroup are located on the same side of the second portion in the second direction, that is, the three portions of the second fan-out line form a groove area, which can increase the length of the fan-out line and increase the resistance of the fan-out line while saving wiring.

[0355] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0356] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, The array substrate includes: A first substrate; including: a first region, and a fan-out region located on one side of the first region in a first direction; At least one set of fan-out lines, located on one side of the first substrate in the fan-out region; each set of the fan-out lines includes m subgroups arranged along a second direction, and each subgroup includes a plurality of fan-out lines arranged along the second direction; the second direction intersects with the first direction; the fan-out lines of the (m - i)-th subgroup among the m subgroups include: a first portion, a second portion, and a third portion that are electrically connected in sequence; in the first direction, the first portion is located on a side of the second portion close to the first region, and the third portion is located on a side of the second portion away from the first region; the second portion extends along the first direction, and the extending directions of the first portion and the third portion intersect with both the first direction and the second direction; The (m - i)-th subgroup includes: a plurality of first fan-out lines, and a plurality of second fan-out lines located on one side of the plurality of first fan-out lines in the second direction; in the second direction, the first portion and the third portion of the first fan-out line are respectively located on both sides of the second portion of the first fan-out line, and the first portion and the third portion of the second fan-out line are located on the same side of the second portion of the second fan-out line in the second direction; where m is an integer greater than 2, and i is an integer greater than 0 and less than m - 1.

2. The array substrate according to claim 1, wherein, The extending direction of the first portion of the first fan-out line has a first angle with the positive direction of the second direction; The extending direction of the first portion of the second fan-out line has a second angle with the positive direction of the second direction; The extending direction of the third portion has a third angle with the positive direction of the second direction; The first angle and the third angle are greater than 0° and less than 90°, and the second angle is greater than 90° and less than 180°; or, the first angle and the third angle are greater than 90° and less than 180°, and the second angle is greater than 0° and less than 90°.

3. The array substrate according to claim 2, wherein, In the (m - i)-th subgroup, the number of the first fan-out lines is less than the number of the second fan-out lines; the total width of the second portions of the plurality of first fan-out lines is less than the total width of the second portions of the plurality of second fan-out lines.

4. The array substrate according to any one of claims 1 to 3, wherein, In the direction from the first fan-out line to the second fan-out line, the lengths of the first portions of the plurality of first fan-out lines gradually decrease in their extending directions, the lengths of the first portions of the plurality of second fan-out lines gradually increase in their extending directions, the lengths of the second portions of the plurality of first fan-out lines gradually increase in the first direction, the lengths of the second portions of the plurality of second fan-out lines gradually decrease in the first direction, and the lengths of the plurality of third portions are equal in their extending directions.

5. The array substrate according to any one of claims 1 to 4, wherein, The first fan-out line farthest from the second fan-out line is adjacent to the (m - i - 1)-th subgroup among the m subgroups, and the second fan-out line farthest from the first fan-out line is adjacent to the (m - i + 1)-th subgroup among the m subgroups.

6. The array substrate according to any one of claims 1 to 5, wherein, The pattern of at least a part of the second part on the first substrate includes a broken line extending along the first direction.

7. The array substrate according to any one of claims 1 to 6, wherein, The fan-out lines of the (m - i + 1)-th subgroup in the m subgroups include: a fourth part, a fifth part, and a sixth part that are electrically connected in sequence; In the first direction, the fourth part is located on the side of the fifth part closer to the first region, and the sixth part is located on the side of the fifth part farther from the first region; The fourth part and the sixth part extend along the first direction, and the extending direction of the fifth part intersects both the first direction and the second direction.

8. The array substrate according to claim 7, wherein, In the second direction, the fourth part is located on the side of the fifth part farther from the (m - i)-th subgroup, and the sixth part is located on the side of the fifth part closer to the (m - i)-th subgroup.

9. The array substrate according to claim 7 or 8, wherein The pattern of at least a part of the fourth part on the first substrate is a broken line extending along the first direction; and / or The pattern of at least a part of the sixth part on the first substrate is a broken line extending along the first direction.

10. The array substrate according to any one of claims 7 to 9, wherein, The extending direction of the fifth part of the (m - i + 1)-th subgroup has a fourth angle with the positive direction of the second direction; Both the fourth angle and the second angle are greater than 90° and less than 180°; or both the fourth angle and the second angle are greater than 0° and less than 90°.

11. The array substrate according to claim 10, wherein, Among two adjacent fan-out lines respectively located in the (m - i)-th subgroup and the (m - i + 1)-th subgroup, the first part and the fifth part are adjacent; in the first direction, at least a part of the fifth part is located on the side of the first part closest to the (m - i + 1)-th subgroup and farther from the first region.

12. The array substrate according to any one of claims 1 to 11, wherein, The (m - i - 1)-th subgroup in the m subgroups includes multiple third fan-out lines, and the third fan-out lines include: a bent part that turns to the (m - i)-th subgroup in the m subgroups; In the direction from the (m - i - 1)-th subgroup to the (m - i)-th subgroup, the lengths of multiple bent parts gradually increase.

13. The array substrate according to claim 12, wherein, The bent part includes: a seventh part, an eighth part, and a ninth part that are electrically connected in sequence; In the first direction, the seventh part is located on the side of the eighth part closer to the first region, and the ninth part is located on the side of the eighth part farther from the first region; in the second direction, the seventh part and the ninth part are located on the same side of the eighth part; The seventh part and the ninth part intersect both the first direction and the second direction, and the eighth part extends along the first direction.

14. The array substrate according to claim 13, wherein, The third parts of multiple fan-out lines in the (m - i)-th subgroup are parallel to each other; Multiple first parts included in multiple first fan-out lines are parallel to each other; Multiple first parts included in multiple second fan-out lines are parallel to each other; The fan-out lines of the (m - i + 1)-th subgroup include a fifth part, and multiple The fifth parts of the fan-out lines in the (m - i + 1)-th subgroup are parallel to each other; In the (m - i - 1)-th subgroup, multiple seventh parts are parallel to each other, and multiple ninth parts are parallel to each other.

15. The array substrate according to claim 13 or 14, wherein, In the first direction, the lengths of the plurality of eighth portions included in the plurality of third fan-out lines are substantially equal; In the direction from the (m - i - 1)-th subgroup to the (m - i)-th subgroup, the lengths of the plurality of seventh portions included in the plurality of third fan-out lines gradually increase in their extending directions, and the lengths of the plurality of ninth portions included in the plurality of third fan-out lines gradually increase in their extending directions.

16. The array substrate according to any one of claims 13 to 15, wherein, The extending direction of the seventh portion has a fifth angle with the positive direction of the second direction; Both the fifth angle and the first angle are greater than 90° and less than 180°; or both the fifth angle and the first angle are greater than 0° and less than 90°.

17. The array substrate according to claim 16, wherein, The first substrate further includes: a first bonding region located on the side of the fan-out region away from the first region in the first direction; The array substrate further includes: a plurality of first bonding electrodes and dummy bonding electrodes located in the first bonding region; the fan-out line is electrically connected to the first bonding electrode at its end away from the first region; In the second direction, the dummy bonding electrode is included between the first bonding electrodes respectively electrically connected to two adjacent fan-out lines located in the (m - i - 1)-th subgroup and the (m - i)-th subgroup; In the first direction, at least part of the bent portion is located between the dummy bonding electrode and the first portion closest to the (m - i - 1)-th subgroup.

18. The array substrate according to any one of claims 12 to 17, wherein, The third fan-out line further includes: a tenth portion located on the side of the bent portion facing the first region in the first direction, an eleventh portion located on the side of the bent portion facing away from the first region in the first direction, and a twelfth portion located on the side of the tenth portion facing the first region in the first direction; the tenth portion and the eleventh portion extend along the first direction, and the twelfth portion is parallel to the first portion.

19. The array substrate according to claim 18, wherein, The pattern of the orthographic projection of at least part of the fan-out lines in the (m - i - 1)-th subgroup on the first substrate is a broken line extending along the first direction.

20. The array substrate according to any one of claims 12 to 19, wherein, In at least part of the subgroups, the plurality of fan-out lines at at least one edge of the subgroup are dummy fan-out lines; At least part of the dummy fan-out lines include a disconnection region.

21. The array substrate according to claim 20, wherein, At least one edge of at least part of the subgroups includes two dummy fan-out lines, and the two dummy fan-out lines are respectively located in the first conductive layer and the second conductive layer.

22. The array substrate according to claim 20 or 21, wherein, In the dummy fan-out lines of the (m - i)-th subgroup, the disconnection region is located in the second portion; The bent portion includes an eighth portion; in the dummy fan-out lines of the (m - i - 1)-th subgroup, the disconnection region is located in the eighth portion.

23. The array substrate according to any one of claims 10 to 22, wherein, The angle between the extending direction of the plurality of fan-out lines in the first subgroup and the positive direction of the first direction is a sixth angle; The sixth angle is greater than 90° and less than 180°, the fourth angle is greater than 0° and less than 90°, or the sixth angle is greater than 0° and less than 90°, and the fourth angle is greater than 90° and less than 180°.

24. The array substrate according to any one of claims 1 to 23, wherein, m = 4, i = 1; Among the four subgroups, the number of the fan-out lines included in the first subgroup and the second subgroup is equal to the number of the fan-out lines included in the third subgroup and the fourth subgroup; The number of the fan-out lines included in the first subgroup is greater than the number of the fan-out lines included in the second subgroup; The number of the fan-out lines included in the third subgroup is greater than the number of the fan-out lines included in the fourth subgroup.

25. The array substrate according to any one of claims 1 to 24, wherein, The array substrate includes 2n groups of the fan-out lines arranged along the second direction; wherein, n is a positive integer; The 2nth group of the fan-out lines is symmetrically arranged with the (2n - 1)th group of the fan-out lines.

26. The array substrate according to claim 25, wherein, The substrate further includes 2n first bonding regions; In the second direction, the distance between adjacent first bonding regions is not equal to the distance between any first bonding region located at the edge and the edge of the first substrate.

27. The array substrate according to claim 26, wherein, In the second direction, the distance between the 2nth first bonding region and the (2n - 1)th first bonding region is less than the distance between the (2n - 1)th first bonding region and the (2n - 2)th first bonding region; In the second direction, the distance between the (2n - 2)th first bonding region and the (2n - 3)th first bonding region is less than the distance between the (2n - 1)th first bonding region and the (2n - 2)th first bonding region.

28. The array substrate according to any one of claims 1 to 27, wherein, Any two adjacent fan-out lines are located in different conductive layers.

29. The array substrate according to any one of claims 1 to 28, wherein, The array substrate further includes: A plurality of dummy structures located in the fan-out area; the orthographic projection of the dummy structure on the substrate is located in the area between the orthographic projections of adjacent subgroups on the substrate, and / or, the orthographic projection of the dummy structure on the substrate is located within the orthographic projection of the subgroup at the edge on the side away from the other subgroups on the substrate.

30. A display panel, wherein, The display panel includes: The array substrate according to any one of claims 1 to 29; A counter substrate disposed opposite to the array substrate; A liquid crystal layer located between the array substrate and the counter substrate.

31. The display panel according to claim 30, wherein, The substrate further includes 2n first bonding regions; the display panel further includes 2n driving chips; the orthographic projection of the driving chip on the first substrate coincides with the first bonding region; In the second direction, the distance between the orthographic projections of adjacent driving chips on the first substrate is not equal to the distance between the orthographic projection of any driving chip located at the edge on the first substrate and the edge of the first substrate.

32. The display panel according to claim 31, wherein, In the second direction, the distance between the orthographic projection of the 2nth driving chip on the first substrate and the orthographic projection of the (2n - 1)th driving chip on the first substrate is less than the distance between the orthographic projection of the (2n - 1)th driving chip on the first substrate and the orthographic projection of the (2n - 2)th driving chip on the first substrate; In the second direction, the distance between the orthographic projection of the (2n - 3)-th driving chip on the first substrate and the orthographic projection of the (2n - 2)-th driving chip on the first substrate is less than the distance between the orthographic projection of the (2n - 1)-th driving chip on the first substrate and the orthographic projection of the (2n - 2)-th driving chip on the first substrate.

33. A display device, wherein, The display device includes the display panel according to any one of claims 30 to 32.

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