Thin film transistor memory array based on photonic crystal isolation dielectric, and manufacturing method

Abstract

A thin film transistor memory array based on a photonic crystal isolation dielectric, the thin film transistor memory array comprising: memory cells, which are arranged in rows and columns; and write word lines, write bit lines, read bit lines and ground lines, which connect the memory cells, wherein lines in a row direction and lines in a column direction are orthogonal; and a read transistor and a write transistor constituting a memory cell are both thin film transistors, isolation capacitors are provided in intersection areas of the lines in the row direction and the lines in the column direction, and isolation dielectrics in the isolation capacitors are photonic crystals. In the thin film transistor memory array, the photonic crystals are used to reduce parasitic capacitances of bit lines and word lines of a memory, so that the density of the memory array is improved, the read-write speed of the memory array is increased, and read-write disturbance is reduced.

Description

Thin-film transistor memory array based on photonic crystal isolation medium and its fabrication Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a thin film transistor memory array based on a photonic crystal isolation medium, a manufacturing method thereof, and related electronic equipment. Background Art

[0002] Thin film transistors (TFTs) have been widely used in various devices such as memory due to their advantages such as ultra-low leakage current, low temperature growth, high mobility, and large-area growth.

[0003] The existing thin-film transistor structure is shown in Figure 1. A transistor channel layer 101 is located above the substrate, with a source terminal 103 and a drain terminal 102 located on the channel layer 101. A gate dielectric layer 104 is located between the source and drain, and a gate 105 is located on the gate dielectric layer 104. The structure of a thin-film transistor-based memory cell is shown in Figure 2. It includes a read transistor Tr2 and a write transistor Tr1. The gate of the write transistor Tr1 is connected to the write word line WWL, and the source of the write transistor Tr1 is connected to the write bit line WBL. The drain of the read transistor Tr2 is connected to the read bit line RBL, and the source of the read transistor Tr2 is connected to the ground line GND. The drain of the write transistor Tr1 is electrically connected to the gate of the read transistor Tr2.

[0004] Because existing thin-film transistor memories still use a cell structure and have low integration density, they must be arranged to form a memory array. There is still no solution to isolate and reduce the parasitic capacitance of the write word lines, write bit lines, read bit lines, and ground lines introduced into the memory array.

[0005] Due to their unique electromagnetic and optical properties, photonic crystals possess near-zero dielectric constants ε and permeability μ. Consequently, photonic crystal capacitors have near-zero capacitance, effectively reducing isolation parasitic capacitance and offering great potential for improving memory array performance. Summary of the Invention

[0006] The purpose of the present invention is to provide a thin film transistor memory array and a manufacturing method, and an electronic device, which can reduce the parasitic capacitance of the memory array, increase the read and write speed of the memory array, and enhance the data retention characteristics of the memory.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A thin-film transistor memory array comprises memory cells arranged in rows and columns, and write word lines, write bit lines, read bit lines, and ground lines connecting the memory cells, with the lines in the row and column directions being orthogonal. The memory cells comprise read transistors and write transistors, both of which are thin-film transistors. The array is characterized in that an isolation capacitor is provided at the intersection of the write word lines, write bit lines, read bit lines, and ground lines. The isolation capacitor comprises a bottom electrode, an isolation dielectric, and a top electrode. The isolation dielectric is located between the bottom electrode and the top electrode, separating the top and bottom electrodes. The top electrode is connected to a line located on the top layer (which may be a write word line, a write bit line, a read bit line, or a ground line), and the bottom electrode is connected to a line located on the bottom layer (which may be a write word line, a write bit line, a read bit line, or a ground line). The isolation dielectric is a photonic crystal.

[0009] The photonic crystal can be a two-dimensional dielectric photonic crystal at a band-edge frequency, a two-dimensional dielectric photonic crystal at a Dirac-like point frequency (equivalent to a double-zero material), a three-dimensional dielectric photonic crystal in a bound state in a continuous spectrum, optical and infrared materials near the plasma frequency, resonant electromagnetic metamaterials, etc.

[0010] For the write transistor and read transistor that constitute the memory cell, their channel layer can be an oxide semiconductor material such as IGZO, ITO, IZO, ITWO, InO, ZnO, etc.; the materials of the gate, source, and drain can be metallic materials such as Au, Pt, Mo, Pd, Ti, Ni, TiN, etc.

[0011] The materials for the write word line, write bit line, read bit line, ground line, and the top and bottom electrodes of the isolation capacitor of the memory array can be metallic materials such as Au, Pt, Mo, Pd, Ti, Ni, and TiN. Figure 3 shows a memory array with 2T0C memory cells arranged in rows and columns. The array electrically connects the memory cells in each row through the write word line WWL and the read bit line RBL, and electrically connects the memory cells in each column through the write bit line WBL and the ground line GND. In the memory array, the gates of the write transistors in the multiple memory cells arranged in sequence along the rows are electrically connected to the same write word line WWL; the sources of the write transistors in the multiple memory cells arranged in sequence along the columns are electrically connected to the same write bit line WBL; the drains of the read transistors in the multiple memory cells arranged in sequence along the rows are electrically connected to the same read bit line RBL; and the sources of the read transistors in the multiple memory cells arranged in sequence along the columns are electrically connected to the same ground line GND. At the read / write transistor interconnect layer, electrical connections are made between the drain of the write transistor and the gate of the read transistor of each memory cell.

[0012] The lines in the row and column directions of the memory array are orthogonal, and the intersection area is an isolation capacitor structure, as shown in Figure 4, where the isolation medium located between the bottom electrode and the top electrode is a photonic crystal with a dielectric constant of 0 to reduce the isolation parasitic capacitance.

[0013] The present invention also provides a method for preparing the above-mentioned thin film transistor memory array, comprising the following steps:

[0014] 1) Complete the gate patterning of the thin film transistor on the substrate;

[0015] 2) Deposition of gate dielectric materials for thin film transistors;

[0016] 3) Depositing oxide semiconductor channel material and patterning the channel;

[0017] 4) Depositing the source and drain materials of the thin film transistor and patterning them;

[0018] 5) Photolithography defines the interconnection lines of the read transistor and the write transistor, the write bit line, the write word line, the read bit line, the ground line and the interconnection area between them, and etches the gate dielectric material;

[0019] 6) preparing the underlying interconnect structure, including the wires located at the bottom layer and the electrodes connecting them to the transistors;

[0020] 7) Preparation of photonic crystal isolation dielectric layer;

[0021] 8) Prepare the top interconnect structure, including the wires on the top layer and their electrodes connecting the transistors.

[0022] The lines located at the bottom layer are lines connecting the memory cells in the horizontal or column direction, and correspondingly, the lines located at the top layer are lines connecting the memory cells in the column or horizontal direction; the lines in the horizontal and column directions are isolated by a photonic crystal isolation dielectric layer in the intersection area.

[0023] The thin film transistor memory array based on the photonic crystal isolation medium of the present invention can be applied to electronic devices in the fields of memory, display, communication equipment, etc.

[0024] Compared with the prior art, the advantages of the present invention are mainly reflected in that it significantly reduces the parasitic capacitance of the memory array, and has obvious advantages in improving memory density, increasing read and write speed, and reducing read and write interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of the structure of a thin film transistor, wherein 101 is a channel layer, 102 is a drain terminal, 103 is a source terminal, 104 is a gate dielectric layer, and 105 is a gate.

[0026] FIG2 is a schematic diagram of the structure of a 2T0C memory unit based on thin film transistors, where Tr1 is a write transistor and Tr2 is a read transistor.

[0027] FIG3 is a schematic diagram of the structure of a 2T0C memory array based on thin film transistors.

[0028] FIG4 is a schematic diagram showing a method of reducing parasitic capacitance by inserting a photonic crystal as an isolation layer, wherein 106 is a photonic crystal isolation medium, 107 is a bottom electrode, and 108 is a top electrode. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below by way of embodiments in conjunction with the accompanying drawings. It should be understood that the embodiments described herein are only intended to explain the present invention and are not intended to limit the present invention.

[0030] As shown in FIG3 , the thin-film transistor memory array is composed of memory cells arranged in n rows by n columns. The memory cells in each row are electrically connected via write word lines WWL1 to WWLn and read bit lines RBL1 to RBLn, while the memory cells in each column are electrically connected via write bit lines WBL1 to WBLn and ground lines GND1 to GNDn. The memory cell includes a read transistor and a write transistor, both of which are thin-film transistors. In the read / write transistor interconnect layer, the drain of the write transistor of each memory cell is electrically connected to the gate of the read transistor. A write word line WWL is located between the gates of a row of write transistors in the array, enabling electrical connection between the gates of different write transistors in the same row. A write bit line WBL is located between the sources of a column of write transistors in the array, enabling electrical connection between the sources of different write transistors in the same row. A read bit line RBL is located between the drains of a row of read transistors in the array, enabling electrical connection between the drains of different read transistors in the same row. The ground line GND is located between the sources of a column of read transistors in the array, enabling electrical connection between the sources of different read transistors in the same row. Isolation capacitors are provided at the intersections between the write word line, write bit line, read bit line, and ground line. As shown in Figure 4, the isolation capacitor includes a bottom electrode 107, a top electrode 108, and a photonic crystal isolation medium 106 located therebetween, wherein the bottom electrode is located at the bottom layer of the intersection area between the write word line, the write bit line, the read bit line, and the ground line, and the top electrode is located at the top layer of the intersection area between the write word line, the write bit line, the read bit line, and the ground line, and the photonic crystal isolation medium realizes electrical isolation between the bottom electrode and the top electrode.

[0031] The steps of preparing the thin film transistor memory array include:

[0032] 1) On substrates such as Si, Ge, SiC, and diamond, electron beam photoresist is spin-coated and exposed to form a thin film transistor gate pattern; after development, a metal film is deposited by thermal evaporation, electron beam evaporation, and other methods, and then the thin film transistor gate patterning is completed through dry etching, wet etching, and stripping processes.

[0033] 2) Depositing thin film transistor gate dielectric materials through methods such as atomic layer deposition.

[0034] 3) Depositing oxide semiconductor channel materials by reactive magnetron sputtering, atomic layer deposition, etc.

[0035] 4) Realize the patterning of channel materials.

[0036] 5) Deposit the source and drain materials of the thin film transistor and pattern them.

[0037] 6) Photolithographically define the interconnection lines of the read transistor and the write transistor, the write bit line, the write word line, the read bit line, the ground line, and the interconnection area therebetween by the method described in step 1), and etch the gate dielectric material by dry etching, wet etching, or other methods.

[0038] 7) Patterning of the write word line and the read bit line and their corresponding metal electrodes is achieved by the method described in step 1).

[0039] 8) Prepare photonic crystal isolation dielectric layers by spin coating, atomic layer deposition, physical deposition, vapor phase reaction deposition, etc.

[0040] 9) Implementing the method described in step 1) to pattern the write bit line and ground line as well as the corresponding metal electrodes.

[0041] The above steps 7) and 9) can be interchanged, and the effect achieved is not related to the order.

[0042] Those skilled in the art should understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A thin film transistor memory array includes memory cells arranged in rows and columns, and write word lines, write bit lines, read bit lines, and ground lines connecting the respective memory cells, with the lines in the row direction and the column direction being orthogonal; wherein, The memory cell includes a read transistor and a write transistor, both of which are thin film transistors. It is characterized in that an isolation capacitor is provided in the cross - region of the write word line, write bit line, read bit line, and ground line. The isolation capacitor includes a bottom electrode, an isolation dielectric, and a top electrode. The isolation dielectric is located between the bottom electrode and the top electrode. The top electrode is connected to the line located at the top layer, and the bottom electrode is connected to the line located at the bottom layer; the isolation dielectric is a photonic crystal.

2. The thin film transistor memory array according to claim 1, characterized in that, The dielectric constant of the photonic crystal is 0.

3. The thin film transistor memory array according to claim 1, characterized in that, The photonic crystal is a two - dimensional dielectric photonic crystal at the edge frequency, a two - dimensional dielectric photonic crystal at the Dirac - like point frequency, a three - dimensional dielectric photonic crystal in the bound state in the continuous spectrum, an optical and infrared material near the plasma frequency, or a resonant electromagnetic metamaterial.

4. The thin film transistor memory array according to claim 1, wherein, The channel layers of the write transistor and the read transistor are made of an oxide semiconductor material.

5. The thin film transistor memory array according to claim 4, wherein, The oxide semiconductor material is selected from IGZO, ITO, IZO, ITWO, InO, ZnO.

6. The thin film transistor memory array according to claim 1, wherein The gate, source, and drain of the write transistor and the read transistor, the top electrode and the bottom electrode of the isolation capacitor, and the materials of the write word line, write bit line, read bit line, and ground line are selected from Au, Pt, Mo, Pd, Ti, Ni, TiN.

7. The thin film transistor memory array according to claim 1, wherein Each row of memory cells is electrically connected through the write word line and the read bit line, and each column of memory cells is electrically connected through the write bit line and the ground line.

8. The thin film transistor memory array according to claim 7, wherein The memory cell consists of a read transistor and a write transistor; the gates of the write transistors in multiple memory cells arranged in sequence along a row are electrically connected to the same write word line; the sources of the write transistors in multiple memory cells arranged in sequence along a column are electrically connected to the same write bit line; the drains of the read transistors in multiple memory cells arranged in sequence along a row are electrically connected to the same read bit line; the sources of the read transistors in multiple memory cells arranged in sequence along a column are electrically connected to the same ground line; the gates of the read transistors and the drains of the write transistors in each memory cell are electrically connected.

9. The method for preparing the thin film transistor memory array according to any one of claims 1 - 8, comprising the following steps: 1) Complete the patterning of the gate of the thin film transistor on the substrate; 2) Deposit the gate dielectric material of the thin film transistor; 3) Deposit the oxide semiconductor channel material and achieve channel patterning; 4) Deposit the source and drain materials of the thin film transistor and pattern them; 5) Define the interconnections of the read transistor and the write transistor, the write bit line, the write word line, the read bit line, the ground line, and their interconnection regions by photolithography, and etch the gate dielectric material; 6) Prepare the bottom - layer interconnection structure, including the lines located at the bottom layer and the electrodes connecting them to the transistors; 7) Prepare the photonic crystal isolation dielectric layer; 8) Prepare the top - layer interconnection structure, including the lines located at the top layer and the electrodes connecting them to the transistors.

10. The preparation method according to claim 9, characterized in that, The lines located at the bottom layer are the lines in the horizontal or column direction connecting each memory cell. Correspondingly, the lines located at the top layer are the lines in the column or horizontal direction connecting each memory cell; the lines in the horizontal and column directions are isolated by the photonic crystal isolation dielectric layer in the cross - region.

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