Trench-type lateral MOS device and preparation method therefor

Abstract

The present application provides a trench-type lateral MOS device and a preparation method therefor. The trench-type lateral MOS device comprises a semiconductor structure (1), a trench structure (2), a source region (13), an interlayer dielectric layer (3), source / drain / gate electrode contact holes (31 / 32 / 33), and source / drain / gate electrodes (4 / 5 / 6). The semiconductor structure (1) comprises a drift region (11) and a body region (12); the trench structure (2) comprises a trench (21), a gate dielectric layer (22) and a gate conductive layer (23), at least one drain lead-out region (14) being defined in the drift region (11) at the bottom of the trench, a projection area of the drain lead-out region (14) onto a bottom surface of the trench being spaced apart from a sidewall of the trench, and the gate conductive layer (23) filling the area in the trench apart from the area directly above the drain lead-out region (14); the source region (13) is located at an upper surface layer of the body region (12); the interlayer dielectric layer (3) covers an upper surface of the semiconductor structure (1), and fills the trench (21); the bottoms of the source / drain / gate electrode contact holes (31 / 32 / 33) expose the source region (13), the drift region (11) and the gate conductive layer (23), respectively, and the drain contact hole (32) penetrates the interlayer dielectric layer (3) above the drain lead-out region (14); the source / drain / gate electrodes (4 / 5 / 6) fill the source, drain, and gate electrode contact holes (31 / 32 / 33), respectively.

Description

Trench-type lateral MOS device and its manufacturing method

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202311802949.9, filed on December 25, 2023, entitled “A Trench-Type Lateral MOS Device and Its Preparation Method,” the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a trench-type lateral MOS device and a method for manufacturing the same. Background Art

[0004] Power metal oxide semiconductor field effect transistors (MOSFETs, MOS for short) have the advantages of fast switching speed and low power loss and are widely used in the field of consumer electronics. In recent years, with the development of mid-to-high-end fields such as communications and lithium battery protection, the functionality and integration requirements of MOSFETs have become increasingly higher. For analog circuits or digital circuits with higher integration, the use of Bipolar-CMOS-DMOS (BCD) process can realize the manufacture and integration of bipolar devices, complementary metal oxide semiconductor (CMOS) devices, and laterally diffused metal oxide semiconductor (LDMOS) devices. However, for discrete power devices, especially vertical power devices such as vertical double diffused metal oxide semiconductor (VDMOS), since their reverse blocking voltage is designed on the back side of the chip, it is difficult to achieve integration and interconnection of different devices, which will lead to certain limitations in some application fields that require the integration of VDMOS.

[0005] Currently, conventional medium- and low-voltage VDMOS devices are mostly trench-type designs. The vertical channel design significantly reduces the device's cell pitch and lowers the device's on-resistance. A conventional trench-type VDMOS device, as shown in Figure 1, includes a substrate 01, a drift region 011, a body region 012, a source region 013, a trench structure 02, a trench 021, a gate oxide layer 022, gate polysilicon 023, an interlayer dielectric layer 03, a source contact hole 031, a source electrode 04, and a drain electrode 05. During chip operation, the drain voltage is applied to the back side of the device. This structure makes the device difficult to use in applications requiring high device integration, such as lithium battery protection. Consequently, the device's application range is limited. Furthermore, because the current in the device flows from the drain to the source, located opposite the drain, the device's on-resistance is relatively high.

[0006] Therefore, there is an urgent need to find a trench lateral MOS device that can expand the application range of the trench MOS device and reduce the on-resistance of the device.

[0007] Summary of the Invention

[0008] The purpose of this application is to provide a trench-type lateral MOS device and a method for manufacturing the same.

[0009] The present application provides a trench-type lateral MOS device, comprising:

[0010] A semiconductor structure comprising a drift region having a first conductivity type and a body region having a second conductivity type stacked in sequence;

[0011] A trench structure comprising a trench, a gate dielectric layer, and a gate conductive layer, wherein the trench penetrates the body region and has a bottom surface extending into the drift region, at least one drain lead-out region is defined in the drift region below the bottom of the trench, the drain lead-out region being spaced a predetermined distance from the sidewalls of the trench in a projection area of ​​the trench bottom surface, the gate dielectric layer covering the inner wall and bottom surface of the trench except for a region directly above the drain lead-out region, and the gate conductive layer filling the region of the trench except for a region directly above the drain lead-out region;

[0012] a source region of the first conductivity type, located on an upper surface of the body region and close to a sidewall of the trench and adjacent to two sidewalls of the trench that are opposite to each other in the X direction, where the X direction is a direction parallel to the bottom surface of the trench;

[0013] an interlayer dielectric layer, covering the upper surface of the semiconductor structure and filling the remaining area of ​​the trench above the drain lead-out region;

[0014] a source contact hole, a drain contact hole, and a gate contact hole, wherein the source contact hole penetrates the interlayer dielectric layer and at least partially exposes the source region at its bottom; the drain contact hole penetrates the interlayer dielectric layer directly above the drain lead-out region and at least partially exposes the drift region at its bottom; a vertical projection of the drain contact hole on the drain lead-out region is spaced a preset distance from an edge of the drain lead-out region; and the gate contact hole penetrates the interlayer dielectric layer and at its bottom exposes the gate conductive layer;

[0015] A source, a drain and a gate, wherein the source fills the source contact hole, the drain fills the drain contact hole, and the gate fills the gate contact hole.

[0016] Optionally, the drain lead-out region has a size in the Y direction that is smaller than the size of the trench in the Y direction, where the Y direction refers to a vertical direction from the opening of the trench to the bottom of the trench, and is perpendicular to the X direction.

[0017] Optionally, the drain lead-out region has the same size in the Y direction as the trench in the Y direction, where the Y direction refers to a vertical direction from the opening of the trench to the bottom of the trench, and is perpendicular to the X direction.

[0018] Optionally, a source contact region of the second conductivity type is further provided on the upper surface layer of the body region, and the source contact region is exposed at the bottom of the source contact hole.

[0019] Optionally, a drain contact region with the first conductivity type is further provided in the drain lead-out region, and the drain contact region is exposed at the bottom surface of the drain contact hole.

[0020] Optionally, the doping concentration of the drain contact region is greater than the doping concentration of the drift region, so that an ohmic contact is formed between the drain and the drain contact region.

[0021] Optionally, a substrate with a preset thickness is further provided in the semiconductor structure, and the drift region is located on the upper surface of the substrate.

[0022] Optionally, the doping type of the substrate is the same as the doping type of the drift region, the bottom surface of the drain contact hole exposes the substrate, and an ohmic contact is formed between the drain and the substrate.

[0023] Optionally, the doping type of the substrate is opposite to the doping type of the drift region.

[0024] Optionally, the doping concentration of the substrate is greater than the doping concentration of the drift region, so that an ohmic contact is formed between the drain and the substrate.

[0025] The present application also provides a method for preparing a trench-type lateral MOS device, comprising the following steps:

[0026] A semiconductor structure is provided, comprising a drift region having a first conductivity type and a body region having a second conductivity type stacked in sequence;

[0027] forming a trench structure including a trench, a gate dielectric layer, and a gate conductive layer, wherein the trench penetrates the body region and has a bottom surface extending into the drift region, wherein the drift region below the bottom of the trench defines at least one drain lead-out region, wherein a projection area of ​​the at least one drain lead-out region on the bottom surface of the trench is spaced a predetermined distance from a sidewall of the trench, the gate dielectric layer covers an inner wall and bottom surface of the trench except for a region directly above the drain lead-out region, and the gate conductive layer fills a region of the trench except for a region directly above the drain lead-out region;

[0028] forming a source region of the first conductivity type located on an upper surface of the body region, the source region being adjacent to two sidewalls of the trench that are disposed opposite to each other in the X direction, where the X direction is a direction parallel to the bottom surface of the trench;

[0029] forming an interlayer dielectric layer covering the upper surface of the semiconductor structure and filling the remaining area of ​​the trench above the drain lead-out region;

[0030] forming a source contact hole penetrating the interlayer dielectric layer and exposing the source region at its bottom, forming a drain contact hole penetrating the interlayer dielectric layer directly above the drain lead-out region and exposing at least a portion of the drift region at its bottom, and forming a gate contact hole penetrating the interlayer dielectric layer and exposing the gate conductive layer at its bottom, wherein a vertical projection area of ​​the drain contact hole on the drain lead-out region is spaced a predetermined distance from an edge of the drain lead-out region;

[0031] A source electrode is formed to fill the source contact hole, a drain electrode is formed to fill the drain contact hole, and a gate electrode is formed to fill the gate contact hole.

[0032] Optionally, the step of forming the trench structure includes:

[0033] forming a patterned shielding layer on the upper surface of the semiconductor structure, and forming the trench based on the patterned shielding layer;

[0034] forming a gate dielectric material layer covering the upper surface of the semiconductor structure and the inner wall and bottom surface of the trench, and forming a gate conductive material layer of a predetermined thickness on the upper surface of the gate dielectric material layer, wherein the predetermined thickness is no greater than the distance between the drain lead-out region and the inner wall of the trench;

[0035] The gate conductive material layer directly above the semiconductor structure and the drain lead-out region is removed to obtain the gate conductive layer, and the gate dielectric material layer directly above the drain lead-out region is removed to obtain the gate dielectric layer, thereby obtaining the trench structure consisting of the trench, the gate dielectric layer and the gate conductive layer.

[0036] Optionally, the drain lead-out region has a size in the Y direction that is smaller than the size of the trench in the Y direction, where the Y direction refers to a vertical direction from the opening of the trench to the bottom of the trench, and is perpendicular to the X direction.

[0037] Optionally, the drain lead-out region has the same size in the Y direction as the trench in the Y direction, where the Y direction refers to a vertical direction from the opening of the trench to the bottom of the trench, and is perpendicular to the X direction.

[0038] Optionally, the method further includes: performing ion implantation on a bottom of the source contact hole based on the source contact hole to form a source contact region.

[0039] Optionally, after forming the drain contact hole and before forming the drain, the method further includes: forming a drain contact region having a first conductivity type at the bottom of the drain contact hole, the doping concentration of the drain contact region being greater than the doping concentration of the drift region, and an ohmic contact being formed between the drain contact region and the drain.

[0040] As described above, the trench-type lateral MOS device and its preparation method of the present application improve the structure of the device, define at least one drain lead-out region in the drift region below the bottom of the trench, the gate dielectric layer covers the inner wall and bottom surface of the trench except the area directly above the drain lead-out region, the gate conductive layer fills the space of the trench except the area directly above the drain lead-out region, and then uses the interlayer dielectric layer to fill the remaining unfilled area in the trench, and the interlayer dielectric layer covers the upper surface of the semiconductor structure, and a dielectric layer is provided in the interlayer dielectric layer directly above the drain lead-out region to penetrate the interlayer dielectric layer. The bottom surface extends to the drain contact hole in the drift region to lead the drain of the device to the surface where the source of the device is located, thereby reducing the thickness of the device. At the same time, the current in the device is transmitted along the body region and the drift region on the surface of the groove between the source region and the drain, thereby improving the current transmission path in the device and reducing the on-resistance of the device. Since the drain and the source are located on the same surface of the device, the integration and interconnection of the device in the circuit are improved, making the device easy to integrate and interconnect with other devices, expanding its application in highly integrated and complexly interconnected fields such as lithium battery protection, and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram of the cross-sectional structure of a VDMOS device.

[0042] FIG2 is a schematic structural diagram of a cross-section of a trench-type lateral MOS device including a source and a drain according to an embodiment of the present application.

[0043] FIG3 is a schematic structural diagram of a cross-section of a gate of a trench-type lateral MOS device according to an embodiment of the present application.

[0044] FIG4 is a current distribution diagram of a trench-type lateral MOS device according to an embodiment of the present application.

[0045] FIG5 is a process flow chart of a method for fabricating a trench-type lateral MOS device according to an embodiment of the present application.

[0046] FIG6 is a schematic diagram of a cross-sectional structure of a trench-type lateral MOS device after trenches are formed according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0047] FIG. 7 is a schematic diagram of a top surface structure after trenches are formed in a method for preparing a trench-type lateral MOS device according to an embodiment of the present application.

[0048] FIG8 is a schematic diagram of another top surface structure after forming a trench in a method for preparing a trench-type lateral MOS device according to an embodiment of the present application.

[0049] FIG9 is a schematic diagram of a cross-sectional structure of a trench-type lateral MOS device after forming a gate dielectric material layer according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0050] FIG10 is a schematic diagram of the cross-sectional structure of a trench-type lateral MOS device after forming a gate conductive material layer according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0051] FIG11 is a schematic diagram of a cross-sectional structure of a trench-type lateral MOS device after forming a trench structure according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0052] FIG12 is a schematic diagram of the cross-sectional structure of a trench-type lateral MOS device after forming a source region according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0053] FIG13 is a schematic diagram of the cross-sectional structure of a trench-type lateral MOS device after forming an interlayer dielectric layer according to a method for preparing the trench-type lateral MOS device according to an embodiment of the present application.

[0054] Explanation of the accompanying symbols: 01, substrate; 011, drift region; 012, body region; 013, source region; 02, trench structure; 021, trench; 022, gate oxide layer; 023, gate polysilicon; 03, interlayer dielectric layer; 031, source contact hole; 04, source; 05, drain; 1, semiconductor structure; 10, substrate; 11, drift region; 12, body region; 13, source region; 14, drain lead-out region; 15, source contact region; 16, drain contact region; 2, trench structure; 21, trench; 22, gate dielectric layer; 221, gate dielectric material layer; 23, gate conductive layer; 231, gate conductive material layer; 3, interlayer dielectric layer; 31, source contact hole; 32, drain contact hole; 33, gate contact hole; 4, source; 5, drain; 6, gate. DETAILED DESCRIPTION

[0055] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0056] Please refer to Figures 2 to 13. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present application. Therefore, the figures only show components relevant to the present application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed as needed, and the component layout may also be more complex.

[0057] Example 1

[0058] This embodiment provides a trench-type lateral MOS device. As shown in FIG2 and FIG3 , they are schematic structural diagrams of a cross-section of the source and drain electrodes of the trench-type lateral MOS device, and a schematic structural diagram of a cross-section of the gate electrode of the trench-type lateral MOS device. The MOS device includes a semiconductor structure 1, a trench structure 2, a source region 13 of a first conductivity type, an interlayer dielectric layer 3, a source contact hole 31, a drain contact hole 32, a gate contact hole 33, a source electrode 4, a drain electrode 5, and a gate electrode 6. The semiconductor structure includes a drift region 11 of a first conductivity type and a body region 12 of a second conductivity type stacked in sequence. The trench structure 2 includes a trench 21, a gate dielectric layer 22, and a gate conductive layer 23. The trench 21 penetrates the body region 12 and extends its bottom surface into the drift region. At least one drain lead-out region 14 is defined in the drift region 11 below the bottom of the trench 21. The projected area of ​​the drain lead-out region 14 on the bottom surface of the trench 21 is spaced a predetermined distance from the sidewalls of the trench 21. The gate dielectric layer 22 covers the inner walls and bottom surface of the trench 21, excluding the area directly above the drain lead-out region 14. The gate conductive layer 23 fills the area of ​​the trench 21, excluding the area directly above the drain lead-out region 14. The source region 13 is located on the upper surface of the body region 12, adjacent to the sidewalls of the trench 21 and two opposing sidewalls of the trench 21 in the X direction. The interlayer dielectric layer 3 covers the upper surface of the semiconductor structure 1 and fills the remaining area of ​​the trench 21 above the drain lead-out region 14. The source contact hole 31 penetrates the interlayer dielectric layer 3, with at least a portion of the source region 13 exposed at its bottom. The drain contact hole 32 penetrates the interlayer dielectric layer 3 directly above the drain lead-out region 14, with at least a portion of the drift region 11 exposed at its bottom. The vertical projection of the drain contact hole 32 on the drain lead-out region 14 is spaced a predetermined distance from the edge of the drain lead-out region 14. The gate contact hole 33 penetrates the interlayer dielectric layer 3, with the gate conductive layer 23 exposed at its bottom. The source electrode 4 fills the source contact hole 31 , the drain electrode 5 fills the drain contact hole 32 , and the gate electrode 6 fills the gate contact hole 33 .

[0059] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0060] Specifically, while ensuring device performance, the size, shape, thickness and doping concentration of the drift region 1 can be selected according to actual conditions and are not limited here.

[0061] Specifically, while ensuring device performance, the thickness and doping concentration of the body region 12 can be selected according to actual conditions and are not limited here.

[0062] Specifically, under the premise of ensuring device performance, the opening size, opening shape and depth of the trench 21 can be selected according to actual conditions and are not limited here. The depth here refers to the distance between the bottom surface of the trench 21 and the opening of the trench 21.

[0063] Specifically, while ensuring device performance, the dimensions and shape of the drain lead-out region 14 in the X and Y directions can be selected based on practical needs and are not limited here. For example, the cross-sectional shape of the drain lead-out region 14 in the XY plane can be circular or a polygon of appropriate dimensions. In one embodiment, the X direction is parallel to the bottom surface of the trench 21; the Y direction is the vertical direction from the opening of the trench 21 to the bottom surface of the trench 21; the X direction is perpendicular to the Y direction.

[0064] As an example, the dimension of the drain lead-out region 14 in the Y direction is smaller than the dimension of the trench 21 in the Y direction.

[0065] Specifically, when the size of the drain lead-out region 14 in the Y direction is smaller than the size of the trench 21 in the Y direction, in order to ensure the performance of the device, multiple drain lead-out regions 14 can be set in the semiconductor structure 1 at the bottom of the trench 21, or only one drain lead-out region 14 can be set.

[0066] As an example, the size of the drain lead-out region 14 in the Y direction is the same as the size of the trench 21 in the Y direction, and the Y direction is perpendicular to the X direction.

[0067] In one embodiment, the gate dielectric layer 22 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0068] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 22 can be selected according to actual conditions and is not limited here.

[0069] Specifically, the gate conductive layer 23 is made of polysilicon or other suitable conductive materials. In this embodiment, polysilicon is used as the material of the gate conductive layer 23 .

[0070] In one embodiment, the source region 13 forms an ohmic contact with the source electrode 4. The size, thickness, and doping concentration of the source region 13 can be selected based on actual conditions while ensuring device performance and forming an ohmic contact between the source electrode 4 and the source region 13, and are not limited here.

[0071] As an example, a source contact region 15 having the second conductivity type is further provided on the upper surface layer of the body region 12 , and the source contact region 15 is exposed at the bottom of the source contact hole 31 .

[0072] In one embodiment, the source contact hole 31 penetrates the source region 13 and extends its bottom surface into the body region 12 . The source contact region 15 is located in the body region 12 at the bottom of the source contact hole 31 , and the source contact region 15 wraps the bottom of the source contact hole 31 .

[0073] Specifically, source contact region 15 is located on the upper surface of body region 12, and the upper surface of body region 12 is flush with the upper surface of source region 13. The sidewall of source contact region 15 close to source region 13 is adjacent to the sidewall of source region 13 away from trench 21. The bottom surface of source contact hole 31 exposes source region 13 and source contact region 15.

[0074] As an example, the doping concentration of the source contact region 15 is greater than the doping concentration of the body region 12 , so that an ohmic contact is formed between the source contact region 15 and the source 4 .

[0075] Specifically, while ensuring device performance and forming an ohmic contact between the source contact region 15 and the source 4 , the size, thickness and doping concentration of the source contact region 15 can be selected according to actual conditions and are not limited here.

[0076] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0077] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 above the semiconductor structure 1 can be selected according to actual conditions and is not limited here.

[0078] Specifically, while ensuring device performance, the opening size, opening shape, and number of the source contact holes 31 can be selected based on actual conditions and are not subject to any restrictions. The opening size, opening shape, and number of the gate contact holes 33 can be selected based on actual conditions and are not subject to any restrictions. The opening size, opening shape, and number of the drain contact holes 32 can be selected based on actual conditions and are not subject to any restrictions. The distances between the source contact holes 31, the gate contact holes 33, and the drain contact holes 32 can be selected based on actual conditions and are not subject to any restrictions.

[0079] Specifically, while ensuring device performance, the distance between the bottom surface of the drain contact hole 32 and the bottom surface of the trench 21 (i.e., the depth of the bottom surface of the drain contact hole 32 extending from the bottom surface of the trench 21 to the drift region 11) can be selected according to actual conditions and is no longer restricted here.

[0080] As an example, a drain contact region 16 of the first conductivity type is further provided in the drain lead-out region 14 , and the drain contact region 16 is exposed at the bottom surface of the drain contact hole 32 .

[0081] As an example, the doping concentration of the drain contact region 16 is greater than the doping concentration of the drift region 11 , and an ohmic contact is formed between the drain 5 and the drain contact region 16 .

[0082] Specifically, when the doping concentration of the drift region 11 is low and the drain 5 cannot form a good ohmic contact with the drift region 11, the purpose of forming an ohmic contact between the drift region 11 and the drain 5 can be achieved by setting a drain contact region 16 with the same doping type as the drift region 11 in the drift region 11 at the bottom of the drain contact hole 32.

[0083] Specifically, the drain contact region 16 wraps the bottom of the drain contact hole 32. While ensuring device performance and forming an ohmic contact between the drain contact region 16 and the drain 5, the doping concentration and size of the drain contact region 16 can be selected according to actual conditions and are not limited here.

[0084] As an example, a substrate 10 with a preset thickness is further provided in the semiconductor structure 1 , and the drift region 11 is located on the upper surface of the substrate 10 .

[0085] In one embodiment, the substrate 10 is used as a platform for forming the drift region 11 . The material of the substrate 10 includes glass, sapphire, silicon, silicon germanium, silicon carbide or other suitable substrate materials.

[0086] As an example, the doping type of the substrate 10 is the same as the doping type of the drift region 11 , the bottom surface of the drain contact hole 32 exposes the substrate 10 , and an ohmic contact is formed between the drain 5 and the substrate 10 .

[0087] In one embodiment, the doping concentration of the substrate 10 is greater than the doping concentration of the drift region 11 , so that an ohmic contact is formed between the drain 5 and the substrate 10 .

[0088] Specifically, when the doping concentration of the drift region 11 is low and it is difficult to form an ohmic contact with the drain 5, by selecting a semiconductor substrate with the same doping type as the drift region 11 and a doping concentration greater than that of the drift region 11 as the substrate 10, the drain contact hole 32 can be made to pass through the drift region 11, so that an ohmic contact is formed between the substrate 10 and the drain 5, avoiding the formation of a drain contact region 16 at the bottom of the drain contact hole 32.

[0089] As an example, the doping type of the substrate 10 is opposite to the doping type of the drift region 11 , so that a PN junction is formed between the drift region 11 and the substrate 10 , thereby suppressing the current in the device from passing through the substrate 10 and reducing the on-resistance of the device.

[0090] Specifically, the source electrode 4 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials. The gate electrode 6 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials. The drain electrode 5 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials.

[0091] Specifically, by improving the trench structure 2 of the MOS device, a drain lead-out region 14 of a preset size is defined in the drift region 11 at the bottom of the trench 21, and the edge of the area where the drain lead-out region 14 is located at the bottom of the trench 21 is spaced a preset distance from the sidewall of the trench 21. The interlayer dielectric layer 3 is used to fill the remaining area of ​​the trench 21 above the drain lead-out region 14, and a drain contact hole 32 is provided above the drain lead-out region 14, penetrating the interlayer dielectric layer 3 and extending its bottom surface to the drift region 11. Then, the drain contact hole 32 is filled with the drain electrode 5, thereby achieving the goal of leading the drain of the device to the device surface where the source electrode 4 and the gate electrode 6 are located, thereby reducing the thickness of the device.

[0092] In one embodiment, since the drain electrode 5 penetrates the interlayer dielectric layer 3 filling the trench 21 above the drain lead-out region 14, the current in the device is transmitted along the transmission path close to the surface of the trench 21, reducing the on-resistance of the device to 4.25mΩ / mm. 2 , while making the device's breakdown conduction reach 15V.

[0093] In one embodiment, as shown in Figure 4, it is a current distribution diagram of the trench-type lateral MOS device of the present application (the density of black dots in the drift region 11 in the figure represents the current size in the area). It can be seen from the figure that the current in the device is concentrated in the conductive channel of the device and the surface of the trench 21 between the conductive channel of the device and the drain 5. Only a small amount of current is distributed in other areas of the drift region 11. Then, by setting the drain 5 in the drain lead-out region 14 of the trench 21, the current transmission path is improved, so that the current in the device is transmitted along the body region 12 and the drift region 11 on the surface of the trench 21 between the source region 13 and the drain 5, and then the on-resistance of the device can be reduced.

[0094] The trench-type lateral MOS device of this embodiment improves the device structure by defining at least one drain lead-out region 14 in the drift region 11 directly below the bottom of the trench 21. The gate dielectric layer 22 covers the inner wall and bottom surface of the trench 21 outside the drain lead-out region 14. The gate conductive layer 14 fills the area of ​​the trench 21 outside the area directly above the drain lead-out region 14. The interlayer dielectric layer 3 covers the upper surface of the semiconductor structure 1 and fills the area of ​​the trench 21 not filled by the gate conductive layer. The drain 5 is led out above the drain lead-out region 14 so that the drain 5, source 4, and gate 6 are located on the same side of the device, eliminating the need to form the drain 5 on the back side of the device. This reduces the thickness of the device and improves the current transmission path in the device. The current in the device is transmitted along the body region 12 and drift region 11 on the surface of the trench 21 between the source region 13 and the drain 5, shortening the current transmission path and reducing the on-resistance of the device. At the same time, the breakdown voltage of the device can reach 15V.

[0095] Example 2

[0096] This embodiment provides a method for fabricating a trench-type lateral MOS. FIG5 is a process flow chart of the method for fabricating a trench-type lateral MOS, which includes the following steps:

[0097] S1: providing a semiconductor structure, the semiconductor structure comprising a drift region having a first conductivity type and a body region having a second conductivity type stacked in sequence;

[0098] S2: forming a trench structure including a trench, a gate dielectric layer, and a gate conductive layer, wherein the trench penetrates the body region and the bottom surface extends into the drift region, at least one drain lead-out region is defined in the drift region below the bottom of the trench, a projection area of ​​the at least one drain lead-out region on the bottom surface of the trench is spaced a preset distance from the sidewall of the trench, the gate dielectric layer covers the inner wall and bottom surface of the trench except for the area directly above the drain lead-out region, and the gate conductive layer fills the area of ​​the trench except for the area directly above the drain lead-out region;

[0099] S3: forming a source region of the first conductivity type on the upper surface of the body region, the source region being adjacent to the sidewalls of the trench and two sidewalls of the trench that are opposite to each other in the X direction, where the X direction is a direction parallel to the bottom surface of the trench;

[0100] S4: forming an interlayer dielectric layer covering the upper surface of the semiconductor structure and filling the remaining area of ​​the trench above the drain lead-out region;

[0101] S5: forming a source contact hole penetrating the interlayer dielectric layer and exposing the source region at its bottom, forming a drain contact hole penetrating the interlayer dielectric layer directly above the drain lead-out region and exposing at least a portion of the drift region at its bottom, and forming a gate contact hole penetrating the interlayer dielectric layer and exposing the gate conductive layer at its bottom, wherein a vertical projection area of ​​the drain contact hole on the drain lead-out region is spaced a preset distance from an edge of the drain lead-out region;

[0102] S6: forming a source electrode filling the source contact hole, forming a drain electrode filling the drain contact hole, and forming a gate electrode filling the gate contact hole.

[0103] In one embodiment, referring to FIG. 6 to FIG. 12 , steps S1 to S3 are performed:

[0104] S1: providing a semiconductor structure 1, the semiconductor structure 1 comprising a drift region 11 having a first conductivity type and a body region 12 having a second conductivity type stacked in sequence;

[0105] S2: forming a trench structure 2 including a trench 21, a gate dielectric layer 22, and a gate conductive layer 23, wherein the trench 21 penetrates the body region 12 and extends its bottom surface into the drift region 11, and at least one drain lead-out region 14 is defined in the drift region 11 below the bottom of the trench 21, wherein a projection area of ​​the drain lead-out region 14 on the bottom surface of the trench 21 is spaced apart from a sidewall of the trench 21 by a predetermined distance, the gate dielectric layer 22 covers the inner wall and bottom surface of the trench 21 except for the area directly above the drain lead-out region 14, and the gate conductive layer 23 fills the area of ​​the trench 21 except for the area directly above the drain lead-out region 14;

[0106] S3: forming a source region 13 of the first conductivity type on the upper surface of the body region 12. The source region 13 is adjacent to the sidewalls of the trench 21 and two sidewalls of the trench 21 that are opposite to each other in the X direction. The X direction is a direction parallel to the bottom surface of the trench.

[0107] Specifically, the semiconductor structure 1 further includes a substrate 10 located below the drift region 11 . The drift region 11 is located on the upper surface of the substrate 10 . The substrate 10 may be made of an insulating material or a semiconductor material.

[0108] Specifically, when the substrate 10 is made of a semiconductor material, the doping type of the substrate 10 may be opposite to or the same as the doping type of the drift region 11 .

[0109] Specifically, the drift region 11 may be formed on the upper surface of the substrate 10 by epitaxial growth or by an ion implantation process.

[0110] Specifically, the method of forming the body region 12 includes ion implantation or other suitable methods.

[0111] Specifically, as shown in Figures 10 and 11, Figure 11 is a schematic diagram of the cross-sectional structure after the trench structure 2 is formed. The formation of the trench structure 2 includes the following steps: forming a patterned shielding layer (not shown) on the upper surface of the semiconductor structure 1, and forming a trench 21 based on the patterned shielding layer; forming a gate dielectric material layer 221 covering the upper surface of the semiconductor structure 1 and the inner wall and bottom of the trench 21, and forming a gate conductive material layer 231 of a preset thickness on the upper surface of the gate dielectric material layer 221, wherein the thickness of the gate conductive material layer 231 is not greater than the distance between the drain lead-out region 14 and the inner wall of the trench 21; removing the gate conductive material layer 231 directly above the semiconductor structure 1 and the drain lead-out region 14 to obtain a gate conductive layer 23, and removing the gate dielectric material layer 221 directly above the drain lead-out region 14 to obtain a gate dielectric layer 22, thereby obtaining a trench structure 2 consisting of the trench 21, the gate dielectric layer 22 and the gate conductive layer 23.

[0112] Specifically, as shown in FIG6 , which is a schematic diagram of a cross-sectional structure after the trench 21 is formed, the method of forming the trench 21 includes dry etching, wet etching or other suitable methods.

[0113] Specifically, as shown in FIG9 , which is a schematic diagram of a cross-sectional structure after forming the gate dielectric material layer 221 , the method of forming the gate dielectric material layer 221 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0114] Specifically, as shown in FIG10 , which is a schematic diagram of a cross-sectional structure after forming the gate conductive material layer 231 , the method of forming the gate conductive material layer 231 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0115] Specifically, the gate conductive material layer 231 directly above the semiconductor structure 1 and the drain lead-out region 14 may be removed by dry etching, wet etching, or other suitable methods. The gate dielectric material layer 221 directly above the drain lead-out region 14 may be removed by dry etching, wet etching, or other suitable methods.

[0116] Specifically, under the condition of ensuring the device performance, the gate dielectric material layer 221 covering the drain lead-out region 14 and the upper surface of the semiconductor structure 1 may not be removed.

[0117] Specifically, as shown in Figure 7, which is a schematic diagram of the top surface structure after the groove 21 is formed, the size of the drain lead-out region 14 in the Y direction is smaller than the size of the groove 21 in the Y direction. The Y direction refers to the vertical direction from the opening of the groove to the bottom surface of the groove, and the Y direction is perpendicular to the X direction.

[0118] Specifically, as shown in Figure 8, which is a schematic diagram of another top surface structure after the groove 21 is formed, while ensuring device performance, the size of the drain lead-out region 14 in the Y direction is the same as the size of the groove 21 in the Y direction. The Y direction refers to the vertical direction from the opening of the groove to the bottom surface of the groove, and the Y direction is perpendicular to the X direction.

[0119] Specifically, as shown in FIG12 , it is a schematic diagram of the cross-sectional structure after the source region 13 is formed. The method of forming the source region 13 includes ion implantation or other suitable methods.

[0120] Specifically, a source contact region 15 of the second conductivity type is formed on the upper surface of the body region 12 and is adjacent to the sidewall of the source region 13 away from the trench 21 . The doping concentration of the source contact region 15 is greater than that of the body region 12 .

[0121] Specifically, the method of forming the source contact region 15 includes ion implantation or other suitable methods.

[0122] Please refer to FIG. 13 again and execute steps S4 to S6:

[0123] S4: forming an interlayer dielectric layer 3 covering the upper surface of the semiconductor structure 1 and filling the remaining area of ​​the trench 21 above the drain lead-out region 14;

[0124] S5: forming a source contact hole 31 penetrating the interlayer dielectric layer 3 and exposing the source region 13 at its bottom, forming a drain contact hole 32 penetrating the interlayer dielectric layer 3 just above the drain lead-out region 14 and exposing at least a portion of the drift region 11 at its bottom, and forming a gate contact hole 33 penetrating the interlayer dielectric layer 3 and exposing the gate conductive layer 23 at its bottom, wherein a vertical projection area of ​​the drain contact hole 32 on the drain lead-out region 14 is spaced a predetermined distance from an edge of the drain lead-out region 14;

[0125] S6 : forming a source electrode 4 filling the source contact hole 31 , forming a drain electrode 5 filling the drain contact hole 32 , and forming a gate electrode 6 filling the gate contact hole 33 .

[0126] Specifically, the method of forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0127] Specifically, the method for forming the source contact hole 31 includes dry etching, wet etching, or other suitable methods. The method for forming the drain contact hole 32 includes dry etching, wet etching, or other suitable methods. The method for forming the gate contact hole 33 includes dry etching, wet etching, or other suitable methods.

[0128] Specifically, before the interlayer dielectric layer 3 is formed, the source contact region 15 is not formed in the body region 12; after the source contact hole 31 is formed, the preparation method also includes a step of forming the source contact region 15 in the body region 12 at the bottom of the source contact hole 31 based on the source contact hole 31, that is, ion implantation is performed on the bottom of the source contact hole 31 based on the source contact hole 31 to form the source contact region 15.

[0129] In one embodiment, after forming the drain contact hole 32 and before forming the drain 5, the preparation method also includes a step of forming a drain contact region 16 having a first conductivity type at the bottom of the drain contact hole 32, the doping concentration of the drain contact region 16 is greater than the doping concentration of the drift region 11, and an ohmic contact is formed between the drain contact region 16 and the drain 5.

[0130] In one embodiment, a substrate 10 having a first conductivity type is provided at the bottom of the semiconductor structure 1, the bottom surface of the drain contact hole 32 extends into the substrate 10, and the substrate 10 can form an ohmic contact with the drain 5, and before the drain 5 is formed, it is not necessary to form a drain contact region 16 at the bottom of the drain contact hole 32.

[0131] In one embodiment, the method for forming the source 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The method for forming the drain 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The method for forming the gate 6 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0132] Specifically, at least one drain lead-out region 14 is defined in the drift region 11 at the bottom of the trench 21, a preset distance is separated between the drain lead-out region 14 and the sidewalls of the trench 21, and a gate dielectric layer 22 covering the sidewalls and bottom of the trench 21 area other than the area directly above the drain lead-out region 14 and a gate conductive layer 23 filling the trench 21 area other than the area directly above the drain lead-out region 14 are formed, thereby forming an interlayer dielectric layer 3 covering the upper surface of the semiconductor structure 1 and filling the remaining unfilled area of ​​the trench 21, and forming a drain contact hole 32 that penetrates the interlayer dielectric layer 3 and extends to the bottom surface of the drain lead-out region 14 to lead out the drain 5, thereby achieving the goal of leading the drain 5 to the device surface where the source 4 is located, thereby facilitating the integration and interconnection of the device with other devices.

[0133] In one embodiment, by leading the drain 5 and the source 4 to the same side of the device, the device can be better applied to fields requiring high device integration, such as lithium battery protection, thereby expanding its application in fields with high integration and complex interconnection, such as lithium battery protection.

[0134] The method for preparing a trench-type lateral MOS device of this embodiment is as follows: at least one drain lead-out region 14 is defined in the drift region 11 at the bottom of the trench 21, with a preset distance between the drain lead-out region 14 and the sidewalls of the trench 21. A gate dielectric layer 22 is formed to cover the sidewalls and bottom of the trench 21 area except the area above the drain lead-out region 14, and a gate conductive layer 23 is formed to fill the area of ​​the trench 21 except the area directly above the drain lead-out region 14. An interlayer dielectric layer 3 is formed to cover the upper surface of the semiconductor structure 1 and fill the remaining unfilled area of ​​the trench 21. A drain contact hole 32 is formed that penetrates the interlayer dielectric layer 3 and extends its bottom surface to the drain lead-out region 14 to lead out the drain 5. In this way, the drain 5 and the source 4 are led to the same surface of the device, which facilitates the integration and interconnection of the device with other devices and expands its application in fields with high integration and complex interconnection, such as lithium battery protection.

[0135] In summary, the trench-type lateral MOS device and its preparation method of the present application improve the structure of the device, define at least one drain lead-out region in the drift region below the bottom of the trench, the gate dielectric layer covers the inner wall and bottom surface of the trench except the area directly above the drain lead-out region, the gate conductive layer fills the trench area except the area directly above the drain lead-out region, the interlayer dielectric layer fills the remaining area in the trench and covers the upper surface of the semiconductor structure, and a drain contact hole is provided in the interlayer dielectric layer directly above the drain lead-out region, which penetrates the interlayer dielectric layer and extends to the drift region to lead the drain to the surface where the source is located, thereby reducing the thickness of the device and allowing the current in the device to be transmitted along the body region and drift region of the trench surface between the source region and the drain, improving the current transmission path and reducing the on-resistance of the device; at the same time, the device is improved in the circuit integration and interconnection, making it easy to integrate and interconnect with other devices, and expanding its application in fields with high integration and complex interconnection such as lithium battery protection. Therefore, the present application effectively overcomes the various shortcomings in the related art and has high industrial utilization value.

[0136] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A trench-type lateral MOS device, comprising: A semiconductor structure including a drift region of a first conductivity type and a body region of a second conductivity type that are stacked in sequence; A trench structure including a trench, a gate dielectric layer, and a gate conductive layer. The trench penetrates the body region and its bottom surface extends into the drift region. At least one drain lead-out region is defined in the drift region below the bottom of the trench. The projection area of the at least one drain lead-out region on the bottom surface of the trench is spaced apart from the sidewall of the trench by a preset distance. The gate dielectric layer covers the inner wall and the bottom surface of the trench except for the region directly above the drain lead-out region. The gate conductive layer fills the region in the trench except for the region directly above the drain lead-out region; A source region of a first conductivity type, located on the upper surface layer of the body region and adjacent to the sidewalls of the trench that are opposite to each other in the X direction. The X direction refers to the direction parallel to the bottom surface of the trench; An interlayer dielectric layer covering the upper surface of the semiconductor structure and filling the remaining region of the trench above the drain lead-out region; A source contact hole, a drain contact hole, and a gate contact hole. The source contact hole penetrates the interlayer dielectric layer and at least part of its bottom exposes the source region. The drain contact hole penetrates the interlayer dielectric layer directly above the drain lead-out region and at least part of its bottom exposes the drift region. The vertical projection area of the drain contact hole on the drain lead-out region is spaced apart from the edge of the drain lead-out region by a preset distance. The gate contact hole penetrates the interlayer dielectric layer and its bottom surface exposes the gate conductive layer; A source electrode, a drain electrode, and a gate electrode. The source electrode fills the source contact hole, the drain electrode fills the drain contact hole, and the gate electrode fills the gate contact hole.

2. The trench-type lateral MOS device according to claim 1, wherein the size of the drain lead-out region in the Y direction is smaller than the size of the trench in the Y direction. The Y direction refers to the vertical direction from the opening of the trench to the bottom surface of the trench, and the Y direction is perpendicular to the X direction.

3. The trench-type lateral MOS device according to claim 1, wherein the size of the drain lead-out region in the Y direction is the same as the size of the trench in the Y direction. The Y direction refers to the vertical direction from the opening of the trench to the bottom surface of the trench, and the Y direction is perpendicular to the X direction.

4. The trench-type lateral MOS device according to claim 1, wherein a source contact region of a second conductivity type is further provided on the upper surface layer of the body region, and the bottom of the source contact hole exposes the source contact region.

5. The trench-type lateral MOS device according to claim 1, wherein a drain contact region of a first conductivity type is further provided in the drain lead-out region, and the bottom surface of the drain contact hole exposes the drain contact region.

6. The trench-type lateral MOS device according to claim 5, wherein the doping concentration of the drain contact region is greater than the doping concentration of the drift region, and an ohmic contact is formed between the drain electrode and the drain contact region.

7. The trench-type lateral MOS device according to claim 1, wherein a substrate with a preset thickness is further provided in the semiconductor structure, and the drift region is located on the upper surface of the substrate.

8. The trench-type lateral MOS device according to claim 7, wherein the doping type of the substrate is the same as that of the drift region, the bottom surface of the drain contact hole exposes the substrate, and an ohmic contact is formed between the drain and the substrate.

9. The trench-type lateral MOS device according to claim 7, wherein the doping type of the substrate is opposite to that of the drift region.

10. The trench-type lateral MOS device according to claim 7, wherein the doping concentration of the substrate is greater than that of the drift region, and an ohmic contact is formed between the drain and the substrate.

11. A method for manufacturing a trench-type lateral MOS device, comprising: providing a semiconductor structure, the semiconductor structure including a drift region having a first conductivity type and a body region having a second conductivity type that are stacked in sequence; forming a trench structure including a trench, a gate dielectric layer, and a gate conductive layer, the trench penetrating through the body region and the bottom surface extending into the drift region, at least one drain lead-out region being defined in the drift region below the bottom of the trench, a projection region of the at least one drain lead-out region on the bottom surface of the trench being spaced from the sidewall of the trench by a preset distance, the gate dielectric layer covering the inner wall and the bottom surface of the trench except for the region directly above the drain lead-out region, and the gate conductive layer filling the region of the trench except for the region directly above the drain lead-out region; forming a source region having a first conductivity type on the upper surface layer of the body region, the source region being adjacent to two sidewalls of the trench that are opposite to each other in the X direction, where the X direction refers to the direction parallel to the bottom surface of the trench; forming an interlayer dielectric layer covering the upper surface of the semiconductor structure and filling the remaining region of the trench above the drain lead-out region; forming a source contact hole penetrating through the interlayer dielectric layer and the bottom surface of which exposes the source region, forming a drain contact hole penetrating through the interlayer dielectric layer directly above the drain lead-out region and the bottom surface of which at least partially exposes the drift region, forming a gate contact hole penetrating through the interlayer dielectric layer and the bottom surface of which exposes the gate conductive layer, a vertical projection region of the drain contact hole on the drain lead-out region being spaced from the edge of the drain lead-out region by a preset distance; forming a source electrode filling the source contact hole, forming a drain electrode filling the drain contact hole, and forming a gate electrode filling the gate contact hole.

12. The method according to claim 11, wherein the step of forming the trench structure includes: forming a patterned masking layer on the upper surface of the semiconductor structure, and forming the trench based on the patterned masking layer; forming a gate dielectric material layer covering the upper surface of the semiconductor structure and the inner wall and the bottom surface of the trench, and forming a gate conductive material layer with a preset thickness on the upper surface of the gate dielectric material layer, the preset thickness being not greater than the distance between the drain lead-out region and the inner wall of the trench; Remove the gate conductive material layer directly above the semiconductor structure and the drain lead-out region to obtain the gate conductive layer, and remove the gate dielectric material layer directly above the drain lead-out region to obtain the gate dielectric layer, thereby obtaining the trench structure composed of the trench, the gate dielectric layer, and the gate conductive layer.

13. The method according to claim 11, wherein the size of the drain lead-out region in the Y direction is smaller than the size of the trench in the Y direction, the Y direction refers to the vertical direction from the opening of the trench to the bottom surface of the trench, and the Y direction is perpendicular to the X direction.

14. The method according to claim 11, wherein the size of the drain lead-out region in the Y direction is the same as the size of the trench in the Y direction, the Y direction refers to the vertical direction from the opening of the trench to the bottom surface of the trench, and the Y direction is perpendicular to the X direction.

15. The method according to claim 11, wherein after forming the source contact hole, the method further comprises: Perform ion implantation on the bottom of the source contact hole based on the source contact hole to form a source contact region.

16. The method according to claim 11, wherein after forming the drain contact hole and before forming the drain, the method further comprises: Form a drain contact region of the first conduction type at the bottom of the drain contact hole, the doping concentration of the drain contact region is greater than the doping concentration of the drift region, and an ohmic contact is formed between the drain contact region and the drain.

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