Method and apparatus for handling memory access failure queue, and electronic device

Abstract

The present application relates to the technical field of computers. Provided are a method and apparatus for handling a memory access failure queue, and an electronic device. The method comprises: acquiring a first memory access failure request currently entering a memory access failure queue; on the basis of failure information corresponding to an allocated failure queue entry in the memory access failure queue, determining a target handling mode of the first memory access failure request, wherein the target handling mode is that the allocated failure queue entry merges and handles the first memory access failure request, the allocated failure queue entry rejects to handle the first memory access failure request, or the allocated failure queue entry neither merges and handles nor rejects to handle the first memory access failure request; and handling the first memory access failure request on the basis of the target handling mode.

Description

Method, device and electronic device for processing memory access failure queue

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311829734.6 and application date of December 28, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a method, device and electronic device for processing a memory access failure queue. Background Art

[0004] Instructions in the processor that access the memory, such as load instructions and store instructions, will access the data cache. For load instructions and store instructions, both may cause data cache access failures. Failed instructions will be cached in the memory access failure queue for processing.

[0005] Currently, the way to handle instructions in the memory access invalidation queue is usually to assign respective invalidation queue items to multiple instructions, and then access the lower-level storage system based on the assigned invalidation queue items, retrieve the data that needs to be backfilled from the lower-level storage system, and backfill it into the data cache, so that the instructions in the memory access invalidation queue can normally access the corresponding data in the data cache.

[0006] However, the above-mentioned processing method of the memory access failure queue is not flexible enough, resulting in low efficiency of the processor in processing the memory access failure queue.

[0007] Summary of the Invention

[0008] The present application provides a method, device and electronic device for processing a memory access failure queue to improve the flexibility of the processing method of the memory access failure queue, thereby improving the efficiency of the processor in processing the memory access failure queue.

[0009] In a first aspect, the present application provides a method for processing a memory access failure queue, comprising:

[0010] Get the first memory access invalidation request currently entering the memory access invalidation queue;

[0011] determining, based on the invalidation information corresponding to the allocated invalidation queue entry in the memory access invalidation queue, a target processing mode for the first memory access invalidation request, wherein the target processing mode is: the allocated invalidation queue entry merges the first memory access invalidation request, the allocated invalidation queue entry refuses to process the first memory access invalidation request, or the allocated invalidation queue entry does not merge the first memory access invalidation request and does not refuse to process the first memory access invalidation request;

[0012] Processing the first memory access invalidation request based on the target processing mode;

[0013] The determining of a target processing method for the first memory access invalidation request based on invalidation information corresponding to an allocated invalidation queue entry in the memory access invalidation queue includes:

[0014] determining whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request in the allocated invalidation queue entry;

[0015] determining the target processing mode based on whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request;

[0016] The determining the target processing mode based on whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request includes:

[0017] determining the target processing mode based on the acquisition request corresponding to the second memory access invalidation request, the request type of the first memory access invalidation request, and the request type of the second memory access invalidation request when the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request;

[0018] determining the target processing mode based on the block address of the first memory access invalidation request and the block address of the second memory access invalidation request when the block address of the first memory access invalidation request is different from the block address of the second memory access invalidation request;

[0019] The determining the target processing mode based on the acquisition request corresponding to the second memory access invalidation request, the request type of the first memory access invalidation request, and the request type of the second memory access invalidation request includes:

[0020] When the first preset condition or the second preset condition is met, determining that the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request;

[0021] If the first preset condition and / or the second preset condition is not satisfied, determining that the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0022] The first preset condition is: the acquisition request is not received by the lower-layer storage system, the request type of the first memory access invalidation request is a data access request or a data storage request, and the second memory access invalidation request is a data access request or a data storage request;

[0023] The second preset condition is: the request type of the first memory access invalidation request is a data retrieval request, and the request type of the second memory access invalidation request is a data retrieval request or a data storage request; and the retrieval request has been received by the lower-level storage system, but no retrieval request response has been received from the lower-level storage system, or the retrieval request response has not been sent to the data retrieval queue.

[0024] In some embodiments, when the first preset condition is met and the request type of the first memory access invalidation request is a data storage request, the method further includes:

[0025] An acquisition request corresponding to the second memory access invalidation request is updated to obtain an updated acquisition request, wherein the updated acquisition request is used to request the write permission corresponding to the first memory access invalidation request.

[0026] In some embodiments, determining the target processing mode based on the block address of the first memory access invalidation request and the block address of the second memory access invalidation request includes:

[0027] When the block address of the first memory access invalidation request and the block address of the second memory access invalidation request belong to the same cache line, determining the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0028] When the block address of the first memory invalidation request and the block address of the second memory invalidation request do not belong to the same cache line, the target processing manner is determined as not merging the allocated invalidation queue entries and not rejecting the first memory invalidation request.

[0029] In some embodiments, processing the first memory access invalidation request based on the target processing mode includes:

[0030] When the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request, backfilling data for the first memory access invalidation request based on the allocated invalidation queue entries;

[0031] If the target processing mode is that the allocated invalidation queue entry refuses to process the first memory access invalidation request, refusing to process the first memory access invalidation request;

[0032] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is an unallocated invalidation queue entry in the memory access invalidation queue, backfilling data for the first memory access invalidation request based on the unallocated invalidation queue entry;

[0033] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is no unallocated invalidation queue entry in the memory access invalidation queue, reject the first memory access invalidation request.

[0034] In some embodiments, backfilling data for the first memory access invalidation request includes:

[0035] Determining a replacement block corresponding to the first memory access invalidation request in the data cache;

[0036] Reading data in the replacement block into a write-back queue;

[0037] After obtaining the backfill data corresponding to the first memory access failure request, the backfill data is backfilled into the replacement block.

[0038] In some embodiments, the data in the replacement block is in a dormant state in the write-back queue, and backfilling the backfill data to the replacement block includes:

[0039] Updating the state of the data in the replacement block in the write-back queue to a wake-up state;

[0040] When the data in the replacement block is in the awake state in the write-back queue, the backfill data is backfilled into the replacement block.

[0041] In some embodiments, each type of access request in the memory access failure queue includes a corresponding queue head, and the method further includes:

[0042] For each type of access request, determining, from the invalidation queue items included in the memory access invalidation queue, a target invalidation queue item currently pointed to by the queue head corresponding to the type of access request;

[0043] Starting from the target invalidation queue entry, determining a first invalidation queue entry that meets a preset condition among the invalidation queue entries included in the memory access invalidation queue, wherein the preset condition is that the access request in the invalidation queue entry is an access request of the type;

[0044] issuing a target access request based on the first invalidation queue entry that meets the preset condition;

[0045] The invalidation queue entry currently pointed to by the queue head corresponding to the access request of the type is updated from the target invalidation queue entry to the next invalidation queue entry of the target invalidation queue entry.

[0046] In a second aspect, the present application provides a memory access failure queue processing device, comprising:

[0047] An acquisition module, configured to acquire the first memory access invalidation request currently entering the memory access invalidation queue;

[0048] a first processing module, configured to determine a target processing mode for the first memory access invalidation request based on invalidation information corresponding to an allocated invalidation queue entry in the memory access invalidation queue, the target processing mode being: merging the first memory access invalidation request with the allocated invalidation queue entry, refusing to process the first memory access invalidation request with the allocated invalidation queue entry, or not merging the first memory access invalidation request with the allocated invalidation queue entry and not refusing to process the first memory access invalidation request;

[0049] a second processing module, configured to process the first memory access invalidation request based on the target processing mode;

[0050] Wherein, the first processing module is specifically used for:

[0051] determining whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request in the allocated invalidation queue entry;

[0052] determining the target processing mode based on whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request;

[0053] The first processing module is specifically configured to:

[0054] determining the target processing mode based on the acquisition request corresponding to the second memory access invalidation request, the request type of the first memory access invalidation request, and the request type of the second memory access invalidation request when the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request;

[0055] determining the target processing mode based on the block address of the first memory access invalidation request and the block address of the second memory access invalidation request when the block address of the first memory access invalidation request is different from the block address of the second memory access invalidation request;

[0056] The first processing module is specifically configured to:

[0057] When the first preset condition or the second preset condition is met, determining that the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request;

[0058] If the first preset condition and / or the second preset condition is not satisfied, determining that the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0059] The first preset condition is: the acquisition request is not received by the lower-layer storage system, the request type of the first memory access invalidation request is a data access request or a data storage request, and the second memory access invalidation request is a data access request or a data storage request;

[0060] The second preset condition is: the request type of the first memory access invalidation request is a data retrieval request, and the request type of the second memory access invalidation request is a data retrieval request or a data storage request; and the retrieval request has been received by the lower-level storage system, but no retrieval request response has been received from the lower-level storage system, or the retrieval request response has not been sent to the data retrieval queue.

[0061] In some embodiments, when the first preset condition is met and the request type of the first memory access invalidation request is a data storage request, the first processing module is further configured to:

[0062] An acquisition request corresponding to the second memory access invalidation request is updated to obtain an updated acquisition request, wherein the updated acquisition request is used to request the write permission corresponding to the first memory access invalidation request.

[0063] In some embodiments, the first processing module is specifically configured to:

[0064] When the block address of the first memory access invalidation request and the block address of the second memory access invalidation request belong to the same cache line, determining the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0065] When the block address of the first memory invalidation request and the block address of the second memory invalidation request do not belong to the same cache line, the target processing manner is determined as not merging the allocated invalidation queue entries and not rejecting the first memory invalidation request.

[0066] In some embodiments, the second processing module is specifically configured to:

[0067] When the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request, backfilling data for the first memory access invalidation request based on the allocated invalidation queue entries;

[0068] If the target processing mode is that the allocated invalidation queue entry refuses to process the first memory access invalidation request, refusing to process the first memory access invalidation request;

[0069] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is an unallocated invalidation queue entry in the memory access invalidation queue, backfilling data for the first memory access invalidation request based on the unallocated invalidation queue entry;

[0070] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is no unallocated invalidation queue entry in the memory access invalidation queue, reject the first memory access invalidation request.

[0071] In some embodiments, the second processing module is specifically configured to:

[0072] Determining a replacement block corresponding to the first memory access invalidation request in the data cache;

[0073] Reading data in the replacement block into a write-back queue;

[0074] After obtaining the backfill data corresponding to the first memory access failure request, the backfill data is backfilled into the replacement block.

[0075] In some embodiments, the data in the replacement block is in a dormant state in the write-back queue, and the second processing module is specifically configured to:

[0076] Updating the state of the data in the replacement block in the write-back queue to a wake-up state;

[0077] When the data in the replacement block is in the awake state in the write-back queue, the backfill data is backfilled into the replacement block.

[0078] In some embodiments, each type of access request in the memory access failure queue includes a corresponding queue head, and the second processing module is further configured to:

[0079] For each type of access request, determining, from the invalidation queue items included in the memory access invalidation queue, a target invalidation queue item currently pointed to by the queue head corresponding to the type of access request;

[0080] Starting from the target invalidation queue entry, determining a first invalidation queue entry that meets a preset condition among the invalidation queue entries included in the memory access invalidation queue, wherein the preset condition is that the access request in the invalidation queue entry is an access request of the type;

[0081] issuing a target access request based on the first invalidation queue entry that meets the preset condition;

[0082] The invalidation queue entry currently pointed to by the queue head corresponding to the access request of the type is updated from the target invalidation queue entry to the next invalidation queue entry of the target invalidation queue entry.

[0083] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the memory access failure queue processing method as described in any one of the first aspects is implemented.

[0084] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the memory access failure queue processing method as described in any one of the first aspects is implemented.

[0085] In a fifth aspect, the present application provides a computer program product, wherein the computer program product includes a computer program, the computer program is stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer executes the memory access failure queue processing method as described in any one of the first aspects.

[0086] The memory access invalidation queue processing method, device and electronic device provided by the present application first obtain the first memory access invalidation request currently entering the memory access invalidation queue, and determine the target processing method of the first memory access invalidation request based on the invalidation information corresponding to the allocated invalidation queue item in the memory access invalidation queue, the target processing method is that the allocated invalidation queue item merges the first memory access invalidation request, the allocated invalidation queue item refuses to process the first memory access invalidation request, or the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request; after determining the target processing method, the first memory access invalidation request is processed based on the target processing method. The solution of the present application can flexibly determine the target processing method of the first memory access invalidation request based on the first memory access invalidation request currently entering the memory access invalidation queue and the invalidation information corresponding to the allocated invalidation queue, and determine whether the allocated invalidation queue item merges the processing, refuses the processing, or does not merge the processing and does not refuse to process the first memory access invalidation request, thereby improving the flexibility of memory access invalidation request processing and thus improving the efficiency of memory access invalidation queue processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0088] FIG1 is a flow chart of a method for processing a memory access failure queue according to an embodiment of the present application;

[0089] FIG2 is a schematic diagram of memory access failure queue processing according to an embodiment of the present application;

[0090] FIG3 is a schematic diagram of a status register control according to an embodiment of the present application;

[0091] FIG4 is a flow chart of a target determination processing method provided in an embodiment of the present application;

[0092] FIG5 is a schematic diagram of the structure of a memory access failure queue processing device provided in an embodiment of the present application;

[0093] FIG6 is a schematic diagram of the physical structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0094] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0095] With the advancement of computer processor technology, especially the development of high-performance processors into multi-core processors, the performance of the processor memory system has an increasingly significant impact on processor performance. Instructions in the processor that access memory, such as load and store instructions, access the data cache. These instructions can cause data cache misses.

[0096] One way to handle a data cache miss is to process only the missing data until the miss is resolved, preventing the processor from executing any further load or store instructions. Because the load or store instruction that caused the miss blocks the execution of subsequent instructions, this approach is called blocking the cache.

[0097] Generally, instructions following a load instruction will use the data from that instruction. Therefore, the sooner the load instruction is executed, the better it is for subsequent instructions. Considering the relatively long processing time for a data cache miss, if this time blocks the execution of other load or store instructions, it will significantly reduce the parallelism of processor program execution and hinder processor performance. Therefore, the approach to handling cache blocking has significant shortcomings.

[0098] To improve the parallelism of processor program execution, non-blocking caches were proposed. These caches allow the processor to continue executing new load and store instructions even when a data cache miss occurs, masking the time taken up by the data cache miss and thus effectively improving processor performance.

[0099] To support non-blocking cache operation, the processor needs to store and process access requests to the lower-level storage system for load or store instructions that have already generated cache access failures. This requires a memory invalidation queue to cache missed memory access requests to ensure that subsequent cache access commands are received, allowing the processor to handle multiple memory access requests simultaneously. In multi-core processors, the memory invalidation queue is also responsible for handling external consistency requests from other processor cores to maintain cache coherence across the multi-core processor.

[0100] At present, the memory access failure queue includes multiple failure queue items, each of which is responsible for receiving a memory access failure request, and then retrieving the data that needs to be backfilled from the lower-level storage system and backfilling it into the data cache to realize the processing of the memory access failure request. However, the processing method of this memory access failure queue has poor flexibility and low processing efficiency. Since the access addresses of multiple data retrieval instructions and multiple data storage instructions to the cache, the replacement addresses of the cache for the data returned by the lower-level storage system, and the addresses of the external consistency requests of other processor cores in the multi-core processor may all have the same address, the judgment and processing of the same address by the memory access failure queue can be merged or processed separately, either serially or in parallel. Based on this, the embodiment of the present application provides a processing scheme for the memory access failure queue, which enables the memory access failure requests that meet the merging conditions to be merged as much as possible by judging whether the memory access failure request meets the merging conditions or the rejection conditions, so as to improve the processing efficiency of the memory access failure queue and thereby improve the performance of the processor.

[0101] FIG1 is a flowchart of a method for processing a memory access failure queue provided in an embodiment of the present application. As shown in FIG1 , the method includes steps S11 to S13 .

[0102] S11, obtaining the first memory access invalidation request currently entering the memory access invalidation queue.

[0103] The memory access invalidation queue includes multiple invalidation queue items, which may include allocated invalidation queue items and unallocated invalidation queue items. The invalidation queue item is responsible for receiving memory access invalidation requests, which may be read requests or store requests.

[0104] The first memory access invalidation request currently entering the memory access invalidation queue refers to a new memory access invalidation request. Currently, no invalidation queue entry has been allocated to the first memory access invalidation request, that is, currently, no invalidation queue entry receives the first memory access invalidation request.

[0105] S12, based on the invalidation information corresponding to the allocated invalidation queue item in the memory access invalidation queue, determine the target processing method for the first memory access invalidation request, the target processing method is that the allocated invalidation queue item merges the first memory access invalidation request, the allocated invalidation queue item refuses to process the first memory access invalidation request, or the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request.

[0106] An allocated invalidation queue entry is an invalidation queue entry in the memory access invalidation queue that has received a memory access invalidation request. For example, if a certain invalidation queue entry has received the second memory access invalidation request, the invalidation queue entry is an allocated invalidation queue entry.

[0107] The allocated invalidation queue entry will record the corresponding relevant invalidation information, which may include the following information:

[0108] Status information: used to record the status of the memory access failure queue;

[0109] Operation code: used to identify whether the failure is caused by a store operation, a load operation, or an external consistency request;

[0110] Physical address: used to record the physical address for accessing the underlying storage system or the physical address of the external consistency request;

[0111] Data: used to record the data returned by the underlying storage system;

[0112] Full write: The failed data request fills the entire cache line in the data cache.

[0113] The embodiments of the present application do not exhaustively list all the contents included in the invalidation information. The invalidation information may also include control information of other memory access invalidation queues, etc.

[0114] Based on the invalidation information corresponding to the allocated invalidation queue item in the memory invalidation queue, the target processing method of the first memory invalidation request can be determined, wherein the target processing method includes three types. The first is that the allocated invalidation queue item merges the first memory invalidation request. Since the allocated invalidation queue item has received other memory invalidation requests, for example, the second memory invalidation request has been received, the merge processing method is that the allocated invalidation queue item receives the first memory invalidation request, and merges the first memory invalidation request and the second memory invalidation request into one memory invalidation request for processing. It should be noted that the premise of merging the memory invalidation requests is that the two memory invalidation requests meet the merge conditions. The second is that the allocated invalidation queue item refuses to process the first memory invalidation request. Since the allocated invalidation queue item has received other memory invalidation requests, if the memory invalidation request received in the allocated invalidation queue conflicts with the first memory invalidation request, the allocated invalidation queue item refuses to process the first memory invalidation request. The third type is that the allocated invalidation queue entry is not merged and the first memory access invalidation request is not rejected, indicating that the memory access invalidation request received in the allocated invalidation queue entry and the first memory access invalidation request do not meet the merging conditions, but do not conflict with each other.

[0115] S13: Process the first memory access invalidation request based on the target processing mode.

[0116] After determining the target processing method for the first memory access invalidation request, the first memory access invalidation request is processed based on the target processing method. For example, in the case where the target processing method is to merge the allocated invalidation queue item to process the first memory access invalidation request, the allocated invalidation queue item can receive the first memory access invalidation request, merge the first memory access invalidation request with the original memory access invalidation request of the allocated invalidation queue item, obtain the merged memory access invalidation request, and process it. For example, in the case where the target processing method is that the allocated invalidation queue item refuses to process the first memory access invalidation request, the processing of the first memory access invalidation request is suspended first. For example, in the case where the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request, it can be determined whether there is an unassigned invalidation queue item in the memory access invalidation queue. If so, it can be used to receive the first memory access invalidation request and process it.

[0117] The memory access invalidation queue processing method provided by the embodiment of the present application first obtains the first memory access invalidation request currently entering the memory access invalidation queue, and determines the target processing method of the first memory access invalidation request based on the invalidation information corresponding to the allocated invalidation queue item in the memory access invalidation queue, the target processing method is that the allocated invalidation queue item merges the first memory access invalidation request, the allocated invalidation queue item refuses to process the first memory access invalidation request, or the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request; after determining the target processing method, the first memory access invalidation request is processed based on the target processing method. The solution of the embodiment of the present application can flexibly determine the target processing method of the first memory access invalidation request based on the first memory access invalidation request currently entering the memory access invalidation queue and the invalidation information corresponding to the allocated invalidation queue, and determine whether the allocated invalidation queue item merges the processing, refuses the processing, or does not merge the processing and does not refuse to process the first memory access invalidation request, thereby improving the flexibility of memory access invalidation request processing and thus improving the efficiency of memory access invalidation queue processing.

[0118] Based on any of the above embodiments, the solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0119] FIG2 is a schematic diagram of the memory access failure queue processing provided by an embodiment of the present application. As shown in FIG2 , the memory access failure queue in the processor includes N failure queue items, where N is a positive integer, such as 16. Each failure queue item is responsible for receiving failed access requests or storage requests, and retrieving the data that needs to be backfilled from the lower-level storage system (such as the secondary cache), backfilling it to the data cache, and returning the missing access data to the access queue. The memory access failure queue is also responsible for receiving external consistency requests from other processor cores, accessing the data cache, and returning a consistency response to the requesting processor core.

[0120] Load or store instructions can access the data cache. The data cache includes tags, which are used for comparison to determine whether the load or store instruction hits the data cache. If so, the load or store instruction retrieves the data from the data cache. If not, a memory access invalidation request is initiated, accessing the underlying storage system through the memory invalidation queue.

[0121] Taking data access requests as an example, the processing flow of failed data access requests in the access failure queue is as follows:

[0122] (1) Allocate an empty invalidation queue item in the memory access invalidation queue and record relevant invalidation information in the invalidation queue item.

[0123] (2) Determine the replacement way according to the cache replacement algorithm, and judge whether replacement is required based on whether the block where the replacement way is located is valid. If replacement is required, send a replacement request to the data cache.

[0124] (3) Send a get request to the lower-level storage system at the same time as sending a replace request.

[0125] If it is a data access request, a get request needs to be sent to the lower-level storage system at the same time as the replacement request is sent; if it is a data storage request, and it is an overwrite write to the entire cache block, it is necessary to send a get permission request to request write permission. In this case, the data storage instruction will fill the entire cache line, and there is no need to read the original data in the lower-level storage system. The lower-level storage system will save a static random-access memory (SRAM) read operation. Otherwise, a request to get the cache block is sent.

[0126] (4) Wait for the lower-level storage system to return permissions or data permissions.

[0127] Permissions mean obtaining write permissions, excluding data, while data plus permissions include both writing data and write permissions.

[0128] By returning permissions or data plus permissions from the lower-level storage system, it is to confirm that the backups of this cache line in other processor cores have been invalidated so that the write operation can be performed. Otherwise, the other processor cores will have old data.

[0129] (5) If the data access instruction fails, after receiving each data return with data plus permission, the returned data must be forwarded to the memory access failure queue. Because the width of the cache line may be wider than the width of the data return bus, the data may be returned in multiple times.

[0130] (6) After receiving the first data return of the permission or data plus permission, return the permission response to the lower-level storage system.

[0131] (7) After receiving the last data return of the permission or data plus permission, and the replacement request has been completed, send a fill request and wait for a response to complete the data backfill.

[0132] (8) Release the invalidation queue item.

[0133] The processing flow for store requests and retrieval requests is essentially the same, with the difference being that store requests do not need to forward backfilled data to the retrieval queue. Furthermore, after the store request completes the backfill, it returns a response to the store buffer, indicating that the backfill of the cache block is complete and that the cache can now perform write data caching operations.

[0134] The processing status of the memory failure queue for memory failure requests is controlled by a series of status registers. Figure 3 is a schematic diagram of the status register control provided by an embodiment of the present application. As shown in Figure 3, an example of the status registers involved in the processing status of the memory failure queue for memory failure requests and the execution order of the corresponding operations are illustrated.

[0135] The Get Request Status Register records whether a request to get a cache block or a permission request has been sent to the underlying storage system. If a replacement block requires overwriting the entire cache block, only write permission is required. If a cache block get request or permission request has not been sent, this status register is set to 0. If a cache block get request or permission request has been sent, this status register is set to 1.

[0136] Data plus permission first data return response status register: used to record whether the first data return of data plus permission is received. If the first data return of data plus permission is not received, the status register is set to 0; if the first data return of data plus permission is received, the status register is set to 1.

[0137] Data plus permission last data return response status register: used to record whether the data plus permission last data return is received. If the data plus permission last data return is not received, the status register is set to 0; if the data plus permission last data return is received, the status register is set to 1.

[0138] Data return status register: used to record whether a data response is returned to the lower-layer storage system after receiving data returned by the lower-layer storage system. If so, the status register is set to 1; otherwise, the status register is set to 0.

[0139] Replacement Request Status Register: This register records whether a replacement request has been sent to the data cache. Before a memory invalidation request enters the memory invalidation queue, a replacement path is selected based on the cache block replacement algorithm. After entering the memory invalidation queue, the replacement request is sent to the data cache. If no replacement request has been sent to the data cache, this status register is set to 0; if a replacement request has been sent to the data cache, this status register is set to 1.

[0140] Replacement completion status register: used to record whether the replacement operation is completed. If so, the status register is set to 1; if not, the status register is set to 0.

[0141] Data backfill status register: used to record whether the memory access failure request sends data to the data cache for backfill. If so, the status register is set to 1, otherwise, the status register is set to 0.

[0142] Data backfill completion status register: used to record whether data backfill is completed. If so, the status register is set to 1; if not, the status register is set to 0.

[0143] Figure 3 illustrates the relationship between the multiple status registers described above. Different status registers correspond to different events in the memory fail queue, and the events in the memory fail queue are executed sequentially based on certain dependencies. Figure 3 illustrates the transition process between the status registers, with arrows indicating that the event corresponding to the next status register can only be executed after the previous status register is set to 1.

[0144] In the above embodiment, the processing process of the memory access invalidation request in the current memory access invalidation queue is introduced. After the new memory access invalidation request enters the memory access invalidation queue, in some cases it can be determined whether it can be merged with the memory access invalidation request in the allocated queue item to improve the processing efficiency of the processor.

[0145] For the first memory invalidation request currently entering the memory invalidation queue and the second memory invalidation request in the allocated invalidation queue entry, the processor first determines whether the block address of the first memory invalidation request is the same as the block address of the second memory invalidation request in the allocated invalidation queue entry. The block address of the first memory invalidation request is the address of the cache block accessed by the first memory invalidation request in the data cache, and the block address of the second memory invalidation request is the address of the cache block accessed by the second memory invalidation request in the data cache. Based on whether the block addresses of the first memory invalidation request and the second memory invalidation request are the same, the target processing method is determined.

[0146] FIG4 is a flow chart of a target processing method according to an embodiment of the present application, as shown in FIG4 , including:

[0147] S41, when the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request, determine the target processing method based on the acquisition request corresponding to the second memory access invalidation request, the request type of the first memory access invalidation request, and the request type of the second memory access invalidation request.

[0148] When the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request, and the first preset condition or the second preset condition is met, the target processing method is determined to be to merge the allocated invalidation queue items to process the first memory access invalidation request, that is, the first memory access invalidation request and the second memory access invalidation request can be merged.

[0149] The first preset condition is: the acquisition request is not received by the lower storage system, the request type of the first memory access failure request is a data access request or a data storage request, and the second memory access failure request is a data access request or a data storage request.

[0150] The reason why the first memory invalidation request and the second memory invalidation request can be merged when the first preset condition is met is that as long as the acquire request corresponding to the second memory invalidation request has not been received by the lower-layer storage system, that is, the acquire request has not yet completed the handshake, various parameters of the acquire request can be modified. The modifiable parameters include, for example, whether the acquire request corresponds to a retrieve or store operation, and whether a store operation can override a retrieve operation to retrieve a cache block with write permission.

[0151] If the first memory access invalidation request is a data storage request, and the second memory access invalidation request is a data retrieval request or a data storage request, then after the first memory access invalidation request and the second memory access invalidation request are merged, the permission to be obtained in the acquisition request is set to the write permission required for data storage. That is, when the first preset condition is met and the request type of the first memory access invalidation request is a data storage request, the acquisition request corresponding to the second memory access invalidation request is updated to obtain an updated acquisition request, wherein the updated acquisition request is used to request the write permission corresponding to the first memory access invalidation request. By modifying the acquisition request, the write permission can be requested, thereby performing data storage operations based on the acquired write permission. After receiving the backfill data from the lower-level storage system, the backfill data also needs to be sent to the data retrieval queue.

[0152] The second preset condition is: the request type of the first memory access failure request is a data retrieval request, and the request type of the second memory access failure request is a data retrieval request or a data storage request; and, the retrieval request has been received by the lower-level storage system, but no retrieval request response has been received from the lower-level storage system, or the retrieval request response has not been sent to the data retrieval queue.

[0153] The get request response refers to the response returned by the underlying storage system to a received get request. Since the get request is used to request write permission or data permission, the get request response is the write permission or data permission returned by the underlying storage system.

[0154] If the second pre-set condition is met, the first and second memory invalidation requests can be merged because the allocated invalidation queue entry has not yet sent the data to the access queue, and the new access request can be merged in. After the memory invalidation queue receives the backfill data, it wakes up all the access requests waiting for the data in the access queue at once.

[0155] When the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request, and the first preset condition and / or the second preset condition are not met, the target processing method is determined to be that the allocated invalidation queue entry refuses to process the first memory access invalidation request.

[0156] Since the first preset condition and / or the second preset condition are not met, the allocated invalidation queue item can no longer merge the first memory access invalidation request with the same block address, but the data retrieval pipeline and the data storage pipeline cannot be blocked by this memory access invalidation queue, so the allocated invalidation queue item needs to refuse to process the first memory access invalidation request, and the first memory access invalidation request will be resent after waiting for a period of time.

[0157] S42 , when the block address of the first memory access failure request is different from the block address of the second memory access failure request, determine a target processing mode based on the block address of the first memory access failure request and the block address of the second memory access failure request.

[0158] When the block address of the first memory access invalidation request is different from the block address of the second memory access invalidation request, and the block address of the first memory access invalidation request and the block address of the second memory access invalidation request belong to the same cache line, the target processing method is determined to be that the allocated invalidation queue entry refuses to process the first memory access invalidation request.

[0159] In order to write the backfilled data into the data cache immediately after obtaining it from the lower-level storage system, the second memory invalidation request will determine the replacement way before entering the memory invalidation queue. In this way, after obtaining the backfilled data, there is no need to perform another tag comparison before deciding the replacement way. However, if the block addresses of the first memory invalidation request and the second memory invalidation request are located in the same cache line, but the access requests belong to different tags, they are invalidated one after another when accessing the data cache, but the two access requests decide to replace the same way and allocate an invalidation queue entry to each, which will eventually cause the later backfilled block to overwrite the earlier backfilled block. Therefore, it is necessary to set the target processing method to refuse to process the first memory invalidation request if the block address of the first memory invalidation request and the block address of the second memory invalidation request belong to the same cache line, so as to ensure that there are no two identical cache line addresses in the memory invalidation queue.

[0160] When the block address of the first memory access invalidation request is different from the block address of the second memory access invalidation request, and the block address of the first memory access invalidation request and the block address of the second memory access invalidation request do not belong to the same cache line, the target processing method is determined to not merge the allocated invalidation queue items and not refuse to process the first memory access invalidation request.

[0161] In the above embodiment, the process of determining the target processing mode for the first memory access invalidation request is described. After the target processing mode is determined, different target processing modes will result in different processes for processing the first memory access invalidation request, which will be described below.

[0162] If the target processing method is to merge the first memory invalidation request with the allocated invalidation queue entry, data backfill is performed on the first memory invalidation request based on the allocated invalidation queue entry. Specifically, the first memory invalidation request and the second memory invalidation request in the allocated invalidation queue entry are merged into a single memory invalidation request for synchronous processing. The process of backfilling the first memory invalidation request after merging can be found in the memory invalidation request processing process described in the above embodiment and will not be further described here.

[0163] When the target processing mode is that the allocated invalidation queue entry refuses to process the first memory access invalidation request, the first memory access invalidation request is refused to be processed.

[0164] When the target processing method is that the allocated invalidation queue item refuses to process the first memory access invalidation request, it indicates that there is a conflict between the first memory access invalidation request and the second memory access invalidation request in the allocated invalidation queue item. Therefore, the memory access invalidation queue will also refuse to process the first memory access invalidation request and resend the first memory access invalidation request for processing within a period of time.

[0165] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and there are unallocated invalidation queue entries in the memory access invalidation queue, data backfill is performed on the first memory access invalidation request based on the unallocated invalidation queue entries.

[0166] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and there is no unallocated invalidation queue entry in the memory access invalidation queue, the first memory access invalidation request is rejected.

[0167] That is, when the first memory access invalidation request and the second memory access invalidation request in the allocated invalidation queue item do not meet the first preset condition or the second preset condition for merging, and there is no conflict between the first memory access invalidation request and the second memory access invalidation request, whether to process the first memory access invalidation request can be determined based on whether there are still unallocated invalidation queue items in the memory access invalidation queue. If there are still unallocated invalidation queue items in the memory access invalidation queue, the first memory access invalidation request can be received by the unallocated invalidation queue item, and data backfilling can be performed on the first memory access invalidation request based on the unallocated invalidation queue item. If there are multiple unallocated invalidation queue items, a polling mechanism can also be used to allocate corresponding unallocated invalidation queue items to the first memory access invalidation request. The process of backfilling data for the first memory access invalidation request can be referred to the memory access invalidation request processing process in the above embodiment and will not be repeated here. If there are no unallocated invalidation queue items in the memory access invalidation queue, the memory access invalidation queue will refuse to process the first memory access invalidation request and resend the first memory access invalidation request for processing within a period of time.

[0168] For the first memory invalidation request, the memory invalidation queue determines the replacement path when the new invalidation queue entry is allocated, so that backfilling can occur immediately after receiving the block to be backfilled. To achieve this, the data cache needs to perform replacements in advance, at least reading the replacement block before backfilling occurs. Therefore, replacement can be performed immediately after the invalidation queue entry is allocated, that is, the replacement request is sent.

[0169] For performance reasons, it is not desirable to invalidate the replacement block too early, so as to avoid the processor core accessing the replacement block again while accessing the lower-level storage system or even the memory, resulting in a ping-pong effect and generating new unnecessary memory invalidation requests.

[0170] Therefore, before data backfilling, the embodiment of the present application does not invalidate the replacement block. Instead, the data in the replacement block is first read out and temporarily placed in a write-back queue for dormancy. Specifically, the processor first determines the replacement block corresponding to the first memory access invalidation request in the data cache, where the corresponding data is stored. The processor then reads the data in the replacement block into the write-back queue and goes into dormancy. During the dormant period, other memory access invalidation requests can still access the replacement block in the data cache normally. If there is a write to the replacement block, a copy needs to be synchronized to the write-back queue. After obtaining the backfill data corresponding to the first memory access invalidation request from the lower-level storage system, the dormant replacement block in the write-back queue is awakened, and the status of the data in the replacement block in the write-back queue is updated to the awake state. If the data in the replacement block is in the awake state in the write-back queue, the backfill data is backfilled into the replacement block. The write-back queue begins writing the replacement block downward, that is, backfilling the backfill data into the replacement block. Simultaneously, the memory access invalidation queue completes the data backfill, and the replacement block is overwritten during the backfill.

[0171] For data retrieval requests or data storage requests, a replacement path will be selected before entering the memory access failure queue. After obtaining the data returned by the lower-level storage system, it can be sent to the backfill block. Therefore, only one beat is needed to write the backfill data into the data cache without accessing the data cache again.

[0172] In some embodiments, the memory access invalidation queue can also receive scheduling of external consistency requests. The processing flow after the memory access invalidation queue receives the external consistency request from other processor cores is: allocate an empty invalidation queue item for the external consistency request; send the external consistency request to the data cache; wait for the data cache to return a response to the external consistency request; release the invalidation queue item.

[0173] To avoid deadlock between external consistency requests and requests inside the processor core, in the memory access invalidation queue, in addition to the invalidation queue items shared with the fetch request or store request, exclusive invalidation queue items can be reserved for external consistency requests in the memory access invalidation queue. The number can be set as needed, such as 1 item, 2 items, etc.

[0174] Because the external consistency request may be an external consistency listening request caused by a request inside the processor core, if there is no empty item in the memory access invalidation queue (i.e., an unassigned invalidation queue item) to be allocated to the external consistency request, and the invalidation queue items in the memory access invalidation queue that have been occupied by the data access request or the data storage request need to wait for a response before exiting, and the issuance of these responses depends on the processor core's response to the external consistency request, this will cause a deadlock. Therefore, by reserving exclusive invalidation queue items for external consistency requests, deadlock can be effectively avoided. In some embodiments, a consistency request queue independent of the memory access invalidation queue can also be designed to handle external consistency requests.

[0175] There are multiple invalidation queue items in the memory access invalidation queue that can perform the same operation, such as accessing the underlying storage system, filling the data cache, or making consistency requests to the data cache. A queue head can be set for each type of access request. Starting from the queue head of each request, an item in the memory access invalidation queue is selected to issue the corresponding operation, and then the queue head is switched to the next item.

[0176] In some embodiments, each type of access request in the memory invalidation queue includes a corresponding queue head, wherein the types of access requests include requests to access the underlying storage system, requests to fill the data cache, requests for consistency of the data cache, and the like.

[0177] For each type of access request, first, the target invalidation queue item currently pointed to by the queue head corresponding to the access request of that type is determined among the invalidation queue items included in the memory invalidation queue. Then, when determining the invalidation queue item to be issued for each type of access request, starting from the target invalidation queue item for that type of access request, the first invalidation queue item that meets a preset condition is determined among the invalidation queue items included in the memory invalidation queue, wherein the preset condition is that the access request to be issued in the invalidation queue item is an access request of the corresponding type. Then, based on the first invalidation queue item that meets the preset condition, the target access request of the corresponding type is issued, and the invalidation queue item currently pointed to by the queue head corresponding to the access request of that type is updated from the target invalidation queue item to the invalidation queue item next to the target invalidation queue item.

[0178] It should be noted that for any type of access request, the queue head corresponding to this type of access request initially points to the first invalid queue item in the memory access invalid queue. Therefore, in the initialization state, the target invalid queue item is the first invalid queue item in the memory access invalid queue. After the target access request is issued based on the first invalid queue item that meets the preset conditions, the queue head corresponding to this type of access request will point to the next invalid queue item. If the target invalid queue item currently pointed to by the queue head corresponding to this type of access request is the last invalid queue item in the memory access invalid queue, then after the target access request is issued based on the first invalid queue item that meets the preset conditions, the queue head corresponding to this type of access request will point to the first invalid queue item in the memory access invalid queue.

[0179] By using the above method, each invalid queue item can be given an opportunity to issue a request, so as to give each invalid queue item an equal request opportunity, thereby preventing old requests from not being able to be issued for a long time and occupying processor resources.

[0180] In summary, the solution of the embodiment of the present application can flexibly determine the target processing method for the first memory access invalidation request based on the first memory access invalidation request currently entering the memory access invalidation queue and the invalidation information corresponding to the allocated invalidation queue, determine whether to merge the allocated invalidation queue items, reject them, or not merge them and not reject the first memory access invalidation request, merge the memory access invalidation requests that meet the merging conditions, reduce the memory access invalidation queue's access to the lower-level storage system, and improve the processing efficiency and flexibility of the memory access invalidation queue. For the cache replacement block to be replaced by the failed block backfill, a trigger replacement and write-back queue sleep mechanism is provided, which not only avoids the replacement block being invalidated prematurely and generating unnecessary invalidation requests, but also reduces the overhead and time of reading the replacement block.

[0181] The memory access failure queue processing device provided in the present application is described below. The memory access failure queue processing device described below and the memory access failure queue processing method described above can be referenced to each other.

[0182] FIG5 is a schematic structural diagram of a memory access failure queue processing device provided in an embodiment of the present application. As shown in FIG5 , the device includes an acquisition module 51 , a first processing module 52 , and a second processing module 53 .

[0183] An acquisition module 51 is configured to acquire a first memory access failure request currently entering a memory access failure queue;

[0184] a first processing module 52, configured to determine a target processing mode for the first memory access invalidation request based on invalidation information corresponding to an allocated invalidation queue entry in the memory access invalidation queue, wherein the target processing mode is: merging the first memory access invalidation request with the allocated invalidation queue entry, refusing to process the first memory access invalidation request with the allocated invalidation queue entry, or not merging the first memory access invalidation request with the allocated invalidation queue entry and not refusing to process the first memory access invalidation request;

[0185] The second processing module 53 is configured to process the first memory access invalidation request based on the target processing mode.

[0186] In some embodiments, the first processing module 52 is specifically configured to:

[0187] determining whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request in the allocated invalidation queue entry;

[0188] The target processing mode is determined based on whether the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request.

[0189] In some embodiments, the first processing module 52 is specifically configured to:

[0190] determining the target processing mode based on the acquisition request corresponding to the second memory access invalidation request, the request type of the first memory access invalidation request, and the request type of the second memory access invalidation request when the block address of the first memory access invalidation request is the same as the block address of the second memory access invalidation request;

[0191] When the block address of the first memory access invalidation request is different from the block address of the second memory access invalidation request, the target processing mode is determined based on the block address of the first memory access invalidation request and the block address of the second memory access invalidation request.

[0192] In some embodiments, the first processing module 52 is specifically configured to:

[0193] When the first preset condition or the second preset condition is met, determining that the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request;

[0194] If the first preset condition and / or the second preset condition is not satisfied, determining that the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0195] The first preset condition is: the acquisition request is not received by the lower-layer storage system, the request type of the first memory access invalidation request is a data access request or a data storage request, and the second memory access invalidation request is a data access request or a data storage request;

[0196] The second preset condition is: the request type of the first memory access invalidation request is a data retrieval request, and the request type of the second memory access invalidation request is a data retrieval request or a data storage request; and the retrieval request has been received by the lower-level storage system, but no retrieval request response has been received from the lower-level storage system, or the retrieval request response has not been sent to the data retrieval queue.

[0197] In some embodiments, when the first preset condition is met and the request type of the first memory access invalidation request is a data storage request, the first processing module 52 is further configured to:

[0198] An acquisition request corresponding to the second memory access invalidation request is updated to obtain an updated acquisition request, wherein the updated acquisition request is used to request the write permission corresponding to the first memory access invalidation request.

[0199] In some embodiments, the first processing module 52 is specifically configured to:

[0200] When the block address of the first memory access invalidation request and the block address of the second memory access invalidation request belong to the same cache line, determining the target processing manner is that the allocated invalidation queue entry refuses to process the first memory access invalidation request;

[0201] When the block address of the first memory invalidation request and the block address of the second memory invalidation request do not belong to the same cache line, the target processing manner is determined as not merging the allocated invalidation queue entries and not rejecting the first memory invalidation request.

[0202] In some embodiments, the second processing module 53 is specifically configured to:

[0203] When the target processing mode is to merge the allocated invalidation queue entries to process the first memory access invalidation request, backfilling data for the first memory access invalidation request based on the allocated invalidation queue entries;

[0204] If the target processing mode is that the allocated invalidation queue entry refuses to process the first memory access invalidation request, refusing to process the first memory access invalidation request;

[0205] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is an unallocated invalidation queue entry in the memory access invalidation queue, backfilling data for the first memory access invalidation request based on the unallocated invalidation queue entry;

[0206] When the target processing mode is not to merge the allocated invalidation queue entries and not to reject the first memory access invalidation request, and when there is no unallocated invalidation queue entry in the memory access invalidation queue, reject the first memory access invalidation request.

[0207] In some embodiments, the second processing module 53 is specifically configured to:

[0208] Determining a replacement block corresponding to the first memory access invalidation request in the data cache;

[0209] Reading data in the replacement block into a write-back queue;

[0210] After obtaining the backfill data corresponding to the first memory access failure request, the backfill data is backfilled into the replacement block.

[0211] In some embodiments, the data in the replacement block is in a dormant state in the write-back queue, and the second processing module 53 is specifically configured to:

[0212] Updating the state of the data in the replacement block in the write-back queue to a wake-up state;

[0213] When the data in the replacement block is in the awake state in the write-back queue, the backfill data is backfilled into the replacement block.

[0214] In some embodiments, each type of access request in the memory access failure queue includes a corresponding queue head, and the second processing module 53 is further configured to:

[0215] For each type of access request, determining, from the invalidation queue items included in the memory access invalidation queue, a target invalidation queue item currently pointed to by the queue head corresponding to the type of access request;

[0216] Starting from the target invalidation queue entry, determining a first invalidation queue entry that meets a preset condition among the invalidation queue entries included in the memory access invalidation queue, wherein the preset condition is that the access request in the invalidation queue entry is an access request of the type;

[0217] issuing a target access request based on the first invalidation queue entry that meets the preset condition;

[0218] The invalidation queue entry currently pointed to by the queue head corresponding to the access request of the type is updated from the target invalidation queue entry to the next invalidation queue entry of the target invalidation queue entry.

[0219] FIG6 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG6 , the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640. The processor 610, the communication interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 may call logic instructions in the memory 630 to execute a memory invalidation queue processing method, the method comprising: obtaining a first memory invalidation request currently entering a memory invalidation queue; determining a target processing method for the first memory invalidation request based on invalidation information corresponding to an allocated invalidation queue entry in the memory invalidation queue, the target processing method being: merging the first memory invalidation request with the allocated invalidation queue entry, rejecting the first memory invalidation request with the allocated invalidation queue entry, or not merging the first memory invalidation request with the allocated invalidation queue entry and not rejecting the first memory invalidation request; and processing the first memory invalidation request based on the target processing method.

[0220] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0221] On the other hand, the present application also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the memory access invalidation queue processing method provided by the above methods, the method including: obtaining the first memory access invalidation request currently entering the memory access invalidation queue; based on the invalidation information corresponding to the allocated invalidation queue item in the memory access invalidation queue, determining the target processing method for the first memory access invalidation request, the target processing method is that the allocated invalidation queue item merges the first memory access invalidation request, the allocated invalidation queue item refuses to process the first memory access invalidation request, or the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request; based on the target processing method, processing the first memory access invalidation request.

[0222] On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the memory access invalidation queue processing method provided by the above-mentioned methods, the method including: obtaining the first memory access invalidation request currently entering the memory access invalidation queue; determining the target processing method for the first memory access invalidation request based on the invalidation information corresponding to the allocated invalidation queue item in the memory access invalidation queue, the target processing method being that the allocated invalidation queue item merges the first memory access invalidation request, the allocated invalidation queue item refuses to process the first memory access invalidation request, or the allocated invalidation queue item does not merge the processing and does not refuse to process the first memory access invalidation request; processing the first memory access invalidation request based on the target processing method.

[0223] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0224] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for processing a memory access miss queue, comprising: Obtaining a first memory access miss request that currently enters the memory access miss queue; Based on the miss information corresponding to the allocated miss queue entries in the memory access miss queue, determining a target processing method for the first memory access miss request, where the target processing method is that the allocated miss queue entry combines and processes the first memory access miss request, the allocated miss queue entry rejects processing the first memory access miss request, or the allocated miss queue entry neither combines nor rejects processing the first memory access miss request; Processing the first memory access miss request based on the target processing method; Wherein, the determining the target processing method for the first memory access miss request based on the miss information corresponding to the allocated miss queue entries in the memory access miss queue includes: Determining whether the block address of the first memory access miss request is the same as the block address of a second memory access miss request in the allocated miss queue entries; Determining the target processing method based on whether the block address of the first memory access miss request is the same as the block address of the second memory access miss request; The determining the target processing method based on whether the block address of the first memory access miss request is the same as the block address of the second memory access miss request includes: When the block address of the first memory access miss request is the same as the block address of the second memory access miss request, determining the target processing method based on the fetch request corresponding to the second memory access miss request, the request type of the first memory access miss request, and the request type of the second memory access miss request; When the block address of the first memory access miss request is different from the block address of the second memory access miss request, determining the target processing method based on the block address of the first memory access miss request and the block address of the second memory access miss request; The determining the target processing method based on the fetch request corresponding to the second memory access miss request, the request type of the first memory access miss request, and the request type of the second memory access miss request includes: When a first preset condition or a second preset condition is satisfied, determining the target processing method as that the allocated miss queue entry combines and processes the first memory access miss request; When the first preset condition is not satisfied and / or the second preset condition is not satisfied, determining the target processing method as that the allocated miss queue entry rejects processing the first memory access miss request; The first preset condition is: the fetch request has not been received by the lower-level storage system, the request type of the first memory access miss request is a load request or a store request, and the second memory access miss request is a load request or a store request; The second preset condition is: the request type of the first memory access miss request is a load request, the request type of the second memory access miss request is a load request or a store request; and, the fetch request has been received by the lower-level storage system, the fetch request response from the lower-level storage system has not been received, or the fetch request response has not been sent to the load queue.

2. The method according to claim 1, wherein When the first preset condition is satisfied and the request type of the first memory access failure request is a store request, the method further includes: Updating the acquisition request corresponding to the second memory access failure request to obtain an updated acquisition request, where the updated acquisition request is used to request the write permission corresponding to the first memory access failure request.

3. The method according to claim 1, wherein The determining the target processing method based on the block address of the first memory access failure request and the block address of the second memory access failure request includes: When the block address of the first memory access failure request and the block address of the second memory access failure request belong to the same cache line, determining that the target processing method is that the allocated failure queue entry rejects the processing of the first memory access failure request; When the block address of the first memory access failure request and the block address of the second memory access failure request do not belong to the same cache line, determining that the target processing method is that the allocated failure queue entry does not merge and does not reject the processing of the first memory access failure request.

4. The method according to any one of claims 1 to 3, wherein, The processing the first memory access failure request based on the target processing method includes: When the target processing method is that the allocated failure queue entry merges and processes the first memory access failure request, based on the allocated failure queue entry, performing data backfilling on the first memory access failure request; When the target processing method is that the allocated failure queue entry rejects the processing of the first memory access failure request, rejecting the processing of the first memory access failure request; When the target processing method is that the allocated failure queue entry does not merge and does not reject the processing of the first memory access failure request, and there are unallocated failure queue entries in the memory access failure queue, based on the unallocated failure queue entries, performing data backfilling on the first memory access failure request; When the target processing method is that the allocated failure queue entry does not merge and does not reject the processing of the first memory access failure request, and there are no unallocated failure queue entries in the memory access failure queue, rejecting the processing of the first memory access failure request.

5. The method according to claim 4, wherein The performing data backfilling on the first memory access failure request includes: Determining a replacement block corresponding to the first memory access failure request in the data cache; Reading the data in the replacement block into the write-back queue; After obtaining the backfill data corresponding to the first memory access failure request, backfilling the backfill data into the replacement block.

6. The method according to claim 5, wherein, The data in the replacement block is in a dormant state in the write-back queue, and the backfilling the backfill data into the replacement block includes: Updating the state of the data in the replacement block in the write-back queue to a wake-up state; When the data in the replacement block is in a wake-up state in the write-back queue, backfilling the backfill data into the replacement block.

7. The method according to any one of claims 1 to 3, wherein Each type of access request in the memory access failure queue includes a corresponding queue head, and the method further includes: For each type of access request, determining the target failure queue entry currently pointed to by the queue head corresponding to the type of access request among the failure queue entries included in the memory access failure queue; Starting from the target invalid queue entry, determine the first invalid queue entry that meets the preset condition among the invalid queue entries included in the memory access invalid queue, where the preset condition is that the access request in the invalid queue entry is the access request of the type; Based on the first invalid queue entry that meets the preset condition, issue a target access request; Update the invalid queue entry currently pointed to by the queue head corresponding to the access request of the type from the target invalid queue entry to the next invalid queue entry of the target invalid queue entry.

8. A memory access invalid queue processing device, comprising: An acquisition module, configured to acquire a first memory access invalid request that currently enters the memory access invalid queue; A first processing module, configured to determine a target processing mode of the first memory access invalid request based on the invalid information corresponding to the allocated invalid queue entries in the memory access invalid queue, where the target processing mode is that the allocated invalid queue entry merges and processes the first memory access invalid request, the allocated invalid queue entry rejects processing the first memory access invalid request, or the allocated invalid queue entry neither merges nor rejects processing the first memory access invalid request; A second processing module, configured to process the first memory access invalid request based on the target processing mode; Wherein, the first processing module is specifically configured to: Determine whether the block address of the first memory access invalid request is the same as the block address of a second memory access invalid request in the allocated invalid queue entry; Based on whether the block address of the first memory access invalid request is the same as the block address of the second memory access invalid request, determine the target processing mode; The first processing module is specifically configured to: When the block address of the first memory access invalid request is the same as the block address of the second memory access invalid request, determine the target processing mode based on the acquisition request corresponding to the second memory access invalid request, the request type of the first memory access invalid request, and the request type of the second memory access invalid request; When the block address of the first memory access invalid request is different from the block address of the second memory access invalid request, determine the target processing mode based on the block address of the first memory access invalid request and the block address of the second memory access invalid request. The first processing module is specifically configured to: When the first preset condition or the second preset condition is satisfied, determine that the target processing mode is that the allocated invalid queue entry merges and processes the first memory access invalid request; When the first preset condition and / or the second preset condition is not satisfied, determine that the target processing mode is that the allocated invalid queue entry rejects processing the first memory access invalid request; The first preset condition is that the acquisition request is not received by the lower-level storage system, the request type of the first memory access invalid request is a fetch request or a store request, and the second memory access invalid request is a fetch request or a store request; The second preset condition is that: the request type of the first memory access failure request is a fetch request, and the request type of the second memory access failure request is a fetch request or a store request; and, the acquisition request has been received by the lower-level storage system, and an acquisition request response from the lower-level storage system has not been received, or the acquisition request response has not been sent to the fetch queue.

9. The device according to claim 8, wherein, When the first preset condition is satisfied and the request type of the first memory access failure request is a store request, the first processing module is further configured to: Update the acquisition request corresponding to the second memory access failure request to obtain an updated acquisition request, where the updated acquisition request is used to request the write permission corresponding to the first memory access failure request.

10. The device according to claim 8, wherein, Specifically, the first processing module is configured to: When the block address of the first memory access failure request and the block address of the second memory access failure request belong to the same cache line, determine that the target processing method is that the allocated failure queue entry rejects the first memory access failure request; When the block address of the first memory access failure request and the block address of the second memory access failure request do not belong to the same cache line, determine that the target processing method is that the allocated failure queue entry does not merge and does not reject the first memory access failure request.

11. The device according to any one of claims 8-10, wherein Specifically, the second processing module is configured to: When the target processing method is that the allocated failure queue entry merges the first memory access failure request, perform data backfilling on the first memory access failure request based on the allocated failure queue entry; When the target processing method is that the allocated failure queue entry rejects the first memory access failure request, reject the first memory access failure request; When the target processing method is that the allocated failure queue entry does not merge and does not reject the first memory access failure request, and there is an unallocated failure queue entry in the memory access failure queue, perform data backfilling on the first memory access failure request based on the unallocated failure queue entry; When the target processing method is that the allocated failure queue entry does not merge and does not reject the first memory access failure request, and there is no unallocated failure queue entry in the memory access failure queue, reject the first memory access failure request.

12. The apparatus according to claim 11, wherein the second processing module is specifically configured to: Determine a replacement block corresponding to the first memory access failure request in the data cache; Read the data in the replacement block into the write-back queue; After obtaining the backfill data corresponding to the first memory access failure request, backfill the backfill data into the replacement block.

13. The apparatus according to claim 12, wherein the data in the replacement block is in a dormant state in the write-back queue, and the second processing module is specifically configured to: Update the state of the data in the replacement block in the write-back queue to a wake-up state; When the data in the replacement block is in a wake-up state in the write-back queue, backfill the backfill data into the replacement block.

14. The device according to any one of claims 8-10, wherein each type of access request in the memory access miss queue includes a corresponding queue head, and the second processing module is further configured to: For each type of access request, in the miss queue entries included in the memory access miss queue, determine the target miss queue entry currently pointed to by the queue head corresponding to the type of access request; Starting from the target miss queue entry, determine the first miss queue entry that satisfies a preset condition among the miss queue entries included in the memory access miss queue, where the preset condition is that the access request in the miss queue entry is the type of access request; Based on the first miss queue entry that satisfies the preset condition, issue a target access request; Update the miss queue entry currently pointed to by the queue head corresponding to the type of access request from the target miss queue entry to the next miss queue entry of the target miss queue entry.

15. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the memory access miss queue processing method according to any one of claims 1 to 7.

16. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the memory access miss queue processing method according to any one of claims 1 to 7.

17. A computer program product, wherein, The computer program product includes a computer program, the computer program is stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer executes the memory access miss queue processing method according to any one of claims 1 to 7.

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