Data transmission method, communication system and electronic device

Abstract

The embodiments of the present application relate to the technical field of communications. Provided are a data transmission method, a communication system and an electronic device, which are used for reducing the area of a communication system while increasing the number of Ethernet interfaces. The communication system comprises at least one processor core, an aggregation and distribution module and a plurality of interfaces, wherein the at least one processor core is used for sending a first data frame and first indication information to the aggregation and distribution module, the first indication information being used for indicating at least one interface among the plurality of interfaces, and the first data frame being a data frame corresponding to at least one first message; and the aggregation and distribution module is used for sending a first target data frame by means of the at least one interface indicated by the first indication information, the first target data frame being determined by the aggregation and distribution module on the basis of a multiple access control (MAC) protocol and the first data frame.

Description

Data transmission method, communication system and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 29, 2023, with application number 202311868216.5 and application name “A Data Transmission Method, Communication System and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data transmission method, a communication system, and an electronic device. Background Art

[0003] A fieldbus is an industrial data bus used to solve communication problems between different devices in industrial sites. For example, these devices can include intelligent instruments, controllers, and actuators. Industrial Ethernet is a unit network based on the standard Ethernet protocol (IEEE 802.3). Industrial Ethernet uniformly adopts IEEE 802.3 in terms of physical media, number of nodes, distance, bandwidth, parity, and diagnostics. Compared to fieldbus, Industrial Ethernet offers significant advantages in terms of transmission speed, manufacturing cost, and operating cost. Therefore, Industrial Ethernet has replaced fieldbus and is widely used in various fields, such as industrial automation, robot control, robotics, automated production, and other fields requiring communication. With the rapid development of Industrial Ethernet technology, its corresponding communication protocols have also increased. Currently, there are more than 20 recognized communication protocols, the most representative of which include Ethernet Industry Protocol (EtherNet / IP), Ethernet Control Automation Technology (EtherCAT), and Industrial Ethernet Protocol Profinet. However, when Industrial Ethernet technology is applied to chips, the chips may not support all communication protocols, which cannot meet user selection requirements and reduce the user experience.

[0004] Currently, programmable technology enables processor cores to support multiple communication protocols. The processor core sends and receives messages through an interface (for example, a medium independent interface (MII)). The processor core implements the functions of the media access control (MAC) protocol. When the processor is set on a chip, the chip can support multiple communication protocols.

[0005] However, the MAC protocol functions are implemented using processor cores, and the number of processor cores corresponds to the number of MIIs. If one more MII needs to be supported, one more processor core needs to be added, which increases the area and cost of the communication system.

[0006] Summary of the Invention

[0007] The present application provides a data transmission method, a communication system, and an electronic device, which are used to increase the number of Ethernet interfaces while reducing the area of ​​the communication system.

[0008] To achieve the above objectives, this application adopts the following technical solutions:

[0009] In a first aspect, a communication system is provided, which includes: at least one processor core, a convergence and distribution module, and multiple interfaces (for example, may include medium-independent interfaces); the at least one processor core is used to send a first data frame and first indication information to the convergence and distribution module, the first indication information is used to indicate at least one interface among the multiple interfaces, and the first data frame is a data frame corresponding to at least one first message; the convergence and distribution module is used to send a first target data frame through at least one interface indicated by the first indication information, and the first target data frame is determined by the convergence and distribution module based on a multiple access control MAC protocol and the first data frame.

[0010] In the technical solution provided by the present application, when sending at least one first message, at least one processor core sends a first data frame and a first indication information corresponding to at least one first message to the convergence and distribution module. The convergence and distribution module determines the first target data frame based on the multiple access control MAC protocol and the first data frame, and sends the first target data frame through at least one interface indicated by the first indication information among multiple interfaces. The convergence and distribution module implements the function of the MAC protocol. The convergence and distribution module implements the function originally implemented by the processor core, reduces the load of the processor core, and enables at least one processor core to correspond to multiple interfaces. When sending a message, the communication system shown in Figure 1 uses the processor core to directly send the target data frame corresponding to the message through the interface. The processor core implements the function of the MAC protocol, so that one processor core can only correspond to one interface. Since the area and cost of the convergence and distribution module are smaller than the area and cost of the processor core, the technical solution provided by the present application reduces the area and cost of the communication system while increasing the number of interfaces; further, when the communication system is integrated on a chip, the area of ​​the chip is correspondingly reduced.

[0011] In one possible implementation of the first aspect, the convergence and distribution module includes a convergence and distribution circuit; the convergence and distribution circuit is configured to determine a first target data frame based on a MAC protocol and a first data frame; and is further configured to send the first target data frame via at least one interface. In this possible implementation, the convergence and distribution circuit implements not only the convergence and distribution function but also the MAC function, thereby reducing the processor core load.

[0012] In one possible implementation of the first aspect, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, wherein the multiple digital circuits correspond one-to-one to multiple interfaces. The convergence and distribution circuit is configured to send a first data frame to the digital circuit corresponding to at least one interface based on first indication information. The digital circuit is further configured to determine a first target data frame based on a MAC protocol and the first data frame. The digital circuit is further configured to send the first target data frame via at least one interface. In this possible implementation, the convergence and distribution function is implemented by the convergence and distribution circuit, and the MAC function is implemented by the digital circuit, thereby improving the efficiency of the communication system.

[0013] In a possible implementation of the first aspect, the interface includes a medium-independent interface. In the above possible implementation, the physical layer connected to the medium-independent interface can support different media types.

[0014] In one possible implementation of the first aspect, the first target data frame includes multiple data frames, and the length of each of the multiple data frames is greater than or equal to the first threshold. In this possible implementation, the length of each data frame conforms to the MAC protocol, thereby improving transmission rate and efficiency.

[0015] In one possible implementation of the first aspect, the communication system further includes: multiple physical layers, each corresponding to a plurality of interfaces; and a convergence and distribution module specifically configured to send the first target data frame to the corresponding physical layer via at least one interface. In this possible implementation, each interface corresponds to a physical layer, thereby improving transmission efficiency.

[0016] In one possible implementation of the first aspect, at least one processor core includes a reduced instruction set computer (RISC). In this possible implementation, the RISC has advantages such as small area, low cost, and low power consumption. Incorporating the RISC into a communication system reduces the area, cost, and power consumption of the communication system.

[0017] In one possible implementation of the first aspect, the at least one processor core is further configured to obtain at least one first message and process the at least one first message to obtain a first data frame. In this possible implementation, generating the first data frame by the processor core means that the processor core implements a portion of the MAC functionality, thereby reducing the area of ​​the communication system.

[0018] In a second aspect, a communication system is provided, which includes: at least one processor core, a convergence and distribution module and multiple interfaces (for example, it may include a medium-independent interface); the convergence and distribution module is used to receive a second data frame through each interface of the multiple interfaces, and the second data frame is a data frame corresponding to at least one second message; the convergence and distribution module is also used to store a second target data frame and send a second indication information to at least one processor core, and the second indication information is used to instruct at least one processor core to read the second target data frame from the convergence and distribution module, and the second target data frame is determined by the convergence and distribution module according to the multiple access control MAC protocol and the second data frame.

[0019] In the technical solution provided by the present application, when receiving at least one second message, the aggregation and distribution module receives the second data frame corresponding to the at least one second message through the interface, and determines the second target data frame according to the multiple access control MAC protocol and the second data frame. The aggregation and distribution module stores the second target data frame and sends a second indication information to at least one processor core. The aggregation and distribution module implements the function of the MAC protocol. The aggregation and distribution module implements the function originally implemented by the processor core, reduces the load of the processor core, and enables at least one processor core to correspond to multiple interfaces. When the communication system shown in Figure 1 receives the message, the processor core directly receives and processes the data frame through the interface to obtain the target data frame, that is, the processor core is used to implement the function of the MAC protocol, so that one processor core can only correspond to one interface. Since the area and cost of the aggregation and distribution module are smaller than the area and cost of the processor core, the technical solution provided by the present application reduces the area and cost of the communication system while increasing the number of interfaces; further, when the communication system is integrated on the chip, the area of ​​the chip is correspondingly reduced.

[0020] In one possible implementation of the second aspect, the convergence and distribution module includes a convergence and distribution circuit; the convergence and distribution circuit is configured to receive the second data frame through each of the multiple interfaces; the convergence and distribution circuit is further configured to determine a second target data frame based on the MAC protocol and the second data frame; the convergence and distribution circuit is further configured to store the second target data frame and send second indication information to at least one processor core. In this possible implementation, the convergence and distribution circuit implements not only the convergence and distribution function but also the MAC function, thereby reducing the load on the processor cores.

[0021] In one possible implementation of the second aspect, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, each corresponding to a plurality of interfaces. The digital circuit is configured to receive a second data frame through the corresponding interface. The digital circuit is configured to determine a second target data frame based on the MAC protocol and the second data frame. The convergence and distribution circuit is further configured to store the plurality of second target data frames and send second indication information to at least one processor core. In this possible implementation, the convergence and distribution function is implemented by the convergence and distribution circuit, and the MAC function is implemented by the digital circuit, thereby improving the efficiency of the communication system.

[0022] In a possible implementation of the second aspect, the interface includes a medium-independent interface. In the above possible implementation, the physical layer connected to the medium-independent interface can support different media types.

[0023] In one possible implementation of the second aspect, the second target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to the first threshold. In the above possible implementation, the length of each data frame is made to comply with the MAC protocol, thereby improving transmission rate and efficiency.

[0024] In one possible implementation of the second aspect, the communication system further includes multiple physical layers, each corresponding to a plurality of interfaces. The aggregation and distribution module is further configured to receive, via the interface, a second data frame from the corresponding physical layer. In this possible implementation, each interface corresponds to a physical layer, thereby improving transmission efficiency.

[0025] In one possible implementation of the second aspect, at least one processor core includes a reduced instruction set computer (RISC). In this possible implementation, the RISC has advantages such as small size, low cost, and low power consumption. Incorporating the RISC into a communication system reduces the area, cost, and power consumption of the communication system.

[0026] In a possible implementation manner of the second aspect, at least one processor core is configured to read a second target data frame from the convergence and distribution module based on the second indication information, and process the second target data frame to obtain at least one second message.

[0027] In a possible implementation of the second aspect, the convergence and distribution module is further configured to forward the second target data frame to at least one of the multiple interfaces according to preset information, where the preset information includes at least one interface. In the above possible implementation, forwarding efficiency is improved.

[0028] In a third aspect, a data transmission method is provided, which is applied in a communication system, wherein the communication system includes: at least one processor core, a convergence and distribution module, and multiple interfaces; at least one processor core sends a first data frame and first indication information to the convergence and distribution module, where the first indication information is used to indicate at least one interface among the multiple interfaces, and the first data frame is a data frame corresponding to at least one first message; the convergence and distribution module sends a first target data frame through at least one interface indicated by the first indication information, and the first target data frame is determined by the convergence and distribution module based on the multiple access control MAC protocol and the first data frame.

[0029] In a possible implementation of the third aspect, the convergence and distribution module includes a convergence and distribution circuit, and the convergence and distribution module sends the first target data frame through at least one interface, including: the convergence and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame; the convergence and distribution circuit sends the first target data frame through at least one interface.

[0030] In a possible implementation of the third aspect, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, the multiple digital circuits correspond one-to-one to the multiple interfaces, and the convergence and distribution module sends the first target data frame through at least one interface indicated by the first indication information, including: the convergence and distribution circuit sends the first data frame to the digital circuit corresponding to the at least one interface according to the first indication information; the digital circuit determines the first target data frame according to the MAC protocol and the first data frame; and the digital circuit sends the first target data frame through at least one interface.

[0031] In a possible implementation manner of the third aspect, the interface includes a medium-independent interface.

[0032] In a possible implementation manner of the third aspect, the first target data frame includes multiple data frames, and a length of each data frame in the multiple data frames is greater than or equal to a first threshold.

[0033] In a possible implementation of the third aspect, the communication system also includes multiple physical layers, the multiple physical layers correspond one-to-one to the multiple interfaces, and the aggregation and distribution module sends the first target data frame through at least one interface, including: the aggregation and distribution module sends the first target data frame to the corresponding physical layer through at least one interface.

[0034] In a possible implementation of the third aspect, at least one processor core includes a reduced instruction set computer.

[0035] In a possible implementation manner of the third aspect, the method further includes: at least one processor core acquiring at least one first message, and processing the at least one first message to obtain a first data frame.

[0036] In a fourth aspect, a data transmission method is applied to a communication system, and the communication system includes: at least one processor core, a convergence and distribution module and multiple interfaces; for each of the multiple interfaces, the convergence and distribution module receives a second data frame through the interface, and the second data frame is a data frame corresponding to at least one second message; the convergence and distribution module stores the second target data frame and sends a second indication information to at least one processor core, and the second indication information is used to instruct at least one processor core to read the second target data frame from the convergence and distribution module, and the second target data frame is determined by the convergence and distribution module according to the multiple access control MAC protocol and the second data frame.

[0037] In a possible implementation of the fourth aspect, the convergence and distribution module includes a convergence and distribution circuit, which receives the second data frame through an interface, including: the convergence and distribution circuit receives the second data frame through the interface; the convergence and distribution module stores the second target data frame and sends second indication information to at least one processor core, including: the convergence and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; the convergence and distribution circuit stores the second target data frame and sends the second indication information to at least one processor core.

[0038] In a possible implementation of the fourth aspect, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, the multiple digital circuits correspond one-to-one to multiple interfaces, and the convergence and distribution module receives the second data frame through the interface, including: the digital circuit corresponding to the interface receives the second data frame through the interface; the convergence and distribution module stores the second target data frame and sends second indication information to at least one processor core, including: the digital circuit determines the second target data frame according to the MAC protocol and the second data frame; the convergence and distribution circuit stores the second target data frame and sends the second indication information to at least one processor core.

[0039] In a possible implementation manner of the fourth aspect, the interface includes a medium-independent interface.

[0040] In a possible implementation manner of the fourth aspect, the second target data frame includes multiple data frames, and a length of each data frame in the multiple data frames is greater than or equal to a first threshold.

[0041] In a possible implementation of the fourth aspect, the communication system also includes multiple physical layers, the multiple physical layers correspond one-to-one to the multiple interfaces, and the aggregation and distribution module receives the second data frame through the interface, including: the aggregation and distribution module receives the second data frame from the corresponding physical layer through the interface.

[0042] In a possible implementation of the fourth aspect, at least one processor core includes a reduced instruction set computer.

[0043] In a possible implementation manner of the fourth aspect, the method further includes: at least one processor core reading a second target data frame from the convergence and distribution module based on the second indication information, and processing the second target data frame to obtain at least one second message.

[0044] In a possible implementation manner of the fourth aspect, the method further includes: the aggregation and distribution module forwarding the second target data frame to at least one interface among the multiple interfaces according to preset information, where the preset information includes at least one interface.

[0045] In a fifth aspect, an electronic device is provided, which includes a communication system and a memory, the memory being used to store computer instructions, the communication system including at least one processor core and a convergence and distribution module, the communication system being such as the communication system provided by the first aspect or any possible implementation of the first aspect, or the communication system provided by the second aspect or any possible implementation of the second aspect.

[0046] In a sixth aspect, a computer-readable storage medium is provided, which stores computer instructions. When the computer instructions are executed on a communication system, the communication system executes the data transmission method provided by the third aspect or any possible implementation of the third aspect, or the data transmission method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0047] In the seventh aspect, a computer program product comprising instructions is provided. When the computer program product is run on a communication system, the communication system executes the data transmission method provided by the third aspect or any possible implementation of the third aspect, or the data transmission method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0048] It can be understood that the data transmission method, electronic device, computer-readable storage medium and computer program product provided above, and the device or equipment for executing the transmission method all include all the features of the above-mentioned communication system. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding communication system provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0050] FIG2 is a schematic diagram of the structure of a communication system provided in an embodiment of the present application;

[0051] FIG3 is a flow chart of a data transmission method provided in an embodiment of the present application;

[0052] FIG4 is a schematic diagram of the structure of another communication system provided in an embodiment of the present application;

[0053] FIG5 is a schematic structural diagram of another communication system provided in an embodiment of the present application;

[0054] FIG6 is a schematic diagram of the structure of another communication system provided in an embodiment of the present application;

[0055] FIG7 is a schematic structural diagram of another communication system provided in an embodiment of the present application;

[0056] FIG8 is a schematic diagram of the structure of another communication system provided in an embodiment of the present application;

[0057] FIG9 is a schematic structural diagram of another communication system provided in an embodiment of the present application;

[0058] FIG10 is a schematic diagram of the structure of another communication system provided in an embodiment of the present application;

[0059] FIG11 is a schematic structural diagram of another communication system provided in an embodiment of the present application;

[0060] FIG12 is a schematic diagram of the structure of another communication system provided in an embodiment of the present application;

[0061] FIG13 is a flowchart of another data transmission method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] In this application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. In addition, the embodiments of this application use words such as "first" and "second" to distinguish between identical or similar items with substantially the same function and effect. For example, the first threshold and the second threshold are merely to distinguish different thresholds and do not define their order of precedence. Those skilled in the art will understand that words such as "first" and "second" do not define the quantity or execution order.

[0063] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] Before introducing the embodiments of the present application, the relevant knowledge of Ethernet is first explained.

[0065] Open Systems Interconnect (OSI) is a network interconnection model. The OSI model consists of a seven-layer framework (physical layer, data link layer, network layer, transport layer, session layer, presentation layer, and application layer). The first layer is the physical layer, and so on, and the seventh layer is the application layer. The following describes the physical layer and data link layer involved in the embodiments of this application.

[0066] The physical layer (PHY), the lowest layer in the OSI model, is used to transmit bit streams between computer nodes. For example, PHY can include network cards, network cables, Ethernet cables, and hubs. PHY is also called the port physical layer. PHY chips implement the PHY layer's functions and can be used to send and receive Ethernet data frames. Network devices are connected to each other through PHY chips.

[0067] The data link layer (DLL) includes logical link control (LLC) and media access control (MAC). For example, DLA can include bridges and switches. MAC can be used to generate and receive data frames, as well as control and connect PHY. LLC can be used to connect to the network layer. The MAC protocol is a link layer protocol that defines the Ethernet transmission rate (the transmission rate refers to the maximum transmission rate), transmission mode, the format of the data frame in the data link layer, the length of the data frame, the filling method of the data frame, and the abnormality check of the data frame. The MAC protocol can be used to determine whether the data frame can be sent. Among them, the transmission mode includes half-duplex mode and full-duplex mode. In half-duplex mode, sending and receiving cannot be carried out in parallel, while in full-duplex mode, sending and receiving can be carried out simultaneously.

[0068] The medium independent interface (MII), also known as the media independent interface, consists of a data interface and a management interface between the MAC and the PHY. The data interface consists of two independent channels, one for the transmitter and one for the receiver, each with its own data, clock, and control signals. The management interface is a dual-signal interface, one for the clock signal and the other for the data signal. Through the management interface, higher-level modules can monitor and control the PHY. The MII is also known as the Ethernet interface.

[0069] Optionally, MII may include multiple derivative interfaces, such as gigabit medium independent interface (GMII), serial gigabit medium independent interface (SGMII), reduced media independent interface (RMII) and reduced gigabit media independent interface (RGMII).

[0070] A fieldbus is an industrial data bus used to solve communication problems between different devices in industrial sites. For example, these devices can include intelligent instruments, controllers, and actuators. Industrial Ethernet is a unit network based on the standard Ethernet protocol (IEEE 802.3). This means that Industrial Ethernet uniformly adopts IEEE 802.3 in terms of physical media, number of nodes, distance, bandwidth, parity, and diagnostics. Compared to fieldbus, Industrial Ethernet offers significant advantages in terms of transmission speed, manufacturing cost, and operating cost. Therefore, Industrial Ethernet has replaced fieldbus and is widely used in various fields, such as industrial automation, robot control, robotics, automated production, and other fields requiring communication. With the rapid development of Industrial Ethernet technology, the number of corresponding communication protocols has also increased. Currently, there are over 20 recognized communication protocols, the most representative of which include EtherCAT, Profinet, and EtherNet / IP. However, when Industrial Ethernet technology is applied to chips, the chips may not support all communication protocols, which may not meet user selection requirements and reduce the user experience.

[0071] Currently, programmable technology enables communication systems to support multiple communication protocols, meeting user preferences. Figure 1 is a schematic diagram of the structure of a communication system 10. As shown in Figure 1, communication system 10 includes three processor cores. For example, the three processor cores may include a central processing unit (CPU) core 101, programmable real-time units (PRUs) 102 and 103, memory 104, an interface 105, and two physical layers (PHYs) 106 and 107. Interface 105 includes two medium independent interfaces (MIIs) whose identification information can be represented as MII 0 and MII 1, respectively, and four multiplexers: multiplexer 108 to multiplexer 111, each PRU corresponds to an MII (for example, PRU103 corresponds to MII 0, PRU104 corresponds to MII 1), and each MII has a corresponding receive (RX) channel and transmit (TX) channel, for example, MII 0 includes a receive channel MII 0RX and a transmit channel MII 0TX, and MII 1 includes a receive channel MII 1RX and a transmit channel MII 1TX. Among them, each receive channel can be used to receive data signals from each PHY; each transmit channel can be used to send data signals to each PHY, and each multiplexer can be used to merge multiple data signals into one data signal; each PRU can be used to support different communication protocols with different software, that is, each PRU uses programmable technology to enable each processor core to support different communication protocols. Each PRU accesses and controls each PHY through the corresponding MII and reads and writes to the shared memory 102. In the communication system shown in Figure 1, the functions of two medium access control (MAC) protocols are implemented by two processor cores PRU102 and PRU103, and one processor core (PRU) corresponds to one MII. Optionally, the MII can also be called an Ethernet interface, and the PRU can be a 32-bit reduced instruction set computer (RISC) operating at a frequency of 200MHz to 25MHz. Figure 1 only shows a partial structure of the communication system, and the communication system shown in Figure 1 can be set on a chip.

[0072] However, the MAC protocol functions are implemented using processor cores, and the number of processor cores corresponds to the number of MIIs. If one more Ethernet interface needs to be supported, one more processor core needs to be added, which increases the area and cost of the communication system.

[0073] Based on this, an embodiment of the present application provides a data transmission method, which is applied to a communication system, wherein the communication system includes at least one processor core, a convergence and distribution module, and multiple interfaces, wherein each of the multiple interfaces may include an MII or a derivative interface of the MII. In the communication system, when sending at least one first message, at least one processor core sends a first data frame and first indication information corresponding to at least one first message to the convergence and distribution module, the convergence and distribution module determines a first target data frame according to the MAC protocol and the first data frame, and the convergence and distribution module sends the first target data frame through at least one interface indicated by the first indication information among the multiple interfaces. The convergence and distribution module can implement the function of the MAC protocol, and the convergence and distribution module implements the function originally implemented by the processor core, reducing the load of the processor core, so that at least one processor core can correspond to multiple interfaces. Since the area and cost of the convergence and distribution module are smaller than the area and cost of the processor core, compared with the processor core implementing the function of the MAC protocol in Figure 1 and one processor core can only correspond to one interface, the solution provided by the embodiment of the present application increases the number of interfaces while reducing the area and cost of the communication system.

[0074] The method provided in the embodiment of the present application can be applied to a communication system having a convergence and distribution module. The structure of the communication system is described below.

[0075] Figure 2 is a schematic diagram of the structure of a communication system provided by an embodiment of the present application. The communication system includes a memory, at least one processor core, a convergence and distribution module, multiple interfaces, multiple PHYs, and a bus. The multiple interfaces correspond to the multiple PHYs in a one-to-one manner. For example, the number of multiple interfaces can be greater than the number of at least one processor core. Figure 2 takes the example of multiple interfaces including n interfaces and multiple PHYs including n PHYs, where n is a positive integer.

[0076] The memory can be used to store data, software programs, and software modules; it mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system and application programs required for at least one function, such as a data frame forwarding function or a data frame scheduling function; the data storage area can store data created according to the use of the communication system, such as data frames. For example, the memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous-link dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM). In embodiments of the present application, the memory may be a shared memory of the communication system.

[0077] The at least one processor core may include one processor core or multiple processor cores, which may also be referred to as processing cores or cores. When the at least one processor core includes multiple processor cores, the multiple processor cores may be processor cores in the same processor or in different processors. For example, the processor may be a CPU, a microprocessor, other general-purpose processors, a digital signal processor (DSP), and a neural network processing unit (NPU).

[0078] In addition to being used to implement the aggregation and distribution functions, the convergence and distribution module is also used to implement part or all of the MAC functions. The MAC functions include functions defined by the MAC protocol, such as data frame generation, data frame scheduling, data frame length check, data frame check, and data frame padding. The convergence and distribution module is also used to store data frames. Optionally, the convergence and distribution module is also used to send data frames to the PHY through an interface, or to receive data frames from the PHY through an interface. The convergence and distribution module is also used to receive first indication information, and the first indication information is used to indicate at least one interface. The convergence and distribution module is also used to send second indication information to the processor core, and the second indication information is used to instruct the processor core to read a second target data frame. The second target data frame is a data frame corresponding to at least one second message. In the embodiments of the present application, the convergence and distribution module is used as an example to implement part of the MAC function.

[0079] The interface can be the MII described above or a derivative interface of MII. MII or its derivative interfaces can be collectively referred to as a medium-independent interface. For detailed descriptions of the interface and PHY, please refer to the above and will not be repeated here.

[0080] The bus may include an address bus, a data bus, a control bus, and the like. Data (including data frames) are transmitted between the above components (such as memory, at least one processor core, a convergence and distribution module, an interface, and a PHY) via the bus. For example, the bus may be a 32-bit bus. However, for the sake of clarity, various buses are labeled as buses in the figure. The bus may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), and the like.

[0081] In one possible embodiment, at least one processor core, a convergence and distribution module, multiple interfaces, and a bus are integrated on a single chip, and each of the multiple PHYs is integrated on a separate chip. In another possible embodiment, the memory may be a cache, and the memory, at least one processor core, a convergence and distribution module, multiple interfaces, and a bus are integrated on a single chip, and each of the multiple PHYs is integrated on a separate chip. This embodiment of the present application does not specifically limit this.

[0082] The communication system may be an electronic device or a system on chip (SoC) applied to an electronic device. The electronic device may be used as a terminal device or as a server, such as a server at an industrial site. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptop computers, desktop computers, PDAs, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, camcorders, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as intelligent robots, hot air balloons, drones, airplanes), etc.

[0083] Figure 3 is a flowchart of a data transmission method provided in an embodiment of the present application. The method can be applied to the communication system provided above. The communication system includes: at least one processor core, a convergence and distribution module and multiple interfaces. The method includes the following steps.

[0084] S301: At least one processor core sends a first data frame and first indication information to a convergence and distribution module, where the first indication information is used to indicate at least one interface among a plurality of interfaces, and the first data frame is a data frame corresponding to at least one first message.

[0085] Specifically, at least one processor core may send the first data frame and the first indication information to the aggregation and distribution module via a bus. For example, the bus may include a 32-bit bus.

[0086] When multiple processor cores send the first data frame and the first indication information to the convergence and distribution module, the multiple processor cores can be processor cores in the same processor or processing cores in different processors. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core can all be processor cores in a CPU, or the first processor core and the second processor core can be processor cores in a CPU, and the third processor core can be a processor core in an NPU. This embodiment of the present application does not specifically limit this.

[0087] In addition, the processor core may also include a reduced instruction set computer (RISC). For example, the RISC may include a PRU and a deterministic realtime unit (DRU). In one possible embodiment, the processor core may be a 32-bit RISC operating at a frequency of 200 MHz to 400 MHz. The processor core may also be referred to as a RISC core or a RISC real-time core. In actual applications, the processor core may implement different functions by running different programs. That is, the functions of the processor core are programmable. For example, the processor core may implement a sending function by running a sending program, and the processor core may also implement a receiving function by running a receiving program.

[0088] Optionally, when the at least one processor core includes multiple processor cores, the multiple processor cores may be the same processor core or different processor cores. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core, and the first processor core, the second processor core, and the third processor core may all be RISC cores; or, the first processor core and the second processor core may be RISC cores, and the third processor core may be a CPU core. This is not specifically limited by the embodiments of the present application.

[0089] Furthermore, for each of the multiple interfaces, the interface may include an MII or an interface derived from MII, such as GMII, SGMII, RMII, and RGMII, etc. MII or interfaces derived from MII are collectively referred to as media-independent interfaces. The embodiments of the present application do not specifically limit the number of interfaces and the number of processor cores. For example, the number of interfaces may be greater than the number of processor cores. For example, the multiple interfaces may include n interfaces, and the at least one processor core may include m processor cores, where n is greater than m, and n and m are positive integers. In actual applications, the number n is related to the performance of the m processor cores, and can be specifically set based on actual needs or the experience of relevant staff. The embodiments of the present application do not specifically limit this.

[0090] In addition, the at least one first message may include one first message or multiple first messages. For example, the at least one first message may include 20 first messages. The at least one first message may also be referred to as Ethernet data at or above the third layer (network layer).

[0091] In one possible embodiment, before step S301, at least one processor core obtains at least one first message and processes the at least one first message to obtain a first data frame. For example, the at least one processor core may execute a software upper-layer protocol stack and an application program to obtain the at least one first message. The at least one first message may be a message from a sampler or sensor at an industrial site. Optionally, the at least one processor may receive third indication information and, using the third indication information, obtain the at least one first message from a memory or other storage area. The third indication is used to instruct the at least one processor to obtain the at least one first message from the memory or other storage area.

[0092] In one possible embodiment, assuming that at least one processor core includes one processor core, the processor core processes at least one first message to obtain a first data frame, specifically including: for each first message in the at least one first message, the processor core parses the first message, determines the type of the first message, and splits the first message according to the length corresponding to the type of the first message to obtain multiple sub-data. For each sub-data in the multiple sub-data, the processor core assembles the sub-data to obtain a data frame, wherein the data frame includes a frame header, sub-data, and a frame trailer. The frame header and frame trailer include some necessary control information, for example, the frame header may include a destination MAC address, a source MAC address, and a protocol type, and the frame trailer may include information such as a data frame check sequence (check code). Similarly, the processor core assembles the remaining multiple sub-data to obtain multiple data frames, thereby obtaining a first data frame corresponding to the at least one first message. Exemplarily, when the at least one message includes one message, the multiple data frames corresponding to the first message are first data frames. Different types of messages have different lengths. The length of each data frame complies with the length specified by the MAC protocol. For example, the MAC protocol specifies that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes.

[0093] Since the at least one processor core may include different numbers of processor cores, when the number of processor cores is different, different processor cores acquire the first message and send the first data frame.

[0094] In a first possible embodiment, the at least one processor core includes one processor core.

[0095] As an example, a schematic diagram of the structure of the communication system is shown in Figure 4. In this case, the processor core obtains at least one first message and sends a first data frame. Figure 4 takes the communication system including two interfaces as an example. In this embodiment, one processor core can correspond to multiple interfaces, increasing the number of interfaces while reducing the area and cost of the communication system. When some components of the communication system (e.g., at least one processor core, convergence and distribution module, interface, and bus) are placed on a chip, the chip area and cost are reduced.

[0096] In a second possible embodiment, the at least one processor core includes a first processor core and a second processor core. Optionally, the first processor core and the second processor core may be processor cores in the same processor or in different processors. Different situations are described below.

[0097] In the first case, the first processor core and the second processor core are processor cores in the same processor. The first processor core can be used to obtain at least one first message and send a first data frame. The first processor core can also be called a transmitting (TX) core. The second processor core can be used to read a second data frame from the convergence and distribution module. The second data frame is a data frame corresponding to at least one second message. The second processor core can also be called a receiving (RX) core. In this case, the structural diagram of the communication system is shown in Figure 5. Optionally, the transmitting core and the receiving core can be specified by software running on the communication system. Figure 5 takes the communication system including n interfaces as an example. In this embodiment, the first processor core is set as the transmitting core and the second processor core is set as the receiving core, which reduces the difficulty of software programming in the processor cores (including the first processor core and the second processor core).

[0098] In the second case, the first processor core and the second processor core are processor cores in different processors. For example, the structure of the communication system is shown in FIG6 . The first processor core can be used to obtain at least one first message and write the at least one first message to a memory. The first processor core is also used to send fourth indication information to the second processor core. The fourth indication information is used to instruct the second processor core to read at least one first message from the memory. The second processor core reads and processes the at least one first message from the memory based on the fourth indication information to obtain a first data frame. The second processor core is also used to send the first data frame to the convergence and distribution module. FIG6 takes the communication system including n interfaces as an example.

[0099] In the third case, the first processor core and the second processor core can be processor cores in the same processor or in different processors. For example, as shown in Figure 7 , both the first processor core and the second processor core can be used to obtain the first message and send the first data frame. In this embodiment, the use of two processor cores corresponding to multiple interfaces improves processor processing efficiency. Figure 7 uses a communication system including n interfaces as an example.

[0100] In a third possible embodiment, the at least one processor core includes a first processor core, a second processor core, and a third processor core. The first processor core is a transmitting core, and the second processor core is a receiving core. The first processor core and the second processor core are processor cores in the same processor. The first processor core and the third processor core can be processor cores in the same processor or in different processors. For example, as shown in FIG8 , the third processor core can be configured to obtain at least one first message and write the at least one first message to a memory. The third processor core is further configured to send fifth indication information to the first processor core, the fifth indication information being configured to instruct the first processor core to read the at least one first message from the memory. The first processor core reads and processes the at least one first message from the memory based on the fifth indication information to obtain a first data frame. The first processor core transmits the first data frame, and the second processor core is configured to read a second data frame from the convergence and distribution module. Optionally, the transmitting core and the receiving core can be specified by software running on the communication system. For example, the transmitting core and the receiving core can be specified by a program running on the third processor core. FIG8 illustrates an example of a communication system including four interfaces.

[0101] In a fourth possible embodiment, the at least one processor core includes multiple first processor cores, multiple second processor cores, and a third processor core. The multiple first processor cores may also be referred to as a transmitting core cluster, and the multiple second processor cores may also be referred to as a receiving core cluster. In this case, the structural diagram of the communication system is shown in FIG9 . The functions of the processor cores in FIG9 are similar to those of the processor cores shown in FIG8 , and are not further described here. FIG9 illustrates an example of a communication system including n interfaces.

[0102] In the four possible embodiments described above, the functions of the memory, interface, and convergence and distribution module included in the communication system are similar to those of the memory, interface, and convergence and distribution module included in the communication system shown in Figure 2 and are not further described here. In the four possible embodiments described above, when at least one processor core includes multiple processor cores, the multiple processor cores utilize memory and a bus to implement communication between the multiple processor cores. For example, the bus may include a 32-bit bus.

[0103] Furthermore, at least one processor core sends (schedules) the first data frame to the convergence and distribution module, specifically including: at least one processor core sends the first data frame according to the priority of at least one first message. In actual applications, the first data frame can be sent through multiple beats, with multiple data frames sent in each beat, and multiple data frames corresponding to the first message with a high priority are sent first. Optionally, at least one processor core can also send (schedule) the first data frame according to queue management (i.e., the first-in-first-out principle), or at least one processor core can also send (schedule) the first data frame according to a fixed time period. The embodiments of the present application do not make specific limitations on this.

[0104] Furthermore, the method provided in the embodiment of the present application also includes:

[0105] S302: The convergence and distribution module sends a first target data frame through at least one interface indicated by the first indication information. The first target data frame is determined by the convergence and distribution module according to the multiple access control MAC protocol and the first data frame.

[0106] In one possible embodiment, the convergence and distribution module includes a convergence and distribution circuit. In conjunction with Figure 8 , a schematic diagram of the communication system structure is shown in Figure 10 . The convergence and distribution module transmits a first target data frame via at least one interface, including: determining the first target data frame based on the MAC protocol and the first data frame by the convergence and distribution circuit; and transmitting the first target data frame via the at least one interface by the convergence and distribution circuit. The convergence and distribution circuit implements convergence and distribution functions, as well as some functions of the MAC protocol.

[0107] Specifically, the convergence and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame, including: the convergence and distribution circuit checks whether the length of each data frame in the first data frame meets the length range defined according to the MAC protocol, for example, the MAC protocol defines the minimum length of the data frame as 64 bytes and the maximum length as 1518 bytes. If a data frame does not meet the length range defined by the MAC protocol, for example, the length of a data frame is less than 64 bytes, then the convergence and distribution circuit fills the data frame according to the filling content defined by the MAC protocol, so that the length of the filled data frame is equal to 64 bytes; the convergence and distribution circuit is also used to check each data frame, and use the check code included in the end of each data frame to check the data frame, for example, use the FCS check algorithm to check. If a data frame is abnormal, the data frame is discarded to obtain the first target data frame.

[0108] In another possible embodiment, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond one-to-one to the multiple interfaces. In combination with Figure 8, the structural diagram of the communication system is shown in Figure 11. The convergence and distribution module sends the first target data frame through at least one interface indicated by the first indication information, including: the convergence and distribution circuit sends the first data frame to the digital circuit corresponding to the at least one interface according to the first indication information; the digital circuit determines the first target data frame according to the MAC protocol and the first data frame; and the digital circuit sends the first target data frame through at least one interface. Exemplarily, the interface indicated by the first indication information may include interface 1 to interface 4, and the convergence and distribution circuit sends the first data frame to the digital circuits 1 to digital circuit 4 corresponding to interface 1 to interface 4 respectively. Digital circuit 1 and digital circuit 4 respectively determine the first target data frame according to the MAC protocol and the first data frame; and send the first target data frame through interface 1 and interface 4 respectively. The convergence and distribution circuit is used to implement the convergence and distribution functions, and each digital circuit in the multiple data circuits is used to implement part of the functions of the MAC protocol. In Figure 11, a communication system including 4 interfaces (which can be represented as interface 1 to interface 4) and 4 digital circuits (which can be represented as digital circuit 1 to digital circuit 4) is taken as an example. Interface 1 corresponds to digital circuit 1, and so on, interface 4 corresponds to digital circuit 4.

[0109] Specifically, the digital circuit determines the first target data frame based on the MAC protocol and the first data frame, including: the digital circuit checks whether the length of each data frame in the first data frame meets the length range defined by the MAC protocol according to the MAC protocol. For example, the MAC protocol defines the minimum length of the data frame as 64 bytes and the maximum length as 1518 bytes. If a data frame does not meet the length range defined by the MAC protocol, for example, the length of a data frame is less than 64 bytes, the digital circuit fills the data frame according to the padding content defined by the MAC protocol so that the length of the padded data frame is equal to 64 bytes; the digital circuit is also used to check each data frame, using the check code included in the end of each data frame to check the data frame, for example, using the FCS check algorithm to check. If a data frame is abnormal, the data frame is discarded, thereby obtaining the first target data frame.

[0110] The first target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold. The first threshold is defined by the MAC protocol. For example, the first threshold may be 64 bytes.

[0111] Furthermore, the communication system also includes multiple PHYs, and the multiple PHYs correspond one-to-one to the multiple interfaces. For example, as shown in FIG12 , the communication system may include 4 interfaces and may be represented as interface 1 to interface 4, and 4 PHYs and may be represented as PHY1 to PHY4, wherein interface 1 corresponds to PHY1, and so on, interface 4 corresponds to PHY4. The convergence and distribution module sends the first target data frame through at least one interface, including: the convergence and distribution module sends the first target data frame to the corresponding PHY through at least one interface, for example, the convergence and distribution module sends the first target data frame to PHY3 through interface 3. Optionally, each of the multiple PHYs can be integrated on a chip, and the PHY can also be called a PHY chip. FIG12 takes the communication system including 4 interfaces and 4 PHYs as an example.

[0112] FIG13 is a flowchart of a data transmission method provided in an embodiment of the present application. The method can be applied to the communication system provided above, and the method includes the following steps.

[0113] S130: For each interface among the multiple interfaces, the aggregation and distribution module receives a second data frame through the interface, where the second data frame is a data frame corresponding to the at least one second message.

[0114] Specifically, the aggregation and distribution module may receive the second data frame through a bus and an interface. For example, the bus may include a 32-bit bus.

[0115] Among them, for each interface in the multiple interfaces, the interface may include MII, or a derivative interface of MII, such as GMII, SGMII, RMII and RGMII, etc. MII or derivative interfaces of MII are collectively referred to as medium-independent interfaces. The embodiments of the present application do not specifically limit the number of interfaces and the number of processor cores. For example, the number of interfaces can be greater than the number of processor cores. For example, the multiple interfaces may include n interfaces, and at least one processor core may include m processor cores, where n is greater than m, and n and m are integers. In actual applications, the number n is related to the performance of the m processor cores, and can be specifically set according to actual needs or the experience of relevant staff. The embodiments of the present application do not specifically limit this.

[0116] In addition, the at least one second message may include two first messages, or may include multiple second messages. The at least one second message may also be referred to as Ethernet data at or above the third layer (network layer).

[0117] In a possible embodiment, the convergence and distribution module includes a convergence and distribution circuit. The convergence and distribution module receives the second data frame through an interface, which includes: the convergence and distribution circuit receives the second data frame through the interface.

[0118] In another possible embodiment, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond one-to-one to multiple interfaces. For example, interface 1 corresponds to digital circuit 1, and interface n corresponds to digital circuit n. The convergence and distribution module receives the second data frame through the interface, including: the digital circuit corresponding to the interface receives the second data frame through the interface, and the digital circuit sends the second data frame to the convergence and distribution circuit through the bus. For example, digital circuit 1 receives the second data frame through interface 1 and sends the second data frame to the convergence and distribution circuit through the bus, and digital circuit n receives the second data frame through interface n and sends the second data frame to the convergence and distribution circuit through the bus.

[0119] Furthermore, the communication system includes multiple PHYs, each corresponding to one of the multiple interfaces. For example, the communication system includes n interfaces and n PHYs, with interface 1 corresponding to PHY1, and so on, with interface n corresponding to PHYn. The convergence and distribution module receives the second data frame via the interface, including: the convergence and distribution module receives the second data frame from the corresponding PHY via the interface, for example, the convergence and distribution module receives the second data frame from PHY1 via interface 1, and the convergence and distribution module receives the second data frame from PHYn via interface n. Each of the multiple PHYs can be integrated on a single chip, which can also be referred to as a PHY chip.

[0120] Furthermore, the method provided in the embodiment of the present application also includes:

[0121] S131: The convergence and distribution module stores the second target data frame and sends second indication information to at least one processor core, where the second indication information is used to instruct at least one processor core to read the second target data frame from the convergence and distribution module. The second target data frame is determined by the convergence and distribution module based on the multiple access control MAC protocol and the second data frame.

[0122] In a possible embodiment, the convergence and distribution module includes a convergence and distribution circuit, which stores the second target data frame and sends second indication information to at least one processor core, including: the convergence and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; the convergence and distribution circuit stores the second target data frame and sends the second indication information to at least one processor core.

[0123] Specifically, the convergence and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame, including: the convergence and distribution circuit checks whether the length of each data frame in the second data frame meets the length range defined according to the MAC protocol, for example, the MAC protocol defines the minimum length of the data frame as 64 bytes and the maximum length as 1518 bytes. If a data frame does not meet the length range defined by the MAC protocol, for example, the length of a data frame is less than 64 bytes, then the convergence and distribution circuit fills the data frame according to the filling content defined by the MAC protocol, so that the length of the filled data frame is equal to 64 bytes; the convergence and distribution circuit is also used to check each data frame, and use the check code included in the end of each data frame to check the data frame, for example, use the FCS check algorithm to check. If a data frame is abnormal, the data frame is discarded, thereby obtaining the second target data frame.

[0124] In another possible embodiment, the convergence and distribution module includes a convergence and distribution circuit and multiple digital circuits. The convergence and distribution module stores the second target data frame and sends second indication information to at least one processor core, including: the digital circuit receives the second data frame, and determines and sends the second target data frame to the convergence and distribution circuit based on the MAC protocol and the second data frame; the convergence and distribution circuit stores the second target data frame and sends the second indication information to at least one processor core.

[0125] Specifically, the digital circuit checks, according to the MAC protocol, whether the length of each data frame in the second data frame meets the length range defined by the MAC protocol. For example, the MAC protocol defines that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes. If a data frame does not meet the length range defined by the MAC protocol, for example, the length of a data frame is less than 64 bytes, the digital circuit fills the data frame according to the filling content defined by the MAC protocol so that the length of the padded data frame is equal to 64 bytes; the digital circuit is also used to check each data frame, using the check code included in the end of each data frame to check the data frame, for example, using the FCS check algorithm for verification. If a data frame is abnormal, the data frame is discarded, thereby obtaining the second target data frame.

[0126] The second target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold. The first threshold is defined by the MAC protocol, for example, the first threshold may be 64 bytes.

[0127] In addition, when the at least one processor core includes multiple processor cores, the multiple processor cores may be processor cores in the same processor or in different processors. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core may all be processor cores in a CPU, or the first processor core and the second processor core may be processor cores in a CPU, and the third processor core may be a processor core in an NPU. This embodiment of the present application does not specifically limit this.

[0128] In addition, the processor core may include a reduced instruction set computer (RISC). For example, the RISC may include a PRU and a deterministic realtime unit (DRU). In one possible embodiment, the processor core may be a 32-bit RISC operating at a frequency of 200 MHz to 400 MHz. The processor core may also be referred to as a RISC core or a RISC real-time core. In practical applications, the processor core may implement different functions by running different programs. That is, the functions of the processor core are programmable. For example, the processor core may implement a sending function by running a sending program, and the processor core may implement a receiving function by running a receiving program.

[0129] Optionally, when the at least one processor core includes multiple processor cores, the multiple processor cores may be the same processor core or different processor cores. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core, and the first processor core, the second processor core, and the third processor core may all be RISC cores; or, the first processor core and the second processor core may be RISC cores, and the third processor core may be a CPU core. This is not specifically limited by the embodiments of the present application.

[0130] Furthermore, at least one processor core reads a second target data frame from the convergence and distribution module based on the second indication information, and processes the second target data frame to obtain at least one second message. Specifically, at least one processor core splits the second target data frame to obtain multiple sub-data, that is, removes the frame header and frame footer of each data frame in the multiple data frames included in the second target data frame, thereby obtaining multiple sub-data, and parses the multiple sub-data to obtain at least one message type, and reassembles the multiple sub-data belonging to a message type to obtain at least one second message. Furthermore, at least one processor core writes the at least one second message into a memory, and uses the memory to achieve communication between the multiple processor cores.

[0131] In one possible embodiment, the convergence and distribution module forwards the second target data frame to at least one of the multiple interfaces based on preset information, where the preset information includes at least one interface. For example, the convergence and distribution module directly forwards the second target data frame to at least one of the multiple interfaces based on a forwarding table entry preconfigured by at least one processor core during initialization. This improves forwarding efficiency.

[0132] In another possible embodiment, the convergence and distribution module sends the second target data frame to at least one processor core, and the at least one processor core starts a forwarding function and implements forwarding through steps S301 and S302.

[0133] The data transmission method provided by the present application is as follows: on the sending side: at least one processor core obtains and processes at least one first message to obtain a first data frame, at least one processor core sends the first data frame and first indication information to the convergence and distribution module, the first indication information is used to indicate at least one interface, the convergence and distribution module determines the first target data frame according to the MAC protocol and the first data frame, and sends the first target data frame to the corresponding PHY through at least one interface indicated by the indication information; on the receiving side: the convergence and distribution module receives the second data frame from the corresponding PHY through the interface, and determines the second target data frame according to the MAC protocol and the second data frame, the convergence and distribution module stores the second target data frame and sends second indication information to at least one processor core, the second indication information is used to indicate that the convergence and distribution module stores the second target data frame, at least one processor core reads the second target data frame based on the second indication information, and processes the second target data frame to obtain at least one second message. In this process, the convergence and distribution module implements the functions of the MAC protocol. The convergence and distribution module implements the functions originally implemented by the processor core, reducing the load of the processor core, so that at least one processor core can correspond to multiple interfaces, and the number of multiple interfaces is greater than the number of at least one processor core. Since the area and cost of the convergence and distribution module are smaller than the area and cost of the processor core, compared with the processor core implementing the function of the MAC protocol in Figure 1, where one processor core corresponds to one interface, while increasing the number of interfaces, the area and cost of the communication system are reduced.

[0134] Based on this, an embodiment of the present application further provides a communication system, which includes at least one processor core, a convergence and distribution module, and multiple interfaces. The communication system may be the communication system shown in Figures 2 and 4 through 12 above. In an embodiment of the present application, the at least one processor core may be used to execute S301 in the above method embodiment and / or other steps described herein; the convergence and distribution module may be used to execute S302, S130, and S131 in the above method embodiment and / or other steps described herein.

[0135] It can be understood that the specific structure of at least one processor core, the convergence and distribution module and multiple interfaces, as well as all relevant contents of the steps involved in the above method embodiment can be referred to the embodiment of the communication system, and the embodiments of this application will not be repeated here.

[0136] In another aspect of the present application, an electronic device is also provided, which includes a memory and a communication system, the communication system includes at least one processor core and a convergence and distribution module, the memory is used to store computer instructions, and at least one processor core and the convergence and distribution module are used to execute the computer instructions so that the electronic device implements the data transmission processing method provided above.

[0137] It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the embodiment of the communication system and the embodiment of the electronic device, and the embodiments of the present application will not be repeated here.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0139] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0141] In another embodiment of the present application, a readable storage medium is provided, in which computer execution instructions are stored. When the computer instructions are executed on a communication system, the communication system executes the steps in the above method embodiment.

[0142] In yet another embodiment of the present application, a computer program product is provided. When the computer program product is run on a communication system, the communication system is caused to execute the steps in the above method embodiment.

[0143] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication system, characterized in that, The communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; At least one of the processor cores is configured to send a first data frame and first indication information to the aggregation and distribution module, where the first indication information is used to indicate at least one of the multiple interfaces, and the first data frame is a data frame corresponding to at least one first message; The aggregation and distribution module is configured to send a first target data frame through at least one of the interfaces indicated by the first indication information, where the first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

2. The communication system according to claim 1, wherein The aggregation and distribution module includes an aggregation and distribution circuit; The aggregation and distribution circuit is configured to determine the first target data frame according to the MAC protocol and the first data frame; The aggregation and distribution circuit is further configured to send the first target data frame through at least one of the interfaces.

3. The communication system according to claim 1, wherein The aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to the multiple interfaces one by one; The aggregation and distribution circuit is configured to send the first data frame to the digital circuits corresponding to at least one of the interfaces according to the first indication information; The digital circuit is further configured to determine the first target data frame according to the MAC protocol and the first data frame; The digital circuit is further configured to send the first target data frame through at least one of the interfaces.

4. The communication system according to any one of claims 1-3, wherein The interface includes a media-independent interface.

5. The communication system according to any one of claims 1-4, wherein The first target data frame includes multiple data frames, and the length of each of the multiple data frames is greater than or equal to a first threshold.

6. The communication system according to any one of claims 1-5, characterized in that, The communication system further includes: multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one; The aggregation and distribution module is specifically configured to send the first target data frame to the corresponding physical layer through at least one of the interfaces.

7. The communication system according to any one of claims 1-6, wherein At least one of the processor cores includes a reduced instruction set computer.

8. The communication system according to any one of claims 1-7, wherein At least one of the processor cores is further configured to obtain the at least one first message and process the at least one first message to obtain the first data frame.

9. A communication system, characterized in that, The communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; The aggregation and distribution module is configured to, for each of the multiple interfaces, receive a second data frame through the interface, where the second data frame is a data frame corresponding to at least one second message; The aggregation and distribution module is further configured to store a second target data frame and send second indication information to at least one of the processor cores, where the second indication information is used to instruct at least one of the processor cores to read the second target data frame from the aggregation and distribution module, and the second target data frame is determined by the aggregation and distribution module according to the Media Access Control (MAC) protocol and the second data frame.

10. The communication system according to claim 9, characterized in that, The aggregation and distribution module includes an aggregation and distribution circuit; The aggregation and distribution circuit is configured to receive the second data frame through the interface; The aggregation and distribution circuit is further configured to determine the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit is further configured to store the second target data frame and send the second indication information to at least one of the processor cores.

11. The communication system according to claim 9, characterized in that, The aggregation and distribution module includes an aggregation and distribution circuit and a plurality of digital circuits, and the plurality of digital circuits correspond to the plurality of interfaces one by one; The digital circuit is configured to receive the second data frame through the corresponding interface; The digital circuit is configured to determine the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit is further configured to store a plurality of the second target data frames and send the second indication information to at least one of the processor cores.

12. The communication system according to any one of claims 9-11, wherein The interface includes a Media Independent Interface.

13. The communication system according to any one of claims 9-12, wherein The second target data frame includes a plurality of data frames, and the length of each of the plurality of data frames is greater than or equal to a first threshold.

14. The communication system according to any one of claims 9-13, characterized in that, The communication system further includes a plurality of physical layers, and the plurality of physical layers correspond to the plurality of interfaces one by one, The aggregation and distribution module is specifically further configured to receive the second data frame from the corresponding physical layer through the interface.

15. The communication system according to any one of claims 9-14, wherein At least one of the processor cores includes a Reduced Instruction Set Computer.

16. The communication system according to any one of claims 9-15, wherein At least one of the processor cores is configured to read the second target data frame from the aggregation and distribution module based on the second indication information and process the second target data frame to obtain at least one second message.

17. The communication system according to any one of claims 9-16, wherein The aggregation and distribution module is further configured to forward the second target data frame to at least one of the plurality of interfaces according to preset information, and the preset information includes at least one of the interfaces.

18. A data transmission method, characterized in that, The method is applied to a communication system, and the communication system includes: at least one processor core, an aggregation and distribution module, and a plurality of interfaces; At least one of the processor cores sends a first data frame and first indication information to the aggregation and distribution module, where the first indication information is used to indicate at least one of the plurality of interfaces, and the first data frame is a data frame corresponding to at least one first message; The aggregation and distribution module sends a first target data frame through at least one of the interfaces indicated by the first indication information, where the first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

19. The data transmission method according to claim 18, wherein The aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module sending the first target data frame through at least one of the interfaces includes: The aggregation and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame; The aggregation and distribution circuit sends the first target data frame through at least one of the interfaces.

20. The data transmission method according to claim 18, characterized in that, The aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits. The multiple digital circuits correspond to the multiple interfaces one by one. The aggregation and distribution module sending the first target data frame through at least one of the interfaces indicated by the first indication information includes: The aggregation and distribution circuit sends the first data frame to the digital circuits corresponding to at least one of the interfaces according to the first indication information; The digital circuit determines the first target data frame according to the MAC protocol and the first data frame; The digital circuit sends the first target data frame through at least one of the interfaces.

21. The data transmission method according to any one of claims 18-20, characterized in that The interface includes a media independent interface.

22. The data transmission method according to any one of claims 18-21, characterized in that The first target data frame includes multiple data frames, and the length of each of the multiple data frames is greater than or equal to a first threshold.

23. The data transmission method according to any one of claims 18-22, characterized in that, The communication system further includes multiple physical layers. The multiple physical layers correspond to the multiple interfaces one by one. The aggregation and distribution module sending the first target data frame through at least one of the interfaces includes: The aggregation and distribution module sends the first target data frame to the corresponding physical layer through at least one of the interfaces.

24. The data transmission method according to any one of claims 18-23, characterized in that At least one of the processor cores includes a reduced instruction set computer.

25. The data transmission method according to any one of claims 18-24, characterized in that, The method further includes: At least one of the processor cores obtains at least one of the first packets and processes at least one of the first packets to obtain the first data frame.

26. A data transmission method, characterized in that, The method is applied to a communication system, and the communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; For each of the multiple interfaces, the aggregation and distribution module receives a second data frame through the interface, where the second data frame is a data frame corresponding to at least one second packet; The aggregation and distribution module stores the second target data frame and sends second indication information to at least one of the processor cores. The second indication information is used to instruct at least one of the processor cores to read the second target data frame from the aggregation and distribution module, where the second target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the second data frame.

27. The data transmission method according to claim 26, wherein The aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module receives a second data frame through the interface, including: The aggregation and distribution circuit receives the second data frame through the interface; The aggregation and distribution module stores a second target data frame and sends second indication information to at least one of the processor cores, including: The aggregation and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit stores the second target data frame and sends the second indication information to at least one of the processor cores.

28. The data transmission method according to claim 26, wherein The aggregation and distribution module includes an aggregation and distribution circuit and a plurality of digital circuits. The plurality of digital circuits correspond to the plurality of interfaces one by one. The aggregation and distribution module receives a second data frame through the interface, including: The digital circuit corresponding to the interface receives the second data frame through the interface; The aggregation and distribution module stores a second target data frame and sends second indication information to at least one of the processor cores, including: The digital circuit determines the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit stores the second target data frame and sends the second indication information to at least one of the processor cores.

29. The data transmission method according to any one of claims 26-28, wherein: The interface includes a media-independent interface.

30. The data transmission method according to any one of claims 26-29, wherein: The second target data frame includes a plurality of data frames, and the length of each of the plurality of data frames is greater than or equal to a first threshold.

31. The data transmission method according to any one of claims 26-30, characterized in that, The communication system further includes a plurality of physical layers. The plurality of physical layers correspond to the plurality of interfaces one by one. The aggregation and distribution module receives a second data frame through the interface, including: The aggregation and distribution module receives the second data frame from the corresponding physical layer through the interface.

32. The data transmission method according to any one of claims 26-31, wherein: At least one of the processor cores includes a reduced instruction set computer.

33. The data transmission method according to any one of claims 26-32, characterized in that, The method further includes: At least one of the processor cores reads the second target data frame from the aggregation and distribution module based on the second indication information and processes the second target data frame to obtain at least one second message.

34. The data transmission method according to any one of claims 26-33, characterized in that, The method further includes: The aggregation and distribution module forwards the second target data frame to at least one of the plurality of interfaces according to preset information, and the preset information includes at least one of the interfaces.

35. An electronic device, characterized in that, The electronic device includes a communication system and a memory. The memory is used to store computer instructions. The communication system includes at least one processor core and an aggregation and distribution module. The communication system is the communication system according to any one of claims 1-8 or claims 9-17.

Images